Method for forming active region and method for forming semiconductor structure

Abstract

Embodiments of the present application provide a method for forming an active region and a method for forming a semiconductor structure, wherein the method for forming the active region comprises: providing a semiconductor substrate; sequentially forming a first mask layer and a second mask layer on a surface of the semiconductor substrate; wherein the second mask layer has an initial pattern for forming the active region; forming a sacrificial layer covering the second mask layer; removing the sacrificial layer and part of the second mask layer to form a third mask layer with a preset thickness; wherein the preset thickness is smaller than an initial thickness of the second mask layer; and forming the active region through the third mask layer and the first mask layer. By processing the second mask layer having the initial pattern for forming the active region to obtain the third mask layer with a smaller thickness, and then forming the active region through the third mask layer, the shape of the pattern in the subsequent etching process can be easily controlled, which is conducive to the formation of the active region.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and to, but is not limited to, a method for forming an active region and a method for forming a semiconductor structure. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a type of semiconductor memory widely used in electronic products such as mobile phones, computers, and automobiles. With the advancement of technology and the continuous shrinking of integrated circuit device feature sizes, the critical dimensions of DRAM are also becoming smaller, making its fabrication increasingly challenging.

[0003] In related technologies, during the etching process of the active area (AA) of dynamic random access memory, the use of double pattern technology results in a smaller linewidth, which can easily lead to adverse effects such as pattern deformation, hindering the formation of the active area in the future. Summary of the Invention

[0004] In view of this, embodiments of this application provide a method for forming an active region and a method for forming a semiconductor structure.

[0005] In a first aspect, embodiments of this application provide a method for forming an active region, the method comprising:

[0006] Provide semiconductor substrates;

[0007] A first mask layer and a second mask layer are sequentially formed on the surface of the semiconductor substrate; wherein the second mask layer has an initial pattern for forming the active region;

[0008] A sacrificial layer is formed covering the second mask layer;

[0009] The sacrificial layer and a portion of the second mask layer are removed to form a third mask layer with a preset thickness; wherein the preset thickness is less than the initial thickness of the second mask layer.

[0010] The active region is formed by the third mask layer and the first mask layer.

[0011] In some embodiments, removing the sacrificial layer and a portion of the second mask layer to form a third mask layer with a predetermined thickness includes:

[0012] The sacrificial layer and the second mask layer are thinned to remove a portion of the thickness of the second mask layer, forming the third mask layer and the sacrificial layer with the preset thickness; wherein the third mask layer has the initial pattern;

[0013] Remove the sacrificial layer having the preset thickness.

[0014] In some embodiments, the second mask layer includes a first hard mask layer, a second hard mask layer, and an anti-reflection layer stacked sequentially from bottom to top;

[0015] The process of thinning the sacrificial layer and the second mask layer, removing a portion of the thickness of the second mask layer, to form the third mask layer with a preset thickness includes:

[0016] The sacrificial layer, the anti-reflection layer, and the second hard mask layer are thinned, while retaining a portion of the thickness of the second hard mask layer, to form the third mask layer.

[0017] In some embodiments, the second mask layer is formed by the following steps:

[0018] A second initial mask layer and a patterned photoresist layer are sequentially formed on the surface of the first mask layer; wherein the patterned photoresist layer has the initial pattern;

[0019] The second initial mask layer is etched through the patterned photoresist layer to obtain a second mask layer with the initial pattern.

[0020] In some embodiments, the method further includes:

[0021] After forming the second mask layer, the patterned photoresist layer is removed.

[0022] In some embodiments, the initial pattern in the second mask layer exposes a portion of the first mask layer;

[0023] The sacrificial layer forming the second mask layer includes:

[0024] Sacrificial material is deposited on the exposed surfaces of the first and second mask layers to form the sacrificial layer.

[0025] In some embodiments, the etching selectivity between the sacrificial material and the first mask layer is greater than the etching selectivity between the first hard mask layer and the first mask layer, and the etching selectivity between the sacrificial material and the first mask layer is greater than the etching selectivity between the second hard mask layer and the first mask layer.

[0026] In some embodiments, the initial pattern in the third mask layer exposes a portion of the first mask layer;

[0027] The formation of the active region through the third mask layer and the first mask layer includes:

[0028] A sidewall material layer is formed on the surface of the exposed first mask layer and the third mask layer;

[0029] A portion of the sidewall material layer and a portion of the third mask layer are removed to form a fourth mask layer;

[0030] The active region is formed through the fourth mask layer and the first mask layer.

[0031] In some embodiments, the sidewall material layer includes a first sidewall material layer and a second sidewall material layer;

[0032] The process of forming a sidewall material layer on the exposed surfaces of the first and third mask layers includes:

[0033] A first sidewall material is deposited on the top and sidewalls of the third mask layer and on the exposed surface of the first mask layer to form the first sidewall material layer;

[0034] A second sidewall material is deposited on the surface of the first sidewall material layer to form the second sidewall material layer.

[0035] In some embodiments, the third mask layer includes a first hard mask layer and a second hard mask layer of a certain thickness;

[0036] The process of removing part of the sidewall material layer and part of the third mask layer to form a fourth mask layer includes:

[0037] The sidewall material layer is planarized until the top surface of the second hard mask layer is exposed; the remaining first sidewall material layer is a plurality of U-shaped structures formed by two vertical sidewalls and one horizontal sidewall.

[0038] Remove the vertical sidewalls from the remaining first sidewall material layer;

[0039] The second hard mask layer and the remaining second sidewall material layer are removed to form the fourth mask layer.

[0040] In some embodiments, the fourth mask layer has a preset pattern; the pattern density of the preset pattern is greater than the pattern density of the initial pattern.

[0041] In some embodiments, forming the active region through the fourth mask layer and the first mask layer includes:

[0042] The first mask layer is etched by the fourth mask layer to transfer the preset pattern into the first mask layer, thereby obtaining a patterned first mask layer;

[0043] The active region is formed by etching the semiconductor substrate through the patterned first mask layer.

[0044] In some embodiments, the method further includes:

[0045] After forming the patterned first mask layer, the fourth mask layer is removed.

[0046] In some embodiments, the method further includes:

[0047] After the active region is formed, the patterned first mask layer is removed.

[0048] Secondly, embodiments of this application provide a method for forming a semiconductor structure, the method comprising:

[0049] Provide semiconductor substrates;

[0050] An active region is formed on the semiconductor substrate using the above-described method for forming an active region.

[0051] A character line is formed, wherein the character line intersects the active region in the character line extension direction;

[0052] A bit line is formed, which intersects the active region in the bit line extension direction.

[0053] The active region formation method and semiconductor structure formation method provided in this application include providing a semiconductor substrate; sequentially forming a first mask layer and a second mask layer on the surface of the semiconductor substrate, the second mask layer having an initial pattern for forming the active region; forming a sacrificial layer covering the second mask layer; removing the sacrificial layer and a portion of the second mask layer to form a third mask layer with a preset thickness; the preset thickness being less than the initial thickness of the second mask layer; and forming the active region through the third mask layer and the first mask layer. In this application embodiment, by processing the second mask layer having the initial pattern for forming the active region, a third mask layer with a smaller thickness is obtained, and then the active region is formed through the third mask layer. This makes it easier to control the shape of the pattern during subsequent etching, which is beneficial for the formation of the active region. Attached Figure Description

[0054] In the accompanying drawings (which are not necessarily drawn to scale), similar reference numerals may describe similar parts in different views. Similar reference numerals with different letter suffixes may indicate different examples of similar parts. The drawings illustrate, by way of example and not limitation, the various embodiments discussed herein.

[0055] Figures 1a-1e This is a structural schematic diagram of the formation process of the active region in related technologies;

[0056] Figure 2 A flowchart illustrating the method for forming an active region provided in an embodiment of this application;

[0057] Figures 3a-3n A schematic diagram of the formation process of the active region provided in the embodiments of this application;

[0058] Figure 4 A schematic flowchart illustrating a method for forming a semiconductor structure according to an embodiment of this application;

[0059] Figure 5 A top view of a semiconductor structure provided in an embodiment of this application;

[0060] Explanation of reference numerals in the attached figures:

[0061] 100 / 200 - Semiconductor substrate; 101 - First hard mask layer; 102 - Second hard mask layer; 103 - Photoresist layer; 102a - Etched second hard mask layer; 103 - Sidewall layer; 104 - Third hard mask layer; 201 - First mask layer; 201a - First mask layer; 201b - First mask layer; 201c - First mask layer; 201d - First mask layer; 201e - Barrier layer; 202' - Second initial mask layer; 203 - Patterned photoresist layer; 202a' - First initial hard mask layer; 202b' - Second initial hard mask layer; 202c' - Initial anti-reflective layer; 202 - Second mask layer; 202a - First hard mask layer; 202b - Second hard mask layer; 202c - Anti-reflective layer; 204-Sacrificial layer; 204'-Sacrificial layer of preset thickness; 206-First sidewall material layer; 207-Second sidewall material layer; 207'-Remaining second sidewall material layer; 206a-Vertical sidewall; 206b-Horizontal sidewall; 208-Fourth mask layer; 201'-Patterned first mask layer; 201a'-Patterned first mask layer; 201b'-Patterned second mask layer; 201c'-Patterned third mask layer; 201d'-Patterned fourth mask layer; 201e'-Patterned barrier layer; 209-Active region; 210-Shallow trench isolation; 50-Semiconductor structure; 501-Bit line; 502-Word line; A-Intermediate pattern; B-Initial pattern; C-Preset pattern. Detailed Implementation

[0062] Exemplary embodiments of the present application will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the disclosure of the present application to those skilled in the art.

[0063] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, to avoid confusion with this application, some technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0064] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0065] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this application.

[0066] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0067] Before describing in detail the method for forming the active region in the embodiments of this application, the method for forming the active region in related technologies will be explained first.

[0068] Figures 1a-1e This is a structural schematic diagram of the formation process of the active region in related technologies, such as... Figures 1a-1eAs shown, the formation process of the active region in the related technology includes the following steps: First, as Figure 1a As shown, a first hard mask layer 101 and a second hard mask layer 102 are formed on the surface of the semiconductor substrate 100, and a photoresist layer 103 is formed on the surface of the second hard mask layer 102. The photoresist layer 103 has an initial pattern for forming the active region; next, a first etching process is performed, such as... Figure 1b As shown, the second hard mask layer 102 is etched through the photoresist layer 103 to obtain the etched second hard mask layer 102a, which exposes a portion of the surface of the first hard mask layer 101; again, as... Figure 1c As shown, sidewall layers 103 are formed on the exposed surface of the first hard mask layer 101, the top of the etched second hard mask layer 102a, and its sidewalls; additionally, as... Figure 1d As shown, a third hard mask layer 104 is formed on the surface of the sidewall layer 103, and the third hard mask layer 104 and part of the sidewall layer 103 are etched to form a shape as shown. Figure 1e The intermediate pattern A is shown; finally, a second etching process and a third etching process are performed to etch the first hard mask layer 101 and the semiconductor substrate 100 through the intermediate pattern A, forming multiple spaced active regions and shallow trench isolation structures in the semiconductor substrate 100.

[0069] In related technologies, after the first etching, a sidewall layer 103 (e.g., silicon oxide) is deposited on the surface of the etched second hard mask layer 102a using a dual-patterning process. Since the height of the etched second hard mask layer 102a is relatively high in related technologies, the deposition surface is difficult to control. Therefore, the pattern shape of the subsequent second and third etching processes is difficult to control, which is not conducive to the formation of the active region.

[0070] Based on the aforementioned problems in related technologies, this application provides a method for forming an active region and a semiconductor structure. The method for forming the active region includes providing a semiconductor substrate; sequentially forming a first mask layer and a second mask layer on the surface of the semiconductor substrate, the second mask layer having an initial pattern for forming the active region; forming a sacrificial layer covering the second mask layer; removing the sacrificial layer and a portion of the second mask layer to form a third mask layer with a predetermined thickness; the predetermined thickness being less than the initial thickness of the second mask layer; and forming the active region through the third mask layer and the first mask layer. In this application embodiment, by processing the second mask layer having the initial pattern for forming the active region, a third mask layer with a smaller thickness is obtained, and then the active region is formed through the third mask layer. This makes it easier to control the shape of the pattern during subsequent etching, which is beneficial for the formation of the active region.

[0071] This application provides a method for forming an active region. Figure 2 A flowchart illustrating the method for forming an active region provided in an embodiment of this application is shown below. Figure 2 As shown, the method for forming the active region includes the following steps:

[0072] Step S201: Provide a semiconductor substrate.

[0073] In this embodiment of the application, the semiconductor substrate may be a silicon substrate, or it may include other semiconductor elements, such as germanium (Ge), or include semiconductor compounds, such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs) or indium antimonide (InSb), or include other semiconductor alloys, such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and / or gallium indium arsenide phosphide (GaInAsP) or combinations thereof.

[0074] Step S202: A first mask layer and a second mask layer are sequentially formed on the surface of a semiconductor substrate; wherein the second mask layer has an initial pattern for forming an active region.

[0075] In the embodiments of this application, a first mask layer and a second mask layer can be sequentially formed on the surface of a semiconductor substrate by any suitable deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), spin coating, or coating process.

[0076] The first mask layer or the second mask layer can be composed of a single mask layer or multiple mask layers.

[0077] Step S203: Form a sacrificial layer covering the second mask layer.

[0078] In this embodiment, since the second mask layer has an initial pattern for forming the active region, the second mask layer exposes a portion of the surface of the first mask layer, and the sacrificial layer covers the surface of the second mask layer. Therefore, the sacrificial layer also covers a portion of the surface of the first mask layer. The sacrificial layer can be composed of any material that is relatively easy to remove from either the second or first mask layer.

[0079] Step S204: Remove the sacrificial layer and part of the second mask layer to form a third mask layer with a preset thickness; wherein the preset thickness is less than the initial thickness of the second mask layer.

[0080] Here, the process of removing the sacrificial layer and part of the second mask layer can be etching or chemical mechanical polishing (CMP). In this embodiment, the method of removing the sacrificial layer and part of the second mask layer is not limited.

[0081] In this embodiment, the third mask layer is only thinner than the second mask layer, and the third mask layer also has an initial pattern for forming the active region.

[0082] Step S205: An active region is formed through the third mask layer and the first mask layer.

[0083] Figures 3a-3n This is a schematic diagram of the formation process of the active region provided in an embodiment of this application. Please refer to the following. Figures 3a-3n The method for forming the active region provided in the embodiments of this application will be described in further detail.

[0084] First, step S201 is performed, providing a semiconductor substrate.

[0085] Next, you can refer to Figure 3a and 3b Step S202 is executed, in which a first mask layer and a second mask layer are sequentially formed on the surface of a semiconductor substrate; wherein the second mask layer has an initial pattern for forming an active region.

[0086] In some embodiments, the second mask layer may be formed by the following steps:

[0087] Step S2021: A second initial mask layer and a patterned photoresist layer are sequentially formed on the surface of the first mask layer; wherein the patterned photoresist layer has an initial pattern.

[0088] like Figure 3a As shown, the first mask layer 201 is located on the surface of the semiconductor substrate 200, and in this embodiment, the first mask layer 201 includes a first mask layer 201a, a second mask layer 201b, a third mask layer 201c, a fourth mask layer 201d, and a barrier layer 201e stacked sequentially from bottom to top. The first mask layer 201a may be a silicon oxide layer, the second mask layer 201b and the fourth mask layer 201d may be silicon nitride layers, the third mask layer 201c may be a spin-coated carbon layer or a spin-coated hard mask layer, and the barrier layer 201e may be an amorphous silicon layer. A second initial mask layer 202' is formed on the surface of the first mask layer 201, and a patterned photoresist layer 203 is formed on the surface of the second initial mask layer 202'. The photoresist layer 203 has an initial pattern B for forming the active region.

[0089] In this embodiment of the application, the second initial mask layer 202' includes a first initial hard mask layer 202a', a second initial hard mask layer 202b', and an initial anti-reflection layer 202c' stacked sequentially from bottom to top. The first initial hard mask layer 202a' may be a silicon oxide layer, the second initial hard mask layer 202b' may be a carbon layer, and the initial anti-reflection layer 202c' may be a silicon oxynitride layer.

[0090] In other embodiments, the first mask layer and the second mask layer may also be composed of other hard mask layers or other materials. In the embodiments of this application, the composition of the first mask layer and the second mask layer is not limited.

[0091] Step S2022: Etch the second initial mask layer through the patterned photoresist layer to obtain the second mask layer with the initial pattern.

[0092] like Figure 3b As shown, the second initial mask layer 202' is etched through the patterned photoresist layer 203 to obtain the second mask layer 202 with the initial pattern B. The second mask layer 202 includes a first hard mask layer 202a, a second hard mask layer 202b, and an anti-reflection layer 202c stacked sequentially from bottom to top.

[0093] In some embodiments, please continue to see Figure 3b After forming the second mask layer 202, the method for forming the active region further includes removing the patterned photoresist layer 203. In this embodiment, wet etching technology can be used to remove the patterned photoresist layer 203.

[0094] Next, you can refer to Figure 3c Step S203 is executed to form a sacrificial layer covering the second mask layer.

[0095] In some embodiments, the initial pattern B in the second mask layer exposes a portion of the first mask layer. Step S203 can be achieved by the following steps: depositing sacrificial material on the surfaces of the exposed first and second mask layers to form a sacrificial layer.

[0096] like Figure 3cAs shown, a sacrificial material is deposited on the exposed surfaces of the first mask layer 201 and the second mask layer 202 to form a sacrificial layer 204. In this embodiment, the etching selectivity between the sacrificial material and the first mask layer 201 is greater than the etching selectivity between the first hard mask layer 202a and the first mask layer 201, and the etching selectivity between the sacrificial material and the first mask layer 201 is greater than the etching selectivity between the second hard mask layer 202b and the first mask layer 201. That is, the sacrificial layer is easier to remove than the first hard mask layer 202a and the second hard mask layer 202b. In this embodiment, the sacrificial material can be photoresist (PR).

[0097] Next, you can refer to Figure 3d and 3e Step S204 is executed to remove the sacrificial layer and part of the second mask layer to form a third mask layer with a preset thickness.

[0098] In some embodiments, step S204 may include the following steps:

[0099] Step S2041: Thin the sacrificial layer and the second mask layer, remove part of the thickness of the second mask layer, and form a third mask layer and a sacrificial layer with a preset thickness; wherein the third mask layer has an initial pattern.

[0100] In this embodiment, the process of thinning the sacrificial layer and the second mask layer can be achieved through chemical mechanical polishing or through a specific etching process.

[0101] In some embodiments, step S2041 can be achieved by the following steps: thinning the sacrificial layer, the anti-reflection layer, and the second hard mask layer, retaining a portion of the thickness of the second hard mask layer, to form a third mask layer.

[0102] like Figure 3d As shown, starting from the top surface of the sacrificial layer 204, the sacrificial layer 204, the anti-reflection layer 202c, and the second hard mask layer 202b are thinned. Part of the sacrificial layer, the anti-reflection layer 202c, and part of the second hard mask layer are removed, while a portion of the second hard mask layer 202b is retained, forming a third mask layer 205 and a sacrificial layer 204' with a preset thickness h1. The preset thickness h1 is less than the initial thickness h0 of the second mask layer 202 (e.g., h0). Figure 3c (As shown).

[0103] Step S2042: Remove the sacrificial layer with a preset thickness.

[0104] like Figure 3eAs shown, the sacrificial layer 204' with a preset thickness has been removed. In this embodiment, a wet etching technique can be used to remove the sacrificial layer with a preset thickness. For example, a solution such as sulfuric acid, nitric acid, or hydrofluoric acid can be used to etch and remove the sacrificial layer with a preset thickness.

[0105] It should be noted that in the embodiments of this application, the process of removing the sacrificial layer with a high etching selectivity using wet etching technology will not damage the second hard mask layer in the third mask layer. In this way, the integrity of the third mask layer can be maintained, which is beneficial to the subsequent etching process.

[0106] Finally, you can refer to Figures 3f to 3n In step S205, an active region is formed through the third mask layer and the first mask layer.

[0107] In some embodiments, the initial pattern in the third mask layer exposes a portion of the first mask layer; step S205 may include the following steps:

[0108] S2051. A sidewall material layer is formed on the exposed surfaces of the first and third mask layers.

[0109] In this embodiment of the application, the sidewall material layer includes a first sidewall material layer and a second sidewall material layer. The sidewall material layer is used to increase the pattern density of the initial pattern. Step S2051 may include the following steps:

[0110] Step S10: Deposit a first sidewall material on the top and sidewalls of the third mask layer and on the exposed surface of the first mask layer to form a first sidewall material layer.

[0111] In this embodiment, the first sidewall material layer can be formed by any suitable deposition process, and the second sidewall material layer can be an oxide layer, such as a silicon oxide layer.

[0112] like Figure 3f As shown, a first sidewall material is deposited on the top and sidewalls of the third mask layer 205 and on the exposed surface of the first mask layer 201 to form a first sidewall material layer 206.

[0113] In this embodiment, since the thickness of the third mask layer is lower than that of the second mask layer, the pattern of the first sidewall material layer deposited on the sidewall of the third mask layer is easier to control and maintain, and better meets the requirements of subsequent processes.

[0114] Step S11: Deposit a second sidewall material on the surface of the first sidewall material layer to form a second sidewall material layer.

[0115] The second sidewall material layer differs from the first sidewall material layer, and the second sidewall material layer is easier to remove than the first sidewall material layer. In this embodiment, the second sidewall material layer may be a carbon layer.

[0116] like Figure 3g As shown, a first sidewall material is deposited on the surface of the first sidewall material layer 206 to form a second sidewall material layer 207.

[0117] S2052. Remove part of the sidewall material layer and part of the third mask layer to form the fourth mask layer.

[0118] In some embodiments, the third mask layer includes a first hard mask layer and a second hard mask layer of a certain thickness, and step S2052 may include the following steps:

[0119] Step S12: Planarize the sidewall material layer until the top surface of the second hard mask layer is exposed; the remaining first sidewall material layer consists of multiple U-shaped structures formed by two vertical sidewalls and one horizontal sidewall.

[0120] like Figure 3h As shown, the second sidewall material layer 207 and the first sidewall material layer 206 are planarized by removing a portion of the second sidewall material layer 207 and a portion of the first sidewall material layer 206 located on the top surface of the second hard mask layer 202b, exposing the top surface of the second hard mask layer 202b, and retaining the remaining second sidewall material layer 207' and the remaining first sidewall material layer. The remaining first sidewall material layer consists of multiple U-shaped structures formed by two vertical sidewalls 206a and one horizontal sidewall 206b.

[0121] Step S13: Remove the vertical sidewalls from the remaining first sidewall material layer.

[0122] In this embodiment, a dry etching technique, such as plasma etching, can be used to etch away the vertical sidewalls in the remaining first sidewall material layer.

[0123] like Figure 3i As shown, the vertical sidewall 206a in the remaining first sidewall material layer is removed, exposing the horizontal sidewall 206b in the remaining first sidewall material layer.

[0124] Step S14: Remove the second hard mask layer and the remaining second sidewall material layer to form the fourth mask layer.

[0125] In this embodiment, dry or wet etching techniques can be used to remove the second hard mask layer and the remaining second sidewall material layer.

[0126] like Figure 3jAs shown, the second hard mask layer 202b and the remaining second sidewall material layer 207' are removed to form a fourth mask layer 208. The fourth mask layer 208 is composed of the first hard mask layer 202a and the horizontal sidewalls 206b in the remaining first sidewall material layer. In this embodiment, the fourth mask layer 208 has a preset pattern C; the pattern density of the preset pattern C is greater than the pattern density of the initial pattern B. For example, the pattern density of the preset pattern C can be twice the pattern density of the initial pattern B.

[0127] In this embodiment, since the height of the third mask layer is reduced relative to the height of the second mask layer, a better pattern etching effect can be obtained during the formation of the fourth mask layer through the third mask layer, reducing the curvature of the pattern and facilitating the control of key dimensions and the maintenance of pattern integrity during subsequent etching processes.

[0128] S2053. An active region is formed through the fourth mask layer and the first mask layer.

[0129] In some embodiments, step S2053 may include the following steps:

[0130] Step S15: Etch the first mask layer through the fourth mask layer to transfer the preset pattern to the first mask layer and obtain a patterned first mask layer.

[0131] like Figure 3k As shown, the first mask layer 201 is etched by the fourth mask layer 208 to obtain a patterned first mask layer 201', thereby transferring the preset pattern C into the first mask layer 201. The patterned first mask layer 201' includes, from bottom to top, a patterned first mask layer 201a', a patterned second mask layer 201b', a patterned third mask layer 201c', a patterned fourth mask layer 201d', and a patterned barrier layer 201e'.

[0132] In some embodiments, after forming the patterned first mask layer 201', the method for forming the active region further includes removing the fourth mask layer 208.

[0133] Step S16: Etch the semiconductor substrate through the patterned first mask layer to form the active region.

[0134] like Figures 3l-3n As shown, the semiconductor substrate 200 is etched through a patterned first mask layer 201' to transfer a preset pattern C into the semiconductor substrate 200, forming an active region 209 and a shallow trench isolation 210 located between adjacent active regions.

[0135] In some embodiments, please continue to see Figure 3m and 3nAfter forming the active region 209, the method for forming the active region also includes: removing the patterned first mask layer 201'.

[0136] In this embodiment, by processing the second mask layer with the initial pattern for forming the active region, a third mask layer with a smaller thickness is obtained, and then the active region is formed through the third mask layer. In this way, the shape of the pattern can be easily controlled during the subsequent etching process, which is beneficial to the formation of the active region.

[0137] In addition, embodiments of this application also provide a method for forming a semiconductor structure. Figure 4 This is a schematic flowchart of a method for forming a semiconductor structure provided in an embodiment of this application. Figure 5 This is a top view of a semiconductor structure provided in an embodiment of this application. The semiconductor structure 50 includes: an active region 209, a shallow trench isolation 210 located between adjacent active regions, a bit line 501, and a word line 502. Figure 4 As shown, the method for forming a semiconductor structure includes the following steps:

[0138] Step S401: Provide a semiconductor substrate.

[0139] In this embodiment of the application, the semiconductor substrate may be a silicon substrate, or it may include other semiconductor elements, such as germanium (Ge), or include semiconductor compounds, such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs) or indium antimonide (InSb), or include other semiconductor alloys, such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and / or gallium indium arsenide phosphide (GaInAsP) or combinations thereof.

[0140] Step S402: Form an active region on the semiconductor substrate.

[0141] In this embodiment, the active region 209 can be formed on the semiconductor substrate by the active region formation method provided in the above embodiments, which will not be described in detail here.

[0142] Step S403: Form word lines, where the word lines intersect the active area in the direction of word line extension.

[0143] Step S404: Form a bit line, which intersects the active region in the bit line extension direction.

[0144] In some embodiments, the active region 209 is used to form a memory cell, which includes a transistor. A word line 502 is connected to the gate of the transistor and is used to provide a word line voltage, thereby controlling the transistor to be turned on or off. A bit line 501 is connected to the source or drain of the transistor and is used to perform read or write operations on the memory cell when the transistor is turned on.

[0145] In this embodiment, word line 502 or bit line 501 is formed by forming metal lines at preset word line positions or preset bit line positions. The metal lines include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polycrystalline silicon, titanium nitride, doped silicon, silicides, or any combination thereof.

[0146] In some embodiments, the semiconductor structure 50 may further include a storage capacitor; correspondingly, the method of forming the semiconductor structure further includes forming a storage capacitor on the surface of the active region. One end of the storage capacitor is connected to the drain or source of the transistor, and the other end of the storage capacitor is grounded. The storage capacitor is used to store data written to the memory cell.

[0147] In other embodiments, the semiconductor structure 50 may further include an adjustable resistor; correspondingly, the method of forming the semiconductor structure further includes forming an adjustable resistor. The adjustable resistor is connected between the bit line 501 and the source of the transistor, or the adjustable resistor is connected between the bit line 501 and the drain of the transistor 401. The adjustable resistor is used to adjust the state of the data stored in the memory cell by the bit line voltage provided by the bit line 501.

[0148] The method for forming the semiconductor structure in this application embodiment is similar to the method for forming the active region in the above embodiments. For technical features not disclosed in detail in this application embodiment, please refer to the above embodiments for understanding. Here, they will not be repeated.

[0149] The semiconductor structure formation method provided in this application makes the etching pattern easier to control and maintain during the formation of the active region in the semiconductor structure, thus making the formation process of the active region more precise, and consequently making the semiconductor structure formation process more controllable and efficient, which is beneficial to improving the performance of the formed semiconductor structure.

[0150] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in a non-target manner. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components may be combined, or integrated into another system, or some features may be ignored or not executed. In addition, the various components shown or discussed are coupled to each other or directly coupled.

[0151] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units may be selected to achieve the purpose of this embodiment according to actual needs.

[0152] The features disclosed in the several method or device embodiments provided in this application can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0153] The above descriptions are merely some embodiments of this application, but the protection scope of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the embodiments of this application should be included within the protection scope of this application. Therefore, the protection scope of this application should be determined by the scope of the claims.

Claims

1. A method for forming an active region, the method comprising: providing a semiconductor substrate; sequentially forming a first mask layer and a second mask layer on a surface of the semiconductor substrate, wherein the second mask layer has an initial pattern for forming the active region; forming a sacrificial layer covering the second mask layer; removing the sacrificial layer and part of the second mask layer to form a third mask layer having a preset thickness, wherein the preset thickness is less than an initial thickness of the second mask layer; and forming the active region through the third mask layer and the first mask layer.

2. The method of claim 1, wherein: the second mask layer comprises, from bottom to top, a first hard mask layer, a second hard mask layer, and an anti-reflective layer; and the removing the sacrificial layer and part of the second mask layer to form the third mask layer having the preset thickness comprises: performing a thinning process on the sacrificial layer, the anti-reflective layer, and the second hard mask layer, and leaving part of the second hard mask layer to form the third mask layer.

3. The method of any one of claims 1-2, wherein: the second mask layer is formed by: sequentially forming a second initial mask layer and a patterned photoresist layer on a surface of the first mask layer, wherein the patterned photoresist layer has the initial pattern; and etching the second initial mask layer through the patterned photoresist layer to obtain the second mask layer having the initial pattern.

4. The method of claim 3, further comprising: removing the patterned photoresist layer after forming the second mask layer.

5. The method of claim 2, wherein: the initial pattern in the second mask layer exposes part of the first mask layer; and the forming the sacrificial layer covering the second mask layer comprises: depositing a sacrificial material on a surface of the exposed first mask layer and the second mask layer to form the sacrificial layer.

6. The method of claim 5, wherein: ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ An etching selectivity ratio between the sacrificial material and the first mask layer is greater than an etching selectivity ratio between the first hard mask layer and the first mask layer, and the etching selectivity ratio between the sacrificial material and the first mask layer is greater than an etching selectivity ratio between the second hard mask layer and the first mask layer.

7. The method of claim 1, wherein, the sidewall material layer comprises a first sidewall material layer and a second sidewall material layer; the forming the sidewall material layer on the exposed surface of the first mask layer and the third mask layer comprises: depositing a first sidewall material on a top and sidewall of the third mask layer and a surface of the exposed first mask layer to form the first sidewall material layer; depositing a second sidewall material on a surface of the first sidewall material layer to form the second sidewall material layer.

8. The method of claim 7, wherein, the third mask layer comprises a first hard mask layer and a partially-thickened second hard mask layer; the removing part of the sidewall material layer and part of the third mask layer to form a fourth mask layer comprises: planarizing the sidewall material layer until a top surface of the second hard mask layer is exposed; the remaining first sidewall material layer is a plurality of U-shaped structures formed by two vertical sidewalls and one horizontal sidewall; removing the vertical sidewalls in the remaining first sidewall material layer; removing the second hard mask layer and the remaining second sidewall material layer to form the fourth mask layer.

9. The method of claim 8, wherein, the fourth mask layer has a preset pattern; a pattern density of the preset pattern is greater than a pattern density of the initial pattern.

10. The method of claim 9, wherein, the forming the active region through the fourth mask layer and the first mask layer comprises: etching the first mask layer through the fourth mask layer to transfer the preset pattern to the first mask layer to obtain a patterned first mask layer; etching the semiconductor substrate through the patterned first mask layer to form the active region.

11. The method of claim 10, wherein, the method further comprises: after forming the patterned first mask layer, removing the fourth mask layer.

12. The method of claim 11, wherein, the method further comprises: after forming the active region, removing the patterned first mask layer.

13. A method for forming a semiconductor structure, comprising: providing a semiconductor substrate; forming an active region on the semiconductor substrate by the method of any one of claims 1 to 12; forming a word line intersecting the active region in a word line extension direction; forming a bit line intersecting the active region in a bit line extension direction. ​

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