A memory device and a manufacturing method thereof

Abstract

An embodiment of the present disclosure discloses a memory and a manufacturing method thereof. The memory includes: a substrate; a plurality of bit lines located on the substrate, the plurality of bit lines being parallel to each other and extending in a first direction; a plurality of active pillars located on the bit lines, and the bottom ends of the active pillars being connected to the bit lines; a plurality of word lines parallel to each other and extending in a second direction, the word lines surrounding the outer sidewalls of the active pillars, and the top ends of the active pillars being exposed outside the word lines, the active pillars and the word lines together constituting a vertical storage transistor of the memory; a plurality of capacitors and a plurality of connection pads, the capacitors being located above the active pillars, and the connection pads being located between the active pillars and the capacitors for electrically connecting the active pillars and the capacitors; wherein, the first direction and the second direction are perpendicular to each other, and the plurality of active pillars are arranged in a hexagonal array.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and more particularly to a memory and a manufacturing method thereof. Background Art

[0002] With the continuous improvement of requirements such as computing speed and computing capacity, the application side has an increasingly high requirement for the storage density of the memory. To meet the continuously growing demand for storage density on the application side, finding a memory that is conducive to integration is a problem that those skilled in the art need to solve. Summary of the Invention

[0003] In view of this, embodiments of the present disclosure provide a memory and a manufacturing method thereof to solve at least one problem in the background art.

[0004] According to a first aspect of embodiments of the present disclosure, there is provided a memory, including:

[0005] A substrate;

[0006] A plurality of bit lines located on the substrate, the plurality of bit lines being parallel to each other and extending in a first direction;

[0007] A plurality of active pillars located on the bit lines, and a bottom end portion of the active pillars being connected to the bit lines;

[0008] A plurality of word lines parallel to each other and extending in a second direction, the word lines surrounding an outer sidewall of the active pillars, and a top end of the active pillars being exposed outside the word lines, the active pillars and the word lines jointly forming a vertical storage transistor of the memory;

[0009] A plurality of capacitors and a plurality of connection pads, the capacitors being located above the active pillars, and the connection pads being located between the active pillars and the capacitors for electrically connecting the active pillars and the capacitors;

[0010] Wherein, the first direction is perpendicular to the second direction, and the plurality of active pillars are arranged in a hexagonal array.

[0011] In some embodiments, the memory further includes:

[0012] In a projection along a third direction, there is an offset between a center of the active pillar and a central axis of the bit line, and offset directions of centers of two adjacent active pillars on the same bit line with respect to the central axis of the bit line are opposite, wherein the third direction is perpendicular to the first direction and the second direction, and the central axis of the bit line is a central axis of the bit line extending in the first direction.

[0013] In some embodiments, the memory further includes:

[0014] One of the vertical storage transistors and a capacitor located on the vertical storage transistor form a storage cell, and the cell configuration size of one storage cell is 4F 2 .

[0015] In some embodiments, the memory further includes:

[0016] The multiple bit lines are arranged in parallel at equal intervals, the distance between adjacent bit lines is defined as the bit line distance, and the distance between the center of the active column and the central axis of the bit line to which it is connected is defined as the offset distance, and the offset distance is 1 / 3 to 2 / 3 of the bit line distance.

[0017] In some embodiments, the memory further includes:

[0018] A contact layer, the contact layer is located above the bit line and is electrically connected to the bit line.

[0019] In some embodiments, the memory further includes:

[0020] The connection pad includes a first connection pad extending perpendicular to the third direction and a second connection pad extending along the third direction, the first connection pad covers the top of the active column, and the second connection pad extends along the side wall of the active column; and / or,

[0021] The contact layer includes a horizontal portion extending perpendicular to the third direction and a vertical portion extending parallel to the third direction, the horizontal portion covers the top of the bit line, and the vertical portion extends along the side wall of the bit line; wherein,

[0022] The third direction is perpendicular to the first direction and the second direction.

[0023] In some embodiments, the memory further includes:

[0024] The ratio of the height of the second connection pad along the third direction to the height of the portion of the active column above the word line along the third direction is 0.5 - 0.75.

[0025] In some embodiments, the memory further includes:

[0026] The ratio of the height of the vertical portion along the third direction to the height of the bit line along the third direction is 0.6 - 0.9.

[0027] In some embodiments, the memory further includes:

[0028] The connection pad and the contact layer are made of the same material.

[0029] In some embodiments, the memory further includes:

[0030] The material of the connection pad and / or the contact layer includes metal silicide.

[0031] In some embodiments, the memory further includes:

[0032] The connection pad and / or the contact layer includes a multi-layer structure, and the materials of each layer are different.

[0033] According to a second aspect of the embodiments of the present disclosure, there is provided a method for manufacturing a memory, including:

[0034] Providing a substrate;

[0035] Forming a plurality of active pillars, the plurality of active pillars being located on the substrate and arranged in a hexagonal array;

[0036] Forming a plurality of bit lines, the bit lines extending along a first direction, and the bottom ends of the active pillars being connected to the bit lines;

[0037] Forming a connection pad, the connection pad being located on top of the active pillar and electrically connected to the active pillar;

[0038] Forming a plurality of word lines, the word lines extending along a second direction perpendicular to the first direction, the word lines surrounding the outer sidewalls of the active pillars, the top ends of the active pillars and the connection pads being exposed outside the word lines, and the active pillars and the word lines together constituting the vertical memory transistor of the memory;

[0039] Forming a plurality of capacitors, the capacitors being located above the connection pads and electrically connected to the connection pads.

[0040] In some embodiments, the method further includes:

[0041] Forming a contact layer together with the step of forming the connection pad, the contact layer being located above the bit line and electrically connected to the bit line.

[0042] In some embodiments, forming a contact layer together with the step of forming the connection pad includes:

[0043] Forming a dielectric layer on the outer sidewalls of the bit lines and the active pillars;

[0044] Removing the dielectric layer located on the tops of the active pillars and the bit lines;

[0045] Thermally oxidizing the tops of the active pillars and the bit lines to respectively form the connection pad and the contact layer.

[0046] In some embodiments, forming the plurality of word lines includes:

[0047] Fill the gap between the bit line and the active column with a lower filling material, and perform a back-etching on the lower filling material to expose the channel doping region in the active column, thereby forming a lower filling layer;

[0048] Form a word line material layer on the lower filling layer, and etch the word line material layer along a second direction to form a plurality of word lines extending along a first direction, and the word lines surround the channel doping region in the active column;

[0049] Fill the gap between the word line and the active column with an upper filling material to form an upper filling layer.

[0050] In some embodiments, after forming the connection pads, the method further includes:

[0051] Perform a heat treatment on the connection pads by using a stepped annealing or an alternating annealing.

[0052] Embodiments of the present disclosure provide a memory, including: a substrate; a plurality of bit lines located on the substrate, the plurality of bit lines being parallel to each other and extending along a first direction; a plurality of active columns located on the bit lines, and a bottom end portion of the active column being connected to the bit line; a plurality of word lines parallel to each other and extending along a second direction, the word lines surrounding an outer sidewall of the active column, and a top end of the active column being exposed outside the word line, and the active column and the word line together form a vertical storage transistor of the memory; a plurality of capacitors and a plurality of connection pads, the capacitors being located above the active columns, and the connection pads being located between the active columns and the capacitors for electrically connecting the active columns and the capacitors; wherein, the first direction and the second direction are perpendicular to each other, and the plurality of active columns are arranged in a hexagonal array. The present invention adopts a vertical storage transistor structure and arranges the vertical storage transistors in a hexagonal arrangement, which can allow the capacitors to achieve the closest hexagonal close-packed arrangement structure, thereby obtaining the largest capacitance gain. At the same time, compared with the horizontal transistor structure, the design of the vertical transistor can further reduce the occupied area of the storage unit and improve the storage density. In addition, by setting the vertical transistor, the problem of bit line (BL) / capacitor contact (NC) coupling in the traditional structure can be solved, and the whole structure is very regular, and has excellent feasibility in the manufacturing process and ideal stability.

[0053] Additional aspects and advantages of the present disclosure will be given in part in the following description, become apparent in part from the following description, or be learned through the practice of the present disclosure. Description of the Drawings

[0054] Figure 1a A top view schematic diagram of a memory according to an embodiment of the present disclosure;

[0055] Figure 1b A top view schematic diagram of the structure of a memory after stripping the capacitor and word line according to an embodiment of the present disclosure;

[0056] Figure 1c For a memory according to an embodiment of the present disclosure along Figure 1a A cross-sectional schematic diagram taken along line AA' in;

[0057] Figure 1d A top view schematic diagram of the structure of a word line in another embodiment;

[0058] Figure 1e A top view schematic diagram of an active column and a bit line;

[0059] Figure 1f For a memory according to an embodiment of the present disclosure along Figure 1e A cross-sectional schematic diagram taken along line BB' in;

[0060] Figure 1g For a memory according to an embodiment of the present disclosure along Figure 1e A cross-sectional schematic diagram taken along line CC' in;

[0061] Figure 1h A top view schematic diagram of a contact layer;

[0062] Figure 2 A flowchart of a manufacturing method of a memory according to an embodiment of the present disclosure;

[0063] Figures 3a to 3h A schematic diagram of a device structure in the preparation process of a memory provided by an embodiment of the present disclosure, where Figures 3a - 3h All the I diagrams in are cross-sectional schematic diagrams, Figures 3a - 3h All the II diagrams in are top view schematic diagrams. Detailed implementation manners

[0064] The exemplary embodiments disclosed in the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure can be more thoroughly understood and the scope of the present disclosure can be completely conveyed to those skilled in the art.

[0065] In the drawings, for clarity, the dimensions of layers, regions, elements and their relative dimensions may be exaggerated. The same reference numerals denote the same elements throughout.

[0066] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or portions, these elements, components, regions, layers and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or portion from another element, component, region, layer or portion. Thus, without departing from the teachings of the present disclosure, the first element, component, region, layer or portion discussed below may be denoted as the second element, component, region, layer or portion. And when discussing the second element, component, region, layer or portion, it does not imply that a first element, component, region, layer or portion necessarily exists in the present disclosure.

[0067] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. are used herein for convenience in describing the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientation shown in the figures, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, then an element or feature described as "under" or "beneath" or "below" other elements or features will be oriented "on" the other elements or features. Thus, the exemplary terms "under" and "below" can include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatial descriptors used herein are to be interpreted accordingly.

[0068] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of the present disclosure. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, specify the presence of the stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups. As used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0069] The present disclosure provides a memory, attached Figure 1a is a top view of the memory of the present disclosure, attached Figure 1b is a top view of the memory after stripping the capacitor, attachedFigure 1c is a vertical cross-sectional view of the memory along the AA' line in the attached Figure 1a , as shown in the attached Figures 1a - 1c , the memory includes:

[0070] Substrate 100;

[0071] Multiple bit lines 301, the multiple bit lines 301 are located on the substrate 100, and the multiple bit lines 301 are parallel to each other and extend along a first direction;

[0072] Multiple active pillars 304, the active pillars 304 are located on the bit lines 301, and the bottom ends of the active pillars 304 are connected to the bit lines 301;

[0073] Multiple word lines 302, the multiple word lines 302 are parallel to each other and extend along a second direction, the word lines 302 surround the outer sidewalls of the active pillars 304, and the top ends of the active pillars 304 are exposed outside the word lines 302 (see the attached Figure 1b ), the active pillars 304 and the word lines 302 together form the vertical memory transistors of the memory;

[0074] Multiple capacitors 303 and multiple connection pads 306, the capacitors 303 are located above the active pillars 304, and the connection pads 306 are located between the active pillars 304 and the capacitors 303 for electrically connecting the active pillars 304 and the capacitors 303;

[0075] Wherein, the first direction is perpendicular to the second direction, and the multiple active pillars 304 are arranged in a hexagonal array.

[0076] In actual operation, the substrate 100 can be, for example, a single-element semiconductor material substrate (such as a silicon (Si) substrate, a germanium (Ge) substrate, etc.), a compound semiconductor material substrate (such as a silicon germanium (SiGe) substrate, etc.), or a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc. In a specific embodiment, the substrate 101 is a silicon-on-insulator (SOI) substrate. By setting vertical transistors on the silicon-on-insulator (SOI) substrate, the capacitance of the bit lines can be reduced, thereby increasing the ratio of Cs / Cbl to improve the access degree, where Cs refers to the capacitance of a single capacitor unit; Cbl is the capacitance of the entire bit line.

[0077] In one embodiment, the bit line 301 and the active column 304 may include the same material, such as a semiconductor material, including but not limited to silicon (Si), silicon germanium (SiGe), zinc oxide (ZnO), or group III-V semiconductor materials, etc. In some embodiments, the bit line 301 may include a heavily doped region. The region where the active column 304 is surrounded and covered by the word line 302 includes a channel doping region. The upper and lower portions of the active column 304 that are not surrounded and covered by the word line 302 include source / drain doping regions. The upper and lower portions may serve as the source / drain or drain / source of a vertical transistor respectively, where the doping types of the channel doping region and the source / drain doping region are opposite. In actual operation, the bit line 301 and the active column 304 may be formed in the same semiconductor material through an etching process to achieve the connection between the bottom end of the active column 304 and the bit line 301. In other embodiments, the bit line 301 and the active column 304 may include different materials. For example, the bit line 301 and the active column 304 may include different semiconductor materials, or the bit line 301 includes a metal material and the active column 304 includes a semiconductor material. In some embodiments, there may also be a connection member between the bit line 301 and the active column 304, and the bit line 301 and the active column 304 are electrically connected through the connection member, thereby reducing the contact resistance between the bit line 301 and the active column 304.

[0078] In actual operation, the material of the word line 302 may include a conductive material, which includes but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof.

[0079] The material of the connection pad 306 may include but not limited to metal silicide. Specifically, for example, tungsten silicide, cobalt silicide, etc. By selecting a metal silicide material as the connection pad material in the embodiments of the present invention, using the resistance characteristics and high melting point characteristics of the metal silicide, it is possible to reduce the RC resistance while allowing a capacitive process that can maintain a high temperature.

[0080] In some other embodiments, the connection pad 306 may include a multi-layer structure, and the materials of each layer may be different. By setting the multi-layer structure, it is possible to flexibly adjust the resistance and melting point of the metal silicide material to obtain optimal device performance and process benignity.

[0081] In one embodiment, as Figure 1aAs shown, the capacitor 303 may include, from the inside to the outside, an inner capacitor protection layer 303-5, a capacitor upper electrode 303-4, a capacitor dielectric layer 303-3, a capacitor lower electrode 303-2, and an outer capacitor protection layer 303-1. Here, multiple capacitors 303 are arranged in a hexagonal close-packed pattern. The "hexagonal close-packed pattern" mentioned here refers to the tightest hexagonal arrangement that the capacitor 303 can achieve under the minimum limit line width size and minimum limit line pitch size that can be obtained based on the resolution of the current lithography equipment.

[0082] In one embodiment, as Figure 1c shown, the memory further includes a gate insulating layer 305. The gate insulating layer 305 covers the sidewalls of the active pillars 304 and is used to isolate the active pillars 304 from the word lines 302. The part of the word line 302 surrounding the active pillar 304 constitutes the gate of the vertical transistor. The on and off of the vertical transistor can be controlled by the control voltage applied through the word line 302. In some embodiments, the gate insulating layer 305 also covers the sidewalls of the bit lines 301 to isolate the bit lines 301 and avoid affecting the device stability such as bit line short circuits.

[0083] In one embodiment, as Figure 1c shown, the memory provided by the present invention further includes a lower filling layer 308-1 and an upper filling layer 308-2. The lower filling layer 308-1 and the upper filling layer 308-2 cover the part of the active pillar 304 not covered by the word line 302 and wrap the word line 302. The materials of the lower filling layer 308-1 and the upper filling layer 308-2 include but are not limited to silicon oxide, silicon nitride, silicon oxynitride, or polymer materials, etc. In some embodiments, the materials of the upper filling layer and the lower filling layer may be different.

[0084] In a specific embodiment, as Figure 1cAs shown, the connection pad 306 may include a first connection pad 306-1 extending perpendicular to a third direction and a second connection pad 306-2 extending parallel to the third direction, wherein the first connection pad 306-1 covers the top of the active pillar 304, and the second connection pad 306-2 extends along the side wall of the active pillar 304 and may contact the side wall of the active pillar 304, and the third direction is perpendicular to the first direction and the second direction. By providing the second connection pad 306-2 extending along the side wall of the active pillar 304, on the one hand, the contact area between the connection pad 306 and the active pillar 304 is increased, and the wrapping of the active pillar is better. In addition, the increase in the contact area between the connection pad and the active pillar can prevent the capacitor from contacting the gate insulating layer when the capacitor is subsequently formed, affecting the electrical performance, and better forming an isolation structure with the filling layer next to it. On the other hand, when the connection pad is only located at the top of the active column 304, the current flows from the connection pad through the top of the active column to the channel area in the middle of the active column. When the second connection pad 306-2 extends downward along the side wall, the current can be directly transferred to the channel area through the side wall portion through the second connection pad 306-2, shortening the current path, reducing the resistance value, and improving device performance.

[0085] In some embodiments, the ratio of the height of the second connection pad 306-2 along the third direction to the height of the portion of the active pillar 304 located above the word line along the third direction is 0.5-0.75, for example, 0.55, 0.6, 0.68. Adjacent second connection pads 306-2 and the dielectric layer or semiconductor layer located between two adjacent second connection pads 306-2 will form a large parasitic capacitance, which is not conducive to the performance of the device. When the ratio is greater than 0.75, the above parasitic capacitance is large and has a greater impact on the performance of the device. When the ratio is less than 0.5, it will be difficult to obtain the optimal effect of reducing the resistance value.

[0086] In some embodiments, the second connection pad 306-2 may be disposed only on one side of the active pillar 304. By disposing the second connection pad only on one side of the active pillar, the formation of parasitic capacitance can be reduced due to the absence of the second connection pad on the other side, which is beneficial to the electrical performance of the device.

[0087] In the attached Figures 1a - 1c In the embodiment shown, the word line 302 is formed as a whole, and the gate is formed by the portion of the word line 302 surrounding the active pillar 304. In some other embodiments, such as Figure 1dAs shown, the word line 302 can also be composed of two parts. One part is a tubular gate 302-1 that surrounds the active column 304 one by one, and the other part is a word line connection part 302-2 that connects adjacent tubular gates. A plurality of tubular gates and a plurality of word line connection parts are alternately connected and arranged along the second direction. In this embodiment, the materials of the tubular gate and the word line connection part can be different. In some embodiments, the material of the tubular gate can include, for example, a stacked structure, such as a gate work function layer and a gate conductive layer stacked in sequence. The material of the gate work function layer includes, for example, one or a combination of titanium (Ti) or titanium nitride (TiN), and the material of the gate conductive layer includes, for example, one or a combination of polysilicon (Poly) and tungsten (W).

[0088] In some embodiments, as Figure 1e shown, in the projection along the third direction, there is an offset between the center of the active column 304 and the central axis of the bit line 301, and the offset directions of the centers of two adjacent active columns on the same bit line with respect to the central axis of this bit line are opposite, where the third direction is perpendicular to the first direction and the second direction, and the central axis of the bit line 301 is the central axis of the bit line 301 extending along the first direction.

[0089] Figure 1f and Figure 1g are Figure 1e the schematic cross-sectional structures along the dotted lines BB’ and CC’ in Figures 1f - 1g shown. In some embodiments, as

[0090] shown, the offset directions of the centers of two adjacent active columns 304 on the same bit line 301 with respect to the central axis of this bit line 301 are opposite. Through the alternating offset manner of the active columns in the above solution, the hexagonal close packing of the capacitors can be achieved. 2 . Here, the unit configuration size is the size of the area occupied by a storage cell on the substrate 100. Specifically, as Figure 1e shown, the area occupied by a vertical transistor on the substrate 100 is a square with a side length of F. Since a storage cell is composed of a vertical transistor and a capacitor 303 formed on the vertical transistor, then, the occupied area of a capacitor, the occupied area of a storage cell, and the occupied area of a vertical transistor are equal, and all are the area of the square with a side length of F. Among them, "F" is the minimum limit line width size and the minimum limit line pitch size that can be obtained based on the resolution of the current lithography equipment. At this unit configuration size, the capacitors will exhibit the closest hexagonal close packing arrangement, which means that the memory can obtain the maximum storage density.

[0091] In one embodiment, as Figure 1e shown, the multiple bit lines 301 are arranged in parallel at equal intervals. The distance between adjacent bit lines 301 is defined as the bit line distance D, and the distance from the center of the active column 304 to the central axis of the bit line it is connected to is defined as the offset distance d. The offset distance d is 1 / 3 to 2 / 3 of the bit line distance D, such as 1 / 3 or 1 / 2. When this ratio is greater than 2 / 3, it will cause the width of the protrusion 309 to be too large, resulting in the distance between the protrusion 309 and the adjacent bit line 301 being too close, so that the protrusion is likely to have unnecessary short - circuit and other device stability problems with the adjacent bit line. At the same time, it also increases the difficulty of etching to prepare the bit line and the active column. In addition, when this ratio is less than 1 / 3, the width of the protrusion is too small, the area of the bit line covered by the active column increases, the space reserved for the contact layer decreases, and the resistance of the bit line will increase, affecting the device performance. By selecting the ratio of d to D within the above range in the embodiment of the present invention, the optimal bit line resistance and device stability can be obtained. In some embodiments, the offset distance d can be 1 / 2 of the bit line distance D.

[0092] In some embodiments, as Figure 1c shown, the memory provided by the present disclosure further includes: a contact layer 307, and the contact layer 307 is located above the bit line 301 and is electrically connected to the bit line. In one embodiment, the contact layer 307 extends along a first direction and is wavy. For example, Figure 1h is a top - view schematic diagram of the contact layer. As Figure 1h shown, the contact layer 307 includes a first contact portion 307 - 1 and a second contact portion 307 - 2 (as shown in the dotted box) that are alternately connected along the first direction. The width of the first contact portion 307 - 1 along the second direction is greater than the width of the second contact portion 307 - 2 along the second direction; the width of the first contact portion 307 - 1 along the second direction is equal to the width of the bit line, and the width of the second contact portion 307 - 2 along the second direction is less than the width of the bit line 301. The central axes of adjacent second contact portions 307 - 2 along the first direction do not coincide. In one embodiment, the side wall of the contact layer 307 can also be in contact with the side wall of the active column 304.

[0093] In actual operation, the material of the contact layer 307 includes but is not limited to metal silicide. Specifically, for example, tungsten silicide, cobalt silicide, etc. The high - melting - point metal silicide material can reduce the resistance of the bit line and can also allow the capacitor process to maintain high temperature. At the same time, in the embodiment where the side wall of the contact layer 307 is in contact with the side wall of the active column, the contact layer 307 is in contact with the active column 304, which can further reduce the contact resistance between the bit line 301 and the active column 304.

[0094] In some embodiments, the materials of the contact layer 307 and the connection pad 306 may be the same, which allows the contact layer 307 and the connection pad 306 to be formed simultaneously in the same step, thereby simplifying the steps and saving the process.

[0095] In some specific embodiments, Figure 1c As shown, the contact layer 307 further includes a horizontal portion 307-1 extending perpendicular to the third direction and a vertical portion 307-h extending parallel to the third direction, wherein the third direction is perpendicular to the first direction and the second direction, the horizontal portion 307-1 covers the top of the bit line, and the vertical portion 307-h extends along the side wall of the bit line. By providing the vertical portion 307-h extending along the side wall of the bit line 301, the contact area between the contact layer 307 and the bit line 301 is increased, the RC resistance is reduced, and the wrapping between the contact layer 307 and the bit line 301 is increased.

[0096] In some embodiments, the ratio of the height of the vertical portion along the third direction to the height of the bit line along the third direction is 0.6-0.9, such as 0.7 or 0.85. When the ratio is greater than 0.9, a large parasitic capacitance will be formed between the adjacent vertical portions and the dielectric layer and the semiconductor layer between the two adjacent vertical portions, which is detrimental to the performance of the device. When the ratio is less than 0.6, it will be difficult to obtain the optimal effect of reducing the contact resistance.

[0097] In some other embodiments, the contact layer 307 may include a multi-layer structure, and the material of each layer may be different. By setting the multi-layer structure, the resistance and melting point of the contact layer can be flexibly adjusted to obtain the best device performance and process quality.

[0098] The present disclosure also provides a method for manufacturing a memory, for details, see the attached Figure 2 , as shown in the figure, the method includes:

[0099] Step 501: providing a substrate;

[0100] Step 502: forming a plurality of active pillars, wherein the plurality of active pillars are located on the substrate and arranged in a hexagonal array;

[0101] Step 503: forming a plurality of bit lines, wherein the bit lines extend along a first direction, and the bottom ends of the active pillars are connected to the bit lines;

[0102] Step 504: forming a connection pad, wherein the connection pad is located on the top of the active pillar and is electrically connected to the active pillar;

[0103] Step 505: Form a plurality of word lines. The word lines extend along a second direction perpendicular to the first direction. The word lines surround the outer sidewalls of the active pillars. The top ends of the active pillars and the connection pads are exposed outside the word lines. The active pillars and the word lines together form the vertical memory transistors of the memory.

[0104] Step 506: Form a plurality of capacitors. The capacitors are located above the connection pads and are electrically connected to the connection pads.

[0105] The following further elaborates on the manufacturing method of the memory provided in the embodiments of the present disclosure in combination with specific embodiments.

[0106] Figures 3a to 3h It is a schematic cross-sectional view of the device structure during the preparation of the memory provided in the embodiments of the present disclosure.

[0107] First, perform Step 501. Refer to Figure 3a , and provide a substrate 100. The substrate 101 can be, for example, a single-element semiconductor material substrate (such as a silicon (Si) substrate, a germanium (Ge) substrate, etc.), a compound semiconductor material substrate (such as a silicon-germanium (SiGe) substrate, etc.), or a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc.

[0108] Next, perform Step 502. Refer to Figures 3a - 3b , and form a plurality of active pillars 304. The plurality of active pillars 304 are located on the substrate 100 and are arranged in a hexagonal array.

[0109] In actual operation, first, as Figure 3a shown, form a semiconductor layer 200 on the substrate 100; then, as Figure 3b shown, etch the semiconductor layer 200 to form a plurality of active pillars 304 arranged in a hexagonal array. It should be noted that this etching process stops above the bottom surface of the semiconductor layer 200, and a bottom semiconductor layer 200 with a certain thickness is reserved without being etched, serving as a bit line pre-layer 201 for subsequent formation of bit lines 301. Specifically, to etch and form a plurality of active pillars 304, a mask layer can be first formed on the semiconductor layer 200. The mask layer has, for example, a plurality of windows arranged in a hexagonal array, and then the semiconductor layer 200 is etched using this mask layer to achieve a plurality of active pillars 304 arranged in a hexagonal array.

[0110] In actual operation, the formation of the semiconductor layer 200 can adopt an in-situ doping process. While growing the semiconductor layer 200, a heavily doped region, a source doping region, a channel doping region, and a drain doping region are sequentially formed on the semiconductor layer 200 in the direction from bottom to top, or a heavily doped region, a drain doping region, a channel doping region, and a source doping region are formed. Among them, the heavily doped region, the source doping region, the channel doping region, and the drain doping region are respectively used to form the bit line 301, the source region, the channel, and the drain region.

[0111] Next, step 503 is executed. Refer to Figure 3c : Form a plurality of bit lines 301. The bit lines 301 extend along a first direction, and the bottom end of the active column 304 is connected to the bit line 301.

[0112] In actual operation, first, a bit line mask can be formed above the active column 304. Using the bit line mask as an etching mask, the bit line pre-layer 201 not covered by the bit line mask 400 is etched to form a plurality of bit lines 301 extending along the first direction below the active column 304.

[0113] Then, step 504 is executed. Refer to the appendix Figures 3d - 3f to form a connection pad 306. The connection pad 306 is located at the top of the active column 304 and is electrically connected to the active column 304.

[0114] In some embodiments, a contact layer 307 is formed together in the step of forming the connection pad. The contact layer 307 is located above the bit line 301 and is electrically connected to the bit line. By forming the connection pad and the contact layer in the same step, the process can be simplified and the cost can be saved.

[0115] In one embodiment, forming the contact layer 307 together in the step of forming the connection pad 306 includes:

[0116] Form a dielectric layer on the outer sidewalls of the bit line 301 and the active column 304;

[0117] Remove the dielectric layer located on the tops of the active column 304 and the bit line 301;

[0118] Thermally oxidize the tops of the active column 304 and the bit line 301 to respectively form the connection pad 306 and the contact layer 307.

[0119] Specifically, first, as Figure 3d shown, a gate insulating layer 305 is formed on the exposed surfaces of the active column 304 and the bit line 301; then, as Figure 3eAs shown, the gate insulating layer 305 on the upper surfaces of the active pillar 304 and the bit line 301 is removed to expose the upper surfaces of the active pillar 304 and the bit line 301; then, as Figure 3f shown, a connection pad 306 and a contact layer 307 are respectively formed on the exposed upper surface of the active pillar 304 and the upper surface of the bit line 301. The connection pad 306 is located at the top of the active pillar 304 and is electrically connected to the active pillar 304, and the contact layer 307 is located on the upper surface of the bit line 301 and is electrically connected to the bit line 301.

[0120] In actual operation, the material of the gate insulating layer 305 includes but is not limited to silicon oxide, silicon oxynitride, or High-K materials, etc. The gate insulating layer 305 can be formed by a thermal oxidation process. In addition, removing the gate insulating layer 305 on the upper surface of the active pillar 304 can be achieved by a dry etching process, such as including but not limited to reactive ion etching (RIE) and high-density plasma etching (HDP), etc.

[0121] In some embodiments, the material of the connection pad 306 and / or the contact layer 307 includes metal silicide, such as tungsten silicide or cobalt silicide, etc. In actual operation, forming the connection pad 306 and the contact layer 307 on the exposed upper surface of the active pillar 304 and the upper surface of the bit line 301 respectively includes: forming a metal material on the upper surfaces of the active pillar 304 and the bit line 301, and then performing heat treatment to make the metal material react with the materials of the active pillar 304 and the bit line 301 to generate metal silicide. Finally, the unreacted metal material is removed to form the connection pad 306 and the contact layer 307 on the upper surfaces of the active pillar 304 and the bit line 301 respectively.

[0122] In some embodiments, stepped annealing or alternating annealing is used to perform heat treatment on the connection pad and / or the contact layer. In actual operation, for stepped annealing, for example, annealing is first performed at 1200 °C, then at 1000 °C, and finally at 800 °C. Alternating annealing refers to an annealing method in which the annealing temperature is alternately changed back and forth, for example, alternately annealing back and forth at two temperatures of 1000 °C and 900 °C. By using stepped annealing or alternating annealing to perform heat treatment on the connection pad and / or the contact layer, the performance of the formed connection pad / contact layer can be made more compatible with the active pillar / bit line, and the stress problem can be alleviated.

[0123] By using a metal silicide material with a high melting point as the material of the connection pad 306 in the present invention, the capacitance and the contact resistance of the transistor can be reduced, and at the same time, a high-temperature capacitance process can be allowed to be maintained. In addition, the connection pad 306 and the contact layer 307 in the present invention are formed in the same process step, saving the process and reducing the cost.

[0124] In some embodiments, the contact layer 307 contacts the sidewall of the active column 304. The contact between the contact layer 307 and the active column 304 can further reduce the contact resistance between the bit line 301 and the active column 304.

[0125] Next, step 505 is performed. Refer to the appendix Figure 3g : Form a plurality of word lines 302. The word lines 302 extend along a second direction perpendicular to the first direction. The word lines 302 surround the outer sidewall of the active column 304. The top of the active column 304 and the connection pad 306 are exposed outside the word lines 302. The active column 304 and the word lines 302 together constitute the vertical memory transistor of the memory.

[0126] In actual operation, the gap between the bit line 301 and the active column 304 can be first filled with a bottom-fill material, and the bottom-fill material is etched until the channel doping region in the active column 304 is exposed to form a bottom-fill layer 308-1; then, a word-line material layer is formed on the bottom-fill layer, and the word-line material layer covers the channel doping region in the active column 304; then, the word-line material layer is etched along the second direction to form a plurality of word lines 302 extending along the first direction. The word lines 302 surround the channel doping region in the active column 304; finally, the gap between the word lines 302 and the active column 304 is filled with a top-fill material to form a top-fill layer 308-2, and a plurality of connection pads 306 are exposed from the surface of the top-fill layer 308-2.

[0127] Finally, as Figure 3h shown, step 506 is performed: form a plurality of capacitors 303. The capacitors 303 are located above the connection pads 306 and are electrically connected to the connection pads 306.

[0128] Appendix Figure 3h II of shows a top view of the capacitor 303. From Figure 3hIt can be seen that the capacitor 303 includes, from the inside out, an inner capacitor protection layer 303-5, a capacitor upper electrode 303-4, a capacitor dielectric layer 303-3, a capacitor lower electrode 303-2, and an outer capacitor protection layer 303-1. In actual operation, an upper stacked structure with alternating sacrificial layers and support layers can be first formed on the upper filling layer 308-2 and the connection pad 306; then, a plurality of through holes are formed, and the through holes sequentially penetrate the upper stacked structure to expose the connection pad 306; then, a capacitor lower electrode 303-2 is formed, and the capacitor lower electrode 303-2 covers the side walls and the bottom of the through holes to form a plurality of cylindrical structures; the sacrificial layer is removed, and the remaining support layer connects to the outer walls of the capacitor lower electrode cylindrical structures; after that, a capacitor dielectric layer 303-3 and a capacitor upper electrode 303-4 are sequentially formed on the inner and outer surfaces of the capacitor lower electrode 303-2. Finally, an inner capacitor protection layer 303-5 that fills the inside of the cylindrical structure formed by the capacitor upper electrode 303-4 and an outer capacitor protection layer 303-1 that covers the outer side walls of the cylindrical structures formed by the capacitor lower electrode 303-2 are formed.

[0129] After the capacitor 303 is fabricated, a filling material can also be used to fill the gaps between the capacitors and cover the top of the capacitor 303 to form a support layer in the gaps between the capacitors and a cover layer on the top of the capacitor 303.

[0130] The above fabrication method is only an example of one way to fabricate the memory provided by the embodiments of the present invention. It should be understood that the above embodiments are not the only limitation on the fabrication method of the memory provided by the present invention. In some embodiments, a plurality of active pillars are formed, and the plurality of active pillars are located on the substrate and arranged in a hexagonal array; a plurality of bit lines are formed, the bit lines extend along a first direction, and the bottom ends of the active pillars are connected to the bit lines. It can also be carried out in the following manner: a bit line material layer is formed on the substrate 100, and the bit line material layer is etched along the first direction to form a plurality of bit lines 301 extending along the first direction; the gaps between adjacent bit lines 301 are filled with a filling layer, and the tops of the bit lines 301 and the filling material are planarized so that the tops of the bit lines 301 are flush with the filling material; a sacrificial layer is formed, and the sacrificial layer is etched to form a plurality of through holes, the through holes expose a part of the bit lines 301, and the through holes are arranged in a hexagonal array; then, an active material is filled in the through holes to form the active pillars 111. Here, the formation of the active pillars can adopt an in-situ doping process, so as to form a source doping region, a channel doping region, and a drain doping region, or a drain doping region, a channel doping region, and a source doping region from the bottom to the top. In this embodiment, the sacrificial layer can then be removed; after the sacrificial layer is removed, the fabrication of the memory provided by the embodiments of the present invention can be completed by using steps 403 to 406 in the foregoing implementation manner.

[0131] In summary, the present disclosure adopts a vertical storage transistor with a vertical structure, which occupies a small area on the substrate and can suppress the short-channel effect by adjusting the height of the active pillar. At the same time, the hexagonal array arrangement of multiple active pillars can maximize the space utilization rate and arrangement density of the memory capacitor.

[0132] It should be noted that the memory and its manufacturing method provided by the embodiments of the present disclosure can be applied to any integrated circuit including this structure. Among the technical features of the technical solutions recorded in each embodiment, they can be arbitrarily combined without conflict.

[0133] The above is only a preferred embodiment of the present disclosure and is not intended to limit the protection scope of the present disclosure. Any modifications, equivalent replacements, and improvements made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A memory, characterized in that, Comprising: A substrate; Multiple bit lines located on the substrate, the multiple bit lines being parallel to each other and extending in a first direction; Multiple active pillars located on the bit lines, and the bottom ends of the active pillars being connected to the bit lines; Multiple word lines parallel to each other and extending in a second direction, the word lines surrounding the outer sidewalls of the active pillars, and the top ends of the active pillars being exposed outside the word lines, the active pillars and the word lines jointly constituting the vertical memory transistors of the memory; Multiple capacitors and multiple connection pads, the capacitors being located above the active pillars, and the connection pads being located between the active pillars and the capacitors for electrically connecting the active pillars and the capacitors; Wherein the first direction is perpendicular to the second direction, and the multiple active pillars are arranged in a hexagonal array; In a projection along a third direction, there is an offset between the center of the active pillar and the central axis of the bit line, and the offset directions of the centers of two adjacent active pillars on the same bit line with respect to the central axis of the bit line are opposite, wherein the third direction is perpendicular to the first direction and the second direction, and the central axis of the bit line is the central axis of the bit line extending along the first direction.

2. The memory according to claim 1, wherein Comprising: One of the vertical storage transistors and a capacitor located on the vertical storage transistor form a storage cell, and the cell configuration size of one of the storage cells is 4F 2 .

3. The memory according to claim 1, wherein Comprising: The multiple bit lines are arranged in parallel at equal intervals, with the distance between adjacent bit lines defined as the bit line distance, and the distance between the center of the active pillar and the central axis of the bit line to which it is connected defined as the offset distance, and the offset distance is 1 / 3 to 2 / 3 of the bit line distance.

4. The memory according to claim 1, wherein Comprising: A contact layer located above the bit line and electrically connected to the bit line.

5. The memory according to claim 4, characterized in that, Comprising: The connection pad includes a first connection pad extending perpendicular to the third direction and a second connection pad extending along the third direction, the first connection pad covering the top of the active pillar, and the second connection pad extending along the sidewall of the active pillar; And / or The contact layer includes a horizontal portion extending perpendicular to the third direction and a vertical portion extending parallel to the third direction, the horizontal portion covering the top of the bit line, and the vertical portion extending along the sidewall of the bit line; wherein The third direction is perpendicular to the first direction and the second direction.

6. The memory according to claim 5, wherein Comprising: The ratio of the height of the second connection pad along the third direction to the height of the portion of the active pillar above the word line along the third direction is 0.5 - 0.

75.

7. The memory according to claim 5, characterized in that, Comprising: The ratio of the height of the vertical portion along the third direction to the height of the bit line along the third direction is 0.6 - 0.

9.

8. The memory according to claim 4, wherein Comprising: The connection pad and the contact layer are made of the same material.

9. The memory according to claim 4, wherein Comprising: The material of the connection pad and / or the contact layer includes metal silicide.

10. The memory according to claim 4, wherein Comprising: The connection pad and / or the contact layer include a multi-layer structure, and the materials of each layer are different.

11. A manufacturing method of a memory, characterized in that, Comprising: Providing a substrate; Forming multiple active pillars located on the substrate and arranged in a hexagonal array; Forming multiple bit lines, the bit lines extending along the first direction, and the bottom ends of the active pillars being connected to the bit lines; Forming a connection pad located on the top of the active pillar and electrically connected to the active pillar; Form a plurality of word lines, which extend along a second direction perpendicular to the first direction, and the word lines surround the outer sidewall of the active column. The top end of the active column and the connection pad are exposed outside the word lines. The active column and the word lines together constitute the vertical memory transistor of the memory; Form a plurality of capacitors, which are located above the connection pad and electrically connected to the connection pad; In the projection along the third direction, there is an offset between the center of the active column and the central axis of the bit line, and the offset directions of the centers of two adjacent active columns on the same bit line with respect to the central axis of the bit line are opposite, where the third direction is perpendicular to the first direction and the second direction, and the central axis of the bit line is the central axis extending along the first direction of the bit line.

12. The method according to claim 11, wherein The method further includes: Form a contact layer together in the step of forming the connection pad, and the contact layer is located above the bit line and electrically connected to the bit line.

13. The method according to claim 12, wherein Forming a contact layer together in the step of forming the connection pad includes: Form a dielectric layer on the outer sidewall of the bit line and the active column; Remove the dielectric layer located on the tops of the active column and the bit line; Thermally oxidize the tops of the active column and the bit line to respectively form the connection pad and the contact layer.

14. The method according to claim 11, wherein The forming of the plurality of word lines includes: Fill the gap between the bit line and the active column with a bottom-fill material, and etch back the bottom-fill material to expose the channel doping region in the active column, thereby forming a bottom-fill layer; Form a word line material layer on the bottom-fill layer, and etch the word line material layer along the second direction to form a plurality of word lines extending along the first direction, and the word lines surround the channel doping region in the active column; Fill the gap between the word line and the active column with a top-fill material to form a top-fill layer.

15. The method according to claim 11, wherein After forming the connection pad, the method further includes: Perform heat treatment on the connection pad by using step annealing or alternating annealing.

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