Single polysilicon layer non-volatile memory cell and related array structure

Abstract

The present invention is a programmable and erasable single polysilicon layer non-volatile memory cell and its related array structure. In the memory cell of the array structure, the auxiliary gate region is composed of at least two plate capacitors, and one of the at least two plate capacitors is a polysilicon / polysilicon plate capacitor, and the other is a metal / polysilicon plate capacitor. The plate capacitor has simple structure and easy manufacturing process, and can effectively reduce the size of the memory cell.

Description

Technical Field

[0001] This invention relates to a nonvolatile memory, and more particularly to a nonvolatile memory cell with a programmable and erasable single polysilicon layer and its associated array structure. Background Technology

[0002] As is well known, a memory cell in non-volatile memory includes a memory cell. For example, a memory cell can be a floating-gate transistor. The storage state of the memory cell is determined by the amount of charge stored in the floating gate of the floating-gate transistor.

[0003] To be compatible with the fabrication process of traditional standard CMOS transistors, it is now possible to design single-poly floating gate transistors in the memory cells of non-volatile memory. By combining floating gate transistors with other electronic components, a single-poly nonvolatile memory cell can be formed.

[0004] US Patent 8,941,167 discloses an erasable programmable single-poly nonvolatile memory. Please refer to... Figure 1A and Figure 1B The diagram shows a top view and equivalent circuit of a conventional single-layer polysilicon non-volatile memory cell. In the following description, the single-layer polysilicon non-volatile memory cell will be simply referred to as a memory cell.

[0005] like Figure 1A As shown, the N-type well region NW1 includes three p-type doped regions 31, 32, and 33. Above the surface between the three p-type doped regions 31, 32, and 33 are two selection gates 34 and a floating gate 36, both composed of polysilicon layers. The floating gate 36 extends outward and is adjacent to the p-type doped region 48 and the n-type doped region 49, which are located within the N-type well region NW2. Additionally, the floating gate 36 is also adjacent to the n-type doped region 53.

[0006] Existing memory cells include: selection transistor M S Floating gate transistor M F p-type transistors and n-type transistors. Among them, the selector transistor M... SWith floating gate transistor M F The N-type transistor is fabricated in the N-type well region NW1, the p-type transistor is fabricated in the N-type well region NW2, and the n-type transistor is fabricated in the P-type well region PW (not shown, located below the n-type doped region 53).

[0007] Select transistor M S It consists of a p-type doped region 31, a p-type doped region 32, a select gate 34, and an N-type well region NW1. Floating gate transistor M F It consists of a p-type doped region 32, a p-type doped region 33, a floating gate 36, and an N-type well region NW1. The p-type transistor consists of a floating gate 36 and an erase gate region 45. The n-type transistor consists of a floating gate 36 and an assistant gate region 55. Furthermore, the erase gate region 45 includes an N-type well region NW2, a p-type doped region 48, and an n-type doped region 49. The assistant gate region 55 includes a p-type well region PW and an n-type doped region 53.

[0008] like Figure 1B As shown, select transistor M S The select gate 34 is connected to a select gate voltage V SG Select transistor M S The first drain / source terminal receives the source line voltage V. SL Select transistor M S The body terminal receives the N-type well voltage V. NW1 Floating gate transistor M F The first drain / source terminal is connected to the select transistor M. S The second drain / source terminal, floating gate transistor M F The second drain / source terminal receives the bit line voltage V. BL Floating gate transistor M F The body terminal receives the N-type well voltage V. NW1 .

[0009] Furthermore, the p-type doped region 48 can be considered as the two drain / source terminals of a p-type transistor connected to each other, and the body terminal of the p-type transistor receives the N-type well voltage V. NW2 In other words, p-type transistors are connected to form a metal-oxide-semiconductor capacitor (MOS capacitor). MOS1 MOS capacitor CMOS1 The first terminal is connected to the floating gate 36, and the MOS capacitor C MOS1 The second terminal receives the erase line voltage V EL .

[0010] Similarly, the n-type doped region 53 can be considered as the two drain / source terminals of an n-type transistor connected to each other, and the body terminal of the n-type transistor receives the voltage V from the P-type well region. PW In other words, the n-type transistors are connected to form a MOS capacitor C. MOS2 MOS capacitor C MOS2 The first terminal is connected to the floating gate 36, and the MOS capacitor C MOS2 The second terminal receives the auxiliary gate voltage V AG .

[0011] Furthermore, an appropriate bias voltage is provided as the selection gate voltage V. SG Source line voltage V SL Line voltage V SL ,Eliminate line voltage V EL Auxiliary gate voltage V AG N-type well voltage V NW1 N-type well voltage V NW2 P-type well voltage V PW It can perform programming, erasing, or reading operations on non-volatile memory units.

[0012] Basically, in the auxiliary gate region 55, the MOS capacitor C MOS2 The second terminal receives the auxiliary gate voltage V AG During programming, erasing, or reading operations, the auxiliary gate voltage V... AG It can be coupled to the floating gate 36 to improve the programming efficiency, erasure efficiency and read speed of the non-volatile memory cell.

[0013] In existing non-volatile memory cells, the auxiliary gate region 55 is a MOS capacitor composed of n-type transistors. This means that fabricating the auxiliary gate region 55 is complex, requiring the formation of a P-type well region PW on the semiconductor substrate and the fabrication of the n-type doped region 53. Furthermore, the existing auxiliary gate region 55 design increases the size of the non-volatile memory cell. Summary of the Invention

[0014] This invention relates to an array structure having a programmable and erasable single polysilicon layer non-volatile memory cell. The array structure is fabricated on a substrate and includes: an isolation structure formed on the substrate, dividing the substrate surface into a first region and a second region; a first well region formed below the surface of the first region; a second well region formed below the surface of the second region; a first gate structure and a second gate structure formed on the surface of the first region, the first gate structure and the second gate structure dividing the first region... The domain surface is divided into a first doped region, a second doped region, and a third doped region. The first gate structure is connected to a first select gate line. The second gate structure extends outward through the surface of the isolation structure to the second region and covers a portion of the second region. The first doped region is connected to a source line, and the third doped region is connected to a first bit line. A third gate structure is formed on the isolation structure and located on a first side of the second gate structure. A fourth doped region is formed below the surface of the second region and is connected to an erase line. A metal... A metal layer is formed above the second gate structure, and the metal layer is electrically connected to the third gate structure and connected to an auxiliary gate line; wherein the first gate structure includes a first gate oxide layer and a first polysilicon gate layer, the second gate structure includes a second gate oxide layer and a second polysilicon gate layer, and the third gate structure includes a third gate oxide layer and a third polysilicon gate layer; wherein the first doped region, the first gate structure, and the second doped region form a first select transistor; the second doped region, the second gate structure, and the third doped region form a first select transistor. A first floating gate transistor is formed; the second gate structure and the fourth doped region form a first metal-oxide-semiconductor capacitor; the second polysilicon gate layer and the third polysilicon gate layer form a first polysilicon / polysilicon parallel plate capacitor; the second polysilicon gate layer and the metal layer form a first metal / polysilicon parallel plate capacitor; wherein, a first memory cell of the array structure includes: the first selection transistor, the first floating gate transistor, the first metal-oxide-semiconductor capacitor, the first polysilicon / polysilicon parallel plate capacitor and the first metal / polysilicon parallel plate capacitor.

[0015] To provide a better understanding of the above and other aspects of the present invention, specific embodiments are described below in conjunction with the accompanying drawings: Attached Figure Description

[0016] Figure 1A and Figure 1B The top view and equivalent circuit diagram of an existing single polysilicon layer non-volatile memory cell;

[0017] Figures 2A to 2HThe fabrication process and equivalent circuit diagram of a single polysilicon layer non-volatile memory cell according to the first embodiment of the present invention are shown.

[0018] Figures 3A to 3D A bias gauge and a schematic diagram illustrating the programming, erasing and reading operations performed on the storage unit of the first embodiment of the present invention.

[0019] Figure 4A and Figure 4B This is a top view of the array structure and its equivalent circuit diagram.

[0020] Figure 5A and Figure 5B A schematic diagram of a memory cell composed of a p-type select transistor and a p-type floating gate transistor, and a bias meter for performing programming, erasing and reading operations;

[0021] Figures 6A to 6C This is a top view of the array structure composed of a single polysilicon layer non-volatile memory cell, an equivalent circuit, and the memory cell, according to the second embodiment of the present invention.

[0022] Figures 7A to 7C This is a flowchart illustrating the fabrication process of a single polysilicon layer non-volatile memory cell according to a third embodiment of the present invention; and

[0023] Figures 8A to 8C This is a flowchart illustrating the fabrication process of a single polysilicon layer non-volatile memory cell according to the fourth embodiment of the present invention.

[0024] Symbol Explanation

[0025] 31, 32, 33, 48: p-type doped regions

[0026] 34: Select Gate

[0027] 36: Floating gate

[0028] 45: Erasure gate region

[0029] 49,53: n-type doped regions

[0030] 55: Auxiliary gate region

[0031] 102, 402, 702, 802: Isolation Structure

[0032] 103, 105, 107, 109, 603, 703, 705, 707, 803, 805, 807, 809: Gate oxide layer

[0033] 113,115,117,119,423,425,427,429,443,445,447,449,452,454,456,458,613,713,715,717,813,815,817,819: Polysilicon gate layer

[0034] 123,125,127,129,623,723,725,727,823,825,827,829: Gate structure

[0035] 141, 142, 143, 145, 411, 412, 413, 414, 415, 416, 431, 432, 433, 434, 435, 504, 741, 742, 743, 745, 841, 842, 843, 845: n-type doped regions

[0036] 150, 560, 750, 850: Metal layer

[0037] 501, 502, 503: p-type doped regions Detailed Implementation

[0038] Figures 2A to 2G This describes the fabrication process of a single polysilicon layer non-volatile memory cell according to the first embodiment of the present invention. Figure 2H This is the equivalent circuit of a single polysilicon layer non-volatile memory cell according to the first embodiment of the present invention. In the following description, the single polysilicon layer non-volatile memory cell will be simply referred to as a memory cell.

[0039] like Figure 2A The diagram illustrates the steps involved in forming the isolation structure. For example, the isolation structure can be a shallow trench isolation (STI) structure. First, an isolation structure 102 is formed on a substrate (sub), and regions A and B are defined. The substrate (sub) can be a p-type semiconductor substrate, an n-type semiconductor substrate, a glass substrate, or other types of substrate. That is, the substrate (sub) is covered by the isolation structure 102, with only regions A and B exposing its surface. Essentially, in subsequent fabrication processes, region A will form two cascaded n-type transistors, and region B will form an erase gate region.

[0040] Next, the trap formation step is performed. For example... Figure 2BAs shown, region A is exposed, and a first well region formation step is performed. For example, the first well region is a P-type well region PW. Therefore, a P-type well region PW is formed below region A on the substrate sub-surface.

[0041] Of course, other well regions can also be formed below region B on the subsurface of the substrate. For example... Figure 2C As shown, it is Figure 2B A cross-sectional view along the ab direction. A second well region is formed below region B on the subsurface of the substrate. For example, the second well region can be a lightly-doped P-type well region (LPW). The first well region (PW) and the second well region (LPW) can be in contact with each other below the isolation structure 102. Of course, in other embodiments, the second well region can also be a P-type well region (PW) or an N-type well region (NW).

[0042] Figure 2D This is the gate structure formation step. Four polysilicon gate layers 113, 115, 117, and 119 are formed above the surface of the substrate sub. In this embodiment, four gate oxide layers 103, 105, 107, and 109 are formed first, and then the polysilicon gate layers 113, 115, 117, and 119 are respectively covered to form four gate structures 123, 125, 127, and 129.

[0043] exist Figure 2D In this design, two gate structures 123 and 125 are formed on the surface of region A, dividing the surface of region A into three sub-regions. One of the gate structures 125 extends outward through the surface of the isolation structure 102 to region B and covers a portion of region B. According to an embodiment of the present invention, the polysilicon gate layer 115 of the gate structure 125 covering region B is a floating gate. The polysilicon gate layer 113 in the other gate structure 123 is a select gate.

[0044] According to a first embodiment of the present invention, the other two gate structures 127 and 129 only cover the surface of the isolation structure 102. Furthermore, the two gate structures 127 and 129 are located on both sides of the gate structure 125, and the two gate structures 127 and 129 do not contact the gate structure 125.

[0045] Next, the doped region formation step is performed. For example... Figure 2EAs shown, the doping step is performed using two gate structures 123 and 125 as masks. Therefore, the three sub-regions in region A that are not covered by the two gate structures 123 and 125 form three n-type doped regions 141, 142, and 143. The portion of region B that is not covered by gate structure 125 forms one n-type doped region 145.

[0046] In region A, gate structure 123 and its two n-type doped regions 141 and 142 form a select transistor. Gate structure 125 and its two n-type doped regions 142 and 143 form a floating gate transistor. The floating gate transistor and the select transistor are n-type transistors fabricated within the P-type well region PW. That is, the body terminals of the floating gate transistor and the select transistor are connected to the P-type well region PW.

[0047] Furthermore, the n-type doped region 145 in region B is the erased gate region, and the gate structure 125 extends outward and is adjacent to the erased gate region. Therefore, the erased gate region and the gate structure 125 form an n-type transistor, and the n-type transistor is connected to form a MOS capacitor.

[0048] like Figure 2F As shown, a metal layer 150 is formed above the polysilicon gate layer 115, and the metal layer 150 does not contact the polysilicon gate layer 115. Furthermore, the metal layer 150 is electrically connected to the two polysilicon gate layers 117 and 119. Then, a wiring step is performed to complete the memory cell of the first embodiment of the present invention. That is, the n-type doped region 141 is connected to the source line SL, the n-type doped region 143 is connected to the bit line BL, the n-type doped region 145 is connected to the erase line EL, the polysilicon gate layer 113 is connected to the select gate line SG, and the metal layer 150 is connected to the auxiliary gate line AG. Additionally, according to an embodiment of the present invention, at least 50% of the polysilicon gate layer 115 overlaps with the metal layer 150. In terms of vertical projection, at least 50% of the area of ​​the polysilicon gate layer 115 overlaps with the projection of the metal layer 150.

[0049] Please refer to Figure 2G The drawing shows Figure 2FA cross-sectional view along the cd direction. According to a first embodiment of the present invention, gate structures 127 and 129 are located on the surface of isolation structure 102, and metal layer 150 is located above gate structure 125 and electrically connected to polysilicon gate layers 117 and 119. Therefore, polysilicon gate layer 115 and polysilicon gate layer 117 form a first polysilicon / polysilicon parallel plate capacitor. Polysilicon gate layer 115 and polysilicon gate layer 119 form a second polysilicon / polysilicon parallel plate capacitor. Polysilicon gate layer 115 and metal layer 150 form a metal / polysilicon parallel plate capacitor.

[0050] like Figure 2H As shown, the memory cell of the first embodiment of the present invention includes a selection transistor M. S A floating gate transistor M F A MOS capacitor C MOS First polycrystalline silicon / polycrystalline silicon parallel plate capacitor C P1 A metal / polycrystalline silicon parallel plate capacitor C P2 A second polycrystalline silicon / polycrystalline silicon parallel plate capacitor C P3 Among them, the first polycrystalline silicon / polycrystalline silicon parallel plate capacitor C P1 Metal / polycrystalline silicon parallel plate capacitor C P2 Second polycrystalline silicon / polycrystalline silicon parallel plate capacitor C P3 They are connected in parallel.

[0051] Select transistor M S The gate terminal is connected to a select gate line SG, and the select transistor M S The first drain / source terminal is connected to the source line SL. Floating gate transistor M F The first drain / source terminal is connected to the select transistor M. S The second drain / source terminal, floating gate transistor M F The second drain / source terminal is connected to the bit line BL.

[0052] Furthermore, MOS capacitor C MOS The first terminal is connected to the floating gate 115, and the MOS capacitor C MOS1 The second terminal is connected to the erase line EL. First polysilicon / polysilicon parallel plate capacitor C P1 The first terminal is connected to the floating gate 115, and the first polysilicon / polysilicon parallel plate capacitor C P1 The second terminal is connected to the auxiliary gate line AG. Metal / polysilicon parallel plate capacitor C P2The first terminal is connected to the floating gate 115, and the metal / polysilicon parallel plate capacitor C P2 The second terminal is connected to the auxiliary gate line AG. The second polysilicon / polysilicon parallel plate capacitor C... P3 The first terminal is connected to the floating gate 115, and the second polysilicon / polysilicon parallel plate capacitor C P3 The second end is connected to the auxiliary gate line AG.

[0053] As can be seen from the above description, in the memory cell of the first embodiment of the present invention, the auxiliary gate region consists of three parallel-plate capacitors C P1 C P2 C P3 Composed of. A parallel-plate capacitor C P1 C P2 C P3 It has a simple structure and is easy to manufacture. In addition, it can effectively reduce the size of storage units.

[0054] Please refer to Figures 3A to 3D The diagram shows a bias gauge and an operational schematic of the storage unit performing programming, erasing, and reading operations according to the first embodiment of the present invention.

[0055] During programming (PGM), erasing (ERS), and reading operations, the P-type well region PW and the source line SL receive a ground voltage (0V). Additionally, the auxiliary gate line voltage V... AG Greater than the erase voltage V EE , erase voltage V EE Greater than the programming voltage V PP Programming voltage V PP Greater than the reading voltage V R Read voltage V R Greater than the ground voltage (0V). For example, the auxiliary gate line voltage V AG The voltage is 15V, and the erase voltage is V. EE 12V, programming voltage V PP It is 9V, read the voltage V R It is 5V.

[0056] like Figure 3B As shown, during the programming operation, the bit line BL receives the programming voltage V. PP Select the gate line SG to receive the programming voltage V. PP The voltage received by the erase line EL can be set between the ground voltage (0V) and the erase voltage V. EE Between these two voltages, the voltage received by the auxiliary gate line AG can be set between the ground voltage (0V) and the auxiliary gate line voltage V. AG between.

[0057] When programming, select transistor M.S When the bit line BL is turned on, a programming current I is generated between the bit line BL and the source line SL. P Therefore, when the programming current I... P When hot carriers (e.g., electrons) pass through the channel region corresponding to the floating gate 115, a channel hot electron injection effect (CHE effect) is generated, causing hot carriers to be injected into the floating gate 115. The voltage received by the auxiliary gate line AG can increase the number of hot carriers injected into the floating gate 115, thereby improving programming efficiency.

[0058] According to an embodiment of the present invention, since the polysilicon gate layers 117 and 119 are formed above the isolation structure 102, a higher auxiliary gate line voltage V can be provided. AG The addition of metal layer 150 and polysilicon gate layers 117 and 119 effectively improves the voltage coupling ratio during programming. Compared with existing memory cells, the memory cell of the present invention exhibits better coupling ratio performance when the auxiliary gate region sizes of two memory cells are the same. In other words, when two memory cells have the same coupling ratio, the size of the auxiliary gate region of the memory cell of the present invention is smaller.

[0059] like Figure 3C As shown, during the erase operation, the bit line BL receives the ground voltage (0V), the select gate line SG receives the ground voltage (0V), and the erase line EL receives the erase voltage V. EE The voltage received by the auxiliary gate line AG can be set to a negative auxiliary gate line voltage -V. AG Between and ground voltage (0V).

[0060] During the erase operation, select transistor M. S Turn off. At this time, the MOS capacitor C... MOS The two ends generate an FN tunneling effect, and hot carriers are ejected from the floating gate 115 to the erase line EL. The voltage received by the auxiliary gate line AG can accelerate the exit of hot carriers from the floating gate 115, thereby improving the erase efficiency.

[0061] like Figure 3D As shown, during the read operation, the bit line BL receives the read voltage V. R The source line SL receives the ground voltage (0V), and the select gate line SG receives the read voltage V. RThe erase line EL receives the ground voltage (0V), and the voltage received by the auxiliary gate line AG can be set to the negative auxiliary gate line voltage -V. AG With auxiliary gate line voltage V AG Between. The voltage received by the auxiliary gate line AG can be appropriately adjusted to control the read current I. R Size.

[0062] During the read operation, transistor M is selected. S When the bit line BL is turned on, a read current I is generated between the bit line BL and the source line SL. R And according to the reading current I R The size of the current determines the storage state of the memory cell. For example, when electrons are stored in the floating gate 115, the read current I... R Very small, almost zero, the visible memory cell is in its first storage state. When no electrons are stored in the floating gate 115, the read current I... R The size is relatively large, and the visible storage unit is in the second storage state.

[0063] Furthermore, multiple storage units from the first embodiment can be combined to form an array structure.

[0064] Please refer to Figure 4A and Figure 4B The diagram shows a top view of the array structure and its equivalent circuit. The array structure consists of 2×2 memory cells and is connected to the source line SL, select gate lines SG1 and SG2, bit lines BL1 and BL2, erase line EL, and auxiliary gate line AG. The array structure includes: an isolation structure 402, n-type doped regions 411, 412, 413, 414, 415, 416, 431, 432, 433, 434, and 435, polysilicon gate layers 423, 425, 427, 429, 443, 445, 447, 449, 452, 454, 456, and 458, and a metal layer 560 (diagonally lined area).

[0065] Because the structure of each storage unit is similar to Figure 2F The following only describes memory cell c11; the other memory cells will not be described in detail. In memory cell c11, n-type doped regions 411 and 412 and polysilicon gate layer 423 form a selection transistor; n-type doped regions 412 and 413 and polysilicon gate layer 425 form a floating gate transistor; polysilicon gate layer 425 and n-type doped region 416 form an n-type transistor and are connected to form a MOS capacitor; polysilicon gate layer 425 and polysilicon gate layer 454 form a first polysilicon / polysilicon parallel plate capacitor; polysilicon gate layer 425 and polysilicon gate layer 452 form a second polysilicon / polysilicon parallel plate capacitor; polysilicon gate layer 425 and metal layer 560 form a metal / polysilicon parallel plate capacitor.

[0066] Furthermore, n-type doped region 411 is connected to source line SL, n-type doped region 413 is connected to bit line BL, polysilicon gate layer 423 is connected to select gate line SG, n-type doped region 416 is connected to erase line EL, metal layer 560 is connected to polysilicon gate layers 452 and 454, and metal layer 560 is connected to auxiliary gate line AG.

[0067] like Figure 4B The equivalent circuit of the array structure is shown below. The array structure consists of 2×2 memory cells c11 to c22. Since the structure of each memory cell c11 to c22 is similar, only memory cell c11 will be described below, and the other memory cells will not be described in detail. In addition, since the first polysilicon / polysilicon parallel plate capacitor, the second polysilicon / polysilicon parallel plate capacitor, and the metal / polysilicon parallel plate capacitor in memory cell c11 are connected in parallel, the equivalent parallel plate capacitor C is used. Pth To express.

[0068] In memory cell C11, select transistor M S The first drain / source terminal is connected to the source line SL, selecting transistor M. S The gate terminal is connected to the select gate line SG1, and the floating gate transistor M F The first drain / source terminal is connected to the select transistor M. S The second drain / source terminal, floating gate transistor M F The second drain / source terminal is connected to the bit line BL, and the MOS capacitor C MOS The first terminal is connected to the floating gate transistor M F Floating gate, MOS capacitor C MOS The second terminal is connected to the erase line EL, equivalent to a parallel plate capacitor C. Pth The first terminal is connected to the floating gate transistor M F The floating gate, the equivalent parallel plate capacitor C Pth The second end is connected to the auxiliary gate line AG.

[0069] Similarly, appropriate bias is provided to the source line SL, and gate lines SG1 and SG2, bit lines BL1 and BL2, erase line EL, and auxiliary gate line AG are selected. Programming, erasing, and reading operations can be performed on memory cells c11 to c22 in the array structure. Further details are omitted here.

[0070] Furthermore, in the memory cell of the first embodiment of the present invention, the selection transistor and the floating gate transistor are implemented using n-type transistors. Of course, the present invention is not limited thereto. Those skilled in the art can, based on the disclosure of the first embodiment, use p-type selection transistors and p-type floating gate transistors to replace the n-type selection transistors and n-type floating gate transistors, and complete the memory cell and array structure of the present invention.

[0071] Please refer to Figure 5A The diagram illustrates a memory cell composed of a p-type select transistor and a p-type floating gate transistor. The structure of the memory cell is similar to... Figure 2E Similarly, the p-type select transistor and the p-type floating gate transistor form the first well region of the substrate sub, and p-type doped regions 501, 502, and 503 are formed in the first well region. The first well region can be an N-type well region NW. Additionally, a second well region (not shown) can be formed below region B on the surface of the substrate sub, and an n-type doped region 504 is formed in the second well region. For example, the second well region can be an N-type well region NW, a lightly-doped P-type well region LPW, or a P-type well region PW. It is noteworthy that when the second well region is a lightly-doped P-type well region LPW or a P-type well region PW, the first and second well regions do not contact each other below the isolation structure.

[0072] Please refer to Figure 5B The diagram illustrates a bias table for programming, erasing, and reading operations of a memory cell in the first embodiment composed of p-type transistors. The auxiliary gate line voltage V... AG Greater than the erase voltage V EE , erase voltage V EE Greater than the programming voltage V PP Programming voltage V PP Greater than the reading voltage V R Read voltage V R The voltage is greater than the ground voltage (0V). Basically, the operation of the memory cell composed of p-type transistors during programming (PGM), erasing (ERS), and reading operations is similar to that of the first embodiment, and will not be described again here.

[0073] Furthermore, the storage unit in the first embodiment of the present invention can be appropriately modified to reduce the size of the storage unit or to achieve a better layout design. Please refer to... Figure 6A The illustration shows a single polysilicon layer non-volatile memory cell according to the second embodiment of the present invention.

[0074] The storage unit in the second embodiment is modified. Figure 2EThe first embodiment memory cell contains gate structures 123 and 129. That is, the second embodiment memory cell removes gate structure 129 from the first embodiment memory cell and extends gate structure 123. In other words, in the second embodiment memory cell, the gate structure 623, composed of gate oxide layer 603 and polysilicon gate layer 613, extends from region A to another adjacent memory cell (not shown). Apart from this, the other structures of the second embodiment memory cell are the same as those of the first embodiment memory cell, and will not be described further here.

[0075] Therefore, in the memory cell of the second embodiment, the polysilicon gate layer 115 and the polysilicon gate layer 117 form a polysilicon / polysilicon parallel plate capacitor. The polysilicon gate layer 115 and the metal layer 150 form a metal / polysilicon parallel plate capacitor.

[0076] like Figure 6B The equivalent circuit of the memory cell is shown. Compared to Figure 2G The equivalent circuit of the memory cell in the second embodiment shows that the memory cell has only two parallel parallel-plate capacitors C. P1 C P2 Parallel connection. The following only describes the connection relationship between two parallel-plate capacitors; other connections will not be elaborated upon.

[0077] Polycrystalline silicon / polycrystalline silicon parallel plate capacitor C P1 The first terminal is connected to the floating gate 115, polysilicon / polysilicon parallel plate capacitor C P1 The second terminal is connected to the auxiliary gate line AG. Metal / polysilicon parallel plate capacitor C P2 The first terminal is connected to the floating gate 115, and the metal / polysilicon parallel plate capacitor C P2 The second end is connected to the auxiliary gate line AG.

[0078] As can be seen from the above description, in the memory cell of the second embodiment of the present invention, the auxiliary gate region consists of two parallel plate capacitors C P1 C P2 Composed of. A parallel-plate capacitor C P1 C P2 It has a simple structure, is easy to manufacture, and can effectively reduce the size of storage units.

[0079] Similarly, according to Figure 3A The bias gauge can also perform programming, erasing, and reading operations on the memory cells of the second embodiment. Furthermore, in addition to n-type transistors, the memory cells of the second embodiment can also be composed of p-type transistors, and according to... Figure 5B The bias gauge is used to perform various operations. Similarly, multiple memory cells of the second embodiment can also be arranged into an array structure and perform various operations.

[0080] Please refer to Figure 6C The diagram shows a top view of an array structure composed of memory cells according to a second embodiment of the present invention. This array structure consists of 2×2 memory cells. In this array structure, the selection transistors of memory cell c11 and memory cell c21 share the polysilicon gate layer 613 of the gate structure 623. Apart from this, the other parts of the array structure are similar to... Figure 4A This will not be elaborated upon here.

[0081] Figures 7A to 7C This describes the fabrication process of a single polysilicon layer non-volatile memory cell according to the third embodiment of the present invention. Compared to the memory cell of the first embodiment, the memory cell of the third embodiment has an L-shaped floating gate. Similar to the previous embodiments, the memory cell of the third embodiment can improve the coupling rate during programming operations.

[0082] like Figure 7A As shown, an isolation structure 702 is formed on the substrate sub, defining regions A and B. That is, the substrate sub is covered by the isolation structure 702, with only regions A and B exposing the surface of the substrate sub. Next, a well region formation step is performed, forming a first well region, such as a P-type well region PW, below region A on the surface of the substrate sub. Alternatively, a second well region can be formed below region B on the surface of the substrate sub. The second well region can be a lightly doped P-type well region LPW, a P-type well region PW, or an N-type well region NW.

[0083] Figure 7B As shown, three gate oxide layers 703, 705, and 707 are first formed on the surface of the substrate sub. Then, polysilicon gate layers 713, 715, and 717 are formed to cover the three gate oxide layers 703, 705, and 707, respectively, thus forming three gate structures 723, 725, and 727.

[0084] exist Figure 7B In this design, two gate structures 723 and 725 are formed on the surface of region A, dividing the surface of region A into three sub-regions. One of the gate structures 725 has an L-shape. The L-shaped gate structure 725 bends to the left (first side), so the gate structure 725 does not contact the gate structure 727 on the right (second side). That is, the gate structure 725 extends outward through the surface of the isolation structure 702 to region B and covers a portion of region B. Furthermore, the gate structure 727 only covers the surface of the isolation structure 702 and is located on the second side of the gate structure 725.

[0085] Next, the substrate sub-surface is doped using the two gate structures 723 and 725 as masks. Therefore, the three sub-regions in region A not covered by the two gate structures 723 and 725 form three n-type doped regions 741, 742, and 743. The portion of region B not covered by the gate structure 725 forms one n-type doped region 745.

[0086] In region A, gate structure 723 and its two n-type doped regions 741 and 742 form a select transistor. Gate structure 725 and its two n-type doped regions 742 and 743 form a floating gate transistor. The floating gate transistor and the select transistor are n-type transistors fabricated within the P-type well region PW. That is, the body terminals of the floating gate transistor and the select transistor are connected to the P-type well region PW.

[0087] Furthermore, the n-type doped region 745 in region B is the erased gate region, and the gate structure 725 extends outward and is adjacent to the erased gate region. Therefore, the erased gate region and the gate structure 725 form an n-type transistor, and the n-type transistor is connected to form a MOS capacitor.

[0088] like Figure 7C As shown, a metal layer 750 is formed above the polysilicon gate layer 715, and at least 50% of the polysilicon gate layer 715 overlaps with the metal layer 750. Furthermore, the metal layer 750 is electrically connected to the polysilicon gate layer 717. Afterwards, a wiring step is performed to complete the memory cell of the third embodiment of the present invention. That is, the n-type doped region 741 is connected to the source line SL, the n-type doped region 743 is connected to the bit line BL, the n-type doped region 745 is connected to the erase line EL, the polysilicon gate layer 713 is connected to the select gate line SG, and the metal layer 750 is connected to the auxiliary gate line AG.

[0089] In a third embodiment of the present invention, the gate structure 727 is located on the surface of the isolation structure 702, and the metal layer 750 is located above the gate structure 725. Therefore, the polysilicon gate layer 715 and the polysilicon gate layer 717 form a first polysilicon / polysilicon parallel-plate capacitor. The polysilicon gate layer 715 and the metal layer 750 form a metal / polysilicon parallel-plate capacitor.

[0090] As can be seen from the above description, in the memory cell of the third embodiment of the present invention, the auxiliary gate region is composed of two parallel-plate capacitors, and its equivalent circuit is the same as that of... Figure 6B Similarly, according to Figure 3A The bias gauge can also perform programming, erasing, and reading operations on the memory cells of the third embodiment. Furthermore, in addition to n-type transistors, the memory cells of the third embodiment can also be composed of p-type transistors, and according to... Figure 5B The bias gauge is used to perform various operations. Similarly, multiple memory cells of the third embodiment can also be arranged into an array structure and perform various operations.

[0091] Figures 8A to 8C This describes the fabrication process of a single polysilicon layer non-volatile memory cell according to the fourth embodiment of the present invention. Similar to the memory cell in the third embodiment, the memory cell in the fourth embodiment of the present invention has an L-shaped floating gate.

[0092] like Figure 8A As shown, an isolation structure 802 is formed on the substrate sub, defining regions A and B. That is, the substrate sub is covered by the isolation structure 802, with only regions A and B exposing the surface of the substrate sub. Next, a well region formation step is performed, forming a first well region, such as a P-type well region PW, below region A on the surface of the substrate sub. Alternatively, a second well region can be formed below region B on the surface of the substrate sub. The second well region can be a lightly doped P-type well region LPW, a P-type well region PW, or an N-type well region NW.

[0093] Figure 8B As shown, four gate oxide layers 803, 805, 807, and 809 are first formed on the surface of the substrate sub. Then, polysilicon gate layers 813, 815, 817, and 819 are formed to cover the four gate oxide layers 803, 805, 807, and 809, respectively, thus forming four gate structures 823, 825, 827, and 829.

[0094] exist Figure 8B In this design, two gate structures 823 and 825 are formed on the surface of region A, dividing the surface of region A into three sub-regions. One of the gate structures 825 has an L-shape, extending outward through the surface of the isolation structure 802 to region B and covering a portion of region B. Furthermore, gate structures 827 and 829 only cover the surface of the isolation structure 802, located on opposite sides of the gate structure 825, and do not contact the gate structure 825.

[0095] Next, the substrate sub-surface is doped using the two gate structures 823 and 825 as masks. Therefore, the three sub-regions in region A not covered by the two gate structures 823 and 825 form three n-type doped regions 841, 842, and 843. The portion of region B not covered by the gate structure 825 forms one n-type doped region 845.

[0096] In region A, gate structure 823 and its two n-type doped regions 841 and 842 form a select transistor. Gate structure 825 and its two n-type doped regions 842 and 843 form a floating gate transistor. The floating gate transistor and the select transistor are n-type transistors fabricated within the P-type well region PW. That is, the body terminals of the floating gate transistor and the select transistor are connected to the P-type well region PW.

[0097] Furthermore, the n-type doped region 845 in region B is the erased gate region, and the gate structure 825 extends outward and is adjacent to the erased gate region. Therefore, the erased gate region and the gate structure 825 form an n-type transistor, and the n-type transistor is connected to form a MOS capacitor.

[0098] like Figure 8C As shown, a metal layer 850 is formed above the polysilicon gate layer 815, and at least 50% of the polysilicon gate layer 815 overlaps with the metal layer 850. The metal layer 850 is electrically connected to the polysilicon gate layers 817 and 819. Then, a wiring step is performed to complete the memory cell of the fourth embodiment of the present invention. That is, the n-type doped region 841 is connected to the source line SL, the n-type doped region 843 is connected to the bit line BL, the n-type doped region 845 is connected to the erase line EL, the polysilicon gate layer 813 is connected to the select gate line SG, and the metal layer 850 is connected to the auxiliary gate line AG.

[0099] In the fourth embodiment of the present invention, gate structures 827 and 829 are located on the surface of isolation structure 802, and metal layer 850 is located above gate structure 825. Therefore, polysilicon gate layer 815 and polysilicon gate layer 817 form a first polysilicon / polyplate capacitor. Polysilicon gate layer 815 and polysilicon gate layer 819 form a second polysilicon / polyplate capacitor. Polysilicon gate layer 815 and metal layer 850 form a metal / polysilicon plate capacitor.

[0100] As can be seen from the above description, in the memory cell of the fourth embodiment of the present invention, the auxiliary gate region is composed of three parallel-plate capacitors, and its equivalent circuit is the same as that of... Figure 6B Similarly, according to Figure 3A The bias gauge can also perform programming, erasing, and reading operations on the memory cell of the fourth embodiment. Furthermore, in addition to n-type transistors, the memory cell of the fourth embodiment can also be composed of p-type transistors, and according to... Figure 5B The bias gauge is used to perform various operations. Similarly, multiple memory cells of the fourth embodiment can also be arranged into an array structure and perform various operations.

[0101] As described above, this invention proposes a programmable and erasable single polysilicon layer non-volatile memory cell and its related array structure. In the memory cell of the array structure, the auxiliary gate region is composed of at least two parallel-plate capacitors, one of which is a polysilicon / polysilicon parallel-plate capacitor, and the other is a metal / polysilicon parallel-plate capacitor. Because parallel-plate capacitors are simple to construct and easy to manufacture, the size of the memory cell can be effectively reduced.

[0102] In summary, although the present invention has been disclosed in conjunction with the above embodiments, it is not intended to limit the invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be defined by the appended claims.

Claims

1. An array structure of programmable and erasable single polysilicon layer nonvolatile memory cells fabricated on a substrate, the array structure comprising: an isolation structure formed on the substrate, and the isolation structure divides a surface of the substrate into a first region and a second region; a first well region formed under a surface of the first region of the substrate; a second well region formed under a surface of the second region of the substrate; a first gate structure and a second gate structure formed on the surface of the first region, and the first gate structure and the second gate structure divide the surface of the first region into a first doped region, a second doped region and a third doped region, wherein the first gate structure is connected to a first select gate line, the second gate structure extends outwardly through a surface of the isolation structure and to the second region and covers a portion of the second region, the first doped region is connected to a source line, and the third doped region is connected to a first bit line; a third gate structure formed only on the isolation structure, and the third gate structure is located at a first side of the second gate structure, the third gate structure does not contact the second gate structure; a fourth doped region formed under a surface of the second region, and the fourth doped region is connected to an erase line; and a metal layer formed above the second gate structure, and the metal layer is electrically connected to the third gate structure, and the metal layer is connected to an auxiliary gate line; wherein the first gate structure comprises a first gate oxide layer and a first polysilicon gate layer, the second gate structure comprises a second gate oxide layer and a second polysilicon gate layer, and the third gate structure comprises a third gate oxide layer and a third polysilicon gate layer; wherein the first doped region, the first gate structure and the second doped region form a first select transistor, the second doped region, the second gate structure and the third doped region form a first floating gate transistor, the second gate structure and the fourth doped region form a first metal oxide semiconductor capacitor, the second polysilicon gate layer and the third polysilicon gate layer form a first polysilicon / polysilicon plate capacitor, and the second polysilicon gate layer and the metal layer form a first metal / polysilicon plate capacitor; wherein a first memory cell of the array structure comprises the first select transistor, the first floating gate transistor, the first metal oxide semiconductor capacitor, the first polysilicon / polysilicon plate capacitor and the first metal / polysilicon plate capacitor. ​ 2. The array structure of claim 1, wherein in the first memory cell, a gate terminal of the first select transistor is connected to the first select gate line, a first drain / source terminal of the first select transistor is connected to the source line, a first drain / source terminal of the first floating gate transistor is connected to a second drain / source terminal of the first select transistor, a second drain / source terminal of the first floating gate transistor is connected to the first bit line, a first terminal of the first metal oxide semiconductor capacitor is connected to a floating gate of the first floating gate transistor, a second terminal of the first metal oxide semiconductor capacitor is connected to the erase line, a first terminal of the first polysilicon / polysilicon plate capacitor is connected to the floating gate of the first floating gate transistor, a second terminal of the first polysilicon / polysilicon plate capacitor is connected to the auxiliary gate line, a first terminal of the first metal / polysilicon plate capacitor is connected to the floating gate of the first floating gate transistor, and a second terminal of the first metal / polysilicon plate capacitor is connected to the auxiliary gate line.

3. The array structure of claim 2, further comprising a second storage unit comprising: a second select transistor, a second floating gate transistor, a second metal oxide semiconductor capacitor, a second polysilicon / polysilicon plate capacitor, and a second metal / polysilicon plate capacitor, wherein the first select transistor and the second select transistor share the first polysilicon gate layer.

4. The array structure of claim 1, further comprising a fourth gate structure formed on the isolation structure, the fourth gate structure being located on a second side of the second gate structure, the fourth gate structure comprising a fourth gate oxide layer and a fourth polysilicon gate layer, the second polysilicon gate layer and the fourth polysilicon gate layer forming a second polysilicon / polysilicon plate capacitor.

5. The array structure of claim 4, wherein in the first memory cell, the first select transistor, the first floating gate transistor, the first metal oxide semiconductor capacitor, the first polysilicon / polysilicon plate capacitor, the first metal / polysilicon plate capacitor, the second polysilicon / polysilicon plate capacitor, and the second metal / polysilicon plate capacitor, wherein the first select transistor and the second select transistor share the first polysilicon gate layer.

6. The array structure of claim 5, further comprising a second memory cell, the second memory cell comprising: a second select transistor, a second floating gate transistor, a second metal oxide semiconductor capacitor, a third polysilicon / polysilicon plate capacitor, a second metal / polysilicon plate capacitor, and a fourth polysilicon / polysilicon plate capacitor.

7. The array structure of claim 6, wherein a gate terminal of the second select transistor is connected to a second select gate line, a first drain / source terminal of the second select transistor is connected to the source line, a first drain / source terminal of the second floating gate transistor is connected to a second drain / source terminal of the second select transistor, a second drain / source terminal of the second floating gate transistor is connected to the first bit line, a first terminal of the second metal oxide semiconductor capacitor is connected to a floating gate of the second floating gate transistor, a second terminal of the second metal oxide semiconductor capacitor is connected to the erase line, a first terminal of the third polysilicon / polysilicon plate capacitor is connected to the floating gate of the second floating gate transistor, a second terminal of the third polysilicon / polysilicon plate capacitor is connected to the auxiliary gate line, a first terminal of the second metal / polysilicon plate capacitor is connected to the floating gate of the second floating gate transistor, a second terminal of the second metal / polysilicon plate capacitor is connected to the auxiliary gate line, a first terminal of the fourth polysilicon / polysilicon plate capacitor is connected to the floating gate of the second floating gate transistor, and a second terminal of the fourth polysilicon / polysilicon plate capacitor is connected to the auxiliary gate line.

8. The array structure of claim 6, wherein a gate terminal of the second select transistor is connected to the first select gate line, a first drain / source terminal of the second select transistor is connected to the source line, a first drain / source terminal of the second floating gate transistor is connected to a second drain / source terminal of the second select transistor, a second drain / source terminal of the second floating gate transistor is connected to a second bit line, a first terminal of the second metal oxide semiconductor capacitor is connected to a floating gate of the second floating gate transistor, a second terminal of the second metal oxide semiconductor capacitor is connected to the erase line, a first terminal of the third polysilicon / polysilicon plate capacitor is connected to the floating gate of the second floating gate transistor, a second terminal of the third polysilicon / polysilicon plate capacitor is connected to the auxiliary gate line, a first terminal of the second metal / polysilicon plate capacitor is connected to the floating gate of the second floating gate transistor, a second terminal of the second metal / polysilicon plate capacitor is connected to the auxiliary gate line, a first terminal of the fourth polysilicon / polysilicon plate capacitor is connected to the floating gate of the second floating gate transistor, and a second terminal of the fourth polysilicon / polysilicon plate capacitor is connected to the auxiliary gate line.

9. The array structure of claim 1, wherein the second gate structure is an L-shaped gate structure.

10. The array structure of claim 1, wherein the first select transistor and the first floating gate transistor are n-type transistors.

11. The array structure of claim 10, wherein during a program operation, the source line receives a ground voltage, the first select gate line receives a program voltage, the first bit line receives the program voltage, the erase line receives a first voltage ranging between the ground voltage and an erase voltage, the auxiliary gate receives a second voltage ranging between the ground voltage and an auxiliary gate voltage, the auxiliary gate voltage being greater than the erase voltage, the erase voltage being greater than the program voltage, the program voltage being greater than the ground voltage.

12. The array structure of claim 10, wherein during an erase operation, the source line receives a ground voltage, the first select gate line receives the ground voltage, the first bit line receives the ground voltage, the erase line receives an erase voltage, the auxiliary gate receives a voltage ranging between a negative auxiliary gate voltage and the ground voltage, the auxiliary voltage being greater than the erase voltage, the erase voltage being greater than the ground voltage.

13. The array structure of claim 10, wherein during a read operation, the source line receives a ground voltage, the first select gate line receives a read voltage, the first bit line receives the read voltage, the erase line receives the ground voltage, the auxiliary gate receives a voltage ranging between a negative auxiliary gate voltage and a positive auxiliary gate voltage, the auxiliary gate voltage being greater than the read voltage, the read voltage being greater than the ground voltage.

Images