Thin film capacitor, method for manufacturing the same, and electronic circuit substrate having the thin film capacitor

Abstract

The present application provides a thin film capacitor which is less likely to cause short circuit failure. A thin film capacitor (1) includes a metal foil (10) whose upper surface (11) is roughened; a dielectric film (D) which covers the upper surface (11) of the metal foil (10) and has an opening portion which partially exposes the metal foil (10); a first electrode layer which is in contact with the metal foil (10) via the opening portion; a second electrode layer which is in contact with the dielectric film (D) without being in contact with the metal foil (10); and an insulating member (21) which separates the first electrode layer and the second electrode layer. A cross section of the insulating member (21) has a tapered shape. Thus, both the first and second electrode layers can be arranged on the upper surface (11) of the metal foil (10). Furthermore, the cross section of the insulating member (21) has a tapered shape, so that the adhesion of the insulating member (21) can be improved, and short circuit between the first electrode layer and the second electrode layer can be prevented.

Description

TECHNICAL FIELD

[0001] The present application relates to a thin film capacitor and a manufacturing method thereof, particularly to a thin film capacitor using a metal foil and a manufacturing method thereof. The present application also relates to an electronic circuit board provided with such a thin film capacitor. BACKGROUND

[0002] In a circuit board on which an IC is mounted, in order to stabilize the potential of a power supply supplied to the IC, a decoupling capacitor is generally mounted. As the decoupling capacitor, a multilayer ceramic chip capacitor is generally used, and a plurality of multilayer ceramic chip capacitors are mounted on the surface of the circuit board, whereby a necessary decoupling capacity is ensured.

[0003] In recent years, circuit boards are being miniaturized, and therefore, there are cases where there is insufficient space for mounting a plurality of multilayer ceramic chip capacitors. Therefore, a thin film capacitor which can be embedded in a circuit board is sometimes used instead of a multilayer ceramic chip capacitor (see Patent Documents 1 to 4).

[0004] The thin film capacitor described in Patent Document 1 has a structure in which a porous metal substrate is used, and an upper electrode is formed on the surface thereof via a dielectric film. The thin film capacitor described in Patent Document 2 has a structure in which a metal substrate in which one main surface is roughened is used, and an upper electrode is formed on the roughened surface via a dielectric film. The thin film capacitors described in Patent Documents 3 and 4 have a structure in which a conductive porous substrate is formed on a support portion, and an upper electrode is formed on the roughened surface via a dielectric film.

[0005] PRIOR ART DOCUMENTS

[0006] PATENT DOCUMENTS

[0007] Patent Document 1: International Publication No. WO2015-118901

[0008] Patent Document 2: International Publication No. WO2018-092722

[0009] Patent Document 3: International Publication No. WO2017-026247

[0010] Patent Document 4: International Publication No. WO2017-014020 SUMMARY

[0011] PROBLEMS TO BE SOLVED BY THE INVENTION

[0012] However, the thin film capacitor described in Patent Document 1 has a side electrode structure, and thus the line length of the electrode is long, and thus has a problem in structure in which ESR (equivalent series resistance) and ESL (equivalent series inductance) become large. Also, the thin film capacitor described in Patent Document 1 uses a metal base material that is entirely porous, and thus the lower electrode composed of the metal base material and the upper electrode that covers the metal base material via the dielectric film are not easily separated, and thus has a problem in which short circuit failure easily occurs. In addition, the thin film capacitor described in Patent Document 2 has a structure in which one main surface of the metal base material functions as the upper electrode and the other main surface functions as the lower electrode, and in order to arrange the pair of terminal electrodes on the same surface, the electrode needs to be drawn back via the side surface of the [0] element, and thus has a problem in which the structure is complicated. In addition, the thin film capacitors described in Patent Documents 3 and 4 have a structure in which the pair of terminal electrodes are arranged on both surfaces of the metal base material, and thus the pair of terminal electrodes cannot be accessed from one side. Also, since a support body is used, the entire thickness becomes thick.

[0013] Therefore, an object of the present application is to provide an improved thin film capacitor and a manufacturing method thereof. In addition, an object of the present application is to provide an electronic circuit substrate provided with the thin film capacitor.

[0014] Technical Solution for Solving the Problem

[0015] The present application provides a thin film capacitor including a metal foil having one main surface roughened, a dielectric film covering the one main surface of the metal foil and having an opening portion exposing the metal foil partially, a first electrode layer connected to the metal foil via the opening portion, a second electrode layer connected to the dielectric film without being connected to the metal foil, and a first insulating member partitioning the first electrode layer and the second electrode layer, the first insulating member having a tapered shape in which a width thereof becomes narrower as it is away from the one main surface of the metal foil.

[0016] The present application provides a manufacturing method of a thin film capacitor including roughening one main surface of a metal foil, forming a dielectric film on the roughened one main surface of the metal foil, exposing a part of the metal foil by removing a part of the dielectric film, forming a first insulating member having a tapered shape in which a width thereof becomes narrower as it is away from the one main surface of the metal foil on the dielectric film, and forming a first electrode layer connected to the part of the metal foil and a second electrode layer connected to the dielectric film without being connected to the part of the metal foil, which are partitioned by the first insulating member.

[0017] Effects of the Invention

[0018] According to the present application, an opening portion is provided in a part of the dielectric film, and thus a pair of terminal electrodes can be arranged on the same surface without using side electrodes and the like. Further, the first insulating member has a tapered shape in cross section, and thus the adhesion of the first insulating member can be improved, and short-circuiting of the first electrode layer and the second electrode layer can be prevented. BRIEF DESCRIPTION OF DRAWINGS

[0019] Figure 1A is a cross-sectional view for explaining the structure of a thin film capacitor 1 according to an embodiment of the present application, Figure 1B is a plan view of the thin film capacitor 1.

[0020] Figure 1B is a plan view of the thin film capacitor 1.

[0021] Figure 1C is a cross-sectional view for explaining an example in which the conductive member 32 is omitted from the thin film capacitor 1.

[0022] Figure 1D is a plan view of the thin film capacitor 1. Figure 1C

[0023] Figure 2 is a cross-sectional view for explaining the shape of a side surface 13 of the thin film capacitor 1.

[0024] Figure 3 is a process diagram for explaining a manufacturing method of the thin film capacitor 1.

[0025] Figure 4 is a process diagram for explaining a manufacturing method of the thin film capacitor 1.

[0026] Figure 5A is a process diagram for explaining a manufacturing method of the thin film capacitor 1.

[0027] Figure 5B is a process diagram for explaining a manufacturing method of the thin film capacitor 1.

[0028] Figure 6 is a process diagram for explaining a manufacturing method of the thin film capacitor 1.

[0029] Figure 7A is a process diagram for explaining a manufacturing method of the thin film capacitor 1.

[0030] Figure 7B is a plan view of the thin film capacitor 1. Figure 7A

[0031] Figure 8A is a process diagram for explaining a manufacturing method of the thin film capacitor 1.

[0032] Figure 8B is a process diagram for explaining a manufacturing method of the thin film capacitor 1.​​Figure 8A A rough top view.

[0033] Figure 9 This is a process diagram illustrating the manufacturing method of film capacitor 1.

[0034] Figure 10 This is a process diagram illustrating the manufacturing method of film capacitor 1.

[0035] Figure 11A This is a process diagram illustrating the manufacturing method of film capacitor 1.

[0036] Figure 11B yes Figure 11A A rough top view.

[0037] Figure 12A This is a general cross-sectional view showing an example of the location where the insulating component 21 is formed.

[0038] Figure 12B This is a general cross-sectional view showing another example of the location where the insulating component 21 is formed.

[0039] Figure 13A This is a general cross-sectional view used to illustrate the shape of the insulating component 21.

[0040] Figure 13B This is a general cross-sectional view showing an example of the shape of the insulating component 21.

[0041] Figure 13C This is a general cross-sectional view showing another example of the shape of the insulating component 21.

[0042] Figure 14A This is a process diagram illustrating the manufacturing method of film capacitor 1.

[0043] Figure 14B yes Figure 14A A rough top view.

[0044] Figure 15A This is a process diagram illustrating the manufacturing method of film capacitor 1.

[0045] Figure 15B yes Figure 15A A rough top view.

[0046] Figure 16A This is a schematic cross-sectional view showing the case where the crystal grain size of the metal foil 10 is relatively large.

[0047] Figure 16B yes Figure 16A A rough top view.

[0048] Figure 17Ais a schematic cross-sectional view showing a case where the crystal grain diameter of the metal foil 10 is small.

[0049] Figure 17B is a schematic plan view. Figure 17A

[0050] Figure 18 is a process diagram for explaining the manufacturing method of the film capacitor 1.

[0051] Figure 19 is a schematic plan view. Figure 18

[0052] Figure 20A is a process diagram for explaining the manufacturing method of the film capacitor 1.

[0053] Figure 20B is a schematic plan view. Figure 20A

[0054] Figure 21 is a process diagram for explaining the manufacturing method of the film capacitor 1.

[0055] Figure 22A is a process diagram for explaining the manufacturing method of the film capacitor 1.

[0056] Figure 22B is a schematic plan view. Figure 22A

[0057] Figure 23A is a process diagram for explaining the manufacturing method of the film capacitor 1.

[0058] Figure 23B is a schematic plan view. Figure 23A

[0059] Figure 24A is a process diagram for explaining the manufacturing method of the film capacitor 1.

[0060] Figure 24B is a schematic plan view. Figure 24A

[0061] Figure 25A is a process diagram for explaining the manufacturing method of the film capacitor 1.

[0062] Figure 25B is a schematic plan view. Figure 25A

[0063] Figure 26A is a process diagram for explaining the manufacturing method of the film capacitor 1.

[0064] Figure 26B is a schematic plan view. Figure 26A ​​​​​​​​

[0065] Figure 27 This is a process diagram illustrating the manufacturing method of film capacitor 1.

[0066] Figure 28 This is a general cross-sectional view of an electronic circuit board having a structure in which a thin-film capacitor 1 is embedded in a multilayer substrate 100.

[0067] Figure 29 This is a general cross-sectional view of an electronic circuit board having a structure in which a thin-film capacitor 1 is mounted on the surface of a multilayer substrate 300.

[0068] Figure 30 This is a table that represents the evaluation results of the samples. Detailed Implementation

[0069] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0070] Figure 1A This is a general cross-sectional view illustrating the structure of a thin-film capacitor 1 according to an embodiment of the present invention. Figure 1B This is a rough top view of film capacitor 1.

[0071] like Figure 1A and Figure 1B As shown, the film capacitor 1 includes: a metal foil 10; annular or polygonal annular insulating members 21 and 22 formed on the upper surface 11 of the metal foil 10; electrical members 31 and 32 formed on the upper surface 11 of the metal foil 10 and divided by the insulating members 21 and 22; a terminal electrode 51 connected to the conductive member 31 via a seed layer 40; and a terminal electrode 52 connected to the conductive member 32 via the seed layer 40. The metal foil 10 is made of a metal material such as aluminum, copper, chromium, nickel, or tantalum, and at least a portion of the main surfaces located on opposite sides, namely the upper surface 11 and the lower surface 12, is roughened. Aluminum is most preferably used as the material of the metal foil 10. A dielectric film D is formed on the upper surface 11 and the lower surface 12 of the metal foil 10. The insulating members 21 and 22 are made of resin, for example. The conductive members 31 and 32 are made of conductive polymer material, for example. The seed layer 40 and terminal electrodes 51 and 52 are, for example, made of copper, nickel or gold and their alloys or layer structures.

[0072] The annular or polygonal annular insulating member 21 is provided in a slit that electrically separates the electrode layer composed of the terminal electrode 51 and the conductive member 31 from the electrode layer composed of the terminal electrode 52 and the conductive member 32. The terminal electrode 52 and the conductive member 32 are located in a region surrounded by the insulating member 21, and the terminal electrode 51 and the conductive member 31 are located outside the region surrounded by the insulating member 21 and are surrounded by the insulating member 22. In the region surrounded by the insulating member 21, an opening is formed in the dielectric film D formed on the upper surface 11 of the metal foil 10, or a part or all of the dielectric film D is removed. Thus, the terminal electrode 52 is electrically connected to the metal foil 10 via the conductive member 32. Alternatively, as shown in Figs. 2 and 3, the conductive member 32 can be omitted, and the metal foil 10 can be directly or via the seed layer 40 connected to the terminal electrode 52. In contrast, outside the region surrounded by the insulating member 21, the dielectric film D formed on the upper surface 11 of the metal foil 10 is not removed. That is, the conductive member 31 is in contact with the dielectric film D, not the metal foil 10, and the terminal electrode 51 and the metal foil 10 are insulated from each other. Thus, the terminal electrodes 51 and 52 function as a pair of capacitive electrodes opposite each other via the dielectric film D. Further, the dielectric film D is formed on the roughened upper surface 11 of the metal foil 10, and the surface area of the upper surface 11 is increased, so that a large capacitance can be obtained. Figure 1C and Figure 1D As shown in Figs. 2 and 3, the conductive member 32 can be omitted, and the metal foil 10 can be directly or via the seed layer 40 connected to the terminal electrode 52. In contrast, outside the region surrounded by the insulating member 21, the dielectric film D formed on the upper surface 11 of the metal foil 10 is not removed. That is, the conductive member 31 is in contact with the dielectric film D, not the metal foil 10, and the terminal electrode 51 and the metal foil 10 are insulated from each other. Thus, the terminal electrodes 51 and 52 function as a pair of capacitive electrodes opposite each other via the dielectric film D. Further, the dielectric film D is formed on the roughened upper surface 11 of the metal foil 10, and the surface area of the upper surface 11 is increased, so that a large capacitance can be obtained.

[0073] As shown in Figs. 2 and 3, the conductive member 32 can be omitted, and the metal foil 10 can be directly or via the seed layer 40 connected to the terminal electrode 52. In contrast, outside the region surrounded by the insulating member 21, the dielectric film D formed on the upper surface 11 of the metal foil 10 is not removed. That is, the conductive member 31 is in contact with the dielectric film D, not the metal foil 10, and the terminal electrode 51 and the metal foil 10 are insulated from each other. Thus, the terminal electrodes 51 and 52 function as a pair of capacitive electrodes opposite each other via the dielectric film D. Further, the dielectric film D is formed on the roughened upper surface 11 of the metal foil 10, and the surface area of the upper surface 11 is increased, so that a large capacitance can be obtained. Figure 13A As shown in Fig. 2, the cross section of the insulating member 21 has a tapered shape in which the width W becomes narrower as it is away from the upper surface 11 of the metal foil 10. The cross section of the insulating member 21 is a cross section perpendicular to the extending direction of the insulating member 21, and corresponds to a cross section in the radial direction of the annular insulating member 21. The insulating member 21 has such a tapered shape, so that the adhesion of the insulating member 21 to the dielectric film D and the metal foil 10 is improved, and the terminal electrodes 51 and 52 are less likely to be short-circuited due to peeling of the insulating member 21. Further, the width of the insulating member 21 is reduced at the upper portion, so that the gap between the terminal electrodes 51 and 52 can be reduced. Thus, the thin film capacitor 1 can be embedded in a circuit substrate with a small pitch. Here, the tapered lower surface width Wl of the insulating member 21 refers to the linear distance in the width direction of the portion in contact with the dielectric film D and the metal foil 10, and the tapered upper surface width W2 refers to the linear distance in the width direction of the upper surface of the insulating member 21. In the case where the upper surface of the insulating member 21 is not flat, the width of the insulating member 21 at a position 90% of the height is defined as the tapered upper surface width W2. That is, in the case where the height of the insulating member 21 is H, the width of the insulating member 21 at a position 9H / 10 of the height is defined as the tapered upper surface width W2. In the present embodiment, Wl > W2. Similarly to the insulating member 21, the cross section of the insulating member 22 also has a tapered shape.

[0074] On the outside of the region surrounded by the insulating member 22, the dielectric film D provided on the upper surface 11 of the metal foil 10 is exposed. In this way, in the outer peripheral portion of the thin film capacitor 1, the roughened surface is exposed, and thus the adhesion when embedded in a multilayer substrate can be improved. The side surface 13 of the metal foil 10 is not roughened, and the surface thereof is covered with the insulating film 14. Here, the annular or polygonal annular insulating member 22 is present between the conductive member 31 and the side surface 13 of the metal foil 10, and a gap region in which the conductive member is not present is provided on the outside of the annular or polygonal annular insulating member 22, and thus even in the case where the insulating film 14 is thin, the short circuit between the conductive member 31 and the metal foil 10 is prevented.

[0075] As for the crystal grain size of the central portion (non-roughened portion) of the metal foil 10, it is preferable that the crystal grain size be less than 15 μm in the planar direction (direction parallel to the upper surface 11 and the lower surface 12) and less than 5 μm in the thickness direction (direction perpendicular to the upper surface 11 and the lower surface 12), and it is preferable that the crystal orientation be aligned as much as possible in the planar direction. According to this, as described later, the position accuracy of the side surface 13 can be improved.

[0076] The thin film capacitor 1 can be used as a decoupling capacitor by being embedded in a multilayer substrate. The thickness of the thin film capacitor 1 is, for example, 50 μm or less, and thus is very thin. Therefore, in the case where the terminal electrode 51 and the conductive member 31 are formed on the upper surface 11 side, it is easy to become a convex shape toward the lower surface 12 side. Therefore, in the case where mounting in which warping of the element is suppressed is performed when embedded in a multilayer substrate, the terminal electrode 51 and the conductive member 31 are preferably formed on the lower surface 12 side. Figure 2 In the case where a straight line L1 along the upper surface 11, a straight line L2 along the lower surface 12, and a straight line L3 along the side surface 13 are defined in the cross section shown in FIG. 1, the angle θa formed by the straight line L2 and the straight line L3 is preferably 20° < θa < 80°. That is, it is preferable that the area of the lower surface 12 be larger than the area of the upper surface 11. According to this, the adhesion of the side surface 13 of the thin film capacitor 1 to the multilayer substrate is improved, and thus the strength and the reliability of the thin film capacitor 1 can be improved. In this case, it is more preferable that 30° ≦ θa ≦ 60° be satisfied. By designing the angle θa within the above range, the warping of the thin film capacitor 1 at the time of mounting is alleviated, the contact area of the side surface 13 with the insulating resin constituting the multilayer substrate is optimally controlled, and thus the strength and the reliability of the thin film capacitor 1 can be further improved. In addition, the side surface 13 of the thin film capacitor 1 can have a curved shape in which the angle θa is larger as it approaches the upper surface 11 and the angle θa is smaller as it approaches the lower surface 12. In this way, in the case where the angle θa is not necessarily constant, the value of the angle θa is defined by an average value.

[0077] Next, an example of a manufacturing method of the thin film capacitor 1 will be described.

[0078] First, prepare 10 metal foils (e.g., aluminum) with a thickness of approximately 50 μm. Figure 3 ), roughened by etching its upper surface 11 and lower surface 12 ( Figure 4 Alternatively, the metal foil 10 can be formed by sintering metal powder, instead of roughening the flat metal foil 10. This forms a porous layer 11a on the upper surface 11 and a porous layer 12a on the lower surface 12 of the metal foil 10. Between the porous layers 11a and 12a is an unroughened non-porous layer 10a. In this case, roughening only the upper surface 11 is sufficient; roughening the lower surface 12 is not necessary. However, by roughening both surfaces, warping of the metal foil 10 can be prevented. Furthermore, for the upper surface 11, etching is preferably performed under conditions that maximize the surface area. Even when both the upper and lower surfaces 11 and 12 are roughened, the etching conditions for the upper and lower surfaces 11 can differ. For example, for the lower surface 12, etching can be performed under conditions that maximize adhesion to the multilayer substrate.

[0079] Next, a dielectric film D is formed on the surface of the metal foil 10. Figure 5A The dielectric film D can also be formed by oxidizing the metal foil 10, or by using film-forming methods with excellent coverage, such as ALD, CVD, and fog CVD. Materials for the dielectric film D can include Al2O3, TiO2, Ta2O5, and SiNx. The material of the dielectric film D can also be amorphous. In this case, the composition ratio of the dielectric film D may not necessarily be the stated composition ratio. At this time, it is sufficient to form the dielectric film D at least on the upper surface 11; it is not necessary to form the dielectric film D on the lower surface 12. However, by also forming the dielectric film D on the lower surface 12, the insulation of the lower surface 12 can be ensured. Figure 5B As shown, the dielectric film D formed on the lower surface 12 can have the same composition as the dielectric film D formed on the upper surface 11, or it can be a barrier film E with a different composition, or it can be a stacked structure of dielectric film D and barrier film E. Furthermore, if a barrier film E is present on the lower surface 12 of the metal foil 10, the intrusion of reaction-generated gases produced by the resin constituting the multilayer substrate can be suppressed during the curing of the multilayer substrate. After forming the dielectric film D or the barrier film E, a transport substrate 60 is attached to the lower surface 12 of the metal foil 10. Figure 6 ).

[0080] Next, a photosensitive resist layer is formed on the upper surface 11 of the metal foil 10, and then exposed and developed to form a patterned resist layer 61. Figure 7A , 7B An opening 62 is provided on the resist layer 61 to expose the dielectric film D. The resist layer can be positive or negative.

[0081] Next, by using the resist layer 61 as a mask to remove part or all of the dielectric film D, the metal foil 10 is exposed at the opening 62. Figure 8A , 8B As a method for removing the dielectric film D, reverse sputtering, ion polishing, RIE, wet etching, etc., can be used. Furthermore, the upper surface 11 of the metal foil 10 is roughened in this stage; therefore, by using reverse sputtering, ion polishing, RIE, etc., the spread of the etchant caused by capillary action can be prevented. Liquid etchants can also be used in this process. Furthermore, in... Figure 8A In the example shown, the surface of the exposed metal foil 10 and the dielectric film D form approximately the same plane, but depending on the etching conditions, such as Figure 9 As shown, it can also sometimes be a roughened metal foil 10 with a protruding shape.

[0082] Next, after removing the anti-corrosion layer 61 ( Figure 10 Insulating components 21 and 22 are formed on the upper surface 11 of the metal foil 10. Figure 11A , 11B The insulating components 21 and 22 can be formed using photolithography, screen printing, gravure printing, inkjet printing, etc. Therefore, the cross-sections of the insulating components 21 and 22 are as follows: Figure 11A As shown, the side surface is conical. Here, the location of the insulating component 21 can be as follows: Figure 12A The portion shown overlaps with the exposed portion of the metal foil 10, and can also be as follows: Figure 12B The portion shown does not overlap with the exposed portion of the metal foil 10. Furthermore, the cross-sections of the insulating components 21 and 22 do not need to be bilaterally symmetrical, such as... Figure 13B As shown, taking the centerline C in the thickness direction of the metal foil 10 as a reference, the angle θc of the outer portion is reduced compared to the angle θb of the inner portion of the ring, thereby making the tapered surface of the outer portion of the ring wider than the tapered surface of the inner portion. Accordingly, the area surrounded by the insulating member 21 is increased, and therefore, the ESR decreases due to the reduction in contact resistance. Or, as... Figure 13C As shown, taking the centerline C in the thickness direction of the metal foil 10 as a reference, the angle θb of the portion located inside the ring is increased compared to the angle θc of the portion located outside the ring. Therefore, the conical surface of the outer portion of the ring can be made smaller than the conical surface of the inner portion of the ring. Accordingly, the area outside the region surrounded by the insulating member 21 is increased, thus increasing the capacitance. In the insulating member 21, the side forming the inner portion is connected to the conductive member 32 or the terminal electrode 52, and the side forming the outer portion is connected to the conductive member 31 or the terminal electrode 51. By adopting the above structure, abnormal stress is not generated during the shrinkage process when forming the insulating members 21 and 22, reducing cracks in the roughened portions and improving the yield.

[0083] Next, a photosensitive resist layer is formed on the upper surface 11 of the metal foil 10, and exposure and development are performed to form a patterned resist layer 64 Figure 14A 、 14B ). An opening portion 65 is provided in the resist layer 64 to expose a region outside the insulating member 22. The resist layer can be either positive or negative.

[0084] Next, the metal foil 10 is removed by using the resist layer 64 as a mask to singulate the metal foil 10 Figure 15A 、 15B ). As a method of removing the metal foil 10, wet etching using an etchant such as an acid can be used. In this case, even if a liquid etchant is used, the etchant does not spread beyond the insulating member 22.

[0085] To singulate with higher precision, as described above, it is preferable that the crystal grain size of the central portion (non-roughened portion) of the metal foil 10 be less than 15 μm in the planar direction and less than 5 μm in the thickness direction. This is because, as shown in Figs. 7A and 7B, if the crystal grain size of the metal foil 10 is 15 μm or more in the planar direction and 5 μm or more in the thickness direction, the crystal grains protrude from the inner wall of the side surface 13, and the unevenness in the size of the singulated metal foil 10 also becomes large. In contrast, if the crystal grain size of the metal foil 10 is less than 15 μm in the planar direction and less than 5 μm in the thickness direction, as shown in Figs. 8A and 8B, the crystal grains present in the side surface 13 are small, and thus the unevenness in the size of the singulated metal foil 10 is also reduced. Figure 16A 、 16B Figure 17A 、 17B

[0086] Next, after the resist layer 64 is removed Figure 18 、 19 ), a paste- or liquid-shaped conductive member 31, 32 composed of a conductive polymer material is formed in the region surrounded by the insulating member 22 Figure 20A 、 20B ). Here, the conductive member 32 is located in the region surrounded by the insulating member 21, and the conductive member 31 is located outside the region surrounded by the insulating member 21 and in the region surrounded by the insulating member 22. The conductive members 31, 32 are in a paste or liquid shape, and thus are filled to the bottom of the porous layer 11a by capillary action. As a result, the conductive member 31 is in contact with the dielectric film D and not with the metal foil 10, and the conductive member 32 is in contact with the metal foil 10. Here, the conductive member 32 can not be formed and the terminal electrode 52 can be formed directly.

[0087] Next, a seed layer 40 is formed over the entire surface Figure 21 ​​The seed layer 40 can be formed using methods such as sputtering. Next, a photosensitive resist layer is formed on the upper surface 11 of the metal foil 10, and then exposed and developed to form a patterned resist layer 67. Figure 22A , 22B An opening 68 is provided on the resist layer 67, located outside the region surrounded by the insulating member 22 and the region surrounded by the insulating member 21, and an opening 69 is provided in the region surrounded by the insulating member 21. Thus, in the seed layer 40, the portion covering the conductive member 31 is exposed through the opening 68, and the portion covering the conductive member 32 is exposed through the opening 69. The resist layer can be either positive or negative.

[0088] By performing electroplating in this state, terminal electrodes 51 and 52 are formed. Figure 23A , 23B Next, the resist layer 67 is removed by ashing or other methods. Figure 24A , 24B ), remove the seed layer 40 ( Figure 25A , 25B Furthermore, after forming an insulating film 14 on the side 13 of the metal foil 10 (Fig. 26), the transport substrate 60 is removed by peeling or etching. Figure 27 ),but Figure 1A , 1B The thin-film capacitor 1 shown is now complete. Here, the insulating film 14 can be formed by oxidizing the side surface 13 of the metal foil 10 through an ashing process for removing the resist layer 67 and other heat treatment processes. Multiple terminal electrodes 51 and 52 can each be formed, as long as at least one pair is formed.

[0089] The thin-film capacitor 1 in this embodiment can be as follows: Figure 28 The multilayer substrate 100 shown can also be embedded as shown in the figure. Figure 29 It is shown mounted on the surface of the multilayer substrate 300.

[0090] Figure 28 The illustrated electronic circuit board has a structure in which a semiconductor IC 200 is mounted on a multilayer substrate 100. The multilayer substrate 100 is a multilayer substrate comprising multiple insulating layers and multiple wiring patterns. The multiple insulating layers include insulating layers 101 to 104, and the multiple wiring patterns include wiring patterns 111 and 112. The number of insulating layers is not particularly limited. Figure 28In the illustrated example, the thin film capacitor 1 is embedded between the insulating layer 102 and the insulating layer 103. A plurality of bonding patterns including the bonding patterns 141, 142 are provided on the surface of the multilayer substrate 100. The semiconductor IC 200 has a plurality of pad electrodes including the pad electrodes 201, 202. Of the pad electrodes 201, 202, for example, one is a power terminal and the other is a ground terminal. The pad electrode 201 and the bonding pattern 141 are connected via the solder 211, and the pad electrode 202 and the bonding pattern 142 are connected via the solder 212. Further, the bonding pattern 141 is connected to the terminal electrode 51 of the thin film capacitor 1 via the via conductor 121, the wiring pattern 111, and the via conductor 131. On the other hand, the bonding pattern 142 is connected to the terminal electrode 52 of the thin film capacitor 1 via the via conductor 122, the wiring pattern 112, and the via conductor 132. Thus, the thin film capacitor 1 functions as a decoupling capacitor with respect to the semiconductor IC 200.

[0091] Figure 29 The illustrated electronic circuit substrate has a structure in which the semiconductor IC 400 is mounted on the multilayer substrate 300. The multilayer substrate 300 is a multilayer substrate including a plurality of insulating layers including the insulating layers 301, 302 and a plurality of wiring patterns including the wiring patterns 311, 312. The number of layers of the insulating layers is not particularly limited. In the illustrated example, the number of layers of the insulating layers is two. The wiring patterns 311, 312 are provided on the surface 300a of the multilayer substrate 300. The wiring pattern 311 is provided on the insulating layer 301, and the wiring pattern 312 is provided on the insulating layer 302. The wiring patterns 311, 312 are connected to each other via the via conductor 321, 322. The wiring pattern 311 is connected to the terminal electrode 51 of the thin film capacitor 1 via the via conductor 321 and the solder 413. On the other hand, the wiring pattern 312 is connected to the terminal electrode 52 of the thin film capacitor 1 via the via conductor 322 and the solder 414. Thus, the thin film capacitor 1 functions as a decoupling capacitor with respect to the semiconductor IC 400. Figure 29 In the illustrated example, the thin film capacitor 1 is surface-mounted on the surface 300a of the multilayer substrate 300. A plurality of bonding patterns including the bonding patterns 341 to 344 are provided on the surface 300a of the multilayer substrate 300. The semiconductor IC 400 has a plurality of pad electrodes including the pad electrodes 401, 402. Of the pad electrodes 401, 402, for example, one is a power terminal and the other is a ground terminal. The pad electrode 401 and the bonding pattern 341 are connected via the solder 411, and the pad electrode 402 and the bonding pattern 342 are connected via the solder 412. Further, the bonding pattern 341 is connected to the terminal electrode 51 of the thin film capacitor 1 via the via conductor 321, the wiring pattern 311, the via conductor 331, and the solder 413. On the other hand, the bonding pattern 342 is connected to the terminal electrode 52 of the thin film capacitor 1 via the via conductor 322, the wiring pattern 312, the via conductor 332, the bonding pattern 344, and the solder 414. Thus, the thin film capacitor 1 functions as a decoupling capacitor with respect to the semiconductor IC 400.

[0092] The above describes a preferred embodiment of the present application, but the present application is not limited to the above-described embodiment, and various modifications can be made within the scope of the present application without departing from the spirit of the present application, and of course these are included in the scope of the present application.

[0093] Example

[0094] Samples of several film capacitors were fabricated, each having the same structure as the film capacitor 1 shown in Figure 1, but with different cross-sectional shapes for the insulating components 21. Furthermore, the film capacitors were mounted on an evaluation multilayer substrate, and subjected to a thermal cycling test by maintaining the temperature at -55°C for 30 minutes, then raising the temperature to 150°C and maintaining this temperature for 30 minutes. The short-circuit failure rate was evaluated under these conditions. The results were then presented in… Figure 30 As shown in [the image]. Figure 30 In the middle, "width of the tapered lower surface" and Figure 13A The W1 shown corresponds to "width of the tapered upper surface" and Figure 13A The W2 shown corresponds to this. Furthermore, if the difference between θb and θc is within 2°, it is considered a symmetrical shape where θb and θc are practically equal.

[0095] like Figure 30 As shown, among samples A1-A3 and B1 where θb and θc are practically equal, samples A1-A3 where θb and θc are less than 90° (i.e., the insulating component 21 is conical) have a short-circuit failure probability of 8-16%. In contrast, sample B1 where θb and θc are 90° has a short-circuit failure probability of 35%. Furthermore, among samples A4-A9 where θb ≠ θc, the short-circuit failure probability is less than 5%. Particularly, samples A4-A6 where θb > θc exhibit low ESR.

[0096] Explanation of reference numerals in the attached figures

[0097] 1. Thin film capacitor

[0098] 10 metal foil

[0099] 10a non-porous layer

[0100] 11. The upper surface of the metal foil

[0101] 11a porous layer

[0102] 12 Lower surface of metal foil

[0103] 12a porous layer

[0104] 13. Side of metal foil

[0105] 14 insulating film

[0106] 21, 22 Insulating components

[0107] 31, 32 Conductive components

[0108] 40 seed layers

[0109] 51 and 52 terminal electrodes

[0110] 60 Conveyor Base Material

[0111] 61, 64, 67 resist layer

[0112] 62, 65, 68, 69 opening portion

[0113] 100, 300 multilayer substrate

[0114] 101-104, 301, 302 insulating layer

[0115] 111, 112, 311, 312 wiring pattern

[0116] 121, 122, 131, 132, 321, 322, 331, 332 via conductor

[0117] 141, 142, 341-344 bonding pattern

[0118] 200, 400 semiconductor IC

[0119] 201, 202, 401, 402 pad electrode

[0120] 211, 212, 411-414 solder

[0121] 300a surface of multilayer substrate

[0122] D dielectric film

[0123] E barrier film

Claims

1. A thin film capacitor, wherein provided are: a metal foil whose one main surface is roughened; a dielectric film which covers the one main surface of the metal foil, has an opening portion which partially exposes the metal foil; a first electrode layer which is in contact with the metal foil via the opening portion; a second electrode layer which is in contact with the dielectric film without being in contact with the metal foil; a first insulating member which is annular or polygonal annular, which divides the first electrode layer and the second electrode layer; and a second insulating member which is annular or polygonal annular, which is provided on the one main surface of the metal foil, which surrounds the second electrode layer, the first and second electrode layers are separated by a slit, the first electrode layer is provided in a first region surrounded by the slit, the second electrode layer is provided in a second region which is outside the slit, the first insulating member is provided inside the slit, a cross section of the first and second insulating members has a tapered shape in which a width becomes narrower as it departs from the one main surface of the metal foil.

2. The thin film capacitor according to claim 1, wherein upper surfaces of the first and second electrode layers are exposed without being covered by the first and second insulating members.

3. The thin film capacitor according to claim 1, wherein the first insulating member has a first side surface which is in contact with the first electrode layer, and a second side surface which is in contact with the second electrode layer, in a case where an angle formed by the one main surface of the electrode layer and the first side surface of the first insulating member is set as θb, and an angle formed by the one main surface of the electrode layer and the second side surface of the first insulating member is set as θc, both of the θb and θc are smaller than 90°.

4. The thin film capacitor according to claim 3, wherein the θb and the θc are equal to each other.

5. The thin film capacitor according to claim 3, wherein the θb and the θc are not equal to each other.

6. The thin film capacitor according to claim 5, wherein the θb is larger than the θc.

7. The thin film capacitor according to claim 5, wherein the θb is smaller than the θc.

8. The thin film capacitor according to any one of claims 1 to 7, wherein the other main surface of the metal foil is roughened.

9. The thin film capacitor according to any one of claims 1 to 7, wherein the second electrode layer includes a first conductive member which is in contact with the dielectric film and is composed of a conductive polymer material, and a second conductive member which is in contact with the first conductive member and is composed of a metal material.

10. The thin film capacitor according to claim 9, wherein the first electrode layer includes a third conductive member which is in contact with the metal foil and is composed of a conductive polymer material, and a fourth conductive member which is in contact with the third conductive member and is composed of a metal material.

11. The thin film capacitor according to claim 9, wherein the first electrode layer includes a fourth conductive member which is in contact with the metal foil and is composed of a metal material.

12. A method of manufacturing a thin film capacitor, wherein one main surface of a metal foil is roughened, forming a dielectric film on the one main surface of the metal foil that is roughened, exposing a part of the metal foil by removing a part of the dielectric film, in a state where the dielectric film and the part of the metal foil are exposed, forming, on the dielectric film, a first insulating member that is annular or polygonal annular and has a tapered shape that narrows in width as it moves away from the one main surface of the metal foil, in a manner that surrounds the part of the metal foil, and a second insulating member that is annular or polygonal annular and has a tapered shape that narrows in width as it moves away from the one main surface of the metal foil, in a manner that surrounds the first insulating member, forming a first electrode layer that is in contact with the part of the metal foil in a region surrounded by the first insulating member, and forming a second electrode layer that is in contact with the dielectric film and is not in contact with the part of the metal foil in an outer region of the first insulating member that is surrounded by the second insulating member.

13. The method of manufacturing a thin film capacitor according to claim 12, wherein the step of forming the second electrode layer is performed by forming a first conductive member in paste or liquid form on the dielectric film, and forming a second conductive member composed of a metal material on the surface of the first conductive member.

14. The method of manufacturing a thin film capacitor according to claim 12 or 13, wherein the other main surface of the metal foil is further roughened.

15. An electronic circuit substrate, wherein provided are: a substrate having a wiring pattern; and a semiconductor IC provided on the substrate and a thin film capacitor according to any one of claims 1 to 11, the first and second electrode layers of the thin film capacitor are connected to the semiconductor IC via the wiring pattern.

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