Base and method of manufacturing thereof

Abstract

A susceptor capable of uniform plasma processing over the entire surface of a wafer and a method of manufacturing the same are disclosed. A susceptor is provided, including a dielectric plate having an upper surface on which a wafer is loaded and a lower surface facing the upper surface, and an inner RF electrode and an outer RF electrode embedded in the dielectric plate, wherein the height of a first plane in which the inner RF electrode is embedded is less than the height of a second plane in which the outer RF electrode is embedded with respect to the lower surface.

Description

Technical Field

[0001] This disclosure relates to a base and a method for manufacturing the same, and to a base and a method for manufacturing the same capable of uniform plasma treatment over the entire surface of a wafer. Background Technology

[0002] In the semiconductor device manufacturing process, various processes, such as film deposition and etching, are performed on the semiconductor wafers being processed. In semiconductor manufacturing equipment that processes semiconductor wafers, a substrate is used to support the semiconductor wafers. Within the substrate, conductors such as radio frequency (RF) electrodes, clamping electrodes, and / or resistance heating elements are formed within a body made of a ceramic material such as aluminum nitride or on the surface of a substrate, serving as heaters and / or electrostatic chucks.

[0003] Figure 1 This is a schematic diagram illustrating an example of a base according to existing technology.

[0004] Reference Figure 1 The base 1 includes a plate 10 that supports the wafer. The plate 10 may be formed of a dielectric material such as aluminum nitride. RF electrodes 12A and 12B and a heating element 14 may be disposed within the dielectric plate 10.

[0005] Figure 1 It has an inner circular RF electrode 12A positioned closer to the surface of the dielectric substrate and an outer annular RF electrode 12B positioned further away from the substrate surface. The circular RF electrode 12A and the annular RF electrode 12B are provided with power supply terminals and leads 16A, 16B, and 16C. According to... Figure 1 The structure includes an annular RF electrode 12B positioned below the circular RF electrode 12A, thereby eliminating interference between terminals and ensuring uniform potential in the RF electrode to suppress variations in plasma density.

[0006] However, in Figure 1 In the multilayer substrate shown in the prior art, the external RF electrode is located below the internal RF electrode to apply power to the external RF. Due to this structural problem, the design of the internal and external RF electrodes and the construction of the layers are limited.

[0007] In particular, plasma control is more difficult when manufacturing bag-type substrates because the upper dielectric thickness (UDT) of the internal RF electrodes differs from that of the upper dielectric layer (UDT) of the external RF electrodes. For example, to achieve the same plasma density, measures such as applying a frequency to each RF electrode are required.

[0008] To address this issue, a base has been developed with a design in which the wafer mounting surface is positioned relatively high. However, the base is limited to a specific design that provides steps on the wafer mounting surface. Additionally, additional components must be secured to the outside of the ceramic heater to prevent wafer slippage. Summary of the Invention

[0009] Technical issues

[0010] One aspect of this disclosure is to provide a base capable of uniform plasma control.

[0011] Another aspect of this disclosure is to provide a base that improves wafer deposition uniformity by preventing wafer edges from warping up during processing due to airflow.

[0012] Another aspect of this disclosure is to provide a bag-type base having multiple layers of RF electrodes.

[0013] Another aspect of this disclosure is to provide an electrode structure suitable for a bag-type base.

[0014] Another aspect of this disclosure is to provide a method for manufacturing the aforementioned base.

[0015] Solution to the problem

[0016] To address the aforementioned technical problems, this disclosure provides a base including a dielectric plate, an internal RF electrode, and an external RF electrode. The dielectric plate has an upper surface on which a wafer is mounted and a lower surface opposite to the upper surface. The internal RF electrode and the external RF electrode are embedded in the dielectric plate, wherein, relative to the lower surface, the height of a first plane in which the internal RF electrode is embedded is less than the height of a second plane in which the external RF electrode is embedded.

[0017] In this disclosure, the upper surface includes a first surface on which a wafer is mounted and a second surface surrounding the first surface, and the height of the first surface may be lower than the height of the second surface relative to the lower surface.

[0018] At this time, the thickness of the first upper dielectric layer (udt1) from the first plane to the first surface can be basically the same as the thickness of the second upper dielectric layer (udt2) from the second plane to the second surface.

[0019] Conversely, the thickness of the first upper dielectric layer (udt1) from the first plane to the first surface and the thickness of the second upper dielectric layer (udt2) from the second plane to the second surface can satisfy -0.5.

[0020] The relationship is <(udt 1-udt2) / udt 1<0.5.

[0021] In this disclosure, the ratio of the electrode gap (δ) to the radius (r1) of the inner electrode can satisfy -0.9≤r3 / r1≤1.0, where the electrode gap is defined as the difference between the inner circumferential radius (r3) of the outer RF electrode and the radius (r1) of the inner RF electrode.

[0022] In this disclosure, the internal RF electrode and the external RF electrode are either sheet-type or mesh-type.

[0023] Furthermore, this disclosure may include a connection member for supplying power to an external RF electrode. In this case, the connection member is either a plate type or a rod type.

[0024] Furthermore, the base according to this disclosure may also include a heating element disposed within the plate. In addition, the base according to this disclosure may also include clamping electrodes disposed within the plate.

[0025] In this disclosure, the height difference between the first plane and the second plane can be from 0.1 mm to 2.0 mm.

[0026] Beneficial effects of the invention

[0027] According to this disclosure, a base capable of uniform plasma control can be provided.

[0028] Furthermore, according to this disclosure, a base can be provided that improves wafer deposition uniformity by preventing wafer edges from warping up during processing due to airflow.

[0029] Furthermore, this disclosure provides a multilayer RF electrode structure suitable for bag-type substrates. Attached Figure Description

[0030] Figure 1 This is a diagram illustrating an example of a base according to an exemplary embodiment of the present disclosure.

[0031] Figure 2A and Figure 2B These are schematic cross-sectional views and schematic plan views illustrating the electrode structure of the base according to an exemplary embodiment of the present disclosure.

[0032] Figure 3 This is a schematic diagram showing a cross-section of a pre-sintered base precursor according to an exemplary embodiment of the present disclosure.

[0033] Figure 4 It is shown in Figure 3 A schematic diagram of the cross-section of the base precursor in the state where the molded body is stacked on the pre-sintered body.

[0034] Figure 5 This is a schematic diagram showing a cross-section of a pre-sintered base precursor according to another exemplary embodiment of the present disclosure.

[0035] Figure 6 It is shown in Figure 5 A schematic diagram of the cross-section of the base precursor in the state of stacked molded bodies on a pre-sintered body.

[0036] Figures 7A to 7E This specifically illustrates manufacturing according to exemplary embodiments of the present disclosure. Figure 3 An example diagram illustrating a method for stacking pre-sintered bodies. Detailed Implementation

[0037] The present disclosure will now be described in detail with reference to the accompanying drawings. In this context, it should be noted that...

[0038] In the accompanying drawings, the same components are indicated by the same reference numerals. Furthermore, detailed descriptions of well-known functions and configurations that may obscure the main points of this disclosure will be omitted. For the same reason, some components are exaggerated, omitted, or shown schematically in the drawings, and the dimensions of each component do not perfectly reflect actual dimensions. Therefore, the content described herein is not limited to the relative dimensions or spacing of the components depicted in the various drawings.

[0039] Furthermore, in this disclosure, "stacked" is used to define the relative positional relationship between layers. The expression "layer B on layer A" indicates the relative positional relationship between layer A and layer B, without requiring layer A and layer B to be in contact with each other, and a third layer can be inserted between them. Similarly, the expression "layer C inserted between layer A and layer B" does not exclude the possibility of a third layer being inserted between layer A and layer C or between layer B and layer C.

[0040] Figure 2A and Figure 2B These are schematic cross-sectional and plan views illustrating the electrode structure of a base according to an exemplary embodiment of the present disclosure.

[0041] Reference Figure 2A and Figure 2B The base 100 includes a plate 110 on which a bag-type wafer loading surface 116 is formed. The plate 110 may be formed of a dielectric material such as AlN. The dielectric plate 110 has an upper surface and a lower surface, the upper surface being one side that supports the wafer and the lower surface being the opposite side facing the upper surface.

[0042] The upper surface has at least two surfaces, including a loading surface 116, which serves as a first surface on which a wafer is loaded, and an outer peripheral surface 118, which serves as a second surface adjacent to and surrounding the wafer loading surface.

[0043] An internal RF electrode 120A and an external RF electrode 120B are disposed within a base. In this disclosure, the RF electrodes 120A and 120B are preferably embedded in a dielectric substrate, but are not necessarily limited thereto. In this disclosure, the internal and external RF electrodes can be mesh-type or sheet-type.

[0044] Connection member 142 and / or lead 140 may be provided to power the internal RF electrode 120A. Connection member 130 and / or lead 132 may be provided to power the external RF electrode 120B. Connection member and lead 130 and 132 may pass through the interior of support member 150 to connect to a power supply device. Figure 2A A connecting member 130 is shown formed on the outer RF electrode 120B. However, multiple connecting members may also be formed on the outer RF electrode 120B.

[0045] In this disclosure, the internal RF electrode 120A may have a shape corresponding to the shape of the wafer or wafer mounting surface. Preferably, the outer periphery of the internal RF electrode 120A is circular in a plane. Alternatively, the internal RF electrode 120A is typically cylindrical, but may also be divided into multiple regions, each segment of which may be an arc shape with a predetermined angle.

[0046] In this disclosure, the external RF electrode 120B may have an annular shape with a width of w2 on a plane. In this disclosure, the width of the external RF electrode 120B is preferably a constant value along its circumference, but is not limited thereto.

[0047] like Figure 2B As shown, the internal and external RF electrodes can be configured to have a concentric structure. Furthermore, the figures show that the internal and external RF electrodes do not overlap in a plane, but this disclosure is not limited thereto. Depending on the desired plasma distribution, the internal and external RF electrodes can exist on different planes in the plate, and thus can overlap planarly. Therefore, in this disclosure, the descriptions of "internal" and "external" can be defined as the magnitudes of the outer radii (r1 and r2) on the concentric circles of the respective electrodes.

[0048] In this disclosure, the difference between the inner circumference radius (r3) of the outer electrode and the radius (r1) of the inner electrode can be defined as the electrode gap (δ). When the outer and inner electrodes are not concentric circles, the electrode gap can be defined as an average value. In this disclosure, the electrode gap can have positive or negative values.

[0049] In this disclosure, the ratio of the electrode gap (δ) to the radius (r1) of the inner electrode can be suitably designed. When overlapping electrodes are allowed, this ratio can preferably have a value of 0.8 ≤ r3 / r1 ≤ 1.0, more preferably 0.9 ≤ r3 / r1 ≤ 1.0. When the electrodes do not overlap, this ratio can preferably have a value of 1 < r3 / r1 < 1.2, more preferably 1 ≤ r3 / r1 < 1.1. r1 preferably does not exceed r2.

[0050] In this disclosure, the internal RF electrode 120A and the external RF electrode 120B are disposed on different planes. Specifically, the plane on which the external RF electrode is disposed is δh higher than the plane on which the internal RF electrode is disposed (δh > 0). In this disclosure, δh is preferably 0.1 mm to 2.0 mm.

[0051] The vertical arrangement relationship between the internal and external RF electrodes can be defined as the upper dielectric layer thickness (udt), which refers to the distance from the plane where the electrode is located to the surface of the dielectric plate 110 on it. The planar distance between the plane on which the internal RF electrode is disposed and the mounting surface 116 can be represented by udt 1, and the planar distance between the plane on which the external RF electrode is disposed and the outer circumferential surface 118 is represented by udt 2. In this disclosure, the difference between udt 1 and udt 2 is limited to a value within a predetermined range, and the difference between udt 1 and udt 2 is preferably close to zero. Preferably, udt 1 and udt2 can satisfy the relationships -1<(udt 1-udt2) / udt 1<1, -0.9<(udt 1-udt2) / udt 1<0.9, -0.8<(udt 1-udt2) / udt 1<0.8, -0.7<(udt 1-udt2) / udt 1<0.7,-0.6<(udt 1-udt2) / udt 1<0.6,-0.5<(udt 1-udt2) / udt 1<0.5,-0.4<(udt 1-udt2) / udt 1<0.4,-0.3<(udt 1-udt2) / udt 1<0.3, -0.2<(udt 1-udt2) / udt 1<0.2, or -0.1<(udt 1-udt2) / udt 1<0.1.

[0052] In this way, the thickness of the upper dielectric layer can have a substantially uniform value, thereby allowing the plasma to be uniformly distributed on the outer circumferential surface. This uniform plasma distribution offers various advantages. For example, it can provide the advantage of uniform film formation near the wafer edge on the substrate.

[0053] Although not otherwise described, the base according to this disclosure may also include heating elements and / or clamping electrodes disposed within the plate. The heating elements and clamping electrodes may be positioned appropriately above or below the RF electrodes.

[0054] Invention methods

[0055] In the following, a method for implementing a base according to an exemplary embodiment of the present disclosure will be described with reference to the accompanying drawings.

[0056] Various methods can be applied to form two RF electrodes existing on different planes. As an example, Figure 3 and Figure 4 This is a schematic diagram illustrating the process of manufacturing a base using pre-sintering.

[0057] Figure 3 This is a schematic diagram showing a cross-section of the pre-sintered base precursor 200. Figure 4 This is a schematic diagram showing a cross-section of the base precursor 200 in the state where the molded body is stacked on the pre-sintered body.

[0058] Reference Figure 3 The base precursor 200 has a structure in which a lower pre-sintered body 212A and an upper pre-sintered body 212B are stacked. An internal RF electrode 220A is formed on the lower pre-sintered body 212A, and an external RF electrode 220B is formed on the upper pre-sintered body 220B. Electrode connection members 230A and 240A for power supply are provided on the internal and external RF electrodes, respectively. An advantage is that the height of the RF electrodes can be adjusted by the thickness of the pre-sintered body.

[0059] Figure 4 The molded bodies 213 and 214 are shown stacked on Figure 3 The upper and lower states of the stacked pre-sintered bodies 212A and 212B. Part or all of the molded bodies 213 and 214 may also be replaced with molding powder. For example... Figure 4 As shown, raw material powders in a stacked state can be sintered into a sintered body through sintering processes such as hot pressing, and finally manufactured through subsequent processing. Figure 2A and Figure 2B The base shown.

[0060] Despite the above references Figure 3 and Figure 4 The use of multi-layer or multi-stage pre-sintered bodies to ensure the distance between electrodes is described, but this disclosure may be implemented in other ways.

[0061] Reference Figure 5 and Figure 6 The manufacturing process according to another example embodiment of this disclosure will be described. Figure 5 This is a schematic diagram showing a cross-section of the pre-sintered base precursor 200. Figure 6 This is a schematic diagram showing a cross-section of the base precursor 200 in a state where the molded body is stacked on a pre-sintered body. Figure 3 different, Figure 5The base precursor 200 includes a single pre-sintered body 212C. Internal RF electrodes are embedded in the single pre-sintered body 212C, and external RF electrodes are mounted on the upper part of the single pre-sintered body 212C. Furthermore, connecting members 230B and 240B for applying power to the RF electrodes can be provided. Terminals can be manufactured in various ways, such as by inserting terminals formed of metal material after processing the pre-sintered body, or by embedding connecting members formed of metal material before manufacturing the pre-sintered body and then performing a pre-sintering process.

[0062] Next, as Figure 6 As shown, the base can be manufactured by stacking molded bodies (or molded body powders) 213 and 214 on the upper and lower parts of the pre-sintered body 212C and then performing hot pressing.

[0063] Figures 7A to 7E This specifically illustrates manufacturing according to exemplary embodiments of the present disclosure. Figure 3 An example illustration of the processing of stacked pre-sintered bodies.

[0064] First, refer to Figure 7A The lower pre-sintered body 212A is provided. The lower pre-sintered body 212A has multiple stepped surface structures 213, 215 and 217. The central trench 217 corresponds to the location where the internal RF electrode is formed, and the outermost trench 213 and the middle trench 215 serve as a fixing frame for stacking the upper pre-sintered body.

[0065] The stepped surface structures 213, 215, and 217 described above can be obtained by surface treatment of the pre-sintered body in an appropriate manner. Holes 232 for connecting members of the RF electrodes are provided in the lower pre-sintered body 212A. Although not shown, holes for connecting members of the internal RF electrodes can be provided.

[0066] Subsequently, as Figure 7B As shown, an internal RF electrode is formed in the central trench 217. Various methods can be used to form the internal RF electrode, such as methods that provide metal electrodes processed along the shape of the central trench 217, printing methods such as screen printing using a paste of conductive metal particles, etc.

[0067] Subsequently, as Figure 7C As shown, an upper pre-sintered body 212B is stacked on top of a lower pre-sintered body 212A. The upper pre-sintered body 212B has a groove 218 corresponding to the location where an external RF electrode is formed. Additionally, a hole 232 extending for a connection member of the external RF electrode is formed in the pre-sintered body 212B. The method for forming the hole 232 for the connection member of the external RF electrode described above is exemplary. The hole 232 for the connection member can be formed after stacking the upper and lower pre-sintered bodies.

[0068] Next, as Figure 7D As shown, the connecting member 230 is formed by inserting a metal component, processed to have a "C" shape, into a hole 232 for an external RF electrode. The connecting member 230 can be in the form of a thin, long plate processed to have a "C" shape, or a rod with a circular or polygonal cross-section. The connecting member 230 is inserted into the hole 232 for the electrode and then bent in a groove 218 to form the external RF electrode.

[0069] Next, as Figure 7E As shown, an external RF electrode can be formed by setting a machined metal electrode in the electrode hole 232, or by a printing method, such as screen printing using a paste of conductive metal particles, thereby fabricating a substrate precursor, as shown. Figure 3 As shown.

[0070] <Example>

[0071] Film formation tests were conducted using a ceramic heater that meets the following criteria.

[0072] A. RF electrodes and heating element electrodes of the base

[0073] RF electrode: mesh type, 0.6mm thick

[0074] Heating element electrodes: coil type, wire thickness 0.6mm

[0075] B. CVD process conditions

[0076] Film thickness target:

[0077] Heater target temperature: 550℃

[0078] Pressure: 7200mTorr

[0079] RF power: 1600W

[0080] Gases and flow rates: N2 500 sccm, C3H6 1000 sccm, Ar 300 sccm, He 800 sccm

[0081] Table 1 shows the specifications and film formation results of RF electrodes when the udt is the same, and Table 2 shows the specifications and film formation results of RF electrodes when the udt is different.

[0082] [Table 1]

[0083] Sample number δh Udt1 Udt2 Film formation change (%) Notes #1 0.05 2mm 2mm 6.20％ Difference #2 0.1 2mm 2mm 2.10％ good #3 1 2mm 2mm 1.80％ good #4 2 2mm 2mm 1.80％ good #5 3 2mm 2mm 5.20％ Difference

[0084] [Table 2]

[0085] Sample number δh Udt1 Udt2 Film formation change (%) Notes #1 1 2mm 3mm 3.50％ generally #2 2 2mm 3mm 3.21％ generally #3 1 2mm 4mm 5.80％ Difference #4 2 2mm 4mm 5.58％ Difference #5 1 2mm 5mm 12.20％ Difference #6 2 2mm 5mm 14.20％ Difference

[0086] While this disclosure has been described in conjunction with specific details such as particular components and the limited exemplary embodiments and accompanying drawings above, the exemplary embodiments and drawings are provided merely to aid in a comprehensive understanding of this disclosure. This disclosure is not limited to the exemplary embodiments described above, and those skilled in the art to which this disclosure pertains can make various modifications and variations based on the foregoing description. Therefore, the technical spirit of this disclosure should not be determined solely based on the described exemplary embodiments and the appended claims, and all equivalents and equivalent modifications of the claims should be interpreted as falling within the scope of the spirit of this disclosure.

[0087] Industrial applicability

[0088] This disclosure can be used in ceramic heaters and / or bases for manufacturing semiconductors, such as electrostatic chucks.

Claims

1. A base, comprising: A dielectric substrate includes an upper surface on which a wafer is mounted and a lower surface opposite to the upper surface; Internal and external RF electrodes embedded in the dielectric plate; as well as A connecting member for supplying power to the external RF electrode. Wherein, relative to the lower surface, the height of the first plane in which the internal RF electrode is embedded is less than the height of the second plane in which the external RF electrode is embedded, and The dielectric plate comprises a stacked lower pre-sintered body and an upper pre-sintered body, wherein the internal RF electrode is formed on the lower pre-sintered body and the external RF electrode is formed on the upper pre-sintered body.

2. The base according to claim 1, wherein The upper surface includes a first surface on which the wafer is mounted and a second surface surrounding the first surface, and The height of the first surface is lower than the height of the second surface relative to the lower surface.

3. The base according to claim 2, wherein, The thickness of the first upper dielectric layer (udt1) from the first plane to the first surface is substantially the same as the thickness of the second upper dielectric layer (udt2) from the second plane to the second surface.

4. The base according to claim 2, wherein, The thickness of the first dielectric layer udt1 from the first plane to the first surface and the thickness of the second dielectric layer udt2 from the second plane to the second surface satisfy the relationship -0.5 < (udt1 - udt2) / udt1 < 0.

5.

5. The base according to claim 3 or 4, wherein, The electrode gap δ is defined as the difference between the inner circumferential radius r3 of the outer RF electrode and the radius r1 of the inner RF electrode. The ratio of the inner circumferential radius r3 of the outer RF electrode to the radius r1 of the inner RF electrode satisfies the relationship 0.9≤r3 / r1≤1.

0.

6. The base according to claim 1, wherein, The internal RF electrode and the external RF electrode are either sheet-type or mesh-type.

7. The base according to claim 1, further comprising: Heating elements are disposed within the dielectric plate.

8. The base according to claim 1, further comprising: Clamping electrodes are disposed within the dielectric plate.

9. The base according to claim 1, wherein, The height difference between the first plane and the second plane is 0.1 mm to 2.0 mm.

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