Device under test (DUT) anomaly identification method, device, and equipment

Abstract

The present disclosure provides a device under test (DUT) anomaly identification method, device and equipment, and relates to the technical field of chip testing. The method comprises the following steps: obtaining original test data of a plurality of tested chips, wherein the original test data is test data obtained by a plurality of DUTs performing different test items on part of the tested chips; obtaining an average failure rate of a target test item according to the original test data; obtaining a DUT failure rate of the target DUT performing the target test item according to the original test data; and determining that the target DUT is an abnormal DUT if the DUT failure rate and the average failure rate meet a preset condition. The DUT anomaly identification method, device and equipment provided by the present disclosure directly and accurately feed back the failure condition through the test item failure rate, without omission, eliminate the misjudgment caused by the product itself, and have high identification accuracy.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of chip testing, and particularly relates to a DUT abnormality identification method, a DUT abnormality identification device and an electronic device. BACKGROUND

[0002] The production process of a semiconductor includes wafer manufacturing and semiconductor testing. The semiconductor testing process belongs to a key field of the semiconductor industry. The semiconductor testing includes circuit probing (CP) and final testing (FT). The FT testing is a backend process of chip testing and is the last interception before the chip is shipped. The FT testing is used to detect packaged chips to test the process level of a packaging factory. The testing machine used is expensive and has a high cost.

[0003] During the FT testing, a device under test (DUT) is taken as a unit for testing. A DUT is continuously loaded with different chips for testing. However, the signals on the DUT are affected by a socket, a test board card and a test machine, which causes the chip testing to fail. Therefore, it is necessary to find abnormal DUTs in time, and turn off and repair the abnormal DUTs to avoid damaging the chips and reduce the product yield.

[0004] It should be noted that the information disclosed in the above background section is only used to strengthen the understanding of the background of the present disclosure, and therefore can include information that does not constitute prior art known to those of ordinary skill in the art. SUMMARY

[0005] The present disclosure provides a DUT abnormality identification method, device and equipment, which at least partially overcomes the problem that the existing FT testing provided in the related art cannot find abnormal DUTs in time, which causes the chip to be damaged and reduces the product yield.

[0006] Other characteristics and advantages of the present disclosure will become apparent from the following detailed description, or will be learned by practice of the present disclosure.

[0007] According to one aspect of the present disclosure, a method for identifying an abnormal device under test (DUT) is provided. Raw test data of a plurality of DUTs is obtained, wherein the raw test data comprises test data of a plurality of DUTs, each DUT test data comprises test data of a part of the plurality of DUTs, and the test data of the part of the plurality of DUTs is obtained by performing different test items on the each DUT. An average failure rate of a target test item is obtained according to the raw test data. A DUT failure rate of a target DUT performing the target test item is obtained according to the raw test data. If the DUT failure rate and the average failure rate satisfy a preset condition, the target DUT is determined as an abnormal DUT.

[0008] In one embodiment of the present disclosure, if the DUT failure rate and the average failure rate satisfy the preset condition, the target DUT is determined as an abnormal DUT, comprising: calculating a difference between the DUT failure rate and the average failure rate; and if the difference is greater than or equal to a preset difference threshold, the target DUT is determined as an abnormal DUT.

[0009] In one embodiment of the present disclosure, the method further comprises: if the difference is less than the preset difference threshold, the target DUT is determined as a normal DUT.

[0010] In one embodiment of the present disclosure, the difference between the DUT failure rate and the average failure rate comprises at least one of: a standard deviation of the DUT failure rate and the average failure rate; a difference between the DUT failure rate and the average failure rate; and a ratio of the DUT failure rate to the average failure rate.

[0011] In one embodiment of the present disclosure, the average failure rate of the target test item is obtained according to the raw test data, comprising: obtaining a first number of DUTs performing the target test item from the raw test data; obtaining a second number of DUTs performing the target test item and having a failure state from the raw test data; and determining the average failure rate of the target test item according to the first number and the second number.

[0012] In one embodiment of the present disclosure, the DUT failure rate of the target DUT performing the target test item is obtained according to the raw test data, comprising: obtaining a third number of DUTs performing the target test item by the target DUT from the raw test data; obtaining a fourth number of DUTs performing the target test item by the target DUT and having a failure state from the raw test data; and determining the DUT failure rate of the target DUT performing the target test item according to the third number and the fourth number.

[0013] In an embodiment of the present disclosure, the original test data comprises a chip ID of a chip under test, a DUT identifier corresponding to the chip under test, a test item identifier, and a test result.

[0014] In an embodiment of the present disclosure, the original test data is stored in a test result table.

[0015] In an embodiment of the present disclosure, before the operation of determining that the target DUT is an abnormal DUT if the DUT failure rate and the average failure rate satisfy a preset condition, the method further comprises: determining whether the DUT failure rate is less than a preset failure rate threshold; and performing the operation of determining that the target DUT is an abnormal DUT if the DUT failure rate is less than the preset failure rate threshold.

[0016] In an embodiment of the present disclosure, the method further comprises: determining that the target DUT is an abnormal DUT if the DUT failure rate is greater than or equal to a preset failure rate threshold.

[0017] In an embodiment of the present disclosure, the method further comprises: when the target DUT is an abnormal DUT, controlling the target DUT to stop chip testing and sending a prompt information, wherein the prompt information comprises a target DUT identifier and abnormal information.

[0018] According to another aspect of the present disclosure, a DUT abnormality identification apparatus is also provided, comprising: an acquisition module configured to acquire original test data of a plurality of chips under test, wherein the original test data comprises test data of a plurality of DUTs, test data of each DUT comprises test data of part of the chips under test, and the test data of the part of the chips under test is obtained by performing different test items on the each DUT; a calculation module configured to obtain an average failure rate of a target test item according to the original test data, and obtain a DUT failure rate of a target DUT performing the target test item according to the original test data; and a determination module configured to determine that the target DUT is an abnormal DUT if the DUT failure rate and the average failure rate satisfy a preset condition.

[0019] According to another aspect of the present disclosure, an electronic device is also provided, comprising a processor and a memory configured to store executable instructions of the processor; wherein the processor is configured to execute the above-mentioned DUT abnormality identification method by executing the executable instructions.

[0020] According to another aspect of the present disclosure, a computer readable storage medium having a computer program stored thereon is also provided, wherein the computer program is executed by a processor to implement the above-mentioned DUT abnormality identification method.

[0021] According to another aspect of the present disclosure, there is also provided a computer program product comprising computer programs or computer instructions loaded and executed by a processor to enable a computer to implement the above-mentioned DUT abnormality identification method.

[0022] In the embodiments of the present disclosure, by obtaining original test data of a plurality of DUTs, the original test data comprising test data of a plurality of DUTs, the test data of each DUT comprising test data of part of the plurality of DUTs, the test data of the part of DUTs being obtained by performing different test items on each DUT; according to the original test data, obtaining an average failure rate of a target test item and a DUT failure rate of a target DUT performing the target test item; when the DUT failure rate and the average failure rate satisfy a preset condition, determining that the target DUT is an abnormal DUT, directly and accurately feeding back the failure condition through the test item failure rate, without omission, eliminating the misjudgment caused by the product itself, and having high identification accuracy.

[0023] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0024] The accompanying drawings, which are incorporated into and form part of the specification, illustrate embodiments consistent with the present disclosure and, together with the specification, serve to explain the principles of the present disclosure. It is obvious that the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0025] Figure 1 A flow chart of a DUT abnormality identification method provided by an embodiment of the present disclosure is shown;

[0026] Figure 2 A flow chart of another DUT abnormality identification method provided by an embodiment of the present disclosure is shown;

[0027] Figure 3 A flow chart of a method for determining an average failure rate of a target test item provided by an embodiment of the present disclosure is shown;

[0028] Figure 4 A flow chart of a method for determining a DUT failure rate of a target DUT performing a target test item provided by an embodiment of the present disclosure is shown;

[0029] Figure 5 A flow chart of another DUT abnormality identification method provided by an embodiment of the present disclosure is shown;

[0030] Figure 6A flow chart of still another DUT abnormality identification method provided by an embodiment of the present disclosure is shown.

[0031] Figure 7 A structure schematic diagram of a device under test (DUT) abnormality identification apparatus provided by an embodiment of the present disclosure is shown.

[0032] Figure 8 A framework diagram of an electronic device provided by an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0033] The preferred embodiments of the present disclosure will be described in detail with reference to the drawings. Although the preferred embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments described herein. On the contrary, these embodiments are provided so that the present disclosure is more thorough and complete, and the scope of the present disclosure is fully conveyed to those skilled in the art.

[0034] The terms "first", "second" in the specification are only for the purpose of description, and should not be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise explicitly specified and limited.

[0035] In the description of the present application, it should be noted that, unless otherwise explicitly specified and limited, the terms "mounting", "connecting", "connection" should be understood in a broad sense, for example, it can be fixed connection, or detachable connection, or integrally connected; it can be mechanical connection, or electrical connection or can communicate with each other; it can be directly connected, or indirectly connected through intermediate medium, or the internal communication of two elements or the interaction relationship between two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0036] The following disclosure provides many different embodiments or examples for implementing different structures of the present application. In order to simplify the disclosure of the present application, the components and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present application. In addition, the present application can repeatedly refer to numbers and / or letters in different examples. Such repetition is for the purpose of simplification and clarity, and does not itself indicate the relationship between the various embodiments and / or settings discussed.

[0037] Chip FT test refers to the function verification and electrical parameter test of a chip after the chip is packaged and after the reliability verification of the chip is completed. The current FT test is completed by an automatic test equipment (ATE). The ATE includes software and test equipment and test hardware.

[0038] The test machine is composed of an electronic system for generating test signals of the system, establishing appropriate test patterns, and setting in the correct order. The test machine controls the test hardware by executing a set of test programs to drive the chip with test signals and capture the output feedback of the chip, record the output feedback of the chip, or compare it with the feedback threshold value pre-configured in the test machine, so as to determine whether the test chip is good or bad.

[0039] Before the FT test, a test program is written for the test machine, so that the test machine generates different types of test signals, multiple signals together form a test pattern, a mechanical arm is used to capture the DUT and place it in a test area (Loadboard), a socket is set in the test area for placing the packaged chip, different packaging types correspond to different sockets, and the test machine Tester tests them.

[0040] When the chip contacts the socket, the output start signal is sent to the test machine through the interface, the test machine applies a test pattern to the DUT, detects the output feedback generated by the DUT, measures the parameters of the DUT, compares the measurement result with the feedback threshold value, if the measurement result is within the acceptable tolerance range, the DUT is determined to be a good product, otherwise, the DUT is determined to be a bad product, and the failure type is recorded; the mechanical arm places the DUT in the corresponding area according to the test result of the test machine, such as a good product area, a first-class bad product area, a second-class bad product area, etc.

[0041] During the FT test of the chip, the signals on the DUT are affected by the socket, the test board card, the test machine, etc., causing the chip test to fail, so it is urgent to design a technical solution that can identify abnormal DUTs in time and close or repair abnormal DUTs in time, so as to avoid a large number of injuries to the chip.

[0042] In related technologies, the way to identify abnormal DUTs is usually to judge by the yield of the DUT and the failure pin FailBin, if it exceeds the set reference, it is determined to be an abnormal DUT. For example, according to the DUT measurement result, the DUT yield and Fail Bin are calculated, if the DUT yield is lower than the set reference and / or there is a continuous same Fail Bin, the DUT is determined to be an abnormal DUT.

[0043] However, the above-mentioned manner of identifying abnormal DUTs has the following problems: different product test procedures have different Bin rule division, if a test item is not classified, a Fail Bin is missed, resulting in inaccurate calculation results and affecting the accuracy of DUT identification; the failure of some test items is not reflected in yield and Fail Bin, for example, high-speed test items; and when there are more failures caused by product itself, it will cause misjudgment of abnormal DUTs.

[0044] In view of the problems that the related art cannot cover all DUTs and the misjudgment of abnormal DUTs caused by product failures, a more accurate manner is needed to identify the real abnormal DUTs to solve the following technical problems: the missed judgment caused by different product Bin information; the missed judgment of a certain test item failure but the final result is not sorting fail; the misjudgment of abnormal DUTs caused by more failures caused by product itself; and the ambiguity in judgment when repairing abnormal DUTs.

[0045] Based on this, the technical scheme provided by the embodiments of the present disclosure obtains the original test data of a plurality of DUTs, the original test data including test data of a plurality of DUTs, the test data of each DUT including test data of part of the plurality of DUTs, and the test data of the part of DUTs being obtained by performing different test items on each DUT; according to the original test data, the average failure rate of a target test item and the DUT failure rate of the target DUT performing the target test item are obtained; when the DUT failure rate and the average failure rate meet a preset condition, the target DUT is determined as an abnormal DUT, the failure condition is directly and accurately fed back through the test item failure rate, there is no omission, the misjudgment caused by the product itself is eliminated, and the identification accuracy is high.

[0046] The present embodiment can realize automatic detection and pushing of abnormal DUTs, so as to timely close the abnormal DUT when the DUT is abnormal, push the abnormal DUT abnormality prompt, and timely perform maintenance, thereby preventing the abnormal DUT from damaging the chip and causing low chip yield.

[0047] The present example embodiment will be described in detail below in combination with the drawings and examples.

[0048] First, the present disclosure provides a DUT abnormality identification method, which can be executed by any electronic device with computing processing capability, for example, a server can be used to implement the DUT abnormality identification method of the present disclosure, and a terminal device can also be used to implement the method described in the present disclosure. The terminal device described in the present disclosure can include mobile terminals such as mobile phones, tablet computers, notebook computers, palmtop computers, personal digital assistants (PDAs), and fixed terminals such as desktop computers.

[0049] Figure 1 A flowchart of a DUT abnormality identification method provided by an embodiment of the present disclosure is shown. As shown in the flowchart, in one embodiment, the present disclosure provides a DUT abnormality identification method, which includes the following steps. Figure 1

[0050] In S102, original test data of multiple DUTs is acquired, where the original test data includes test data of multiple DUTs, and the test data of each DUT includes test data of part of the multiple DUTs, and the test data of the part of the multiple DUTs is obtained by performing different test items on each DUT.

[0051] In one embodiment, the DUTs are chips to be tested. During the FT test, the multiple DUTs can be divided into multiple groups, and each group of DUTs can perform an FT test of a test item of the DUTs by using one DUT to execute a test program.

[0052] For example, for a batch of DUTs of a lot product, one lot contains 25 wafers, and if each wafer has 1000 dies, a total of 25000 dies are obtained. After packaging, the 25000 dies are sent to different DUTs for testing. The DUTs on each DUT perform different test items to obtain test data of the DUT and test data of all the chips, and then determine whether the test results of the DUTs of the batch product in different test items are abnormal, and whether the DUT is abnormal.

[0053] For example, the main test items of the FT test can include one or more of Open / Short test, Function test, DC test, AC test, Eflash test, Mixed Signal test, and RF test. The Open / Short test is used to detect whether there is an open circuit or a short circuit in the pins of the chip. The Function test is used to test the logic function of the chip. The DC test is used to verify the DC current and voltage parameters of the device. The AC test is used to verify the AC specifications, including the quality and timing parameters of the AC output signal. The Eflash test is used to test the function and performance of the embedded Flash, including read, write, and erase actions, power consumption, and speed and other parameters. The Mixed Signal test is used to verify the function and performance parameters of the DUT digital-analog hybrid circuit. The RF test is used to test the function and performance parameters of the RF module of the chip.

[0054] ​It should be noted that the original test data includes one or more of the chip ID to be tested, the DUT identifier corresponding to the chip to be tested, the test item identifier, and the test result. The chip ID to be tested is used to distinguish different chips to be tested, and the chip ID to be tested can be represented by letters, numbers, symbols, characters, etc. The DUT identifier is used to represent the DUT used when the corresponding chip to be tested is tested, so as to establish the correspondence between the chip to be tested and the DUT. The DUT identifier can be represented by letters, numbers, symbols, etc. For example, DUT-1, DUT-2, etc. The test item identifier is used to distinguish different test programs, so as to establish the correspondence among the chip to be tested, the DUT, and the test item. The test result includes the chip in a normal state or the chip in a failure state, etc., and is used to distinguish the chip grade. In the embodiments of the present disclosure, the original test data of the chip to be tested is collected to calculate the corresponding failure rate through the original test data, thereby providing basic data guarantee for determining whether the DUT is an abnormal DUT according to the failure rate.

[0055] In one embodiment, the original test data is stored in a test result table, which can include the chip ID to be tested, the DUT identifier, the test item identifier, the test result, etc. described above, thereby facilitating subsequent tracking, abnormal analysis, etc.

[0056] S104, obtaining the average failure rate of the target test item according to the original test data.

[0057] It should be noted that the target test item can be any test item that the test machine needs to perform on the chip to be tested according to the preset test program, for example, the target test item is set as a high-speed test item.

[0058] The average failure rate of the target test item is determined by the total number of chips to be tested that execute the target test item (referred to as a first number) and the total failure number of chips to be tested that execute the target test item and have a failure state (referred to as a second number). Specifically, the average failure rate of the target test item is the ratio of the total failure number of chips to be tested that execute the target test item and have a failure state to the total number of chips to be tested, and the average failure rate is usually expressed in percentage.

[0059] S106, obtaining the DUT failure rate of the target DUT executing the target test item according to the original test data.

[0060] It should be noted that the target DUT can be any one of the plurality of DUTs. In the implementation process, one of the plurality of DUTs can be sequentially taken as the target DUT, so as to identify the abnormal DUT according to the DUT failure rate of each DUT executing the target test item, and when the identification of one DUT is completed, the abnormal identification of other DUTs is continued.

[0061] The DUT failure rate of the target DUT performing the target test item is determined by the number of the tested chips (referred to as a third number) of the target DUT performing the target test item and the number of the tested chips (referred to as a fourth number) of the target DUT performing the target test item and having a test result of a failure state. Specifically, the DUT failure rate of the target DUT performing the target test item is a ratio between the number of the tested chips of the target DUT performing the target test item and having a test result of a failure state and the number of the tested chips of the target DUT performing the target test item, and the DUT failure rate is usually expressed in percentage.

[0062] In S108, if the DUT failure rate and the average failure rate satisfy a preset condition, it is determined that the target DUT is an abnormal DUT.

[0063] In one embodiment, the preset condition is pre-configured in the test machine, and the preset condition is determined according to the relationship between the DUT failure rate and the average failure rate. The preset condition is used as a reference condition for identifying an abnormal DUT, and is used to measure the difference between the DUT failure rate and the average failure rate.

[0064] When the DUT failure rate and the average failure rate satisfy the preset condition, it indicates that the difference between the DUT failure rate and the average failure rate is large, that is, the failure rate of the target DUT deviates seriously from the average failure rate of performing the target test item, and it is determined that the target DUT is an abnormal DUT, so as to remind the user to check the abnormal DUT in time for maintenance, prevent the abnormal DUT from damaging other tested chips, and improve the yield of the FT test.

[0065] When the DUT failure rate and the average failure rate do not satisfy the preset condition, it indicates that the difference between the DUT failure rate and the average failure rate is small, that is, the target DUT is close to the average failure rate of performing the target test item, and it is determined that the target DUT is a normal DUT, and then it is determined whether other DUTs are abnormal.

[0066] In the embodiments of the present disclosure, by obtaining original test data of a plurality of tested chips, the original test data including test data of a plurality of DUTs, the test data of each DUT including test data of part of the tested chips in the plurality of tested chips, and the test data of the part of the tested chips being obtained by each DUT performing different test items, the average failure rate of the target test item and the DUT failure rate of the target DUT performing the target test item are obtained according to the original test data. When the DUT failure rate and the average failure rate satisfy a preset condition, it is determined that the target DUT is an abnormal DUT, the failure condition is directly and accurately fed back through the test item failure rate, there is no omission, the misjudgment caused by the product itself is eliminated, and the recognition accuracy is high.

[0067] Figure 2 A flowchart of another DUT abnormality identification method provided in the embodiments of the present disclosure is shown. Figure 1On the basis of the embodiments, S108 is further refined to S1082-S1084 to limit the specific implementation of the DUT failure rate and the average failure rate satisfying the preset condition. As shown in Figure 2 The DUT abnormality identification method provided by the embodiments of the present disclosure includes S102-S106 and S1082-S1084. Specifically, the method includes the following steps:

[0068] S1082, calculating the difference between the DUT failure rate and the average failure rate;

[0069] S1084, if the difference is greater than or equal to a preset difference threshold, determining that the target DUT is an abnormal DUT.

[0070] Optionally, as shown in Figure 2 S1086, if the difference is less than the preset difference threshold, determining that the target DUT is a normal DUT.

[0071] It should be noted that the specific implementation of S102-S106 is the same as that of S102-S106 in the foregoing embodiments, which will not be described here.

[0072] In one embodiment, the difference ΔL between the DUT failure rate and the average failure rate includes at least one of the following: the standard deviation of the DUT failure rate and the average failure rate, and correspondingly, the preset difference threshold can be a preset standard deviation threshold; the difference between the DUT failure rate and the average failure rate, and correspondingly, the preset difference threshold can be a preset difference threshold; the ratio of the DUT failure rate to the average failure rate, and correspondingly, the preset difference threshold can be a preset ratio threshold.

[0073] The standard deviation σ of the DUT failure rate L DUT and the average failure rate L mean can be expressed as follows:

[0074]

[0075] Correspondingly, the preset standard deviation threshold can be configured as 3, 4, etc., which can be determined according to actual conditions. When the standard deviation of the DUT failure rate and the average failure rate is greater than or equal to the preset standard deviation threshold, it is determined that the target DUT is an abnormal DUT; when the standard deviation of the DUT failure rate and the average failure rate is less than the preset standard deviation threshold, it is determined that the target DUT is a normal DUT, so that whether the target DUT is an abnormal DUT is determined by the standard deviation of the DUT failure rate and the average failure rate, effectively eliminating the false positives or false negatives caused by product defects or different Bin information, and improving the identification accuracy of abnormal DUTs.

[0076] For example, the difference ΔL between the DUT failure rate L and the average failure rate L can also be a ratio of the DUT failure rate L to the average failure rate L, that is: DUT The difference between the DUT failure rate L and the average failure rate L mean , that is:

[0077] ΔL = L DUT - L mean (Formula Two)

[0078] Correspondingly, the preset difference threshold can be configured as 10%, 15%, etc., which can be determined according to actual conditions. When the difference between the DUT failure rate and the average failure rate is greater than or equal to the preset difference threshold, the target DUT is determined as an abnormal DUT; when the difference between the DUT failure rate and the average failure rate is less than the preset difference threshold, the target DUT is determined as a normal DUT, so as to determine whether the target DUT is an abnormal DUT through the difference between the DUT failure rate and the average failure rate, improve the identification accuracy of the abnormal DUT, and locate the problem to provide help for repairing the DUT.

[0079] For example, the difference ΔL between the DUT failure rate L and the average failure rate L can also be a ratio of the DUT failure rate L to the average failure rate L, that is: DUT The difference between the DUT failure rate L and the average failure rate L mean , that is:

[0080]

[0081] Correspondingly, the preset ratio threshold can be configured as 100, 150, etc., which can be determined according to actual conditions. When the ratio of the DUT failure rate to the average failure rate is greater than or equal to the preset ratio threshold, the target DUT is determined as an abnormal DUT; when the ratio of the DUT failure rate to the average failure rate is less than the preset ratio threshold, the target DUT is determined as a normal DUT, so as to determine whether the target DUT is an abnormal DUT through the ratio of the DUT failure rate to the average failure rate, and improve the identification accuracy of the abnormal DUT.

[0082] It should be noted that the difference between the DUT failure rate and the average failure rate and the preset difference threshold are only specific examples provided for the implementation of the present disclosure, and cannot be regarded as a limitation on the protection scope. In the specific implementation process, the specific forms of the difference between the DUT failure rate and the average failure rate and the preset difference threshold can be determined according to actual conditions.

[0083] In the embodiments of the present disclosure, the difference between the DUT failure rate and the average failure rate is calculated, the relationship between the above difference and the preset difference threshold is compared, and whether the target DUT is an abnormal DUT is determined according to the comparison result, so as to eliminate the misjudgment or omission caused by the product itself defects or different Bin information, improve the identification accuracy of the abnormal DUT, quickly locate the problem, and provide help for repair.

[0084] Figure 3 A flow chart of a method for determining average failure rate of a target test item is shown in embodiments of the present disclosure. In one embodiment, S104 described above obtains the average failure rate of the target test item according to the original test data, including:

[0085] S302, obtaining a first number of tested chips that execute the target test item from the original test data;

[0086] S304, obtaining a second number of tested chips that execute the target test item and have a failure state of test result from the original test data;

[0087] S306, determining the average failure rate of the target test item according to the first number and the second number.

[0088] In one embodiment, the original test data is stored in a test result table, which includes tested chip ID, DUT identification corresponding to the tested chip, test item identification, and corresponding test result. When the target test item is determined, the test item identification corresponding to the target test item is used as a search key, so that the tested chip ID corresponding to the target test item can be obtained, the number of tested chip IDs corresponding to the target test item is counted, and the first number of tested chips that execute the target test item is obtained.

[0089] On this basis, the test identification corresponding to the target test item and the test result of the failure state are used as search keys to query the test result table, so that the second number of tested chips that execute the target test item and have the failure state of test result can be obtained.

[0090] In addition, the tested chip ID of the tested chip that has the failure state of test result can also be screened in the first number, and the second number of tested chips that execute the target test item and have the failure state of test result can also be obtained.

[0091] The average failure rate of the target test item described above is the ratio of the second number to the first number, which is expressed in the form of percentage.

[0092] In embodiments of the present disclosure, the first number of tested chips that execute the target test item and the second number of tested chips that execute the target test item and have the failure state of test result are obtained from the original test data, and the average failure rate of the target test item is calculated according to the first number and the second number, so that the failure level is directly and accurately reflected by the failure rate, there is no omission, and the identification accuracy of abnormal DUT is improved.

[0093] Figure 4A flow chart of a method for determining a DUT failure rate of a target DUT performing a target test item is shown. In one embodiment, S106 obtains the DUT failure rate of the target DUT performing the target test item according to the original test data, including:

[0094] S402, obtaining a third number of DUTs performing the target test item from the original test data;

[0095] S404, obtaining a fourth number of DUTs performing the target test item and having a failure result from the original test data;

[0096] S406, determining the DUT failure rate of the target DUT performing the target test item according to the third number and the fourth number.

[0097] In one embodiment, the original test data is stored in a test result table, which includes DUT IDs, DUT identifiers corresponding to the DUTs, test item identifiers, and corresponding test results. When the target DUT and the target test item are determined, the test item identifier corresponding to the target DUT and the target test item is used as a search key to obtain the DUT IDs of the DUTs performing the target test item, and the number of the DUT IDs of the DUTs performing the target test item is counted to obtain the third number of the DUTs performing the target test item.

[0098] On this basis, the test identifier and the test result corresponding to the target DUT and the target test item are used as search keys to query the test result table to obtain the fourth number of the DUTs performing the target test item and having a failure result.

[0099] In addition, the DUT IDs of the DUTs performing the target test item and having a failure result can also be filtered from the third number to obtain the fourth number of the DUTs performing the target test item and having a failure result.

[0100] The DUT failure rate of the target DUT performing the target test item is the ratio of the fourth number to the third number, which is expressed in percentage.

[0101] In the embodiments of the present disclosure, the third quantity of the DUTs under test that execute the target test item and the fourth quantity of the DUTs under test that execute the target test item and have a test result in a failure state are obtained from the original test data, and the DUT failure rate of the target DUT executing the target test item is calculated according to the third quantity and the fourth quantity, so that the failure level is directly and accurately reflected by the failure rate, and then the difference between the average failure rate and the DUT failure rate is used to determine the abnormal DUT, without omission, eliminating the misjudgment caused by the product itself, and improving the identification accuracy of the abnormal DUT.

[0102] Figure 5 A flowchart of another DUT abnormality identification method provided in the embodiments of the present disclosure is shown. In Figure 1 On the basis of the embodiments, in one embodiment, before determining that the target DUT is an abnormal DUT in S108 if the DUT failure rate and the average failure rate meet the preset condition, S1072-S1074 are added to limit the case where the DUT failure rate is too high. As Figure 5 shown, in one embodiment, the DUT abnormality identification method provided in the embodiments of the present disclosure includes S102-S108 and S1072-S1074. Specifically, the method includes:

[0103] S1072, determining whether the DUT failure rate is less than a preset failure rate threshold; if the DUT failure rate is less than the preset failure rate threshold, performing the operation of S108 if the DUT failure rate and the average failure rate meet the preset condition, determining that the target DUT is an abnormal DUT.

[0104] Optionally, as Figure 5 shown, the DUT abnormality identification method provided in the embodiments of the present disclosure further includes: S1074, if the DUT failure rate is greater than or equal to the preset failure rate threshold, determining that the target DUT is an abnormal DUT.

[0105] It should be noted that the implementation manners of S102-S108 described above are the same as the specific implementation manners of S102-S108 in the foregoing embodiments, and will not be described herein.

[0106] The preset failure rate threshold described above is used to measure the abnormal level of the DUT failure rate of the target DUT, the preset failure rate threshold is pre-configured in the test machine, and the preset failure rate threshold can be 15%, 20%, 25%, etc., which can be determined according to actual conditions, and the present disclosure does not make specific limitations.

[0107] When the DUT failure rate is less than the preset failure rate threshold, it indicates that the DUT failure rate of the target DUT is within an acceptable range, and it is necessary to determine whether the target DUT is an abnormal DUT through the relationship between the DUT failure rate and the average failure rate and the preset condition; when the DUT failure rate is greater than or equal to the preset failure rate threshold, it indicates that the DUT failure rate of the target DUT is high, and it is determined that the target DUT is an abnormal DUT, which needs to be paid attention to by the user in a timely manner, so as to reduce the amount of data for identifying abnormal DUTs and improve the identification efficiency.

[0108] Figure 6 A flow chart of another DUT abnormality identification method provided by an embodiment of the present disclosure is shown. Figure 1 On the basis of the embodiment, S110 is added after S108 to limit the abnormality prompt. In one embodiment, as shown in the figure, the DUT abnormality identification method provided by an embodiment of the present disclosure includes S102-S110. Specifically, the method includes: Figure 6

[0109] S110, when the target DUT is an abnormal DUT, controlling the target DUT to stop chip testing and sending prompt information, wherein the prompt information includes the target DUT identifier and abnormality information.

[0110] It should be noted that the implementation manners of S102-S108 described above are the same as the specific implementation manners of S102-S108 in the foregoing embodiments, and will not be described here again.

[0111] In one embodiment, after the chips in the current batch lot complete the FT test, the chips in the next batch lot may have been put into the FT test. At this time, if it is determined that the target DUT is an abnormal DUT, a stop test control instruction is output to control the target DUT to stop chip testing, effectively preventing the damage of a large number of tested chips.

[0112] The prompt information described above is used to send the abnormal DUT and the corresponding test item and other abnormal information to the user in a timely manner, so as to repair the abnormal DUT according to the test item and other information.

[0113] The prompt information can be displayed in the form of text on the display screen of the test machine, or pushed to the terminal device used by the user in the form of a short message, and the prompt manner can be determined according to the actual situation, which is not limited by the present disclosure.

[0114] In the embodiment of the present disclosure, when the target DUT is an abnormal DUT, the target DUT identifier and the abnormality information of the abnormal DUT are sent to the user in the form of prompt information by controlling the target DUT to stop chip testing, so as to remind the user to pay attention to the abnormal DUT in a timely manner, analyze the problem according to the abnormality information and repair it in a timely manner, and improve the production efficiency.

[0115] ​Based on the same inventive concept, the disclosure embodiments also provide a device under test (DUT) abnormality identification apparatus and a wafer failure prediction apparatus, as described in the following embodiments. Since the principles of the apparatus embodiments for solving problems are similar to the above-mentioned method embodiments, the implementation of the apparatus embodiments can be referred to the implementation of the above-mentioned method embodiments, and the repeated parts will not be described herein.

[0116] Figure 7 A structure schematic diagram of a device under test (DUT) abnormality identification apparatus provided by the embodiments of the disclosure is shown. As shown in Figure 7 In one embodiment, the DUT abnormality identification apparatus provided by the embodiments of the disclosure includes an acquisition module 701, a calculation module 702, and a determination module 703.

[0117] The acquisition module 701 is configured to acquire original test data of a plurality of DUTs, wherein the original test data includes test data of a plurality of DUTs, and the test data of each DUT includes test data of part of the plurality of DUTs, and the test data of the part of the plurality of DUTs is obtained by performing different test items on each DUT.

[0118] The calculation module 702 is configured to obtain an average failure rate of a target test item according to the original test data, and obtain a DUT failure rate of the target DUT performing the target test item according to the original test data.

[0119] The determination module 703 is configured to determine that the target DUT is an abnormal DUT if the DUT failure rate and the average failure rate meet a preset condition.

[0120] In one embodiment, the calculation module 702 is configured to calculate a difference amount of the DUT failure rate and the average failure rate, and the determination module 703 is specifically configured to determine that the target DUT is an abnormal DUT if the difference amount is greater than or equal to a preset difference amount threshold.

[0121] In one embodiment, the determination module 703 is further configured to determine that the target DUT is a normal DUT if the difference amount is less than the preset difference amount threshold.

[0122] It should be noted that the difference amount of the DUT failure rate and the average failure rate includes at least one of the following: a standard deviation of the DUT failure rate and the average failure rate; a difference value of the DUT failure rate and the average failure rate; and a ratio of the DUT failure rate and the average failure rate.

[0123] In one embodiment, the calculation module 702 is configured to acquire a first number of DUTs performing the target test item from the original test data, acquire a second number of DUTs performing the target test item and having a failure state from the original test data, and determine the average failure rate of the target test item according to the first number and the second number. In one embodiment, the calculation module 702 is configured to acquire a first number of DUTs performing the target test item from the original test data, acquire a second number of DUTs performing the target test item and having a failure state from the original test data, and determine the average failure rate of the target test item according to the first number and the second number.

[0124] In one embodiment, the calculating module 702 is configured to acquire a third number of the DUTs under test from the original test data, which execute the target test item and whose test results are the DUTs under test; acquire a fourth number of the DUTs under test from the original test data, which execute the target test item and whose test results are the failure status; and determine the DUT failure rate of the target DUT executing the target test item according to the third number and the fourth number.

[0125] It should be noted that the original test data includes the ID of the DUT under test, the DUT identification corresponding to the DUT under test, the test item identification, and the test result.

[0126] In one embodiment, the original test data is stored in a test result table.

[0127] In one embodiment, the determining module 703 is further configured to determine whether the DUT failure rate is less than a preset failure rate threshold; and if the DUT failure rate is less than the preset failure rate threshold, execute the operation of determining that the target DUT is an abnormal DUT if the DUT failure rate and the average failure rate satisfy a preset condition.

[0128] In one embodiment, the determining module 703 is further configured to determine that the target DUT is an abnormal DUT if the DUT failure rate is greater than or equal to the preset failure rate threshold.

[0129] In one embodiment, the identification device further includes a reminding module not shown in the drawings, which is configured to control the target DUT to stop the chip test and send a reminding information when the target DUT is an abnormal DUT, wherein the reminding information includes the target DUT identification and abnormal information.

[0130] Those skilled in the art can understand that each aspect of the present application can be implemented as a system, a method or a program product. Therefore, each aspect of the present application can be specifically implemented as follows: a complete hardware implementation, a complete software implementation (including firmware, microcode, etc.), or a combination of hardware and software aspects, which can be collectively referred to as "circuitry", "module" or "system".

[0131] The electronic device 800 according to this embodiment of the present application will be described below with reference to Figure 8 Figure 8 The displayed electronic device 800 is only an example and should not limit the functions and use range of the embodiments of the present application.

[0132] As Figure 8 ​As shown, the electronic device 800 is in the form of a general computing device. Components of the electronic device 800 can include, but are not limited to, the at least one processing unit 810 described above, the at least one storage unit 820 described above, and a bus 830 that connects the various system components, including the storage unit 820 and the processing unit 810.

[0133] The storage unit stores program code that can be executed by the processing unit 810 such that the processing unit 810 performs the steps described above in the "Exemplary Methods" section of this specification in accordance with various exemplary embodiments of the present application. For example, the processing unit 810 can execute program code as shown in Figure 1 The processing unit 810 can execute program code as shown in FIG. 6 to obtain raw test data of a plurality of DUTs, where the raw test data includes test data of a plurality of DUTs, the test data of each DUT includes test data of a portion of the plurality of DUTs, and the test data of the portion of the DUTs is obtained by performing different test items on each DUT; obtain an average failure rate of a target test item based on the raw test data; obtain a DUT failure rate of the target DUT performing the target test item based on the raw test data; and determine that the target DUT is an abnormal DUT if the DUT failure rate and the average failure rate satisfy a preset condition.

[0134] The storage unit 820 can include a readable medium in the form of volatile storage such as a random access memory (RAM) 8201 and / or cache memory 8202, and can further include a read-only memory (ROM) 8203.

[0135] The storage unit 820 can further include a program / utility 8204 having a set (at least one) of program modules 8205, including but not limited to, an operating system, one or more application programs, other program modules, and program data, and each of these examples, or some combination thereof, can include implementation of a network environment.

[0136] The bus 830 can be representative of one or more of several types of bus structures, including a storage unit bus or storage unit controller, a peripheral bus, a graphics acceleration port, a processing unit bus, or a local bus using any of a variety of bus architectures.

[0137] The electronic device 800 can also communicate with one or more external devices 840 such as a keyboard or pointing device, a Bluetooth device, or a Figure 8 The network adapter 860 communicates to the other modules of the electronic device 800 via bus 830. As will be appreciated, while not shown, other hardware and / or software modules could be used in conjunction with the electronic device 800. These include, but are not limited to, microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data archival storage systems, etc.

[0138] Those skilled in the art will readily appreciate that the example embodiments described herein can be implemented by software and / or firmware in addition to or instead of hardware. The application relates to any type of computer system or environment, such as example workstations, laptops, desktops, servers, handheld devices, etc. and includes any system that includes any of the above devices, or any other devices that have some other functionality and can be moni- tored, controlled, and / or augmented by a computer system. A typical implementation might include one or more computers or a similar device operated by one or more persons.

[0139] In an example embodiment, the present disclosure also provides a computer readable storage medium, which can be a readable signal medium or a readable storage medium. In some possible embodiments, various aspects of the present disclosure can also be implemented as a program product in the form of a computer readable storage medium having program code portions stored therein, which can be executed by a user equipment to cause the user equipment to perform steps described in the above "Example Method" section of the specification according to various example embodiments of the present disclosure.

[0140] A program product for implementing the above method according to the embodiments of the present disclosure can take the form of a portable compact disc read-only memory (CD-ROM) and include program code portions, and can be run on a user equipment, such as a personal computer. However, the program product of the present disclosure is not limited to this, and in this document, a readable storage medium can be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, device or apparatus.

[0141] The program product can take any combination of one or more computer-readable media. The computer-readable media can be a computer-readable storage medium or a computer-readable signal medium. The computer-readable storage medium can be, for example but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer-readable storage medium include an electrical connection having one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0142] The computer-readable signal medium can include a computer-readable storage medium that is configured to store and deliver a computer-readable program code. The computer-readable program code can be propagated as a computer-readable signal medium.

[0143] The program code embodied on the computer-readable media can be transmitted using any appropriate medium, including but not limited to wireless, wired, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

[0144] The program code for carrying out operations of the present application can be written in any combination of one or more programming languages, including an object oriented programming language such as Java, C++, etc., and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code can execute entirely on the user's computing device, partly on the user's device, as a stand-alone software package, partly on the user's computing device and partly on a remote computing device or entirely on the remote computing device or server. In the latter scenario, the remote computing device can be connected to the user's computing device through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection can be made to an external computing device, such as through the Internet using an Internet Service Provider.

[0145] It should be noted that, although several modules or units for a device to perform an action are mentioned in the foregoing detailed description, such a division into modules or units is not mandatory. In fact, according to an embodiment of the present disclosure, features and functions of two or more modules or units described above can be embodied in one module or unit. Conversely, features and functions of one module or unit described above can be further divided into a plurality of modules or units.

[0146] Moreover, although individual steps of the methods in the present disclosure are described in a particular order in the drawings, this is not required or implied as to the order of the steps, nor is it required that all of the steps be performed to achieve the desired result. Additionally or alternatively, certain steps can be omitted, multiple steps can be combined into one step, one step can be broken into multiple steps, etc.

[0147] From the above description of the embodiments, those skilled in the art will readily perceive that the example embodiments described herein can be implemented by software and / or by software in combination with the necessary hardware. Thus, the technical solution according to the embodiments of the present disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, a USB flash disk, a mobile hard disk, etc.) or a network, and includes a number of instructions to enable a computing device (which can be a personal computer, a server, a mobile terminal, or a network device, etc.) to perform the methods according to the embodiments of the present disclosure.

[0148] Other embodiments of the present disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure following the general principles thereof and including such departures from the present disclosure that come within known use or custom in the art. The specification and examples are to be regarded as exemplary only, and the true scope and spirit of the present disclosure are indicated by the appended claims.

Claims

1. A method for identifying anomalies in a device under test (DUT), characterized in that, include: Acquire raw test data of multiple chips under test, wherein the raw test data includes test data of multiple DUTs, and the test data of each DUT includes test data of a portion of the multiple chips under test, wherein the test data of the portion of the chips under test is obtained by performing different test items on each DUT. Based on the original test data, the average failure rate of the target test item is obtained, including: Obtain the first number of chips under test that perform the target test item from the original test data; Obtain a second number of tested chips that have performed the target test item and whose test result is a failure state from the original test data; Based on the first quantity and the second quantity, the average failure rate of the target test item is determined, wherein the target test item is any test item performed on the chip under test; Based on the original test data, the DUT failure rate when executing the target test item is obtained, including: Obtain the third number of chips under test that the target DUT performs the target test item from the original test data; Obtain the fourth number of chips under test (DUTs) that have performed the target test item and whose test result is a failure state from the original test data. Based on the third quantity and the fourth quantity, determine the DUT failure rate of the target DUT executing the target test item, wherein the target DUT is any one of the plurality of DUTs; If the failure rate of the DUT and the average failure rate meet a preset condition, then the target DUT is determined to be an abnormal DUT.

2. The method according to claim 1, characterized in that, If the failure rate of the DUT and the average failure rate meet a preset condition, then the target DUT is determined to be an abnormal DUT, including: Calculate the difference between the DUT failure rate and the average failure rate; If the difference is greater than or equal to a preset difference threshold, the target DUT is determined to be an abnormal DUT.

3. The method according to claim 2, characterized in that, The method further includes: If the difference is less than the preset difference threshold, the target DUT is determined to be a normal DUT.

4. The method according to claim 2, characterized in that, The difference between the DUT failure rate and the average failure rate includes at least one of the following: The standard deviation of the DUT failure rate and the average failure rate; The difference between the DUT failure rate and the average failure rate; The ratio of the DUT failure rate to the average failure rate.

5. The method according to claim 1, characterized in that, The raw test data includes the chip ID under test, the DUT identifier corresponding to the chip under test, the test item identifier, and the test results.

6. The method according to claim 5, characterized in that, The original test data is stored in the test results table.

7. The method according to claim 1, characterized in that, Before determining that the target DUT is an anomalous DUT if the failure rate of the DUT and the average failure rate meet a preset condition, the method further includes: Determine whether the failure rate of the DUT is less than a preset failure rate threshold; If the failure rate of the DUT is less than a preset failure rate threshold, then the operation of determining the target DUT as an abnormal DUT is executed if the failure rate of the DUT and the average failure rate meet a preset condition.

8. The method according to claim 1, characterized in that, The method further includes: if the failure rate of the DUT is greater than or equal to a preset failure rate threshold, then the target DUT is determined to be an abnormal DUT.

9. The method according to any one of claims 1-8, characterized in that, The method further includes: When the target DUT is an abnormal DUT, control the target DUT to stop chip testing and send a reminder message, wherein the reminder message includes the target DUT identifier and abnormal information.

10. An electronic device, characterized in that, The device includes a processor and a memory, the memory being used to store executable instructions of the processor; wherein the processor is configured to execute the DUT anomaly identification method according to any one of claims 1-9 by executing the executable instructions.

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