Bandgap Reference Circuit

Abstract

An embodiment of the present disclosure provides a bandgap reference circuit, which includes a core current generating circuit, an operational amplifier, an operational amplifier voltage control circuit, a current mirror circuit, a voltage control circuit, a current source circuit, a first and a second shunt circuit, and an output circuit. The core current generating circuit generates a core current according to a voltage at an output terminal of the operational amplifier and a first voltage. The current mirror circuit generates a mirror current of the core current. The voltage control circuit controls the temperature change rate of the voltage of the first node according to the mirror current. The current source circuit generates a constant current. The first shunt circuit generates a first shunt according to the voltage of the first node and the constant current. The second shunt circuit generates a second shunt according to the voltage of the first input terminal of the operational amplifier and the constant current. The operational amplifier voltage control circuit controls the voltage of the first input terminal of the operational amplifier according to the core current and the first shunt and controls the voltage of the second input terminal of the operational amplifier according to the core current and the second shunt. The output circuit generates a reference voltage according to the core current.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the technical field of integrated circuits, and in particular, to a bandgap reference circuit. Background Art

[0002] Bandgap reference circuits are widely used in integrated circuits as reference sources that are insensitive to temperature changes. In the bandgap reference circuit, a voltage / current with a lower temperature coefficient can be achieved by superimposing a positive temperature coefficient voltage / current and a negative temperature coefficient voltage / current. However, there are voltages / currents with nonlinear temperature coefficients in existing bandgap reference circuits. In order to achieve a voltage / current with a lower temperature coefficient, in addition to compensating for the linear temperature coefficient term, higher-order curvature temperature compensation is also required. Summary of the invention

[0003] Embodiments described herein provide a bandgap reference circuit.

[0004] According to a first aspect of the present disclosure, a bandgap reference circuit is provided. The bandgap reference circuit includes: a core current generating circuit, an operational amplifier, an operational amplifier voltage control circuit, a current mirror circuit, a voltage control circuit, a current source circuit, a first shunt circuit, a second shunt circuit, and an output circuit. The core current generating circuit is configured to generate a core current according to a voltage at an output terminal of the operational amplifier and a first voltage from a first voltage terminal. The current mirror circuit is configured to generate a mirror current of the core current and provide the mirror current to the voltage control circuit via a first node. The voltage control circuit is configured to make the voltage of the first node have a negative temperature coefficient and control the temperature change rate of the voltage of the first node according to the mirror current. The current source circuit is configured to generate a constant current and provide a constant current to both the first shunt circuit and the second shunt circuit via a second node. The first shunt circuit is configured to generate a first shunt according to the voltage of the first node and the constant current. The second shunt circuit is configured to generate a second shunt according to the voltage of the first input terminal of the operational amplifier and the constant current. The operational amplifier voltage control circuit is configured to: control the voltage of the first input terminal of the operational amplifier according to the core current and the first shunt, and control the voltage of the second input terminal of the operational amplifier according to the core current and the second shunt. The output circuit is configured to: generate a reference voltage according to the core current. The temperature change rate of the voltage of the first input terminal of the operational amplifier is less than the temperature change rate of the voltage of the first node.

[0005] In some embodiments of the present disclosure, the core current generating circuit includes: a first transistor and a second transistor. The control electrode of the first transistor is coupled to the control electrode of the second transistor and the output terminal of the operational amplifier. The first electrode of the first transistor is coupled to the first voltage terminal. The second electrode of the first transistor is coupled to the first input terminal of the operational amplifier. The first electrode of the second transistor is coupled to the first voltage terminal. The second electrode of the second transistor is coupled to the second input terminal of the operational amplifier.

[0006] In some embodiments of the present disclosure, the operational amplifier voltage control circuit includes: a third transistor, a fourth transistor, a first resistor, a second resistor, and a third resistor. Among them, the first end of the first resistor is coupled to the first end of the second resistor and the first input end of the operational amplifier. The control electrode of the third transistor is coupled to the second electrode of the third transistor and the second end of the second resistor. The first electrode of the third transistor is coupled to the second voltage end. The control electrode of the fourth transistor is coupled to the second electrode of the fourth transistor, the second input end of the operational amplifier, and the first end of the third resistor. The first electrode of the fourth transistor is coupled to the second voltage end. The second end of the first resistor is coupled to the second voltage end. The second end of the third resistor is coupled to the second voltage end.

[0007] In some embodiments of the present disclosure, the output circuit includes: a fifth transistor, and a fourth resistor. The control electrode of the fifth transistor is coupled to the control electrode of the first transistor. The first electrode of the fifth transistor is coupled to the first voltage terminal. The second electrode of the fifth transistor is coupled to the first terminal of the fourth resistor and the output voltage terminal. The second terminal of the fourth resistor is coupled to the second voltage terminal.

[0008] In some embodiments of the present disclosure, the current mirror circuit includes: a sixth transistor, wherein a control electrode of the sixth transistor is coupled to a control electrode of the first transistor, a first electrode of the sixth transistor is coupled to a first voltage terminal, and a second electrode of the sixth transistor is coupled to a first node.

[0009] In some embodiments of the present disclosure, the voltage control circuit includes: a seventh transistor, wherein a control electrode of the seventh transistor is coupled to a second electrode of the seventh transistor and a first node, and a first electrode of the seventh transistor is coupled to a second voltage terminal.

[0010] In some embodiments of the present disclosure, the current source circuit includes: an eighth transistor, wherein a control electrode of the eighth transistor is coupled to a control electrode of the first transistor, a first electrode of the eighth transistor is coupled to a first voltage terminal, and a second electrode of the eighth transistor is coupled to a second node.

[0011] In some embodiments of the present disclosure, the first shunt circuit includes: a ninth transistor, wherein a control electrode of the ninth transistor is coupled to the first node, and a first electrode of the ninth transistor is coupled to the second node.

[0012] The second electrode of the ninth transistor is coupled to the first input terminal of the operational amplifier.

[0013] In some embodiments of the present disclosure, the second shunt circuit includes: a tenth transistor, wherein a control electrode of the tenth transistor is coupled to a first input terminal of an operational amplifier, a first electrode of the tenth transistor is coupled to a second node, and a second electrode of the tenth transistor is coupled to a second input terminal of the operational amplifier.

[0014] According to a second aspect of the present disclosure, a bandgap reference circuit is provided. The bandgap reference circuit includes: a first transistor to a tenth transistor, a first resistor to a fourth resistor, and an operational amplifier. The control electrode of the first transistor is coupled to the control electrode of the second transistor and the output terminal of the operational amplifier. The first electrode of the first transistor is coupled to the first voltage terminal. The second electrode of the first transistor is coupled to the first input terminal of the operational amplifier, the first terminal of the first resistor, and the first terminal of the second resistor. The first electrode of the second transistor is coupled to the first voltage terminal. The second electrode of the second transistor is coupled to the second input terminal of the operational amplifier, the first terminal of the third resistor, and the control electrode and the second electrode of the fourth transistor. The control electrode of the third transistor is coupled to the second electrode of the third transistor and the second terminal of the second resistor. The first electrode of the third transistor is coupled to the second voltage terminal. The first electrode of the fourth transistor is coupled to the second voltage terminal. The second terminal of the first resistor is coupled to the second voltage terminal. The second terminal of the third resistor is coupled to the second voltage terminal. The control electrode of the fifth transistor is coupled to the control electrode of the first transistor. The first electrode of the fifth transistor is coupled to the first voltage terminal. The second electrode of the fifth transistor is coupled to the first terminal of the fourth resistor and the output voltage terminal. The second terminal of the fourth resistor is coupled to the second voltage terminal. The control electrode of the sixth transistor is coupled to the control electrode of the first transistor. The first electrode of the sixth transistor is coupled to the first voltage terminal. The second electrode of the sixth transistor is coupled to the control electrode and the second electrode of the seventh transistor. The first electrode of the seventh transistor is coupled to the second voltage terminal. The control electrode of the eighth transistor is coupled to the control electrode of the first transistor. The first electrode of the eighth transistor is coupled to the first voltage terminal. The second electrode of the eighth transistor is coupled to the first electrode of the ninth transistor and the first electrode of the tenth transistor. The control electrode of the ninth transistor is coupled to the second electrode of the seventh transistor. The second electrode of the ninth transistor is coupled to the first input terminal of the operational amplifier. The control electrode of the tenth transistor is coupled to the first input terminal of the operational amplifier. The second electrode of the tenth transistor is coupled to the second input terminal of the operational amplifier. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below. It should be noted that the drawings described below only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure, wherein:

[0016] Figure 1 is an exemplary circuit diagram of a bandgap reference circuit;

[0017] Figure 2 is used for Figure 1Waveform diagrams of some signals of the bandgap reference circuit shown;

[0018] Figure 3 is a schematic block diagram of a bandgap reference circuit according to an embodiment of the present disclosure;

[0019] Figure 4 is an exemplary circuit diagram of a bandgap reference circuit according to an embodiment of the present disclosure; and

[0020] Figure 5 is used for Figure 4 Waveform diagrams of some signals of the bandgap reference circuit shown.

[0021] In the drawings, reference numerals with the same last two digits correspond to the same elements. It should be noted that the elements in the drawings are schematic and not drawn to scale. DETAILED DESCRIPTION

[0022] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative work also fall within the scope of protection of the present disclosure.

[0023] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by a person skilled in the art to which the subject matter of the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the specification and the relevant art, and will not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, a statement that two or more parts are "connected" or "coupled" together shall mean that the parts are joined together directly or through one or more intermediate components.

[0024] In all embodiments of the present disclosure, since the source and drain of the metal oxide semiconductor (MOS) transistor are symmetrical, and the conduction current directions between the source and drain of the N-type transistor and the P-type transistor are opposite, in the embodiments of the present disclosure, the controlled middle end of the MOS transistor is referred to as the control electrode, and the remaining two ends of the MOS transistor are referred to as the first electrode and the second electrode, respectively. In addition, for the convenience of unified expression, in the context, the base of the bipolar transistor (BJT) is referred to as the control electrode, the emitter of the BJT is referred to as the first electrode, and the collector of the BJT is referred to as the second electrode. In addition, terms such as "first" and "second" are only used to distinguish one component (or a part of a component) from another component (or another part of a component).

[0025] Figure 1 An exemplary circuit diagram of a bandgap reference circuit 100 is shown. Figure 1 In the example of , transistor M1, transistor M2, transistor Q3, transistor Q4, transistor M5, resistor R1, resistor R2, resistor R3, resistor R4 and operational amplifier Amp constitute a bandgap reference core circuit. Transistor M6, transistor Q7, resistor R5 and resistor R6 constitute a compensation circuit. Among them, transistor M1, transistor M2 and transistor M5 are PMOS transistors. Transistor Q3, transistor Q4 and transistor Q7 are NPN bipolar transistors.

[0026] The current flowing through transistor M5 (i.e., the current flowing through transistor M1 or M2) is core current Icore. Core current Icore flows through resistor R4, thereby generating reference voltage Vref at the first end of resistor R4. Transistor M6 generates a mirror current of the current flowing through transistor M1. By setting the resistance values ​​of resistor R5 and resistor R6 to be equal, the currents flowing through resistor R5 and resistor R6 can be equal. Figure 1 I NL Indicates. Transistor Q3, transistor Q4 and transistor Q7 are NPN bipolar transistors, and their base emitter voltages have negative temperature coefficients. Since the two input terminals of the operational amplifier Amp are virtually shorted, the voltages at the two input terminals are equal. Therefore, the voltages across the resistor R2 have negative temperature coefficients. By setting the parameters of transistor Q3 and transistor Q4, the current I flowing through the resistor R2 can be PATA The current I flowing through the resistor R2 is PATA =Equal to the current flowing through transistor Q3 and transistor Q4 respectively. Since the base emitter voltage of transistor Q4 has a negative temperature coefficient, the current flowing through resistor R3 has a negative temperature coefficient. The current I flowing through transistor Q4 PATA The temperature coefficient of the current flowing through the resistor R3 is opposite to that of the current flowing through the transistor M1 or the transistor M2, so that the temperature coefficient of the current flowing through the transistor M1 or the transistor M2 is smaller than that of the current I PATA The temperature coefficient of transistor Q7 is smaller, so the current I CT The temperature coefficient is smaller.

[0027] According to the characteristics of bipolar transistors, the smaller the temperature coefficient of the current flowing through the bipolar transistor, the greater the temperature change rate of the base-emitter voltage of the bipolar transistor. Therefore, the temperature change rate of the base-emitter voltage of transistor Q7 is greater than the temperature change rate of the base-emitter voltage of transistor Q4. That is, as the temperature rises, the base voltage of transistor Q7 drops faster than the base voltage of transistor Q4. Therefore, the current I NL Has a positive temperature coefficient. Current INL The flow direction is Figure 1 Reference Figure 2 It can be seen that when the core current Icore has a negative temperature coefficient, the current I NL The purpose of curvature compensation can be achieved. Compared with the core current Icore before compensation, the core current Icorr after compensation changes less with the temperature T, and is therefore more stable.

[0028] However, due to differences in component materials and processes, the core current Icore of the bandgap reference circuit 100 may have a positive temperature coefficient. Figure 1 The bandgap reference circuit 100 shown can only compensate for the core current Icore (corresponding to the reference voltage with a negative temperature coefficient) before compensation. If the core current Icore (corresponding to the reference voltage with a positive temperature coefficient) with a positive temperature coefficient is to be compensated, it is necessary to change Icore to NL becomes a negative temperature coefficient or makes Figure 1 Medium current I NL The flow direction is reversed. This cannot be achieved by changing the resistance values ​​of resistors R5 and R6, so Figure 1 The structure shown cannot compensate for a reference voltage with a positive temperature coefficient.

[0029] The embodiments of the present disclosure provide a bandgap reference circuit capable of compensating a reference voltage with a positive temperature coefficient. Figure 3 A schematic block diagram of a bandgap reference circuit 300 according to an embodiment of the present disclosure is shown. The bandgap reference circuit 300 includes: a core current generating circuit 310, an operational amplifier Amp, an operational amplifier voltage control circuit 320, a current mirror circuit 330, a voltage control circuit 340, a current source circuit 350, a first shunt circuit 360, a second shunt circuit 370, and an output circuit 380.

[0030] The core current generating circuit 310 is coupled to the operational amplifier Amp, the operational amplifier voltage control circuit 320, the current mirror circuit 330 and the output circuit 380. The core current generating circuit 310 is also coupled to the first voltage terminal V1. The core current generating circuit 310 is configured to: G1 The core current Icore is generated by the first voltage V1 from the first voltage terminal V1. In some embodiments of the present disclosure, the core current Icore increases with the voltage V at the output terminal of the operational amplifier Amp. G1 decreases with the increase of the voltage V at the output of the op amp Amp. G1 's decrease and increase.

[0031] The current mirror circuit 330 is coupled to the core current generating circuit 310, the operational amplifier Amp, the operational amplifier voltage control circuit 320, the current mirror circuit 330, the voltage control circuit 340 and the output circuit 380. The current mirror circuit 330 is configured to: generate a mirror current I of the core current Icore CT , and provides a mirror current I to the voltage control circuit 340 via the first node N1. CT .

[0032] The voltage control circuit 340 is coupled to the current mirror circuit 330 and the first shunt circuit 360 via the first node N1. The voltage control circuit 340 is configured to: make the voltage of the first node N1 have a negative temperature coefficient, and CT To control the temperature change rate of the voltage of the first node N1. In some embodiments of the present disclosure, the mirror current I CT The temperature coefficient of the mirror current I CT The lower the temperature coefficient of φ, the higher the temperature change rate of the voltage of the first node N1.

[0033] The current source circuit 350 is coupled to the first shunt circuit 360 and the second shunt circuit 370 via the second node N2. The current source circuit 350 is configured to generate a constant current I SUM , and provides a constant current I to both the first shunt circuit 360 and the second shunt circuit 370 via the second node N2. SUM . Constant current I SUM The sum of the currents flowing through the first shunt circuit 360 and the second shunt circuit 370 is defined. In some embodiments of the present disclosure, the constant current I SUM Less than the core current Icore. Constant current I SUM The ratio to the core current Icore can be adjusted according to the actual application.

[0034] The first shunt circuit 360 is coupled to the current source circuit 350 and the second shunt circuit 370 via the second node N2. The first shunt circuit 360 is coupled to the current mirror circuit 330 and the voltage control circuit 340 via the first node N1. The first shunt circuit 360 is coupled to the first input terminal of the operational amplifier Amp. The first shunt circuit 360 is configured to: generate a current according to the voltage of the first node N1 and the constant current I SUM To generate the first branch I NT1 . First branch I NT1 The voltage flows into the operational amplifier voltage control circuit 320 through the first input terminal of the operational amplifier Amp.

[0035] The second shunt circuit 370 is coupled to the current source circuit 350 and the first shunt circuit 360 via the second node N2. The second shunt circuit 370 is coupled to two input terminals of the operational amplifier Amp. The second shunt circuit 370 is configured to: generate a current according to the voltage V+ at the first input terminal of the operational amplifier Amp and the constant current I SUM To generate the second branch I NT2 The temperature change rate of the voltage V+ at the first input terminal of the operational amplifier Amp is smaller than the temperature change rate of the voltage at the first node N1.

[0036] The operational amplifier voltage control circuit 320 is coupled to the two input terminals of the operational amplifier Amp, the core current generating circuit 310, the first shunt circuit 360, and the second shunt circuit 370. The operational amplifier voltage control circuit 320 is configured to: NT1 Control the voltage V+ of the first input terminal of the operational amplifier Amp, and according to the core current Icore and the second shunt current I NT2 Control the voltage V- at the second input terminal of the operational amplifier Amp.

[0037] The output circuit 380 is coupled to the core current generating circuit 310, the operational amplifier Amp, and the current mirror circuit 330. The output circuit 380 is configured to generate a reference voltage Vref according to the core current Icore.

[0038] Since the temperature change rate of the voltage V+ at the first input terminal of the operational amplifier Amp is smaller than the temperature change rate of the voltage at the first node N1, the second shunt I NT2 The temperature change rate is less than that of the first branch I NT1 The temperature change rate. NT1 With the second shunt I NT2 The sum of the constant current I SUM In the case of the first shunt I NT1 With the second shunt I NT2 As the temperature increases, the first shunt I NT1 Rising and the second shunt I NT2 Thus, the first branch I NT1 The voltage V+ at the first input terminal of the operational amplifier Amp can be increased, and the second shunt I NT2 This can reduce the voltage V- at the second input terminal of the op amp Amp. Therefore, the voltage V at the output terminal of the op amp Amp G1 Therefore, the bandgap reference circuit 300 according to the embodiment of the present disclosure can make the core current Icore with a positive temperature coefficient (corresponding to the reference voltage Vref with a positive temperature coefficient) compensated by a negative temperature coefficient term, thereby making the output of the bandgap reference circuit 300 more stable.

[0039] In some embodiments of the present disclosure, the bandgap reference circuit 300 may further include a startup circuit (in Figure 3 The start-up circuit 300 is used to provide a start-up current in the start-up phase. The start-up circuit 300 may stop providing the start-up current after the bandgap reference circuit 300 enters a stable working state. Since the start-up circuit is a circuit commonly provided in the bandgap reference circuit, it will not be further described in the present disclosure.

[0040] Figure 4 An exemplary circuit diagram of a bandgap reference circuit 400 according to an embodiment of the present disclosure is shown. The core current generating circuit 410 includes: a first transistor M1, and a second transistor M2. The control electrode of the first transistor M1 is coupled to the control electrode of the second transistor M2 and the output terminal of the operational amplifier Amp. The first electrode of the first transistor M1 is coupled to the first voltage terminal V1. The second electrode of the first transistor M1 is coupled to the first input terminal of the operational amplifier Amp. The first electrode of the second transistor M2 is coupled to the first voltage terminal V1. The second electrode of the second transistor M2 is coupled to the second input terminal of the operational amplifier Amp.

[0041] The operational amplifier voltage control circuit 420 includes: a third transistor Q3, a fourth transistor Q4, a first resistor R1, a second resistor R2, and a third resistor R3. Among them, the first end of the first resistor R1 is coupled to the first end of the second resistor R2 and the first input end of the operational amplifier Amp. The control electrode of the third transistor Q3 is coupled to the second electrode of the third transistor Q3 and the second end of the second resistor R2. The first electrode of the third transistor Q3 is coupled to the second voltage end V2. The control electrode of the fourth transistor Q4 is coupled to the second electrode of the fourth transistor Q4, the second input end of the operational amplifier Amp, and the first end of the third resistor R3. The first electrode of the fourth transistor Q4 is coupled to the second voltage end V2. The second end of the first resistor R1 is coupled to the second voltage end V2. The second end of the third resistor R3 is coupled to the second voltage end V2.

[0042] The output circuit 480 includes: a fifth transistor M5, and a fourth resistor R4. The control electrode of the fifth transistor M5 is coupled to the control electrode of the first transistor M1. The first electrode of the fifth transistor M5 is coupled to the first voltage terminal V1. The second electrode of the fifth transistor M5 is coupled to the first end of the fourth resistor R4 and the output voltage terminal Vref. The second end of the fourth resistor R4 is coupled to the second voltage terminal V2.

[0043] The current mirror circuit 430 includes: a sixth transistor M6. The control electrode of the sixth transistor M6 is coupled to the control electrode of the first transistor M1. The first electrode of the sixth transistor M6 is coupled to the first voltage terminal V1. The second electrode of the sixth transistor M6 is coupled to the first node N1.

[0044] The voltage control circuit 440 includes: a seventh transistor Q7, wherein a control electrode of the seventh transistor Q7 is coupled to a second electrode of the seventh transistor Q7 and the first node N1, and a first electrode of the seventh transistor Q7 is coupled to the second voltage terminal V2.

[0045] The current source circuit 450 includes an eighth transistor M8. The control electrode of the eighth transistor M8 is coupled to the control electrode of the first transistor M1. The first electrode of the eighth transistor M8 is coupled to the first voltage terminal V1. The second electrode of the eighth transistor M8 is coupled to the second node N2. Figure 4 In the example of , the current flowing through the eighth transistor M8 can be made smaller than the current flowing through the first transistor M1 by setting the ratio of the width-to-length ratio of the eighth transistor M8 to the width-to-length ratio of the first transistor M1. Figure 4 In an alternative embodiment of the example, the control electrode of the eighth transistor M8 may also be coupled to the bias voltage terminal. The current flowing through the eighth transistor M8 may be smaller than the current flowing through the first transistor M1 by setting the magnitude of the bias voltage from the bias voltage terminal. The current flowing through the eighth transistor M8 may be specifically set according to the magnitude of the current to be compensated. In some embodiments of the present disclosure, the current flowing through the eighth transistor M8 is less than one percent of the current flowing through the first transistor M1.

[0046] The first shunt circuit 460 includes a ninth transistor M9, wherein a control electrode of the ninth transistor M9 is coupled to the first node N1, a first electrode of the ninth transistor M9 is coupled to the second node N2, and a second electrode of the ninth transistor M9 is coupled to the first input terminal of the operational amplifier Amp.

[0047] The second shunt circuit 470 includes: a tenth transistor M10, wherein a control electrode of the tenth transistor M10 is coupled to a first input terminal of the operational amplifier Amp, a first electrode of the tenth transistor M10 is coupled to a second node N2, and a second electrode of the tenth transistor M10 is coupled to a second input terminal of the operational amplifier Amp.

[0048] exist Figure 4 In the example, a high voltage signal is input from the first voltage terminal V1, and the second voltage terminal V2 is grounded. The first transistor M1, the second transistor M2, the fifth transistor M5, the sixth transistor M6, the eighth transistor M8 to the tenth transistor M10 are PMOS transistors. The third transistor Q3, the fourth transistor Q4 and the seventh transistor Q7 are NPN bipolar transistors. The first input terminal of the operational amplifier Amp is the non-inverting input terminal of the operational amplifier Amp. The second input terminal of the operational amplifier Amp is the inverting input terminal of the operational amplifier Amp. The resistance value of the first resistor R1 is equal to the resistance value of the third resistor R3. Those skilled in the art should understand that based on the above-mentioned inventive concept, Figure 4 Variations of the circuit shown in the figure should also fall within the scope of protection of the present disclosure. In this variation, the transistor and the voltage terminal may also have the same Figure 4Examples of different setups are shown.

[0049] exist Figure 4 In the example, the third transistor Q3, the fourth transistor Q4 and the seventh transistor Q7 are NPN bipolar transistors, and their base emitter voltages have negative temperature coefficients. Since the two input terminals of the operational amplifier Amp are virtually shorted, the voltages at the two input terminals are substantially equal. Therefore, the voltages at both ends of the second resistor R2 have negative temperature coefficients. By setting the parameters of the third transistor Q3 and the fourth transistor Q4, the current I1 flowing through the second resistor R2 can have a positive temperature coefficient. Therefore, the current I2 flowing through the fourth transistor Q4 also has a positive temperature coefficient. Since the base emitter voltage of the fourth transistor Q4 has a negative temperature coefficient, the current flowing through the third resistor R3 has a negative temperature coefficient. The current I2 flowing through the fourth transistor Q4 is opposite to the temperature coefficient of the current flowing through the third resistor R3, so that the temperature coefficient of the current flowing through the first transistor M1 or the second transistor M2 is smaller than the temperature coefficient of the current I2, and therefore, the mirror current I flowing through the seventh transistor Q7 is smaller than the temperature coefficient of the current I2. CT The temperature coefficient is smaller.

[0050] According to the characteristics of bipolar transistors, the smaller the temperature coefficient of the current flowing through the bipolar transistor, the greater the temperature change rate of the base-emitter voltage of the bipolar transistor. Therefore, the temperature change rate of the base-emitter voltage of the seventh transistor Q7 (the voltage of the first node N1) is greater than the temperature change rate of the base-emitter voltage of the fourth transistor Q4 (the voltage V- at the second input terminal of the operational amplifier Amp). Due to the virtual short of the two input terminals of the operational amplifier Amp, the temperature change rate of the base-emitter voltage of the seventh transistor Q7 (the voltage of the first node N1) is greater than the temperature change rate of the voltage V+ at the first input terminal of the operational amplifier Amp. Reference Figure 5 It can be seen that as the temperature T increases, the voltage V N1 Since the gate of the ninth transistor M9 is coupled to the first node N1 and the gate of the tenth transistor M10 is coupled to the first input terminal of the operational amplifier Amp, the first shunt current I flowing through the ninth transistor M9 is NT1 The rising rate of change is greater than that of the second shunt current I flowing through the tenth transistor M10 NT2 The rising rate of change. NT1 and the second shunt I NT2 The sum is the constant current I SUM , the first branch I NT1 and the second shunt I NT2 The change in the ratio leads to the first split I NT1 Increased and second shunt I NT2 Thus, the first split flow I NT1The voltage V+ at the first input terminal of the operational amplifier Amp can be increased, and the second shunt I NT2 This can reduce the voltage V- at the second input terminal of the op amp Amp. Therefore, the voltage V at the output terminal of the op amp Amp G1 Increase, so that the core current Icore decreases Icp (reference Figure 5 ). According to the voltage-current relationship of the MOS transistor (the temperature coefficient of the current is the square of the temperature coefficient of the voltage), it can be seen that the current Icp has a nonlinear negative temperature coefficient.

[0051] By changing the voltage V at the output of the op amp Amp according to the temperature G1 Before compensating the core current Icore, the core current Icore of the bandgap reference circuit has a positive temperature coefficient. Figure 5 It can be seen that the compensated current Icorr (Icorr=Icore+Icp) can be obtained by superimposing the current Icp having a negative temperature coefficient on the core current Icore having a positive temperature coefficient. The compensated current Icorr is more stable than the core current Icore before compensation. Therefore, after compensation, the reference voltage Vref output from the bandgap reference circuit 400 is also more stable.

[0052] The embodiment of the present disclosure further provides a chip. The chip includes a bandgap reference circuit according to the embodiment of the present disclosure. The chip is, for example, a power management chip.

[0053] An embodiment of the present disclosure further provides an electronic device. The electronic device includes a chip according to an embodiment of the present disclosure. The electronic device is, for example, an intelligent terminal device, such as a tablet computer, a smart phone, etc.

[0054] In summary, the bandgap reference circuit according to the embodiment of the present disclosure performs high-order curvature temperature compensation on the reference voltage with a positive temperature coefficient by adjusting the voltage at the output terminal of the operational amplifier according to the temperature, thereby making the reference voltage output by the bandgap reference circuit more stable.

[0055] Unless the context clearly indicates otherwise, the singular form of the words used herein and in the appended claims includes the plural and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the words "comprise" and "include" are to be interpreted as inclusive rather than exclusive. Likewise, the terms "include" and "or" should be interpreted as inclusive unless such interpretation is expressly prohibited herein. Where the term "example" is used herein, particularly when it is located after a group of terms, the "example" is merely exemplary and illustrative and should not be considered exclusive or comprehensive.

[0056] Further aspects and scopes of adaptability become apparent from the description provided herein. It should be understood that various aspects of the present application can be implemented individually or in combination with one or more other aspects. It should also be understood that the description and specific embodiments herein are intended for purposes of illustration only and are not intended to limit the scope of the present application.

[0057] Several embodiments of the present disclosure are described in detail above, but it is obvious that those skilled in the art can make various modifications and variations to the embodiments of the present disclosure without departing from the spirit and scope of the present disclosure. The protection scope of the present disclosure is defined by the attached claims.

Claims

1. A bandgap reference circuit, comprising: A core current generating circuit, an operational amplifier, an operational amplifier voltage control circuit, a current mirror circuit, a voltage control circuit, a current source circuit, a first shunt circuit, a second shunt circuit, and an output circuit, Wherein, the core current generating circuit is configured to: generate the core current according to the voltage at the output terminal of the operational amplifier and the first voltage from the first voltage terminal; The current mirror circuit is configured to: generate a mirror current of the core current, and provide the mirror current to the voltage control circuit via a first node; The voltage control circuit is configured to: make the voltage of the first node have a negative temperature coefficient, and control the temperature change rate of the voltage of the first node according to the mirror current; The current source circuit is configured to: generate a constant current, and provide the constant current to both the first shunt circuit and the second shunt circuit via a second node; The first shunt circuit is configured to: generate a first shunt according to the voltage of the first node and the constant current; The second shunt circuit is configured to: generate a second shunt according to the voltage at the first input terminal of the operational amplifier and the constant current; The operational amplifier voltage control circuit is configured to: control the voltage of the first input terminal of the operational amplifier according to the core current and the first shunt, and control the voltage of the second input terminal of the operational amplifier according to the core current and the second shunt; The output circuit is configured to: generate a reference voltage according to the core current; The temperature change rate of the voltage at the first input terminal of the operational amplifier is smaller than the temperature change rate of the voltage at the first node.

2. The bandgap reference circuit according to claim 1, wherein: The core current generating circuit comprises: a first transistor and a second transistor, Wherein, the control electrode of the first transistor is coupled to the control electrode of the second transistor and the output terminal of the operational amplifier, the first electrode of the first transistor is coupled to the first voltage terminal, and the second electrode of the first transistor is coupled to the first input terminal of the operational amplifier; A first electrode of the second transistor is coupled to the first voltage terminal, and a second electrode of the second transistor is coupled to the second input terminal of the operational amplifier.

3. The bandgap reference circuit according to claim 1, wherein: The operational amplifier voltage control circuit includes: a third transistor, a fourth transistor, a first resistor, a second resistor, and a third resistor. Wherein, the first end of the first resistor is coupled to the first end of the second resistor and the first input end of the operational amplifier; The control electrode of the third transistor is coupled to the second electrode of the third transistor and the second end of the second resistor, and the first electrode of the third transistor is coupled to the second voltage end; The control electrode of the fourth transistor is coupled to the second electrode of the fourth transistor, the second input terminal of the operational amplifier and the first terminal of the third resistor, and the first electrode of the fourth transistor is coupled to the second voltage terminal; The second end of the first resistor is coupled to the second voltage end; The second end of the third resistor is coupled to the second voltage end.

4. The bandgap reference circuit according to claim 2, wherein: The output circuit includes: a fifth transistor and a fourth resistor, Wherein, the control electrode of the fifth transistor is coupled to the control electrode of the first transistor, the first electrode of the fifth transistor is coupled to the first voltage terminal, and the second electrode of the fifth transistor is coupled to the first terminal of the fourth resistor and the output voltage terminal; The second terminal of the fourth resistor is coupled to the second voltage terminal.

5. The bandgap reference circuit according to claim 2 or 4, wherein: The current mirror circuit comprises: a sixth transistor, The control electrode of the sixth transistor is coupled to the control electrode of the first transistor, the first electrode of the sixth transistor is coupled to the first voltage terminal, and the second electrode of the sixth transistor is coupled to the first node.

6. The bandgap reference circuit according to any one of claims 1 to 4, wherein: The voltage control circuit comprises: a seventh transistor, The control electrode of the seventh transistor is coupled to the second electrode of the seventh transistor and the first node, and the first electrode of the seventh transistor is coupled to the second voltage terminal.

7. The bandgap reference circuit according to claim 2 or 4, wherein: The current source circuit comprises: an eighth transistor, The control electrode of the eighth transistor is coupled to the control electrode of the first transistor, the first electrode of the eighth transistor is coupled to the first voltage terminal, and the second electrode of the eighth transistor is coupled to the second node.

8. The bandgap reference circuit according to any one of claims 1 to 4, wherein: The first shunt circuit comprises: a ninth transistor, The control electrode of the ninth transistor is coupled to the first node, the first electrode of the ninth transistor is coupled to the second node, and the second electrode of the ninth transistor is coupled to the first input terminal of the operational amplifier.

9. The bandgap reference circuit according to any one of claims 1 to 4, wherein: The second shunt circuit comprises: a tenth transistor, The control electrode of the tenth transistor is coupled to the first input terminal of the operational amplifier, the first electrode of the tenth transistor is coupled to the second node, and the second electrode of the tenth transistor is coupled to the second input terminal of the operational amplifier.

10. A bandgap reference circuit, comprising: first to tenth transistors, first to fourth resistors, and an operational amplifier, Wherein, the control electrode of the first transistor is coupled to the control electrode of the second transistor and the output terminal of the operational amplifier, the first electrode of the first transistor is coupled to the first voltage terminal, and the second electrode of the first transistor is coupled to the first input terminal of the operational amplifier, the first terminal of the first resistor, and the first terminal of the second resistor; A first electrode of the second transistor is coupled to the first voltage terminal, and a second electrode of the second transistor is coupled to the second input terminal of the operational amplifier, a first terminal of the third resistor, and a control electrode and a second electrode of the fourth transistor; A control electrode of the third transistor is coupled to the second electrode of the third transistor and the second end of the second resistor, and a first electrode of the third transistor is coupled to the second voltage end; The first electrode of the fourth transistor is coupled to the second voltage terminal; The second end of the first resistor is coupled to the second voltage end; The second end of the third resistor is coupled to the second voltage end; A control electrode of a fifth transistor is coupled to the control electrode of the first transistor, a first electrode of the fifth transistor is coupled to the first voltage terminal, and a second electrode of the fifth transistor is coupled to the first terminal of the fourth resistor and the output voltage terminal; The second end of the fourth resistor is coupled to the second voltage end; A control electrode of a sixth transistor is coupled to the control electrode of the first transistor, a first electrode of the sixth transistor is coupled to the first voltage terminal, and a second electrode of the sixth transistor is coupled to the control electrode and the second electrode of the seventh transistor; The first electrode of the seventh transistor is coupled to the second voltage terminal; A control electrode of an eighth transistor is coupled to the control electrode of the first transistor, a first electrode of the eighth transistor is coupled to the first voltage terminal, and a second electrode of the eighth transistor is coupled to the first electrode of the ninth transistor and the first electrode of the tenth transistor; The control electrode of the ninth transistor is coupled to the second electrode of the seventh transistor, and the second electrode of the ninth transistor is coupled to the first input terminal of the operational amplifier; A control electrode of the tenth transistor is coupled to the first input terminal of the operational amplifier, and a second electrode of the tenth transistor is coupled to the second input terminal of the operational amplifier.

Images