Computer system, memory device and control method based on wafer stacking architecture

Abstract

A computer system based on wafer stack architecture is disclosed. The computer system includes a memory device and a logic circuit layer combined into a wafer stack. The memory device includes a memory array and a line driver. The memory array includes a common line and a plurality of memory cells connected to the common line. The line driver is connected to the common line and drives the memory cells. The logic circuit layer includes a plurality of connection pads for transmitting signals and a delay controller. The delay controller adjusts the number of memory cells connected to the common line through the connection pads to dynamically change the delay characteristics of the memory array. A memory device and a memory control method are also disclosed.

Description

Technical Field

[0001] This application relates to a memory device, and more particularly to a memory architecture whose latency characteristics can be changed according to application requirements, and a computer system implemented using said memory architecture and wafer stacking technology. Background Technology

[0002] In this era, the application of artificial intelligence and blockchain has become a new business opportunity. Blockchain can be widely used in applications such as smart contracts, digital identity, and the sharing economy.

[0003] However, some blockchain platforms frequently alter the blockchain algorithm for various security considerations or vulnerability patching. In addition to increasing computational complexity, they often make special designs to deliberately reduce the computational efficiency of application-specific integrated circuits (ASICs), such as increasing memory throughput requirements or storage capacity requirements.

[0004] Therefore, blockchain server developers must adapt their hardware architecture to accommodate changes in blockchain algorithms. However, the algorithms proposed by these crowdfunding platforms are likely to be constantly updated. Therefore, developing a way to enable the same blockchain server hardware to flexibly change parameters to adapt to new algorithms remains an area for improvement. Summary of the Invention

[0005] This application proposes a computer system that can flexibly adapt to changing requirements of blockchain algorithms. In one embodiment of the computer system, a wafer-on-wafer technique is employed, stacking the wafer containing the memory device and the wafer containing the core logic circuitry into a three-dimensional structure. This approach eliminates the need for extra area between the two wafers, using thousands of interconnect pads directly as the signal transmission path. Since the number of transmission lines is no longer limited by planar design, a large number of dedicated wirings can be used to address data transmission efficiency issues.

[0006] The memory device of this application is configured on a dedicated memory wafer, which may contain multiple memory arrays (BANK). Each memory array mainly consists of a common line and multiple memory cells. The common line, in this embodiment, can be a synonym for data line or address line, and each common line is connected to one row or column of the memory cells. A memory cell refers to the basic unit for storing bit information, which is typically activated by an address signal and read or written to by a data signal.

[0007] The memory device also includes a line driver connected to the shared line for driving the memory cells. The line driver can be a synonym for a data driver or an address decoder.

[0008] As described above, the computer system includes a logic circuit layer that is combined with the memory crystal layer to form a wafer-on-wafer stack. This stack includes multiple connection pads for transmitting signals.

[0009] This application configures a latency controller in the logic circuit layer of a computer system, which is connected to the memory array through the connection pad. Its design aims to flexibly adjust the number of memory cells connected on the shared line to dynamically change the latency characteristics of the memory array.

[0010] In a further embodiment, each memory array is configured with multiple multiplexers. Each multiplexer is spaced a specific number of rows or columns apart. These multiplexers define a memory array as multiple memory regions, each containing a specific number of memory cells in rows or columns. In other words, a multiplexer is configured at every two adjacent memory regions and is connected to the line driver via a dedicated line.

[0011] When the delay controller activates a multiplexer by transmitting a control signal through a connection pad, it will disconnect the common line into a first segment and a second segment, and connect the second segment to the dedicated line.

[0012] Since the shared line originally connected multiple memory units in series, after being broken into two segments, it logically forms two sub-arrays. In other words, the memory area corresponding to the first segment forms a first sub-array, and the memory area corresponding to the second segment forms a second sub-array. For ease of implementation and management, the breaking method in this embodiment can be bisection. Therefore, a memory array can be divided into two equal-sized sub-arrays, and the two sub-arrays can be further divided into four sub-arrays through more multiplexers, and so on.

[0013] In one specific implementation, changing the way the memory array dimensions are changed, i.e., the way the subarrays are formed, can be by breaking the shared data line into two shorter data lines. The line driver includes a data driver. The shared line here represents one or more shared data lines, each connecting the data driver to a corresponding column of memory cells in the memory unit, used to transmit data signals to the memory cells. After the multiplexer is activated, because the shared data line is broken, the second subarray no longer shares the shared data line of the first subarray. Instead, the multiplexer provides a separate dedicated line to transmit data signals to the memory cells in the second subarray. This approach reduces the number of memory cells on the shared line, thereby reducing the capacitive load and accelerating the response speed of the data drive.

[0014] As for the second subarray, since the data lines are connected to the data driver via dedicated lines, it independently receives different data signal sources and also enjoys the same low-load, high-speed effect. Furthermore, the address lines of the second subarray can be changed to share the address lines of the first subarray. This effectively changes the original memory array dimensions, doubling the number of data lines (array width) and halving the number of address lines (array height). The memory device originally contains multiple shared address lines, each connecting the address decoder to a corresponding row of memory cells in the memory array, used to transmit the address signal of the memory cell. The line driver includes an address decoder that connects to each row of memory cells in the memory array through the shared address lines. In practice, after the multiplexer is activated, the address decoder, according to the control signal, causes the memory cells in the second subarray to share the shared address lines of the first subarray, or to synchronously drive the first and second subarrays using the same address signal. In other words, the shared address lines of the corresponding rows in the second and first subarrays receive the same address signal.

[0015] In another specific implementation, the way the memory array dimension is changed, i.e., the way the subarrays are formed, can also be by breaking the shared address lines into two shorter address lines. In this case, the aforementioned shared lines represent one or more shared address lines used to transmit the address signals of the memory cells. After the multiplexer is activated, the memory cells in the second subarray use the dedicated lines to transmit address signals. Simultaneously, the address decoder, according to the control signal, causes the memory cells in the second subarray to share the shared data lines of the first subarray, or to use the same data signals to drive both the first and second subarrays. Because the memory cells in the second subarray use different address lines than those in the first subarray, the memory array dimension is effectively halved in terms of data bits (array width) and doubled in terms of the number of address lines (array height).

[0016] In a further embodiment, the logic layer further includes a memory controller coupled to the memory array via the connection pad. A kernel connects the memory controller and the latency controller for executing an application. The kernel can, based on application conditions required by the application, configure the multiplexer in the memory array via the latency controller, causing the memory array to change its dimension—that is, to be divided into two power-multiple subarrays, and then reassembled into a new array dimension that meets the application conditions. When executing the program, the kernel can use the reassembled memory array via the memory controller.

[0017] In a further embodiment, the application conditions include the response time required by the application. In the embodiment where the data line is disconnected, the more multiplexers the latency controller initiates, the shorter the response time of the newly formed memory array.

[0018] This application also proposes a memory control method applied to the aforementioned computer system and memory device. When an application is executed by a kernel, the kernel, based on application conditions required by the application, configures the multiplexer in the memory array through the latency controller, causing the memory array to be divided into two or more subarrays that meet the application conditions, and uses the memory subarrays through the memory controller when executing the application.

[0019] In summary, this application proposes a memory architecture that can flexibly adjust the array dimensions based on wafer stacking technology, enabling blockchain server products to adapt to the needs of future algorithms. Attached Figure Description

[0020] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0021] Figure 1 This is an embodiment of the computer system described in this application.

[0022] Figure 2 This is an embodiment of the memory device of this application.

[0023] Figures 3 to 5 This is an embodiment of the memory array and multiplexer of this application.

[0024] Figure 6 This is a further embodiment of the memory device 112 of this application.

[0025] Figures 7 to 8 These are various embodiments of memory arrays described in this application.

[0026] Figure 9 This is an embodiment of the memory layer 600 in the computer system 700 of this application.

[0027] Figure 10 This is a further embodiment of the computer system of this application.

[0028] Figure 11 This is a further embodiment of the memory array and multiplexer of this application.

[0029] Figure 12 This is another embodiment of the memory array and multiplexer of this application.

[0030] Figure 13 This is a flowchart of the memory control method of this application. Detailed Implementation

[0031] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0032] Figure 1 This is an embodiment of the 3D wafer product 100 of this application. The 3D wafer product 100 is composed of at least one memory transistor layer 110, one logic circuit layer 120, and one substrate 130 stacked together. The substrate 130 provides basic support and additional wiring space. Multiple connection pads 102 or 104 are configured between each layer to provide signal channels. The 3D wafer product 100 of this embodiment is a semi-finished product of a computer system 700, which, after dicing, can produce multiple independently operating computer systems 700. Figure 1 As shown, each computer system 700 may include a plurality of memory devices 112 and a plurality of logic circuits 122, possessing the same three-dimensional wafer structure. In other words, the memory devices 112 and logic circuits 122 included in each computer system 700 are pre-laid in the memory crystal layer 110 and the logic circuit layer 120, and then fabricated in a three-dimensional structure by stacking wafers. In the three-dimensional structure, the circuit wires between chipsets do not need to occupy extra area, and thousands of connection pads 102 and 104 can be used directly as signal transmission paths, effectively solving the data transmission efficiency problem, thereby realizing the computer system 700 of this application.

[0033] Figure 2This is an embodiment of the memory device of this application. The memory device 112 of this application is disposed on a memory-dedicated memory crystal layer 110. Its manufacturing can be modular, and each memory device 112 may contain multiple memory arrays 200, or memory matrices (BANK). The operation of each memory matrix can be controlled by an array selection signal #SL. Each memory array 200 mainly consists of multiple memory cells 202. The memory cells 202 are arranged in multiple rows and columns, with each row sharing an address line to receive address signals numbered R0 to Rn. Each column shares a data line to transmit data signals numbered B0 to Bn. In other words, each shared line is correspondingly connected to one row or one column of the memory cells 202. A memory cell 202 refers to a basic unit for storing bit information, which is usually turned on by address signals and read or written by data signals. The address line is connected to an address decoder 210 to transmit the address signal 214 generated by the address decoder, so that one or more rows of memory cells 202 are turned on. The data line is connected to a data driver 220 for transmitting data written to or read from the memory unit 202. Figure 2 The disclosed architecture is merely an example. In actual manufacturing, the number of memory array 200, address decoder 210, and data driver 220 is not limited to one, and the connection relationship between them is not limited to one-to-one or many-to-many. In summary, the address decoder 210 and data driver 220 in the memory device are line drivers. The connected data lines and address lines are shared lines, driving multiple memory cells 202 in a mesh-like interlaced manner.

[0034] Figures 3 to 5 This is an embodiment of the memory array 200 and multiplexer 302 of this application. To achieve the effect of dynamically adjusting latency characteristics, this embodiment configures multiple multiplexers 302 in each memory array 200. Each multiplexer 302 is separated by a specific number of rows or columns. These multiplexers 302 can define a memory array 200 as multiple memory regions 310, each memory region 310 containing memory cells 202 with a specific number of rows or columns. Figure 3 For example, a multiplexer 302 is configured at the junction of every two adjacent memory regions 310.

[0035] Figure 4 This displays the operation of the multiplexer 302 upon startup. The multiplexer 302 is connected to the data driver 220 via a dedicated line 224. When a control signal #S is received from... Figure 1When the logic circuit layer 120 shown is transmitted to the multiplexer through one of the connection pads 102, the shared data line 222 is disconnected at the location of the multiplexer 302, so that the upper and lower memory regions 310 no longer share the same data line 222. The data line 222 is divided into a first segment in the upper memory region 310 and a second segment in the lower memory region 310. In this embodiment, the upper memory region 310 can continue to receive the original data signals B0 to B7, but because the number of shared memory cells on the first segment is reduced, the capacitive load is significantly reduced, so the latency of the memory region 310 can be effectively shortened, that is, the response speed is accelerated. The multiplexer 302 reconnects the second segment of the lower memory region 310 to a dedicated line 224, so that the lower memory region 310 continues to be controlled by the data driver 220. For example, the multiplexer 302 continues to receive data signals numbered B0 to B7 from the data driver 220 through the dedicated line 224. Since the number of shared memory units 202 on the second segment is less than before, the effect of reducing latency is also achieved.

[0036] Figure 5 This illustrates another specific implementation method when the multiplexer 302 is started. This embodiment, in addition to changing the latency characteristics of the memory array 200, can also change the dimensions of the memory array 200. The subarrays are formed by breaking the shared data line 222 into two shorter segments. In other words, since the data line 222 originally connected multiple memory cells 202 in series, after being broken into two segments, logically two subarrays are formed. The memory region 310 corresponding to the first segment forms a first subarray, and the memory region 310 corresponding to the second segment forms a second subarray. After the multiplexer 302 is started, since the shared data line 222 is broken, the second subarray no longer shares the shared data line 222 of the first subarray. Instead, the multiplexer 302 provides a dedicated line 224 to transmit data signals to the memory cells 202 in the second subarray. In this embodiment, through improvements to the data driver 220, the data signals transmitted through the dedicated line 224 are no longer numbered B0 to B7, but are instead newly added B8 to B15. Furthermore, this embodiment can improve the address decoder so that the second subarray can share the address lines of the first subarray, or receive the same address signals R0 to R3 as the first subarray.

[0037] In other words, the address decoder 230 can, according to the control signal #S, enable the memory cells in the second subarray to share the common address lines of the first subarray, or use the same address signal to synchronously drive the first and second subarrays. This effectively changes the dimensions of the original memory array 200. The number of data lines (array width) doubles from 8 to 16, while the number of address lines (array height) is halved from 8 to 4. Although this embodiment uses an 8x8 array as an example to illustrate the partitioning and reorganization of the memory array 200, it is understood that in actual manufacturing, each memory array 200 can be a large array with a capacity of hundreds of megabits.

[0038] Figure 6 This is a further embodiment of the memory device 112 of this application. A memory array 200 may be configured with n multiplexers 402#1 to 402#n, dividing the memory array 200 into n memory regions 410#1 to 410#n. When the multiplexers are not activated, the memory array 200 maintains a conventional operating mode. In addition to transmitting data signals through the conventional common data line 222, the data driver 220 also provides multiple dedicated lines 224 connected to the multiplexers 402#1 to 402#n. The memory device 112 further includes an address decoder 230, which transmits address signals #A to each memory region 410#1 to 410#n through address lines 232. Although the data lines 222 and address lines 232 are represented by single lines, it is understood that in practice, multiple lines may be included, each connecting to each row or column in the memory array. Similar to traditional designs, each memory cell in memory array 200 is connected to a common reference voltage, or ground line #Gnd.

[0039] In practice, each multiplexer can be activated upon receiving a control signal #S. For example, the control signal #S can be a power of two, such as 2, 4, 8, or 16, instructing multiplexers 402#1 to 402#n to divide the memory array 200 into a corresponding number of subarrays. When the control signal #S is 2, it indicates that one multiplexer is needed to divide the memory array 200 into two subarrays. In this case, the multiplexer numbered n / 2 in the memory array 200 can be activated in response to the control signal to achieve this. Similarly, when the control signal #S is 4, it indicates that three multiplexers are needed to divide the memory array 200 into four subarrays. In this case, multiplexers numbered n / 4, 2n / 4, and 3n / 4 in the memory array 200 can be activated in response to the control signal #S to achieve the effect of dividing the array into four blocks. In this design, the value of n can be preset as a power of two to facilitate the implementation of the above partitioning method.

[0040] In another implementation, the control signal #S can be used to determine how many memory regions need to be segmented. For example, when the value of control signal #S is 1, it means that each memory region needs to be isolated, that is, all multiplexers 402#1 to 402#n are activated, making the memory array 200 into n subarrays, each containing one memory region. When the value of control signal #S is 2, it means that the memory array 200 needs to be divided into groups of two memory regions. Therefore, multiplexers numbered 2, 4, 6, 8, etc., which are divisible by 2, will be activated in response to the control signal, making the memory array into n / 2 subarrays, each containing two memory regions.

[0041] In a further implementation, the partitioning of the memory array 200 can be more flexible. For example, each multiplexer can receive different control signals to determine whether to start. Therefore, the actual possible partitioning possibilities are not limited to the above embodiments.

[0042] exist Figure 6 In this embodiment, the data driver 220 and the address decoder 230 can be further improved to change the data signal provided to each memory region or the address signal provided to each memory region according to the segmentation of the control signal #S. This approach is similar to... Figure 5 As described in the embodiments, the memory array 200 can be logically and dynamically changed in length and width dimensions.

[0043] Figures 7 to 8 These are various embodiments of memory arrays described in this application. Figure 7 Display in Figure 6 The memory array 200 is divided and reorganized by a multiplexer to form a memory array 500a. Originally, each memory region 410#1 to 410#n had W columns of memory cells (width) and H rows of address lines (height). After dimensional reorganization, a memory array 500a containing multiple sub-arrays 502a is formed. All sub-arrays 502a share the H rows of address lines, and the bit width is expanded to nW columns. This means the multiplexer needs to provide dedicated lines (nW lines) for connecting the nW columns of memory cells to the data driver. With the support of wafer stacking technology, the implementation difficulties can be easily overcome. Figure 7 In this embodiment, the original memory array dimension might be nH*W, but it is reorganized into H*nW. Therefore, when the data lines of each column of memory cells are driven, the capacitive load that needs to be overcome is reduced by a factor of n, making the response speed of the memory cells faster.

[0044] Figure 8 Display in Figure 6The memory array 500b is generated after the memory array 200 is divided and reorganized by a multiplexer. Originally, each memory region 410#1 to 410#n had W columns of memory cells (width) and H rows of address lines (height). Here, the dimensions are reorganized by starting a multiplexer every two memory blocks, forming a memory array 500b containing multiple sub-arrays 502b. Each sub-array 502b contains two memory regions, 2H rows high and W columns wide. Sub-arrays 502a within the memory array 500b share 2H rows of address lines. More specifically, through improvements to the address decoder 230, it is possible to flexibly adjust the memory array 500b based on its division, allowing all memory sub-arrays 502b to share the same address lines, or for the address decoder 230 to transmit the same address signals to these memory sub-arrays. The bit width of the memory array 500b is extended to nW / 2 columns. This means the multiplexer needs to provide a corresponding number of dedicated lines to connect to the data driver for each of the nW / 2 columns of memory cells. Figure 8 Implementation examples and Figure 7 In comparison, due to the larger height (number of address rows) of subarray 502b, the latency is not as good. Figure 7 The architecture is similar, but requires fewer dedicated lines. This illustrates that the architecture of this embodiment can be flexibly adjusted to meet different needs and trade-offs.

[0045] Figure 9 This illustrates a further embodiment of the memory layer 600 in the computer system 700. Based on the concepts described in the foregoing embodiments, the memory layer 600 can be from... Figure 1 One region of the computer system cut out from the memory crystal layer 110 contains multiple memory devices 510a to 510d. Each memory device 510a to 510d can be configured with different latency characteristics by applying various control signals. For example, a computer system 700 can pre-configure the configuration of each memory device 510a to 510d in the firmware, and configure the memory devices 510a to 510d individually through control signals #S1 to #S4 after power-on, and then load the operating system. In a further embodiment, the computer system 700 of this application can also be designed to allow dynamic and seamless changes in memory latency characteristics during operation. For example, when loading an application, the application's memory latency requirements are determined, and control signals are dynamically issued to change the dimensions of the memory devices, thereby changing the latency characteristics.

[0046] Figure 10 This is a further embodiment of the computer system 700 of this application. Figure 1 The 3D wafer product 100 shown, after completing the wafer stacking process, undergoes a further wafer dicing process to form multiple computer systems 700. The memory layer 600 displays [the following information]... Figure 9The memory devices 510a to 510c are configured in the embodiments. A system layer 620 is stacked with the memory layer 600. The system layer 620 is from... Figure 1 The logic circuit layer 120 is divided into layers containing various logic circuits essential to the computer architecture, such as the core 616 and memory controllers 614a to 614c. Each memory controller 614a to 614c is connected to the memory devices 510a to 510c in the memory layer 600 through an interface module 612a to 612c. The interface module is an interface specifically designed to ensure data transmission, commonly known as the physical layer interface (PHY). Figure 1 Similarly, signals are transmitted between the stacked memory layer 600 and system layer 620 via multiple connection pads (not shown). System layer 620 is also secured to substrate 130 via multiple connection pads 104. Substrate 130 provides basic support and additional wiring space. Memory controllers 614a to 614c provide address signals #A to the memory devices 510a to 510c via these interface modules 612a to 612c and connection pads to access data signals #D. This computer system 700 architecture is merely illustrative. The number of memory controllers, interface modules, and memory devices configured is not limited to three groups. Core 616 can be a multi-core architecture.

[0047] exist Figure 10 In the computer system 700, a latency controller 602 is configured and connected to the memory layer 600 via one or more connection pads, transmitting control signals #S to the memory devices 510a to 510c. These memory devices 510a and 510c, as described in the previous embodiments, can flexibly adjust the number of memory cells connected on the common lines in each memory array according to the control signal #S, thereby dynamically changing the latency characteristics of the memory array. The latency controller 602 can be controlled by the kernel 616. When the kernel 616 is executing an application, it can determine the latency requirements of the application in real time and instruct the latency controller 602 to adjust the memory devices 510a to 510c. For example, changing the dimension of the memory array can divide each memory array into two powers of subarrays and then reassemble them into a new array dimension that meets the conditions of the application. When executing the program, the kernel 616 can adaptively use the memory devices 510a to 510c that meet the application requirements through the memory controllers 614a to 614c.

[0048] Figure 11This is a further embodiment of the memory array and multiplexer of this application. Here, memory cells 202a and 202b are used to illustrate how the multiplexer 402 reduces capacitive load on the data line. The basic logic in a memory cell is that a switch controls a capacitor, charging or discharging the capacitor to represent one bit of data. Address lines transmitting address signals R0 and R1 are connected in series to the gates of memory cells 202a and 202b. Data lines for transmitting data signal B0 are connected in series to one end of the switch in memory cells 202a and 202b. When the multiplexer 402 is not activated, the first segment 222a and the second segment of the data line are connected as a single segment, allowing memory cells 202a and 202b to share the same data line to receive data signal B0 and operate normally. When the multiplexer 402 is activated by the control signal #S, the switch in the multiplexer 402 disconnects the second segment 222b from the first segment 222a and reconnects the second segment 222b to a dedicated line 224. The dedicated line is connected to the data driver 220, allowing memory cell 202b to still receive data signals. In this architecture, since the first segment 222a and the second segment 222b each drive half the number of memory cells, the delay effect caused by the load capacitance can be reduced, thus improving the memory's response speed. Although this embodiment only describes one column and two rows of memory cells, it is understood that the multiplexer 402 can actually be multiple, inserted in the middle of multiple rows in a memory array, simultaneously controlling the sharing and disconnection of multiple data lines. The data signal transmitted on the dedicated line 224 is not limited to being the same as the data signal of the first segment 222a. The data driver 220 can also be improved so that memory cells 202a and 202b receive different data signals after disconnection. Conversely, the address decoder can also be improved so that the address lines that originally transmitted address signals R0 and R1 separately share the same address signal, such as R0, after the multiplexer 402 is activated, allowing memory cells 202a and 202b to be turned on simultaneously. In this configuration, memory cells 202a and 202b can logically be considered as different bits on the same row. That is, the width and height dimensions of the memory array change from the original 1*2 to 2*1. This architecture is highly effective in flexibly adapting to different latency requirements. The actual circuit structures of the aforementioned memory cells 202a and 202b are already well-established technologies; therefore, this embodiment is merely illustrative and does not limit the detailed implementation.

[0049] Figure 12The illustration shows an embodiment of setting up a multiplexer on the address line. The aforementioned embodiment mainly describes how to shorten the shared data line. However, the implementation of this application can also start from the address line. Changing the memory array dimension, i.e., the formation of the first subarray 810 and the second subarray 820, can also be done by breaking the shared address line into two shorter address lines. In this case, multiple shared address lines transmit the address signals R0 to R7 of the memory cell 202. After the multiplexer 802 receives the control signal #S and starts, it transfers the multiple address lines that were broken in the second subarray 820 to a dedicated line and connects to the address decoder. Further, the data driver 220 and the address decoder 230 can also be improved so that, according to the control signal #S, the second subarray 820 shares the shared data line of the first subarray 810, or uses the same data signal to drive the first subarray 810 and the second subarray 820. At the same time, the second subarray 820 uses a different address signal source than the first subarray, such as R8 to R15 (not shown). In this way, logically, a new memory array is created, with a dimension that is half the original number of data bits (array width) and a doubling of the number of address lines (array height). Figure 11 This approach, by shortening the address lines, reduces the drive load on the address lines and also has the effect of changing the latency characteristics of the memory array.

[0050] Figure 13 This is a flowchart of the memory control method of this application. This application also proposes a memory control method applied to the aforementioned computer system and memory device. In step 901, when a kernel executes an application, the kernel instructs a latency controller to issue a control signal based on an application condition required by the application. In step 903, the multiplexer in the memory array, according to the control signal, causes the memory array to change its dimensions. For example, the memory array is divided into two or more subarrays that meet the application conditions. In step 905, the kernel uses the memory subarrays through the memory controller when executing the application.

[0051] In summary, this application proposes a memory architecture that can flexibly adjust the array dimensions based on wafer stacking technology, enabling blockchain server products to adapt to the needs of future algorithms.

[0052] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0053] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. A computer system based on a wafer stacking architecture, characterized in that, Include: A memory crystal layer comprising multiple memory devices, wherein each memory device includes: A memory array comprising a common line and multiple memory cells, the common line connecting the memory cells, and the memory array comprising: Multiple memory regions, each containing a specific number of rows or columns of memory units; Multiple multiplexers are configured in pairs adjacent to each other in the memory region; A line driver, connected to the shared line, is used to drive the memory unit; The logic circuit layer, combined with the memory crystal layer to form a wafer stack, includes: Multiple connecting pads are used to transmit signals; as well as A latency controller, connected to the memory array via the connection pad, is used to adjust the number of memory cells connected on the common line to dynamically change the latency characteristics of the memory array; Each of the multiplexers is connected to the line driver via a dedicated line; When the delay controller activates the multiplexer by transmitting a control signal through the connection pad, the common line is disconnected into a first segment and a second segment, and the second segment is connected to the dedicated line; the memory area corresponding to the first segment forms a first subarray; the memory area corresponding to the second segment forms a second subarray.

2. The computer system based on wafer stacking architecture as described in claim 1, characterized in that, in: The line driver includes a data driver; The shared line includes multiple shared data lines, each of which connects the data driver and a corresponding column of memory cells in the memory unit for transmitting data signals. as well as After the multiplexer is activated, the memory cells in the second subarray use the dedicated line to transmit data signals.

3. The computer system based on wafer stacking architecture as described in claim 2, characterized in that, in: The line driver includes an address decoder; The memory device further includes multiple common address lines, each common address line connecting the address decoder and a corresponding row of memory cells in the memory unit, for transmitting address signals; as well as After the multiplexer is activated, the address decoder, according to the control signal, causes the shared address lines of the corresponding rows in the second subarray and the first subarray to receive the same address signal.

4. The computer system based on wafer stacking architecture as described in claim 1, characterized in that, The logic circuit layer further includes: The memory controller is coupled to the memory array via the connection pads; and The kernel, connecting the memory controller and the latency controller, is used to execute applications; wherein: The kernel, based on the application conditions required by the application, configures the multiplexer in the memory array through the latency controller, causing the memory array to be divided into two or more sub-arrays that meet the application conditions, and uses the memory array through the memory controller when the application is executed.

5. The computer system based on wafer stacking architecture as described in claim 4, characterized in that, in: The application conditions include the response time required by the application; and The shorter the required response time, the more multiplexers the delay controller can activate.

6. A memory control method, applied to a computer system based on a wafer stacking architecture as described in claim 4, characterized in that, Include: Execute the application; The kernel, based on the application requirements, configures the multiplexer in the memory array via the latency controller, dividing the memory array into two or more subarrays that meet the application requirements. When executing the application, the kernel uses the memory array via the memory controller, wherein: The application conditions include the response time required by the application.

7. A memory device, disposed in a memory crystal layer and integrated with a logic circuit layer to form a computer system based on a wafer stacking architecture, characterized in that, Include: A memory array comprising a common line and multiple memory cells, the common line connecting the memory cells, and the memory array comprising: Multiple memory regions, each containing a specific number of rows or columns of memory units; Multiple multiplexers are configured in pairs adjacent to each other in the memory region; A line driver, connected to the shared line, is used to drive the memory unit; wherein: The memory crystal layer receives a control signal transmitted from the logic circuit layer to adjust the number of memory cells connected on the common line, thereby dynamically changing the latency characteristics of the memory array; each of the multiplexers is connected to the line driver via a dedicated line; when the multiplexer is activated by the control signal, the common line is disconnected into a first segment and a second segment, and the second segment is connected to the dedicated line; the memory region corresponding to the first segment forms a first subarray; the memory region corresponding to the second segment forms a second subarray.

8. The memory device as claimed in claim 7, characterized in that, in: The line driver includes a data driver; The shared line includes multiple shared data lines, each of which connects the data driver and a corresponding column of memory cells in the memory unit for transmitting data signals. as well as After the multiplexer is activated, the memory cells in the second subarray use the dedicated line to transmit data signals.

9. The memory device as claimed in claim 7, characterized in that, in: The line driver includes an address decoder; The memory device further includes multiple common address lines, each common address line connecting the address decoder and a corresponding row of memory cells in the memory unit, for transmitting address signals; as well as After the multiplexer is activated, the address decoder, according to the control signal, causes the shared address lines of the corresponding rows in the second subarray and the first subarray to receive the same address signal.

10. The memory device as claimed in claim 7, characterized in that, in: The control signal is generated by the computer system when executing an application based on the conditions of the application, causing the multiplexer to divide the memory array into two or more subarrays that meet the conditions of the application for access by the application.

11. The memory device as claimed in claim 10, characterized in that, in: The application conditions include the response time required by the application.

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