This includes the integrated circuits and corresponding calculation methods of a hardware calculator.

Abstract

Embodiments of this disclosure relate to an integrated circuit including a hardware calculator and a corresponding calculation method. In one embodiment, the integrated circuit includes a hardware calculator configured to compute a first output component Y of order n-1 in parallel across a series of operations according to the following formula. n‑1 And the second output component Y of the second order n, which is higher than the first order and continuous with the first order. n The hardware calculator includes components dedicated to the first output component Y. n‑1 The first calculation path, and the second calculation path Y dedicated to the second output component. n For each operation, the first register is configured to contain a pair {x} of first factors corresponding to the terms of the operations in the first path. i ,x i‑1 The second register is configured to contain a pair {b} of second factors corresponding to the terms of the operations in the first path. j ,b j+1}, and the third register is configured to contain a pair {b} of the second factors corresponding to the term of the next operation in the first path. j+2 ,b j+3}

Description

[0001] Priority requirements

[0002] This application claims the benefit of French application No. 2111263, filed on 22 October 2021, which is incorporated herein by reference. Technical Field

[0003] The embodiments and implementations relate to hardware calculators that operate in an integrated manner, particularly those suitable for parallel computation of the output vector components of convolutional multiplication. Background Technology

[0004] Typically, especially in the Finite Impulse Response (FIR) filter algorithm, the input vector {x} i} 0≤i≤M-1 and another input vector {b i} 0≤i≤N-1 The convolution and multiplication between them produce the output vector {Y} m} 0≤m≤N-1 Each component is derived from the formula definition.

[0005] Typically, the input vector {x} i} 0≤i≤M-1 The data can be called "samples", while the input vector {b} i} 0≤i≤N-1 The data can be called "tap". Summary of the Invention

[0006] The hardware calculator can be specifically designed to calculate the components Y of the output vector of this convolution product. m The multiplication and accumulation type is "MAC". The use of hardware calculators allows for optimization of the workload of general-purpose computing units (usually the processor of a system-on-a-chip) and optimization of the computation time of the output vector, known as inference time.

[0007] b i In a single instruction, the optimized hardware calculator can simultaneously perform two multiplication-accumulation calculations, as well as load samples x for the next two multiplication-accumulation operations. i And load the two taps b of the next two multiplication-accumulation operations. i .

[0008] Therefore, the number of multiplications-accumulations used to compute all components of the output vector is equal to the number of samples x. i With the number of taps b i The product of these is, for example, N×M according to the dimension example given above. Furthermore, the number of samples and tap loads is also equal to N×M.

[0009] Applications of convolutional multiplication performed by hardware calculators tend to increase the dimension N, which has a secondary effect on the inference time of the computation.

[0010] Multiplying in parallel by the number of MAC-type calculators allows for optimization of the number of consecutive instructions, but requires multiplying by the number of input data loading processes at each instruction. Loading samples and taps from memory can become time-constraining factors for computing convolutional products.

[0011] The examples provide optimizations to the multiplication-accumulation technique to reduce the time required to compute the full convolution product.

[0012] Various embodiments provide the ability to perform four multiplication-accumulation operations for each operation using only two loads of the input data.

[0013] According to one embodiment, an integrated circuit is provided in this regard, the integrated circuit including a hardware calculator adapted to perform a series of operations based on the following formula. The first output component Y of the first order n-1 is computed in parallel. n-1 And the second output component Y of the second order n, which is higher than the first order and continuous with the first order. n The hardware calculator includes a dedicated function for the first output component Y. n-1 The first calculation path is dedicated to the second output component Y. n The second computation path, wherein for each operation, the first register is configured to contain an item corresponding to the operation in the first path. The first factor pair {x i ,x i-1 The second register is configured to contain items corresponding to the operations in the first path. The second factor of {b} j ,b j+1}, and the third register is configured to contain the item corresponding to the next operation in the first path. The second factor pair {b j+2 ,b j+3 The two computation paths are configured to access the first register, the second register, and the third register, respectively. Thus, in each operation, corresponding to each output component Y... n-1 ,Y n The first factor x is used at the corresponding positions of the summation indices in the expression of order m = n-1, where m = n ≤ k ≤ N-1. m-k Second factor b k .

[0014] Therefore, for each operation, the first computation path uses the factors provided for the operation included in the first and second registers, while the second computation path uses the factors corresponding to the second order m = n and the factors corresponding to the second factors and the summation index 0 ≤ k ≤ N-1 common to the next operation in the first path.

[0015] According to one embodiment, for each operation:

[0016] - The first calculation path is configured to calculate and accumulate the first factor {x} included in the first output register in the first output register. i ,x i-1} and the second factor {b} included in the second register j ,b j+1 The pair of two products between}

[0017] - The second calculation path is configured to calculate and accumulate the same first factor {x} included in the first register in the second output register. i ,x i-1} and the second factor {b} included in the second register and the third register, corresponding to the calculation of the second level j+1 ,b j+2 The pair of two products between}

[0018] - The hardware calculator is configured to compute the first factor of the next operation corresponding to the first path, in pairs {x}. i-2 ,x i-3} Loaded into the first register, and the second factor of the operation corresponding to the next operation of the first path is calculated in pairs {b j+4 ,b j+5} is loaded into the second register.

[0019] In fact, the configuration of two computation paths accessing the three input registers allows only two loads to be performed for each operation, enabling four multiplications-accumulations of the following operations.

[0020] According to another embodiment, an integrated circuit is proposed, which includes a hardware calculator adapted to perform a series of operations based on the following formula. The first output component Y of the first order n-1 is computed in parallel. n-1 And the second output component Y of the second order n, which is higher than the first order and continuous with the first order. n The hardware calculator includes a dedicated function for the first output component Y. n-1The first calculation path is dedicated to the second output component Y. n The second computational path aims to include the pair {x} of the first factor. i ,x i-1 The first register of}, the second register intended to include pairs of the second factors, and the pair of {b} intended to include the second factors j ,b j+1 The third register of}, wherein for each operation, the hardware calculator is configured as follows:

[0021] - Using the first path, calculate and accumulate the first factor {x} included in the first register in the first output register. i ,x i-1} and the second factor {b} included in the second register j ,b j+1 A pair of products between}

[0022] - Using the second path, calculate and accumulate the same first factor {x} included in the first register in the second output register. i ,x i-1} and the second factor {b} corresponding to the calculation of the second order n, included in the second and third registers. j+1 ,b j+2 Pair of two products between}

[0023] - The pair of the first factors of the computation following the next operation of the first path {x i-2 ,x i-3 Loaded into the first register.

[0024] - The second factor of the operation corresponding to the next operation of the first path is the pair of {b}. j+4 ,b j+5 Load it into the second register.

[0025] In other words, these two computation paths are configured to each access the first register, the second register, and the third register, so as to use the values ​​for each output component Y in each operation. n-1 ,Y n The order m = n-1; the first factor x shared by m = n m-k Second factor b k And in each output component Y n-1 ,Y n The order is located at the corresponding position of the summation index 0≤k≤N-1 in the corresponding formula.

[0026] As a result of this configuration, which allows access to two multiplication-accumulation computation paths in three registers, the hardware calculator is able to compute four multiplication-accumulation terms for each operation, for the two loads of factors in the registers.

[0027] In fact, the second factor {b} j+4 ,b j+5 The loading of} corresponds to the computation of the operation following the next operation of the first path; it is allowed during the following operations:

[0028] - Has a usable second factor {b j+4 ,b j+5} (loaded into a register called the "second register" during the previous operation), the second factor {b j+4 ,b j+5} will be used by the first path in subsequent operations, but in that operation it will be used at least partially (at least one) by the second path; and

[0029] - Has a usable second factor {b j+2 ,b j+3} (loaded into a register called the “third register” during the operation prior to the previous operation), which is used by the first path in the operation and at least partially (at least one) by the second path in the operation.

[0030] In practice, the constraints on the "second" and "third" registers are arbitrary. That is, the integrated circuit essentially includes both registers, which can alternately perform the functions of the second and third registers. For example, if during one operation, one register performs the function of the "second" register, then the other performs the function of the "third" register. In another operation (the next operation), one will perform the function of the "third" register, and the other will perform the function of the "second" register.

[0031] For example, in this respect, the hardware calculator is configured to switch between the second and third registers for each consecutive operation in a series of operations.

[0032] According to one embodiment, the first register, the second register, the third register, the first output register, and the second output register have a size of 2M bits, for example, 64 bits (M=32), and each register includes a pair of two data encoded in M ​​bits, for example, 32 bits (M=32).

[0033] According to one embodiment, the hardware calculator includes selection circuitry configured to allocate access to a second register and a third register on a first calculation path and a second calculation path, such that the first path can access a second factor {b} corresponding to the operation included in the second register. j ,b j+1}, and the second path can access the second factor {b} corresponding to the operation included in the second register and the third register. j+2 ,b j+3}

[0034] In other words, unlike traditional hardware calculators, the input registers are not dedicated to a single computation path, but are interconnected and distributed between different computation paths via selection circuitry.

[0035] According to one embodiment, the hardware calculator is also adapted to compute the third output component Y of the third order n+1 in parallel according to the same formula. n+1 The third order n+1 is higher than the second order n and is continuous with the second order. The hardware calculator includes a third computation path dedicated to the third output component, and wherein, for each operation, the hardware calculator is further configured to:

[0036] - Using the third path, calculate and accumulate the same first factor {x} included in the first register in the third output register. i ,x i-1} and the second factor {b} included in the third register, corresponding to the third-order calculation. j+2 ,b j+3 Pair of two products between}

[0037] Therefore, by utilizing a third computation path that is configured to also access the first, second, and third registers, the first factor x can be used for each operation. m-k Second factor b k The first and second factors are common at their respective positions in the expression for order m = n + 1 and summation index 0 ≤ k ≤ N - 1.

[0038] As a result of this configuration, which allows access to three multiplication-accumulation computation paths in three registers, the hardware calculator is able to compute six multiplication-accumulation terms for each operation for two factors loaded into the registers.

[0039] In fact, the second factor {b} j+4 ,b j+5 The loading of} corresponds to the computation of the operation following the next operation of the first path; further, it allows, during the next operation: to have a second factor {b} available. j+4,b j+5 (Loaded into a register called the "second register" during the previous operation), this second factor will be used by the first path in the next operation, but at least in part by the second path in that operation, and further by the third path in that operation.

[0040] According to one embodiment, the integrated circuit defined above includes a digital signal processor.

[0041] On the other hand, a method for implementation in a hardware calculator is proposed, which is based on the following formula. The first output component Y of the first order n-1 is computed in parallel during a series of operations. n-1 And the second output component Y of the second order n, which is higher than the first order and continuous with the first order. n For each operation:

[0042] - First component Y n-1 The calculation includes the first factor {x} included in the first register. i ,x i-1} and the second factor {b} included in the second register j+1 ,b j+2 Calculation and summation of two products between};

[0043] - Second component Y n The calculation includes the same first factor {x} included in the first register. i ,x i-1} and the second factor {b} corresponding to the second order calculation included in the second and third registers. j ,b j+1 The two products between} Calculation and accumulation;

[0044] - The pair of the first factors corresponding to the calculation of the next operation {x i-2 ,x i-3 Loaded into the first register.

[0045] - The pair of the second factors corresponding to the next operation of the first path, {b j+4 ,b j+5 Load it into the second register.

[0046] According to one embodiment, the method includes, in a series of operations, switching between a second register and a third register for each consecutive operation.

[0047] According to one embodiment, the first register, the second register, the third register, the first output register, and the second output register have a size of 2M bits, and each register includes a pair of two data items encoded in M ​​bits.

[0048] According to one embodiment, access to the second and third registers is allocated such that it is dedicated to the first output component Y. n-1 The first computation path can access the second factor {b} corresponding to the operation included in the second register. j+1 ,b j+2}, and is dedicated to the second output component Y n The second computation path can access the second factor {b} corresponding to the operation included in the second and third registers. j+2 ,b j+3}

[0049] According to one embodiment, the method further includes parallel computation of the third output component Y of order n+1 according to the same formula. n+1 The third order is higher than the second order n and is continuous with the second order, where for each operation:

[0050] - Third component Y n+1 The calculation includes the same first factor {x} in the first register. i ,x i-1} and the second factor {b} included in the third register, corresponding to the calculation of the third order n+1. j+2 ,b j+3 The two products between} The calculation and accumulation. Attached Figure Description

[0051] Other advantages and features of the invention will become apparent upon review of the detailed description of the embodiments and implementations, and not limitation thereof, and the accompanying drawings, in which:

[0052] Figure 1 A hardware calculator according to an embodiment is shown;

[0053] Figure 2 The implementation principle according to the embodiment is shown;

[0054] Figure 3 A hardware calculator for a first operation according to an embodiment is shown;

[0055] Figure 4 The implementation principle of the second operation according to the embodiment is shown;

[0056] Figure 5 A hardware calculator is shown according to an embodiment regarding a second operation following a first operation;

[0057] Figure 6 Another implementation principle according to the embodiment is shown; and

[0058] Figure 7 An exemplary embodiment of a hardware calculator is shown. Detailed Implementation

[0059] Figure 1 An example of a hardware calculator (CAL) particularly suitable for calculating convolution products is shown. The hardware calculator can be generated within an integrated circuit of a digital signal processor (DSP).

[0060] The components of the output vector of a convolution product can be expressed by the general formula. This indicates that it is the sum of the products of each term's factors. These factors are the input data used for convolution. The first factor x m-k For example, it could be a component of the input vector, or a "sample," with the second factor b. k For example, it can be a coefficient, or a "tap".

[0061] The hardware calculator CAL includes two parallel computation paths, VC1 and VC2. Each path is configured to perform multiplication-accumulation operations MACg and MACd in a series of consecutive operations, such that the terms accumulated in the output register REGout asymptotically form the output component Y at the end of the series. m Each operation includes data x in the respective input register REGin. m-k b k The multiplication and the accumulation of products in the output register REGout. Furthermore, in one operation, the loading of input data for the next operation can be done in the input register REGin.

[0062] Computation paths VC1 and VC2 advantageously include a first optimization in the use of the input REGin and output REGout registers, thereby allowing for a limitation on the number of times input data is loaded in a series of operations. In practice, registers REGin and REGout have a size of 2M bits, for example, 64 bits (M = 32), and each register includes two distinct data entries encoded in M ​​bits, for example, 32 bits. Arbitrarily, within each 64-bit register, a distinction is made between the 32-bit word stored on the left (marked "g" in the diagram) and the 32-bit word stored on the right (marked "d" in the diagram).

[0063] Therefore, in each computation path VC1, VC2, loading a single 2M-bit word into the input register REGin allows loading a first input factor for the first multiplication—accumulating MACg—performed in the left "g" portion of the input-output registers REGin, REGout, and another first input factor for the second multiplication—accumulating MACd—performed in parallel in the right "d" portion of the input-output registers REGin, REGout. For example, computations in the left "g" and right "d" portions of registers REGin, REGout can be implemented such that a sum with an even index is accumulated in the right "d" portion of the output register REGout. The terms are added to the left "g" part of the output register REGout, while terms with odd index k are added to the left "g" part of the output register REGout.

[0064] Therefore, independently in each path VC1, VC2 and in each operation, two 64-bit payloads are sufficient to perform two multiplications – accumulating MACg and MACd.

[0065] Furthermore, the two computation paths VC1 and VC2 can advantageously share one of the two input registers REGin, for example, to store input data x. n-1 ,x n-2 The input register R3, and the coefficients b with index k corresponding to these input data. k To perform multiplication-accumulation operations, the coefficients and output components The order of m and the sum For each computation path VC1, there is a corresponding VC2.

[0066] For example, the first path VC1 calculates the first-order output component Y. n-1 The second path calculates the second output component Y of the second order. n Then, in the first path VC1 of order m = n-1, the coefficient b is loaded into the second input register R7. k The coefficient has a value corresponding to the input data x. n-1 ,x n-2 product The indices k,k+1 of (i.e., i, j) represent the coefficients i, j. Similarly, in the second path VC2, coefficients b1 and b2 are loaded in the third input register R6, the coefficients having values ​​corresponding to the input data x. n-1 ,x n-2 product (i.e., the indices k, k+1 of i, j, i.e., nk = n-1; n-(k+1) = n-2, i.e., k = 1, (k+1) = 2).

[0067] This allows for interaction between the two paths VC1, VC2 and for each operation, with a 64-bit load in the common register R3, such that three 64-bit loads are sufficient to perform four multiplication-accumulation operations for each operation in the two paths VC1, VC2.

[0068] Now for reference Figures 2 to 5 , Figures 2 to 5 This shows that the input register REGin( Figure 1 The number of loads in the ) is reduced to two, which is a favorable example of performing four multiplications-accumulations in each operation in the set of two paths VC1, VC2.

[0069] Figure 2 The implementation principle that allows interaction of additional loads in the input registers R3, R7, and R6 of the first computation path VC1 and the second computation path VC2 is illustrated above. Figure 1 As stated above.

[0070] On the one hand, the first output component Y calculated by the first path VC1 n-1 The first order n-1 and the second output component Y calculated by the second path VC2 n The second order n is advantageously continuous with each other. The second order is higher than the first order and directly continuous with the first order. This corresponds to the following about Figure 1 The situation described.

[0071] exist Figure 2 , Figure 4 and Figure 6 In this context, the equations are represented by formulas of order n-1 and n. The extension, where the letter-filling mode corresponds to the mode of the input registers R3, R7, R6 containing the corresponding factors, and the "empty" or "white" mode means that these factors are not loaded into the registers during the operation OP1.

[0072] Using input data x n-1 ,x n-2 During the first operation OP1, the coefficients b0 and b1 used by the first VC1 are included in the second register R7. For the same input data x n-1 ,x n-2 The coefficient b1 used by the second path VC2 is included in the second register R7, and the coefficient b2 used by the second path VC2 is included in the third register R6.

[0073] refer to Figure 3 It shows the hardware calculator CAL in the implementation environment of the first operation OP1.

[0074] In the first path VC1, according to the combination Figure 1The multiplication-accumulation operation is implemented as described, that is, the first factor x, which is included in the first register R3, is accumulated in the output register R0 of the first path VC1. n-1 ,x n-2 The two products between the second factor and the second factor included in the second register R7

[0075] In detail, the first factor x n-1 The product between the first and second factors, b0, is accumulated in the right-hand portion of the output register R0d from the data included in the right-hand portions of the first register R3d and the second register R7d. This multiplication-accumulation operation is "R0d += R3d * R7d" ("+=" means "accumulation", "*" means "multiplication"). Similarly, the product of another first factor and another second factor is accumulated in the left-hand portion of the output register R0g, for example, "R0g += R3g * R7g".

[0076] In the second path VC2, a multiplication-accumulation operation is performed, such that the first factor x, which is included in the first register R3, is accumulated in the output register R4 of the second path VC2. n-1 ,x n-2 The two products between the second factor {b0, b1} included in the second register R7 and the third register R6

[0077] In detail, in the second path VC2, the first factor x n-1 The product between the first factor and the second factor b1 is accumulated in the right part of the output register R4d from the data included in the right part of the first register R3d and the left part of the second register R7d, for example, "R4d += R3d * R7g". Furthermore, the product between the other first factor and the other second factor is accumulated in the left part of the output register R4g from the data included in the left part of the first register R3g and the right part of the third register R6d, for example, "R4g += R3g * R7d".

[0078] In this respect, the hardware calculator CAL may include a selection circuit SWT configured to allocate access to a second register R7 and a third register R6 at the first calculation path VC1 and the second calculation path VC2. The selection circuit SWT is configured to clearly allocate the left and right portions of said registers R7 and R6.

[0079] In the first operation OP1, the allocation is performed such that the left part MACg of the first path VC1 receives the left part of the first register R3g and the left part of the second register R7g as input; the right part MACd of the first path VC1 receives the right part of the first register R3d and the right part of the second register R7d as input. Similarly, the left part MACg of the second path VC2 receives the left part of the first register R3g and the right part of the third register R6d as input; the right part MACd of the second path VC2 receives the right part of the first register R3d and the left part of the second register R7g as input.

[0080] Therefore, the first path VC1 can access the second factor {b} included in the corresponding operation in the second register R7. j ,b j+1}, while the second path VC2 can access the second factor {b} included in the corresponding operations in the second register R7g and the third register R6d. j+2 ,b j+3}

[0081] Simultaneously with the parallel multiplication-accumulation calculations in the two computation paths VC1 and VC2, the hardware calculator CAL is configured to perform the next operation OP2 in the first register R3, which is the next operation of the first path VC1 and the second path VC2. Figure 4 and 5 The calculation of the first factor corresponding to {x} n-3 ,x n-4 Loading LD(x) n＝n-2 Furthermore, in the second register R7, only LD(b) is loaded. k＝k+4 The other of the pair of second factors {b4,b5} corresponding to the computation of the operation of the next operation OP2 following the first path VC1.

[0082] Therefore, during the next operation OP2, the second register R7 and the third register R6 will include the second factor {b2,b3}{b4,b5} in a manner equivalent to their contents at the beginning of the first operation OP1.

[0083] Reference in this regard Figure 4 .

[0084] Figure 4 The implementation principle of the computation in the first path VC1 and the second path VC2 is shown during the next operation after the first operation OP1, that is, during the second operation OP2.

[0085] Recall that at the end of the load operation performed during the first operation OP1, the first input register R3 contained the input data x. n-3 ,x n-4The second input register R7 includes coefficients b4 and b5 and corresponds to the input data x of the operation following the second operation OP2 in the first path VC1. n-5 ,x n-6 product The third register R6 was not loaded with new data, therefore the first path VC1 includes the input data x that follows the first operation OP1. n-3 ,x n-4 product The corresponding coefficients b2 and b3 are the second operation OP2 performed in the first path VC1.

[0086] During the second operation OP2, the input data x is used n-3 ,x n-4 Coefficients b2 and b3 and / or the first VC1 are included in the third register R6. For the same input data x n-3 ,x n-4 The coefficient b3 used by the second path VC2 is included in the third register R6, and the coefficient b4 used by the second path VC2 is included in the second register R7.

[0087] refer to Figure 5 This illustrates the hardware calculator CAL within the context of the implementation of the second operation OP2, which follows the first operation OP1.

[0088] In the first path VC1, a multiplication-accumulation operation is performed, such that the first factor x, which is included in the first register R3, is accumulated in the output register R0 of the first path VC1. n-3 ,x n-4 The product between the second factor {b2,b3} included in the third register R6 and the two factors.

[0089] In detail, the multiplication-accumulation in the right part of the output register R0d of the first path VC1 is represented as "R0d+=R3d*R6d", and the multiplication-accumulation in the left part of the output register R0g is represented as "R0g+=R3g*R6g".

[0090] In the second path VC2, a multiplication-accumulation operation is performed, such that the first factor x, which is included in the first register R3, is accumulated in the output register R4 of the second path VC2. n-3 ,x n-4 The two products between the second factor {b3, b4} included in the second register R7 and the third register R6

[0091] In detail, the multiplication-accumulation in the right part of the output register R4d of the second path VC2 is represented as "R4d+=R3d*R6g", and the multiplication-accumulation in the left part of the output register R4g is represented as "R4g+=R3g*R7d".

[0092] Here again, the selection circuit SWT is configured to assign inputs such that the left MACg of the first path VC1 receives the left portion of the first register R3g and the left portion of the third register R6g as inputs; the right MACd of the first path VC1 receives the right portion of the first register R3d and the right portion of the third register R6d as inputs. Similarly, the left MACg of the second path VC2 receives the left portion of the first register R3g and the right portion of the second register R7d as inputs; the right MACd of the second path VC2 receives the right portion of the first register R3d and the left portion of the third register R6g as inputs.

[0093] Furthermore, here again, simultaneously with the parallel multiplication-accumulation calculations in the two computation paths VC1 and VC2, the hardware calculator CAL is configured to perform the calculation of the first factor x corresponding to the next operation of the first path VC1 and the second path VC2 (i.e., the operation after the second operation OP2) in the first register R3. n-5 ,x n-6 Loading LD(x) n＝n-2 Furthermore, in the third register R6, only LD(b) is loaded. k＝k+4 The other of the pair of second factors {b6,b7} corresponding to the operation following the next operation of the first path VC1 (i.e., the operation following the second operation OP2).

[0094] Therefore, during the next operation (after the second operation OP2), the second register R7 and the third register R6 will include the second factor {b4,b5}{b6,b7} in a manner equivalent to their contents at the beginning of the first operation OP1 and the beginning of the second operation OP2.

[0095] From the perspective of accessing and loading into input registers R3, R6, and R7, the implementation of the operation after the second operation OP2 is strictly the same as that of the first operation OP1, except that this time the sum corresponding to index k in order m = n-1 is loaded. The corresponding advance data in the middle.

[0096] It should be noted that the difference between all actions performed in the second register R7 and the third register R6 between the first operation OP1 and the second operation OP2 corresponds to the switching between the actions performed in the second register R7 and the actions performed in the third register R6, i.e., strict exchange.

[0097] Therefore, in a series of operations, the hardware calculator CAL is configured to switch the functions of the second register R7 / R6 and the third register R6 / R7 one after another in each consecutive operation. In other words, for each new operation, the third register becomes the second register, the second register becomes the third register, and the same action is performed in the "new" second register and the "new" third register.

[0098] On the other hand, it can be assumed that the hardware calculator CAL always performs strictly identical actions in both the second and third registers for each operation. In fact, in the first operation OP1 (and the "odd number" operation), the second register is the one labeled R7, and the third register is the one labeled R6; when performing the second operation OP2 (and the "even number" operation), the exact same actions are performed in both the second and third registers, with the second register labeled R6 and the third register labeled R7.

[0099] In summary, the hardware computing technique for multiplication-accumulation operations has been described, wherein for each operation that progressively constructs the first output component of the lower order n-1, the first input factor {x} is... i ,x i-1} is loaded into the first register R3, and the second factor {b} is loaded into the second register R3. j ,b j+1 Loaded into the second register R7 / R6. Further, the third register R6 / R7 is provided to include the next second factor {b} for the next operation of the first output component of lower order n-1. j+2 ,b j+3}. Simultaneously, the same first factor {x} loaded into the first register R3. i ,x i-1} and the second factors corresponding to these first factors {b j ,b j+1 Between}, the multiplication-accumulation operations for the second output component of the higher successive order n are distributed in the second register R7 / R6 and the third register R6 / R7.

[0100] Therefore, this generalized hardware computing technique allows for the use of input registers R3, R7 / R6 (REGin- Figure 1 In the case of only two loads, four multiplication-accumulation operations are performed for each operation in the set of two paths VC1 and VC2.

[0101] It should be noted that before the first operation in this series, the initialization phase of this series includes three loadings of the input registers R3, R7, and R6 with the corresponding data, for example... Figure 2As shown. Then, throughout the entire implementation of a series of operations, each operation consists of only two loads.

[0102] On the other hand, Figure 2 The equations shown in 4 and 6 Equation Y n-1 ,Y n In the expanded expression, the coefficient indices are all in the range from 0 to N-1, while the input data x m-k The index mk is labeled from the corresponding order m to order m-(N-1). In this case, it should be understood that the input vector {x} is assumed to be... i} i Typically, if an index i does not have a negative sign, then the index value (e.g., the value it might represent) is considered to be modulo (N-1), such that when the effective index equals (N-1) + (mk). At this point, the input data {x} i} i The value can usually be stored in a loop register, which can be achieved by constructing a modulo function.

[0103] Figure 6 A supplementary example is shown corresponding to a case where the hardware calculator also includes a third computation path (not shown), which is similar to the first computation path VC1 and the second computation path VC2, and is suitable for parallel computation of the third output component Y of order n+1. n+1 The third order is higher than the second order and continuous with the second order, and according to the same formula.

[0104]

[0105] For each operation, the hardware calculator is configured to calculate and accumulate the same first factor {x} included in the first register R3 in the third output register (not shown). n-1 ,x n-2} and the second factor {b} included in the third register R6 j+2 ,b j+3 A pair of products between}

[0106]

[0107] In the first operation OP11, the first output component Y is processed by the first path VC1. n-1 The multiplication-accumulation operation performed and the second output component Y by the second path VC2. n The multiplication-accumulation operation performed corresponds precisely to the previous operation about... Figure 2 and 3 The first operation described is OP1.

[0108] Therefore, in the previous discussion Figure 2 and 3 In the first operation OP1 described, the third register R6 includes coefficients {b2, b3}.

[0109] However, for the third output component Y of the third path n+1 The term p corresponds to the input data x of order n+1 (i.e., (n+1)-k=n-1; (n+1)-(k+1)=n-2, or k=2; k+1=3). n-1 ,x n-2 product The second factor of index k, k+1 is the coefficient included in the third register R6.

[0110] During the first operation OP11, operations are performed in registers R3 and R7 related to... Figure 2 and 3 The same loading described.

[0111] Then, in the second operation following the first operation OP11, the first register R3 includes the first factor {x}. n-3 ,x n-4 The second register R7 contains the second factor {b4, b5}, and the third register R6 contains the second factor {b2, b3}.

[0112] Therefore, the first output component Y is generated by the first path VC1. n-1 The multiplication-accumulation operation performed and the second output component Y by the second path VC2. n The multiplication-accumulation operation performed by p again corresponds precisely to the previous one regarding... Figure 4 and 5 The second operation described is OP2.

[0113] Furthermore, for the third output component Y of the third path n+1 The terms correspond to the product of input data of order n+1 (i.e., (n+1)-k=n-3; (n+1)-(k+1)=n-4, or k=4; k+1=5). The second factor of index k, k+1 is the coefficient {b4, b5} included in the second register R7.

[0114] Therefore, through the additional third calculation path, the hardware calculator is able to calculate six multiplication-accumulation terms of the two factors loaded into the register at each operation.

[0115] Figure 7 Showing previous information Figures 2 to 6An exemplary embodiment of the described hardware calculator CAL. The hardware calculator CAL belongs to, for example, a digital signal processor (DSP), which is integrated within an integrated circuit such as a microcontroller (MCU).

[0116] Although the invention has been described with reference to illustrative embodiments, this description is not intended to be limiting. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to those skilled in the art based on the description. Therefore, the appended claims are intended to cover any such modifications or embodiments.

Claims

1. An integrated circuit comprising: a hardware calculator configured to calculate according to an algorithm in parallel in a series of operations a first output component of a first order and a second output component of a second order higher than the first order and consecutive to the first order ​ wherein said hardware calculator comprises a first calculation path dedicated to said first output component and a second calculation path dedicated to said second output component ​ wherein for each operation, a first register is configured to contain a pair of terms corresponding to a first factor of the operation in the first computation path a second register is configured to contain a pair of terms corresponding to a second factor of the operation in the first computation path and a third register is configured to contain a pair of terms corresponding to a second factor of the next operation in the first computation path and a fourth register is configured to contain a pair of terms corresponding to a second factor of the next operation in the first computation path and a fifth register is configured to contain a pair of terms corresponding to a second factor of the next operation in the first computation path and a sixth register is configured to contain a pair of terms corresponding to a second factor of the next operation in the first computation path and wherein the first and second computational paths are configured to each access the first register, the second register and the third register, using a first factor and a second factor at respective positions in the summation index of the expression of order corresponding to each output component of each operation , wherein the hardware calculator is configured to switch the function of the second register and the third register for each successive operation in the series of operations.

2. The integrated circuit of claim 1, wherein for each operation, the first computation path is configured to compute and accumulate in a first output register a pair of two products between the first factors contained in the first register and the second factors contained in the second register ,​ wherein for each operation, the second computation path is configured to compute and accumulate in a second output register the same first factor included in the first register with the two products of pairs between the second factors of the computation included in the second register and the third register corresponding to the second order and​ wherein for each operation, the hardware calculator is configured to load into the first register a pair of the first factors of the computation corresponding to the next operation of the first computation path and to load into the second register a pair of the second factors of the computation corresponding to the operation after the next operation of the first computation path. and to load into the second register a pair of the second factors of the computation corresponding to the operation after the next operation of the first computation path.

3. The integrated circuit of claim 2, wherein the first register, the second register, the third register, the first output register, and the second output register have a size of 2M bits and each contain a pair of two data items encoded in M bits.

4. The integrated circuit of claim 1, wherein the hardware calculator comprises a selection circuit configured to allocate access to the second register and to the third register at the first computing path and the second computing path such that the first computing path has access to the second factor of the operation contained in the second register and the second computing path has access to the second factor of the operation contained in the second register and the third register. ​​ 5. The integrated circuit of claim 1, wherein the hardware calculator is configured to compute a third output component of a third order in parallel with the second output component according to the same formula, the third order being higher than the second order and consecutive to the second order, the hardware calculator comprising a third calculation path dedicated to the third output component. and​​​ wherein for each operation, the hardware calculator is further configured to compute and accumulate a pair of two products in a third output register using the third computation path , the pair of two products being between a same first factor included in the first register and the second factor of the computation included in the third register corresponding to the third order 6. The integrated circuit of claim 1, wherein the integrated circuit is a digital signal processor.

7. An integrated circuit comprising: a hardware calculator configured to calculate according to an equation: in parallel in a series of operations a first output component of a first order and a second output component of a second order higher than the first order and consecutive to the first order , wherein the hardware calculator comprises a first calculation path dedicated to the first output component , a second calculation path dedicated to the second output component , a first register configured to contain a pair of first factors , a second register configured to contain a pair of second factors , and a third register configured to contain a pair of second factors . wherein the hardware calculator is configured to: computing and accumulating in a first output register a pair of two products between the first factor contained in the first register and a second factor contained in the second register with the first computing path and ;​ calculating and accumulating in a second output register with said second computing path the same first factors contained in said first register and a pair of two products between the second factors of the calculations corresponding to the second order included in said second register and in said third register ;​ a pair of bits corresponding to a first factor of a computation of a next operation of the first computational path loaded into the first register; a pair of second factors corresponding to a computation of an operation following the next operation of the first computation path loaded into the second register, wherein the hardware calculator is configured to switch the function of the second register and the third register for each successive operation in the series of operations.

8. The integrated circuit of claim 7, wherein the first register, the second register, the third register, the first output register, and the second output register have a size of 2M bits and each contain a pair of two data items encoded in M bits.

9. The integrated circuit of claim 7, wherein the hardware calculator comprises a selection circuit configured to allocate access to the second register and to the third register at the first computing path and the second computing path such that the first computing path has access to the second factor of the operation contained in the second register and the second computing path has access to the second factor of the operation contained in the second register and the third register. ​​ 10. The integrated circuit of claim 7, wherein the hardware calculator is configured to perform parallel calculations of the third order according to the same formula. The third output component The third order is higher than the second order. Furthermore, being continuous with the second order, the hardware calculator includes components dedicated to the third output component. The third calculation path, wherein for each operation, the hardware calculator is further configured to use the third calculation path to calculate and accumulate the same first factor contained in the first register in the third output register. And included in the third register corresponding to the third order The second factor calculated as described above Pair of two products .

11. The integrated circuit of claim 7, wherein the integrated circuit is a digital signal processor.

12. A method for performing a series of operations based on a formula Parallel computing first order First output component Second order Second output component The method, wherein the second order is higher than the first order and continuous with the first order, comprises, for each operation: by a hardware calculator by accumulating a first factor included in a first register and a second factor included in a second register between the two products to calculate the first output component ; by the hardware calculator by accumulating the same first factor included in the first register and the second factor included in the second and third registers corresponding to a second order of the calculation between the two products to calculate the second output component ; a pair of the computed first factors corresponding to the next operation by the hardware calculator loaded into the first register; and a pair of second factors of the computation of the operation following the next operation corresponding to the first computation path by the hardware calculator loaded into the second register, the method further comprising switching the function of the second register and the third register for each successive operation in the series of operations.

13. The method of claim 12, wherein the first register, the second register, and the third register have a size of 2M bits and each contain a pair of two data items encoded in M bits.

14. The method of claim 12, wherein access to the second register and the third register are allocated such that they are dedicated to the first output component. The first computation path has the second factor corresponding to the operation contained in the second register. Access, and dedicated to the second output component. The second computation path has the second factor corresponding to the operation contained in the second register and the third register. Access.

15. The method according to claim 12, further comprising parallel computation of the third order according to the same formula. The third output component The third order is higher than the second order. And it is continuous with the second order n, wherein for each operation, the method further includes calculating the third output component. The third output component includes the same first factor contained in the first register. The second factor corresponding to the third order calculation contained in the third register. The two products between The calculation and accumulation.

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