Method of forming a semiconductor structure

Abstract

A method for forming a semiconductor structure includes: providing a substrate, the substrate including a base and a first fin and a second fin on the base; forming a first work function layer on a surface of the first fin and a surface of the second fin; forming a second work function layer on the first work function layer; forming a patterning layer on the substrate, the patterning layer having an etching opening exposing the second work function layer on the first fin; removing the second work function layer on the first fin by using a first etching process with the patterning layer as a mask, and forming a protection layer on the surface of the first work function layer on the first fin in the process of removing the second work function layer on the first fin. By forming the protection layer on the surface of the first work function layer, the etching damage to the first work function layer in the process of removing the second work function layer can be effectively reduced, and the influence on the threshold voltage required by the corresponding transistor is reduced, so as to improve the performance of the finally formed semiconductor structure.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor manufacturing, and particularly relates to a forming method of semiconductor structure. BACKGROUND

[0002] MOS (Metal-Oxide-Semiconductor) transistor is one of the most important elements in modern integrated circuits, and the basic structure of the MOS transistor includes: a semiconductor substrate; a gate structure on the surface of the semiconductor substrate, the gate structure includes: a gate dielectric layer on the surface of the semiconductor substrate and a gate electrode layer on the surface of the gate dielectric layer; and source / drain doped regions in the semiconductor substrate on both sides of the gate structure. The MOS includes PMOS transistor and NMOS transistor.

[0003] In order to meet the needs of the switching speed of different transistors in integrated circuit design, it is necessary to form a transistor with multiple threshold voltages.

[0004] In order to reduce the threshold voltage of the PMOS transistor and the NMOS transistor, a corresponding work function layer is formed on the surface of the gate dielectric layer of the PMOS transistor and the NMOS transistor. The work function layer of the PMOS transistor needs to have a higher work function, and the work function layer of the NMOS transistor needs to have a lower work function. In the PMOS transistor and the NMOS transistor, the materials of the work function layers are different to meet the needs of the respective work function adjustment.

[0005] However, the performance of the multiple threshold voltage fin field effect transistor formed in the prior art still needs to be improved. SUMMARY

[0006] The technical problem solved by the present application is to provide a forming method of semiconductor structure, which effectively improves the performance of the formed multiple threshold voltage fin field effect transistor.

[0007] To solve the above problems, the application provides a semiconductor structure forming method, which comprises the following steps: providing a substrate, wherein the substrate comprises a base and a first fin and a second fin on the base; forming an isolation layer on the substrate, wherein the isolation layer covers part of the sidewall of the first fin and part of the sidewall of the second fin, and the top surface of the isolation layer is lower than the top surface of the first fin and the second fin; forming a pseudo-gate structure on the isolation layer, wherein the pseudo-gate structure crosses the first fin and the second fin; forming a sidewall on the sidewall of the pseudo-gate structure; forming a dielectric layer on the isolation layer, wherein the dielectric layer covers the pseudo-gate structure and exposes the sidewall of the pseudo-gate structure; removing the pseudo-gate structure to form a gate opening in the dielectric layer, wherein the gate opening exposes part of the surface of the first fin and part of the surface of the second fin; forming a first work function layer on the surface of the first fin and the surface of the second fin exposed by the gate opening; forming a second work function layer on the first work function layer; forming a patterned layer on the substrate, wherein the patterned layer has an etching opening which exposes the second work function layer on the first fin; using the patterned layer as a mask and using a first etching process to remove the second work function layer on the first fin, and in the process of removing the second work function layer on the first fin, a protective layer is formed on the surface of the first work function layer on the first fin.

[0008] Optionally, the first etching process comprises a SiCoNi isotropic dry etching process.

[0009] Optionally, the process parameters of the SiCoNi isotropic dry etching process comprise: etching gas O2, He and Cl2; power is 400 W-440 W; pressure is 25 mTorr-45 mTorr; the flow rate of each etching gas is 7.5 sccm for Cl2, 51 sccm for He and 0.2 sccm-0.4 sccm for O2.

[0010] Optionally, the content of O2 in the etching gas is 0.3%-0.7%.

[0011] Optionally, the first fin is used to form an NMOS transistor, and the second fin is used to form a PMOS transistor.

[0012] Optionally, the material of the first work function layer comprises tantalum nitride, and the material of the second work function layer comprises titanium nitride.

[0013] Optionally, the forming method of the patterned layer comprises: forming an initial patterned layer on the substrate, the initial patterned layer covering the second work function layer; forming a photoresist layer on the initial patterned layer, the photoresist layer exposing a top surface of part of the initial patterned layer; using the photoresist layer as a mask, etching the initial patterned layer by a second etching process to form the patterned layer.

[0014] Optionally, the material of the initial patterned layer comprises an anti-reflective coating.

[0015] Optionally, the second etching process comprises a dry etching process of plasma.

[0016] Optionally, the process parameters of the dry etching process of plasma comprise: etching gases CH4, H2 and N2; the flow rates of the etching gases are 5-10 sccm for CH4, 450-600 sccm for H2 and 40-60 sccm for N2; and the injection energy is 55-70 W.

[0017] Optionally, before forming the first work function layer and the second work function layer, the method further comprises: forming a gate dielectric layer on the surfaces of the first fin portion and the second fin portion exposed by the gate opening, and the first work function layer is located on the surface of the gate dielectric layer.

[0018] Compared with the prior art, the technical scheme of the present application has the following advantages:

[0019] In the forming method of the technical scheme, the first etching process is used to remove the second work function layer located on the first fin portion, and in the process of removing the second work function layer located on the first fin portion, a protective layer is formed on the surface of the first work function layer located on the first fin portion. By forming the protective layer on the surface of the first work function layer, the etching damage to the first work function layer in the process of removing the second work function layer can be effectively reduced, and thus the influence on the threshold voltage required by the corresponding transistor is reduced, so as to improve the performance of the finally formed semiconductor structure.

[0020] Further, the content of O2 in the etching gas is 0.3%-0.7%. When the content of O2 in the etching gas is greater than 0.7%, the content of other etching gases that actually contribute to etching will be reduced, thereby affecting the final etching effect; when the content of O2 in the etching gas is less than 0.3%, the oxidation effect on the first work function layer is weak, so that the thickness of the protective layer formed is small, thereby affecting the protection effect of the protective layer on the first work function layer. BRIEF DESCRIPTION OF DRAWINGS

[0021] Figures 1 to 3 is a structural schematic diagram of a semiconductor structure;

[0022] Figures 4 to 10 is a structural schematic diagram of each step of a method for forming a semiconductor structure in an embodiment of the present application. DETAILED DESCRIPTION

[0023] As described in the background, the performance of the multi-threshold voltage fin field effect transistor formed in the prior art still needs to be improved. The following will be specifically described with reference to the accompanying drawings.

[0024] Referring to Figure 1 , a substrate 100 is provided, the substrate 100 having a first fin portion 101 and a second fin portion 102; a first work function layer 103 and a second work function layer 104 are formed on the first fin portion 101 and the second fin portion 102, the second work function layer 104 being located on the surface of the first work function layer 103; an initial patterned layer 105 is formed on the substrate 100; a photoresist layer 106 is formed on the surface of the initial patterned layer 105, the photoresist layer 106 exposing part of the top surface of the initial patterned layer 105.

[0025] Referring to Figure 2 , the initial patterned layer 105 is etched with the photoresist layer 106 as a mask to form the patterned layer 108, the patterned layer 108 having an etching opening 109 exposing the first fin portion 101.

[0026] Referring to Figure 3 , the second work function layer 104 located on the first fin portion 101 is removed using the first etching process with the patterned layer 108 as a mask; after removing the second work function layer 104 located on the first fin portion 101, the patterned layer 108 and the photoresist layer 106 are removed.

[0027] In this embodiment, the transistors formed based on the first fin portion 101 and the second fin portion 102 have different requirements for the number of work function layers. Therefore, by removing the second work function layer 104 located on the first fin portion 101, the threshold voltage required by the corresponding transistor is met.

[0028] However, the etching process for etching the initial patterning layer 105 with the photoresist layer 106 as a mask is a dry etching process of plasma, which can effectively improve the etching rate of etching the initial patterning layer 105 and make the finally formed etching opening 109 have a good appearance. However, in the process of plasma bombardment, part of the plasma will be injected into the first work function layer 103 and the second work function layer 104, thereby reducing the etching rate ratio of the first etching process to the first work function layer 103 and the second work function layer 104, and thereby damaging the first work function layer 103 in the process of removing the second work function layer 104 (as shown in part A of FIG. 6), thereby affecting the threshold voltage required by the corresponding transistor. Figure 3

[0029] On this basis, the application provides a forming method of a semiconductor structure, which can effectively reduce the etching damage to the first work function layer in the process of removing the second work function layer, thereby reducing the influence on the threshold voltage required by the corresponding transistor, so as to improve the performance of the finally formed semiconductor structure.

[0030] In order to make the above-mentioned purposes, characteristics and advantages of the application more obvious and easy to understand, the specific embodiments of the application will be described in detail below with reference to the drawings.

[0031] Figures 4 to 10 is a structure schematic diagram of a forming process of a semiconductor structure according to an embodiment of the application.

[0032] Please refer to Figure 4 , a substrate is provided, which includes a base 200 and a first fin 201 and a second fin 202 on the base.

[0033] In the embodiment, the forming method of the substrate includes: providing an initial substrate (not shown); forming a first patterning layer (not shown) on the initial substrate, which exposes part of the top surface of the initial substrate; etching the initial substrate with the first patterning layer as a mask to form the substrate; and removing the first patterning layer after forming the substrate.

[0034] In the embodiment, the material of the substrate is silicon; in other embodiments, the material of the substrate can also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.

[0035] ​In the embodiment, the first fin 201 and the second fin 202 are made of silicon; in other embodiments, the first fin and the second fin can also be made of germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.

[0036] Referring to Figure 5 An isolation layer 203 is formed on the substrate, covering part of the sidewall of the first fin 201 and part of the sidewall of the second fin, and the top surface of the isolation layer 203 is lower than the top surface of the first fin 201 and the second fin 202.

[0037] In the embodiment, the isolation layer 203 is formed by forming an isolation material layer (not shown) on the substrate, covering the sidewall of the first fin 201 and the second fin 202; and etching back the isolation material layer to form the isolation layer 203.

[0038] The material of the isolation layer 203 is an insulating material, including silicon oxide, silicon nitride or silicon oxynitride; in the embodiment, the material of the isolation layer 203 is silicon oxide.

[0039] In the embodiment, after the isolation layer 203 is formed, a pseudo gate structure (not shown) is formed on the isolation layer, crossing the first fin 201 and the second fin 202; a sidewall (not shown) is formed on the sidewall of the pseudo gate structure; the first fin 201 and the second fin 202 are etched with the pseudo gate structure and the sidewall as masks, respectively, to form a first source-drain opening (not shown) in the first fin 201 and a second source-drain opening (not shown) in the second fin 202; a first source-drain doped layer (not shown) is formed in the first source-drain opening, and a second source-drain doped layer (not shown) is formed in the second source-drain opening; a dielectric layer (not shown) is formed on the isolation layer 203, covering the pseudo gate structure and exposing the sidewall of the pseudo gate structure; the pseudo gate structure is removed, and a gate opening (not shown) is formed in the dielectric layer, exposing part of the surface of the first fin 201 and part of the surface of the second fin 202.

[0040] In the embodiment, the first fin 201 is used to form an NMOS transistor; and the second fin 202 is used to form a PMOS transistor. Therefore, the doped ions in the first source-drain doped layer are N-type ions, and the doped ions in the second source-drain doped layer are P-type ions.

[0041] Referring to Figure 6After forming the isolation layer 203, a gate dielectric layer 204 is formed on the surface of the first fin 201 and the surface of the second fin 202 exposed by the gate opening.

[0042] In this embodiment, the gate dielectric layer 204 is a multi-layer structure; in other embodiments, the gate dielectric layer can also be a single-layer structure.

[0043] In this embodiment, the material of the gate dielectric layer 204 adopts a high-K dielectric layer material and titanium silicon nitride (TiSiN).

[0044] Please refer to Figure 7 After forming the gate dielectric layer 204, a first work function layer 205 is formed on the surface of the first fin 201 and the surface of the second fin 202 exposed by the gate opening.

[0045] In this embodiment, the first work function layer 205 is located on the surface of the gate dielectric layer 204.

[0046] In this embodiment, the forming process of the first work function layer 205 adopts an atomic layer deposition process.

[0047] In this embodiment, the material of the first work function layer 205 adopts tantalum nitride.

[0048] Please refer to Figure 8 After forming the first work function layer 205, a second work function layer 206 is formed on the first work function layer 205.

[0049] In this embodiment, the forming process of the second work function layer 206 adopts an atomic layer deposition process.

[0050] In this embodiment, the material of the second work function layer 206 adopts titanium nitride.

[0051] In this embodiment, the first work function layer 205 and the second work function layer 206 are used to adjust the threshold voltage of the transistor formed by the first fin 201 and the second fin 202.

[0052] After forming the second work function layer 206, a first etching process is further included to remove the second work function layer 206 on the first fin 201, and in the process of removing the second work function layer 206 on the first fin 201, a protective layer is formed on the surface of the first work function layer 205 on the first fin 201. For details, please refer to Figures 9 to 10 .

[0053] Please refer to Figure 9forming a patterned layer 208 on the substrate, the patterned layer 208 has an etching opening 209 exposing the second work function layer 206 on the first fin 201.

[0054] In the embodiment, the forming method of the patterned layer 208 includes: forming an initial patterned layer (not shown) on the substrate, the initial patterned layer covers the second work function layer 206; forming a photoresist layer 207 on the initial patterned layer, the photoresist layer 207 exposes part of the top surface of the initial patterned layer; using the photoresist layer 207 as a mask, etching the initial patterned layer by a second etching process to form the patterned layer 208.

[0055] In the embodiment, the material of the initial patterned layer is an anti-reflective coating.

[0056] In the embodiment, the second etching process includes: a dry etching process of plasma; the process parameters of the dry etching process of plasma include: etching gases CH4, H2 and N2; the flow rate of each etching gas is that the flow rate of CH4 is 5sccm-10sccm, the flow rate of H2 is 450sccm-600sccm, and the flow rate of N2 is 40sccm-60sccm; the injection energy is 55W-70W.

[0057] In the embodiment, the second etching process is a dry etching process of plasma, which uses plasma ionization to bombard and etch, can effectively improve the etching rate of etching the initial patterned layer, and can make the finally formed etching opening 209 have a good morphology. However, in the process of plasma bombardment, part of the plasma will be injected into the first work function layer 205 and the second work function layer 206, thereby reducing the etching rate ratio of the subsequent etching process on the first work function layer 205 and the second work function layer 206, and thereby damaging the first work function layer 205 in the process of removing the second work function layer 206.

[0058] Please refer to Figure 9 using the first etching process to remove the second work function layer 206 on the first fin 201 with the sacrificial layer 208 as a mask.

[0059] In the embodiment, since the transistors formed based on the first fin 201 and the second fin 202 have different requirements for the number of work function layers, the second work function layer 206 on the first fin 201 is removed to meet the required threshold voltage of the corresponding transistor.

[0060] In the embodiment, the first etching process is a SiCoNi isotropic dry etching process.

[0061] In the embodiment, the SiCoNi isotropic dry etching process includes the following process parameters: etching gases O2, He and Cl2; power 400W-440W; pressure 25mTorr-45mTorr; flow rate of each etching gas Cl2 7.5sccm, He 51sccm, O2 0.2sccm-0.4sccm.

[0062] Since the first etching process includes a certain amount of O2 in the etching gas, a protective layer 210 can be formed on the surface of the first work function layer 205 on the first fin 201 in the process of removing the second work function layer 206 on the first fin 201. By forming the protective layer 210 on the surface of the first work function layer 205, the etching damage to the first work function layer 210 in the process of removing the second work function layer 206 can be effectively reduced, thereby reducing the influence on the threshold voltage required by the corresponding transistor, so as to improve the performance of the finally formed semiconductor structure.

[0063] In the embodiment, the content of O2 in the etching gas is 0.3%-0.7%. When the content of O2 in the etching gas is greater than 0.7%, the content of other etching gases that actually participate in etching will be reduced, thereby affecting the final etching effect; when the content of O2 in the etching gas is less than 0.3%, the oxidation effect on the first work function layer 205 is weak, so that the thickness of the protective layer 210 formed is small, thereby affecting the protection effect of the protective layer 210 on the first work function layer 205.

[0064] Please continue to refer to Figure 10 After removing the second work function layer 206 on the first fin 201, the method further includes: removing the patterned layer 208 and the photoresist layer 207.

[0065] The process of removing the photoresist layer 207 includes a wet stripping process or an ashing process. In the embodiment, the process of removing the photoresist layer 207 adopts an ashing process, and the gas of the ashing process is an oxygen-containing gas, such as oxygen or ozone.

[0066] In the embodiment, the process of removing the patterned layer 208 adopts a wet etching process; in other embodiments, the process of removing the patterned layer can also adopt a dry etching process.

[0067] Although the present application has been disclosed with reference to the above embodiments, the application is not limited to the above embodiments. It will be apparent to those skilled in the art that various modifications and changes can be made thereto without departing from the spirit and scope of the application. The scope of the application should be limited only by the appended claims.

Claims

1. A method of forming a semiconductor structure, characterized by, The application relates to a method for manufacturing a substrate, which comprises the following steps: providing a substrate, which comprises a base and a first fin and a second fin on the base; forming an isolation layer on the substrate, which covers part of the sidewall of the first fin and part of the sidewall of the second fin, and the top surface of the isolation layer is lower than the top surface of the first fin and the second fin; forming a pseudo-gate structure on the isolation layer, which spans the first fin and the second fin; forming a sidewall on the sidewall of the pseudo-gate structure; forming a dielectric layer on the isolation layer, which covers the pseudo-gate structure and exposes the sidewall of the pseudo-gate structure; removing the pseudo-gate structure to form a gate opening in the dielectric layer, which exposes part of the surface of the first fin and part of the surface of the second fin; forming a first work function layer on the surface of the first fin and the surface of the second fin exposed by the gate opening; forming a second work function layer on the first work function layer; forming a patterned layer on the substrate, which has an etching opening exposing the second work function layer on the first fin in the patterned layer; using the patterned layer as a mask, removing the second work function layer on the first fin by a first etching process, and forming a protective layer on the surface of the first work function layer on the first fin in the process of removing the second work function layer on the first fin.

2. The method of forming a semiconductor structure of claim 1, wherein, The first etching process comprises a SiCoNi isotropic dry etching process.

3. The method of forming a semiconductor structure of claim 2, wherein, The process parameters of the SiCoNi isotropic dry etching process comprise: etching gas O2, He and Cl2; power is 400-440 W; pressure is 25-45 mTorr; the flow rate of each etching gas is 7.5 sccm for Cl2, 51 sccm for He and 0.2-0.4 sccm for O2.

4. The method of forming a semiconductor structure of claim 3, wherein, The content of O2 in the etching gas is 0.3-0.7%.

5. The method of forming a semiconductor structure of claim 1, wherein, The first fin is used for forming an NMOS transistor, and the second fin is used for forming a PMOS transistor.

6. The method of forming a semiconductor structure of claim 1, wherein, The material of the first work function layer comprises tantalum nitride, and the material of the second work function layer comprises titanium nitride.

7. The method of forming a semiconductor structure of claim 1, wherein, The forming method of the patterned layer comprises the following steps: forming an initial patterned layer on the substrate, which covers the second work function layer; forming a photoresist layer on the initial patterned layer, which exposes part of the top surface of the initial patterned layer; using the photoresist layer as a mask, etching the initial patterned layer by a second etching process to form the patterned layer.

8. The method of forming a semiconductor structure of claim 7, wherein, The material of the initial patterned layer comprises an antireflection coating.

9. The method of forming a semiconductor structure of claim 7, wherein, The second etching process comprises a plasma dry etching process.

10. The method of forming a semiconductor structure of claim 9, wherein, The process parameters of the dry etching process of the plasma include: etching gas CH4, H2 and N2; the flow rate of each etching gas is 5-10 sccm for CH4, 450-600 sccm for H2 and 40-60 sccm for N2; and the injection energy is 55-70 W.

11. The method of forming a semiconductor structure of claim 1, wherein, Before the first work function layer and the second work function layer are formed, the method further includes: forming a gate dielectric layer on surfaces of the first fin portion and the second fin portion exposed by the gate opening, and the first work function layer is located on a surface of the gate dielectric layer.

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