Display panel and display device

Abstract

The application discloses a display panel and a display device. The display panel comprises a first transistor and a second transistor which are electrically connected, the first transistor comprises a first active part formed by low-temperature polysilicon material, and the second transistor comprises a second gate and a second active part formed by metal oxide material; the display panel further comprises a substrate, the first active part is arranged on the substrate; the second active part is located on a side of the first active part away from the substrate; the second gate is located on a side of the second active part away from the first active part; and a normal projection of the second active part on the substrate and a normal projection of the first active part on the substrate at least partially overlap. The application can improve the space utilization and resolution of the display panel.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel and a display device having the same. BACKGROUND

[0002] Low Temperature Polycrystalline Oxide (LTPO) array substrate generally adopts Low Temperature Poly-Silicon (LTPS) and metal oxide such as Indium Gallium Zinc Oxide (IGZO) to manufacture Thin Film Transistor (TFT), wherein the LTPS is responsible for driving the TFT, and the metal oxide is responsible for switching the TFT. The LTPO array substrate has the advantages of higher charge mobility and lower off-state leakage current, which can reduce the overall power consumption of the screen during operation and achieve the purpose of power saving.

[0003] However, in the display panel with the LTPO array substrate at present, an electrode plate is formed above the gate of the low-temperature polycrystalline silicon TFT, which needs to occupy a large space, and the low-temperature polycrystalline silicon TFT and the metal oxide TFT are both independently arranged in the LTPO array substrate, which also needs to occupy a large space, which is not conducive to the improvement of the space utilization and resolution of the display panel. SUMMARY

[0004] The embodiments of the present application provide a display panel and a display device, which can reduce the occupied space of the first transistor and the second transistor, and improve the space utilization and resolution of the display panel.

[0005] The embodiments of the present application provide a display panel, which comprises a first transistor and a second transistor connected in an electrical manner, the first transistor comprises a first active part formed by a low-temperature polycrystalline silicon material, and the second transistor comprises a second gate and a second active part formed by a metal oxide material.

[0006] The display panel further comprises:

[0007] a substrate;

[0008] a first active layer arranged on the substrate and comprising the first active part;

[0009] a second active layer arranged on a side of the first active layer away from the substrate and comprising the second active part located on a side of the first active part away from the substrate;

[0010] a first metal layer disposed on a side of the second active layer away from the first active layer and including the second gate on a side of the second active part away from the first active part;

[0011] wherein a projection of the second active part on the substrate at least partially overlaps a projection of the first active part on the substrate.

[0012] In an embodiment of the present application, the second transistor further includes a second source and a second drain, and the display panel further includes a second metal layer disposed between the second active layer and the first active layer, the second metal layer including the second source and the second drain, and the second active part having two ends connected to the second source and the second drain respectively.

[0013] In an embodiment of the present application, the second active part includes a second source contact sub-part on a side of the second source away from the first active part, a second drain contact sub-part on a side of the second drain away from the first active part, and a second channel sub-part connected between the second source contact sub-part and the second drain contact sub-part, the second channel sub-part being between the second source and the second drain.

[0014] In an embodiment of the present application, the material of the second source contact sub-part has a resistivity equal to a resistivity of the material of the second drain contact sub-part, which is equal to a resistivity of the material of the second channel sub-part.

[0015] In an embodiment of the present application, the first transistor includes a first source and a first drain overlapped with two ends of the first active part.

[0016] The second metal layer further includes the first source and the first drain, and the second active part is between the first source and the first drain.

[0017] In an embodiment of the present application, the first active part includes a first source contact sub-part connected to the first source and a first drain contact sub-part connected to the first drain, and the second source is electrically connected to the first drain contact sub-part.

[0018] In an embodiment of the present application, the first source is disposed apart from the second drain.

[0019] In an embodiment of the present application, the display panel further comprises a light shielding layer disposed in the substrate, the first active part further comprises a first channel sub-part connected between the first source contact sub-part and the first drain contact sub-part, and a projection of the first channel sub-part on the substrate and a projection of the second channel sub-part on the substrate are both located within a projection of the light shielding layer on the substrate.

[0020] In an embodiment of the present application, the display panel further comprises an anode layer disposed on a side of the first metal layer away from the second active layer, and the anode layer comprises an anode electrically connected to the first transistor.

[0021] The first metal layer comprises a transfer part between the anode and the first drain, and the anode is connected to the first drain through the transfer part.

[0022] In an embodiment of the present application, a projection of the second channel sub-part on the substrate is located within a projection of the anode on the substrate.

[0023] In an embodiment of the present application, the display panel further comprises an inorganic passivation layer and an organic planarization layer disposed between the second active layer and the anode layer, the inorganic passivation layer covers the second active part, and the organic planarization layer covers the inorganic passivation layer.

[0024] In an embodiment of the present application, the first transistor further comprises a first gate disposed between the first active part and the second active part, and an electrode plate disposed between the first gate and the second active part.

[0025] The projection of the second channel sub-part on the substrate is located within a projection of the first gate on the substrate, and / or the projection of the second channel sub-part on the substrate is located within a projection of the electrode plate on the substrate.

[0026] According to the above-mentioned purposes of the present application, the embodiments of the present application further provide a display device comprising the display panel.

[0027] The present application has the following advantages: by at least partially overlapping the first active part of the first transistor and the second active part of the second transistor, the first transistor and the second transistor are at least partially overlapped, the occupied space of the first transistor and the second transistor is effectively reduced, and the space utilization and resolution of the display panel are improved. BRIEF DESCRIPTION OF DRAWINGS

[0028] The technical scheme and other beneficial effects of the present application will be apparent from the following detailed description of the embodiments of the present application, taken in conjunction with the accompanying drawings.

[0029] Figure 1 A schematic view of a cross-section structure of a display panel in the related art;

[0030] Figure 2 A schematic view of a cross-section structure of a display panel provided by an embodiment of the present application;

[0031] Figure 3 A schematic view of another cross-section structure of a display panel provided by an embodiment of the present application;

[0032] Figure 4 A schematic view of another cross-section structure of a display panel provided by an embodiment of the present application;

[0033] Figure 5 A schematic view of another cross-section structure of a display panel provided by an embodiment of the present application;

[0034] Figure 6 A flow chart of a manufacturing method of a display panel provided by an embodiment of the present application. DETAILED DESCRIPTION

[0035] The technical scheme and other beneficial effects of the present application will be apparent from the following detailed description of the embodiments of the present application, taken in conjunction with the accompanying drawings.

[0036] The following disclosure provides many different embodiments, or examples, for implementing different structures of the present application. For purposes of simplicity and clarity, the description is divided into sections. Of course, it is to be understood that not necessarily all objects or advantages described can be achieved in accordance with any particular embodiment. Moreover, it should be noted that the language used is merely descriptive, and not restrictive. Specific details are given in the description to provide a thorough understanding of the embodiments of the application. However, the application may

[0037] Reference will now be made to the drawings, in which Figure 1In the related art, in a display panel with an LTPO array substrate, a low-temperature polysilicon thin film transistor A and a metal oxide thin film transistor B need to be prepared on the substrate respectively, and a capacitor plate 1 is formed above the gate of the low-temperature polysilicon thin film transistor A. Since the area of the capacitor plate 1 is large, a large space needs to be occupied. Moreover, the low-temperature polysilicon thin film transistor A and the metal oxide thin film transistor B are both independently arranged in the LTPO array substrate, which also needs to occupy a large space, and is not conducive to the improvement of the space utilization and resolution of the display panel.

[0038] Please refer to Figure 2 The display panel provided by the embodiments of the present application comprises a first transistor T1 and a second transistor T2 connected in an electrical manner, the first transistor T1 comprises a first active part 21 of a low-temperature polysilicon material, and the second transistor T2 comprises a second gate 41 and a second active part 31 of a metal oxide material.

[0039] Further, the display panel further comprises a substrate 10, a first active layer 20, a second active layer 30, and a first metal layer 40. The first active layer 20 is arranged on the substrate 10 and comprises the first active part 21. The second active layer 30 is arranged on a side of the first active layer 20 away from the substrate 10 and comprises the second active part 31 located on a side of the first active part 21 away from the substrate 10. The first metal layer 40 is arranged on a side of the second active layer 30 away from the first active layer 20 and comprises the second gate 41 located on a side of the second active part 31 away from the first active part 21.

[0040] The second active part 31 is arranged to at least partially overlap the first active part 21 on the substrate 10.

[0041] In the implementation and application process, the first active part 21 of the first transistor T1 and the second active part 31 of the second transistor T2 are arranged to at least partially overlap, so that the first transistor T1 and the second transistor T2 at least partially overlap, the occupied space of the first transistor T1 and the second transistor T2 is effectively reduced, and the space utilization and resolution of the display panel are improved. In addition, the second gate 41 of the second transistor T2 is arranged on a side of the second active part 31 away from the first active part 21, which can avoid the space conflict between the second gate 41 and the electrode plate, reduce the generation of parasitic capacitance, and improve the reliability and stability of the display panel. Figure 1

[0042] Specifically, please refer to Figure 2 The display panel comprises a substrate 10, a driving circuit layer arranged on the substrate 10, and a light-emitting functional layer arranged on a side of the driving circuit layer away from the substrate 10. ​

[0043] The base 10 can include a first flexible substrate layer 11, a first water-oxygen barrier layer 12, a second flexible substrate layer 13, a second water-oxygen barrier layer 14, and a third water-oxygen barrier layer 15 which are sequentially stacked. The first flexible substrate layer 11 and the second flexible substrate layer 13 can include a polyimide material, and the first water-oxygen barrier layer 12, the second water-oxygen barrier layer 14, and the third water-oxygen barrier layer 15 can include at least one of a silicon oxide material and a silicon nitride material.

[0044] The driving circuit layer is disposed on the base 10, and the display panel further includes a buffer layer 71 disposed between the base 10 and the driving circuit layer. The driving circuit layer includes a first transistor T1 and a second transistor T2 disposed on the buffer layer 71. The first transistor T1 and the second transistor T2 are electrically connected. The first transistor T1 includes a first active part 21, a first gate 61, an electrode plate 62, a first source 51, and a first drain 52. The second transistor T2 includes a second active part 31, a second gate 41, a second source 53, and a second drain 54.

[0045] Further, the driving circuit layer includes a first active layer 20 disposed on the buffer layer 71, a first insulating layer 72 covering the first active layer 20, the first gate 61 disposed on the first insulating layer 72, a gate insulating layer 73 covering the first gate 61, the electrode plate 62 disposed on the gate insulating layer 73, a second insulating layer 74 covering the electrode plate 62, a second metal layer 50 disposed on the second insulating layer 74, a second active layer 30 disposed on the second metal layer 50, an inorganic passivation layer 75 covering the second metal layer 50 and the second active layer 30, a first metal layer 40 disposed on the inorganic passivation layer 75, an organic planarization layer 76 covering the first metal layer 40, an anode layer 80 disposed on the organic planarization layer 76, and a pixel definition layer 77 disposed on the anode layer 80.

[0046] Specifically, the first active layer 20 includes the first active part 21, and a material of the first active part 21 includes a low-temperature polysilicon material. The first gate 61 is disposed on a side of the first active part 21 away from the base 10, and the electrode plate 62 is located on a side of the first gate 61 away from the first active part 21. The second metal layer 50 includes the first source 51 and the first drain 52. The first source 51 and the first drain 52 are both connected to both ends of the first active part 21 through the second insulating layer 74, the gate insulating layer 73, and the first insulating layer 72.

[0047] Correspondingly, the first active part 21 includes a first source contact sub-part 211 connected to the first source 51, a first drain contact sub-part 212 connected to the first drain 52, and a first channel sub-part 213 connected between the first source contact sub-part 211 and the first drain contact sub-part 212.

[0048] In an embodiment, the first source contact sub-portion 211 and the first drain contact sub-portion 212 can be subjected to a conductorization process, so that the resistivity of the material of the first source contact sub-portion 211 and the resistivity of the material of the first drain contact sub-portion 212 are less than the resistivity of the material of the first channel sub-portion 213.

[0049] The first transistor T1 can be a dual-gate thin-film transistor, and further, the electrode plate 62 and the first gate 61 can constitute a storage capacitor of a sub-pixel unit, thereby improving the continuous display effect of the display device.

[0050] The second metal layer 50 further comprises a second source electrode 53 and a second drain electrode 54, and the second active layer 30 comprises a second active portion 31, which is partially located on the second insulating layer 74 and partially extends to the side of the second source electrode 53 and the second drain electrode 54 away from the first active portion 21; wherein the second active portion 31 comprises a second source contact sub-portion 311 located on the side of the second source electrode 53 away from the first active portion 21, a second drain contact sub-portion 312 located on the side of the second drain electrode 54 away from the first active portion 21, and a second channel sub-portion 313 connected between the second source contact sub-portion 311 and the second drain contact sub-portion 312, and the second channel sub-portion 313 is located between the second source electrode 53 and the second drain electrode 54.

[0051] It should be noted that in the process, the second source electrode 53 and the second drain electrode 54 are formed first, and then the second active portion 31 is formed, and thus the length of the second channel sub-portion 313 located between the second source electrode 53 and the second drain electrode 54 can be controlled by controlling the distance between the second source electrode 53 and the second drain electrode 54, so as to realize the second transistor T2 with a short channel.

[0052] In the embodiment of the present application, the orthographic projection of the second active portion 31 on the substrate 10 at least partially overlaps with the orthographic projection of the first active portion 21 on the substrate 10, and thus the second transistor T2 can at least partially overlap with the first transistor T1, so as to reduce the space ratio of the first transistor T1 and the second transistor T2, and improve the space utilization and resolution of the display panel; in addition, since the area of the electrode plate 62 is large, and the second gate 41 of the second transistor T2 is arranged on the side of the second active portion 31 away from the first active portion 21 in the embodiment of the present application, thus the space conflict between the second gate 41 and the electrode plate 62 can be avoided, and the generation of parasitic capacitance can be reduced, thereby improving the reliability and stability of the display panel.

[0053] The first metal layer 40 comprises a second gate 41, and the second gate 41 is located on the side of the second active portion 31 away from the first active portion 21.

[0054] In one embodiment, the second channel sub-section 313 is connected between the second source 53 and the second drain 54. When the second gate 41 is subjected to a voltage, a current path can be formed in the second channel sub-section 313. In this way, a current path can be directly formed between the second source 53 and the second drain 54 without the need to perform conductor processing on the second active section 31.

[0055] Compared to related technologies, such as Figure 1 As shown, the active layer 2 of the metal-oxide-slim thin-film transistor B needs to be conductive to form an electrical connection with the source and drain. However, since the active layer 2 of the metal-oxide-slim thin-film transistor B is fabricated using a metal-oxide process, it is easily affected by the thermal process during subsequent film deposition, causing carriers in the conductive portion to diffuse into the channel portion of the active layer, resulting in instability of the metal-oxide-slim thin-film transistor B. Furthermore, in related technologies, two inorganic insulating layers, an interlayer insulating layer 3 and a passivation layer 4, are disposed above the active layer 2 of the metal-oxide-slim thin-film transistor B. In this embodiment of the invention, as... Figure 2 As shown, the second active part 31 is disposed above the first transistor T1, and only one inorganic insulating layer 75 is disposed above the second active part 31. This reduces the number of inorganic insulating layers above the second active part 31, thereby reducing the impact of the thermal process during the formation of the inorganic insulating layer on the second active part 31, and further improving the stability and yield of the second transistor T2.

[0056] Furthermore, such as Figure 2 As shown, by placing the second gate 41 on the second active portion 31 and increasing the coverage area of ​​the second gate 41, the second channel sub-port 313 corresponding to the second gate 41 is connected between the second source 53 and the second drain 54. A current path can be directly formed between the second source 53 and the second drain 54, so that the second active portion 31 does not need to be conductord, which can save the conductor process and avoid the phenomenon of carrier diffusion caused by the thermal process of the second active portion 31, thereby improving the stability and yield of the second transistor T2.

[0057] In one embodiment, since the second active portion 31 does not need to be conductive, and the resistivity of the material of the second source contact portion 311 and the resistivity of the material of the second drain contact portion 312 are both equal to the resistivity of the material of the second channel portion 313.

[0058] In the embodiment of the present application, the first source electrode 51, the first drain electrode 52, the second source electrode 53 and the second drain electrode 54 can be formed in the same process, thereby saving the process steps, and the second active part 31 is located between the first source electrode 51 and the first drain electrode 52, the second drain electrode 54 is arranged apart from the first source electrode 51, and the second source electrode 53 is connected to the first drain electrode 52 through the first drain contact sub-part 212, that is, the second source electrode 53 can be connected to the first drain contact sub-part 212 through the second insulating layer 74, the gate insulating layer 73 and the first insulating layer 72.

[0059] Further, the display panel further comprises a light shielding layer 17 arranged in the substrate 10, and a normal projection of the first channel sub-part 213 on the substrate 10 is located within a coverage range of a normal projection of the light shielding layer 17 on the substrate 10.

[0060] It should be noted that in the embodiment of the present application, the light shielding layer 17 is formed in the substrate 10, and the light shielding layer 17 can be located between any two adjacent film layers in the substrate 10, for example, located on the second water-oxygen barrier layer 14 and covered by the third water-oxygen barrier layer 15.

[0061] In an embodiment, the coverage range of the light shielding layer 17 is increased, that is, a normal projection of the second channel sub-part 313 on the substrate 10 is located within a coverage range of a normal projection of the light shielding layer 17 on the substrate 10, as shown in FIG. 6, and further, the light can be blocked from being irradiated to the second channel sub-part 313 from the side of the second active part 31 close to the substrate 10, thereby improving the stability of the second transistor T2. Figure 2

[0062] In an embodiment, the coverage range of the first gate electrode 61 is increased, that is, a normal projection of the second channel sub-part 313 on the substrate 10 is located within a coverage range of a normal projection of the first gate electrode 61 on the substrate 10, as shown in FIG. 7, and further, the light can be blocked from being irradiated to the second channel sub-part 313 from the side of the second active part 31 close to the substrate 10, thereby improving the stability of the second transistor T2. Figure 3

[0063] In an embodiment, the coverage range of the electrode plate 62 is increased, that is, a normal projection of the second channel sub-part 313 on the substrate 10 is located within a coverage range of a normal projection of the electrode plate 62 on the substrate 10, as shown in FIG. 8, and further, the light can be blocked from being irradiated to the second channel sub-part 313 from the side of the second active part 31 close to the substrate 10, thereby improving the stability of the second transistor T2. Figure 4

[0064] ​​​In one embodiment, the coverage of at least two of the light-shielding layer 17, the first gate 61, and the electrode plate 62 can be increased such that the orthographic projection of the second channel sub-section 313 on the substrate 10 is within the coverage of at least two of the orthographic projections of the light-shielding layer 17 on the substrate 10, the orthographic projections of the first gate 61 on the substrate 10, and the orthographic projections of the electrode plate 62 on the substrate 10.

[0065] In addition, the display panel also includes an anode layer 80 disposed on the side of the first metal layer 40 away from the second active layer 30, and the anode layer 80 includes an anode 81 electrically connected to the first transistor T1, and the anode 81 is electrically connected to the first drain 52.

[0066] In one embodiment, the first metal layer 40 further includes a transition portion 42, and the anode 81 is connected to the first drain 52 through the transition portion 42. By preparing the anode 81 and the transition portion 42 in the same layer, the process can be simplified and the process cost reduced.

[0067] The orthogonal projection of the second channel sub-section 313 onto the substrate 10 is within the coverage area of ​​the orthogonal projection of the anode 81 onto the substrate 10, thereby blocking light from the side of the second active section 31 away from the substrate 10 from shining onto the second channel sub-section 313, further improving the stability of the second transistor T2.

[0068] In one embodiment, please refer to Figure 5 The second source 53 and the second drain 54 are connected, that is, the second source 53 and the second drain 54 are integrally formed, which can further simplify the process and reduce the process cost.

[0069] Continuing from the above, this embodiment of the invention, by at least partially overlapping the first active portion 21 of the first transistor T1 and the second active portion 31 of the second transistor T2, can effectively reduce the space occupied by the first transistor T1 and the second transistor T2, thereby improving the space utilization and resolution of the display panel. In addition, this embodiment of the invention places the second gate 41 of the second transistor T2 on the side of the second active portion 31 away from the first active portion 21. Compared with the prior art, this can avoid spatial conflict between the second gate 41 and the electrode plate, and can reduce the generation of parasitic capacitance, thereby improving the reliability and stability of the display panel.

[0070] In addition, this embodiment of the invention also provides a method for manufacturing a display panel, which is the display panel described in the above embodiments. Please refer to... Figure 2 The manufacturing method of this display panel includes the following steps:

[0071] Provide base 10.

[0072] A first active layer 20 is formed on the substrate 10, and the first active layer 20 includes a first active part 21 of a first transistor T1, which is made of a low-temperature polysilicon material.

[0073] A second active layer 30 is formed on a side of the first active layer 20 away from the substrate 10, and the second active layer 30 includes a second active part 31 of a second transistor T2, which is formed on a side of the first active part 21 away from the substrate 10 and made of a metal oxide material, wherein a normal projection of the second active part 31 on the substrate 10 at least partially overlaps a normal projection of the first active part 21 on the substrate 10.

[0074] A first metal layer 40 is formed on a side of the second active layer 30 away from the first active layer 20, and the first metal layer 40 includes a second gate 41 of the second transistor T2, which is formed on a side of the second active part 31 away from the first active part 21.

[0075] Specifically, please refer to Figure 2 and Figure 6 The manufacturing method of the display panel includes the following steps:

[0076] S10, providing a substrate 10.

[0077] In step S10, the substrate 10 can include a first flexible substrate layer 11, a first water-oxygen barrier layer 12, a second flexible substrate layer 13, a second water-oxygen barrier layer 14, and a third water-oxygen barrier layer 15 which are sequentially stacked; the materials of the first flexible substrate layer 11 and the second flexible substrate layer 13 can include polyimide material, and the materials of the first water-oxygen barrier layer 12, the second water-oxygen barrier layer 14, and the third water-oxygen barrier layer 15 can include at least one of silicon oxide material and silicon nitride material.

[0078] It should be noted that in the embodiment of the present application, the light shielding layer 17 is formed in the substrate 10, and the light shielding layer 17 can be located between any two adjacent film layers in the substrate 10, for example, located on the second water-oxygen barrier layer 14 and covered by the third water-oxygen barrier layer 15.

[0079] S20, forming a first active layer 20 on the substrate 10, and the first active layer 20 includes a first active part 21 of a first transistor T1, which is made of a low-temperature polysilicon material.

[0080] In step S20, a buffer layer 71 is formed on the substrate 10.

[0081] Then, the first transistor T1 is formed on the side of the buffer layer 71 away from the substrate 10, specifically including forming the first active part 21 on the buffer layer 71 using low-temperature polysilicon material, forming the first insulating layer 72 covering the first active part 21 on the buffer layer 71, forming the first gate 61 on the first insulating layer 72 at the side of the first active part 21 away from the substrate 10, forming the gate insulating layer 73 covering the first gate 61 on the first insulating layer 72, forming the electrode plate 62 on the gate insulating layer 73 at the side of the first gate 61 away from the first active part 21, forming the second insulating layer 74 covering the electrode plate 62 on the gate insulating layer 73, and forming the first metal material layer on the second insulating layer 74. The first active part 21 includes the first channel sub-part 213 and the first source contact sub-part 211 and the first drain contact sub-part 212 connected to the two sides of the first channel sub-part 213.

[0082] Then, the first metal material layer is patterned to obtain the second metal layer 50, so as to obtain the first source 51 and the first drain 52 of the first transistor T1, and the first source 51 and the first drain 52 are connected to the first source contact sub-part 211 and the first drain contact sub-part 212 respectively through the second insulating layer 74, the gate insulating layer 73 and the first insulating layer 72.

[0083] In addition, the second metal layer 50 also forms the second source 53 and the second drain 54 of the second transistor T2, and since the second transistor T2 needs to be electrically connected with the first transistor T1, the second source 53 can also be connected to the first drain contact sub-part 212 through the second insulating layer 74, the gate insulating layer 73 and the first insulating layer 72.

[0084] S30, forming the second active layer 30 on the side of the first active layer 20 away from the substrate 10, the second active layer 30 including the second active part 31 of the second transistor T2, the second active part 31 being formed on the side of the first active part 21 away from the substrate 10 and being made of metal oxide material, wherein the orthographic projection of the second active part 31 on the substrate 10 at least partially overlaps the orthographic projection of the first active part 21 on the substrate 10.

[0085] In step S30, the metal oxide layer is formed on the side of the second metal layer 50 away from the substrate 10, and the material of the metal oxide layer can be indium gallium zinc oxide.

[0086] Then, the metal oxide layer is patterned to obtain the second active layer 30, and the second active layer 30 includes a second active part 31 which is patterned, and the second active part 31 is partially located on the second insulating layer 74 and partially extends the second source electrode 53 and the second drain electrode 54 away from one side of the first active part 21; wherein the second active part 31 includes a second source electrode contact sub-part 311 located on one side of the second source electrode 53 away from the first active part 21, a second drain electrode contact sub-part 312 located on one side of the second drain electrode 54 away from the first active part 21, and a second channel sub-part 313 connected between the second source electrode contact sub-part 311 and the second drain electrode contact sub-part 312.

[0087] In the embodiment of the present application, the orthographic projection of the second active part 31 on the substrate 10 at least partially overlaps the orthographic projection of the first active part 21 on the substrate 10, so that the second transistor T2 at least partially overlaps the first transistor T1, thereby reducing the space occupancy of the first transistor T1 and the second transistor T2 and improving the space utilization and resolution of the display panel.

[0088] In addition, in the embodiment of the present application, the second source electrode 53 and the second drain electrode 54 are prepared first, and then the second active part 31 is prepared, so that the length of the second channel sub-part 313 between the second source electrode 53 and the second drain electrode 54 can be controlled by controlling the distance between the second source electrode 53 and the second drain electrode 54, so as to realize the second transistor T2 with a short channel.

[0089] An inorganic passivation layer 75 covering the second metal layer 50 and the second active layer 30 is formed on the second insulating layer 74.

[0090] S40, a first metal layer 40 is formed on one side of the second active layer 30 away from the first active layer 20, and the first metal layer 40 includes a second gate electrode 41 of the second transistor T2, and the second gate electrode 41 is formed on one side of the second active part 31 away from the first active part 21.

[0091] In step S40, a second metal material layer is formed on one side of the inorganic passivation layer 75 away from the second active layer 30, and the second metal material layer is patterned to obtain the first metal layer 40, and the first metal layer 40 includes the second gate electrode 41 formed on one side of the second active part 31 away from the first active part 21 and a transfer part 42 located above the first drain electrode 52, wherein the transfer part 42 is connected with the first drain electrode 52 through the inorganic passivation layer 75.

[0092] In the embodiment of the present application, the second active part 31 comprises a second source contact sub-part 311 located on the side of the second source electrode 53 away from the first active part 21, a second drain contact sub-part 312 located on the side of the second drain electrode 54 away from the first active part 21, and a second channel sub-part 313 connected between the second source contact sub-part 311 and the second drain contact sub-part 312.

[0093] In one embodiment, the orthographic projection of the second channel sub-part 313 on the substrate 10 is within the coverage range of the orthographic projection of the light shielding layer 17 on the substrate 10, which can block the light on the side of the second active part 31 close to the substrate 10 from irradiating on the second channel sub-part 313, further improving the stability of the second transistor T2.

[0094] In one embodiment, the second channel sub-part 313 is connected between the second source electrode 53 and the second drain electrode 54, and thus a current channel can be formed in the second channel sub-part 313 after the second gate 41 is loaded with voltage, and a current channel can be directly formed between the second source electrode 53 and the second drain electrode 54 without the need of conducting treatment of the second active part 31.

[0095] It should be noted that, in the embodiment of the present application, the second gate 41 is arranged on the second active part 31, and the coverage area of the second gate 41 is increased, so that the second channel sub-part 313 corresponding to the second gate 41 is connected between the second source electrode 53 and the second drain electrode 54, a current channel can be directly formed between the second source electrode 53 and the second drain electrode 54, the second active part 31 does not need to be conducted, the conducting process can be saved, and the phenomenon of carrier diffusion of the second active part 31 due to the influence of heat process can be avoided, thereby improving the stability and yield of the second transistor T2.

[0096] In addition, since the area of the electrode plate 62 is large, and the second gate 41 of the second transistor T2 is arranged on the side of the second active part 31 away from the first active part 21 in the embodiment of the present application, the space conflict between the second gate 41 and the electrode plate 62 can be avoided, the generation of parasitic capacitance can be reduced, and the reliability and stability of the display panel are improved.

[0097] Then, an organic planarization layer 76 covering the first metal layer 40 is formed on the side of the first metal layer 40 away from the second active layer 30.

[0098] Next, an anode layer 80 is formed on the side of the organic planarization layer 76 away from the first metal layer 40, and the anode layer 80 comprises an anode 81 electrically connected with the first transistor T1, and the anode 81 is electrically connected with the first drain electrode 52, and further, the anode 81 is electrically connected with the first drain electrode 52 through the adapter 42.

[0099] The second channel sub-part 313 is located in the projection of the anode 81 on the substrate 10, and can block the light from the second active part 31 from the substrate 10 side to the second channel sub-part 313, thereby improving the stability of the second transistor T2.

[0100] Then, a pixel definition layer 77 covering the anode layer 80 is formed on the organic flat layer 76, and a pixel opening is formed in the pixel definition layer 77 to expose part of the upper surface of the anode 81.

[0101] As described above, the first active part 21 of the first transistor T1 and the second active part 31 of the second transistor T2 are at least partially overlapped, thereby effectively reducing the occupied space of the first transistor T1 and the second transistor T2, improving the space utilization and resolution of the display panel. In addition, the second gate 41 of the second transistor T2 is arranged on the side of the second active part 31 away from the first active part 21, which can avoid the space conflict between the second gate 41 and the electrode plate, reduce the generation of parasitic capacitance, and improve the reliability and stability of the display panel.

[0102] In addition, the embodiment of the present application also provides a display device, which comprises the display panel and a device body, and the display panel and the device body are combined as a whole.

[0103] The device body can include a middle frame, a frame glue, etc., and the display device can be a mobile phone, a tablet computer, a television, etc., which are not limited herein.

[0104] In the above embodiments, the description of each embodiment has its own focus, and the parts not described in detail in a certain embodiment can be referred to the related description of other embodiments.

[0105] The display panel and the display device provided by the embodiments of the present application are described in detail above, and the principles and implementation manners of the present application are described by applying specific examples in this paper. The above description of the embodiments is only used to help understand the technical solutions and the core ideas of the present application; those skilled in the art should understand that the technical solutions recorded in the above embodiments can be modified, or some technical features can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display panel, characterized by, The first transistor and the second transistor are electrically connected, the first transistor comprises a first active part formed by a low-temperature polysilicon material, the first transistor comprises a first source and a first drain which are overlapped at two ends of the first active part, and the second transistor comprises a second gate and a second active part formed by a metal oxide material, the second active part comprises a second channel subpart, and the second transistor further comprises a second source and a second drain. The display panel further comprises: a substrate; a first active layer disposed on the substrate and comprising the first active part; a second active layer disposed on a side of the first active layer away from the substrate and comprising the second active part located on a side of the first active part away from the substrate; a first metal layer disposed on a side of the second active layer away from the first active layer and comprising the second gate located on a side of the second active part away from the first active part; a second metal layer disposed between the second active layer and the first active layer, the second metal layer comprising the first source, the first drain, the second source and the second drain, and the second active part being located between the first source and the first drain, and two ends of the second active part being connected to the second source and the second drain respectively; the first transistor further comprises a first gate disposed between the first active part and the second active part, and an electrode plate disposed between the first gate and the second active part; a normal projection of the second channel subpart on the substrate is located within a normal projection of the first gate on the substrate, and / or a normal projection of the second channel subpart on the substrate is located within a normal projection of the electrode plate on the substrate; wherein a normal projection of the second active part on the substrate at least partially overlaps with a normal projection of the first active part on the substrate.

2. The display panel of claim 1, wherein, The second active part comprises a second source contact subpart located on a side of the second source away from the first active part, a second drain contact subpart located on a side of the second drain away from the first active part, and the second channel subpart connected between the second source contact subpart and the second drain contact subpart, the second channel subpart being located between the second source and the second drain.

3. The display panel of claim 2, wherein, The resistivity of the material of the second source contact subpart and the resistivity of the material of the second drain contact subpart are equal to the resistivity of the material of the second channel subpart.

4. The display panel of claim 1, wherein, The first active part comprises a first source contact subpart connected to the first source and a first drain contact subpart connected to the first drain, and the second source is electrically connected to the first drain contact subpart.

5. The display panel of claim 4, wherein, The first source and the second drain are disposed apart from each other.

6. The display panel of claim 4, wherein, The display panel further comprises a light shielding layer arranged in the substrate, the first active part further comprises a first channel sub-part connected between the first source contact sub-part and the first drain contact sub-part, a projection of the first channel sub-part on the substrate and a projection of the second channel sub-part on the substrate are both located within a projection of the light shielding layer on the substrate.

7. The display panel of claim 1, wherein, The display panel further comprises an anode layer arranged on a side of the first metal layer away from the second active layer, the anode layer comprises an anode electrically connected with the first transistor; The first metal layer comprises a transfer part between the anode and the first drain, and the anode is connected with the first drain through the transfer part.

8. The display panel of claim 7, wherein, The projection of the second channel sub-part on the substrate is located within the projection of the anode on the substrate.

9. The display panel of claim 7, wherein, The display panel further comprises an inorganic passivation layer and an organic planarization layer arranged between the second active layer and the anode layer, the inorganic passivation layer covers the second active part, and the organic planarization layer covers the inorganic passivation layer.

10. A display device, characterized by comprising: The display device comprises the display panel according to any one of claims 1 to 9.

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