A light emitting diode chip

Abstract

The present invention relates to the field of semiconductor chip technology, and in particular, to a light-emitting diode chip, comprising: an epitaxial structure unit sequentially arranged on the substrate and an electrode structure unit connected to the electrode of the epitaxial structure unit, wherein the epitaxial structure unit at least comprises an N-type semiconductor layer, an active layer, and a P-type semiconductor layer; the electrode structure unit at least comprises a current spreading layer, a first electrode layer, a first insulating layer, a second electrode layer, a second insulating layer, and a pad layer sequentially arranged, the thickness of the first electrode layer is less than 1.2 μm; the first electrode and the second electrode layer do not contain metal Au. The light-emitting diode chip provided reduces and limits the height of the first electrode, greatly reduces the height of the first electrode, and makes its thickness less than 1.2 μm, and the first electrode layer and / or the second electrode layer do not use metal Au, thereby avoiding a series of problems caused by the breakage of the insulating layer caused by the existing gold particles.

Description

Technical Field

[0001] The present invention relates to the technical field of light-emitting chips, and in particular to a light-emitting diode chip. Background Art

[0002] LED chips are currently widely used in display communications, display lighting, mobile phone flash, display and backlighting, automotive lighting, etc. With the maturity of LED technology and the fierce competition in the industry, higher requirements are put forward for chips, such as reliability, chip thermal resistance, heat dissipation, cost, etc.

[0003] In the metal conductive layer of each LED electrode, metal Au is usually used as the electrode wrapping layer because of its good metal properties. However, during the evaporation process, the insulating layer is broken due to gold particles, which leads to a sharp increase in the failure of the package module end. Although the prior art proposes a way to improve the problem of metal Au particles, it has never been able to solve this problem from the root. Therefore, not using metal Au or using as little metal Au as possible can fundamentally solve this problem.

[0004] like Figure 1 As shown in FIG. 1 , when metal Au is used as an electrode, the metal Au particles will bulge upward, causing the electrode layer to be too thick and the insulating layer to crack. Figure 2 As shown in FIG. 1 , the cracked DBR reflective layer is located in the box. The crack will also cause a certain angle and cracks when depositing the second electrode layer (such as Figure 3 As shown), the film of the insulating layer will be broken, causing leakage, leading to failure of the LED chip and shortening its service life.

[0005] In view of this, the present invention is proposed. Summary of the invention

[0006] The first object of the present invention is to provide a light-emitting diode chip. The provided light-emitting diode chip reduces and limits the height of the first electrode, greatly reduces the height of the first electrode, and makes its thickness less than 1.2 μm. In addition, the first electrode layer and / or the second electrode layer do not use metal Au, thereby avoiding a series of problems caused by the breakage of the insulating layer caused by the existence of gold particles.

[0007] In order to achieve the above-mentioned purpose of the present invention, the following technical solutions are particularly adopted:

[0008] The present invention provides a light emitting diode chip, comprising: a substrate, an epitaxial structure unit sequentially arranged on the substrate, and an electrode structure unit connected to an electrode of the epitaxial structure unit.

[0009] The epitaxial structure unit at least comprises an N-type semiconductor layer, an active layer, and a P-type semiconductor layer; the electrode structure unit at least comprises a current spreading layer, a first electrode layer, a first insulating layer, a second electrode layer, a second insulating layer, and a pad layer which are arranged in sequence.

[0010] The thickness of the first electrode layer is less than 1.2 μm;

[0011] The first electrode layer and the second electrode layer do not contain metal Au.

[0012] Preferably, in the first electrode layer, the structure of the first electrode is a truncated cone structure, and the angle between the side wall and the bottom surface of the truncated cone structure is 10° to 35°.

[0013] Preferably, the thickness of the first electrode layer is

[0014] Preferably, the electrode structure of the first electrode layer and / or the second electrode layer comprises, from bottom to top, a first sublayer, a second sublayer, a third sublayer and a fourth sublayer;

[0015] Wherein, the first sublayer comprises at least one of Cr, Ti, Al or Ag; preferably Cr5 or Ti;

[0016] The second sublayer comprises Al and / or Ag;

[0017] The third sublayer includes at least one of TiPt, NiPt and TiNi;

[0018] The fourth sublayer includes Cr and / or Ti.

[0019] Preferably, the second electrode layer has a thickness of 1-3 μm.

[0020] Preferably, the pad layer includes one or a combination of several metal layers selected from the group consisting of Cr, Ni, Ti, Pt, Sn and Au.

[0021] Preferably, the pad layer includes a single-element layer or an alloy layer.

[0022] Preferably, the pad layer includes at least one metal Au top layer.

[0023] Preferably, the thickness of the metal Au top layer is less than or equal to

[0024] Preferably, the first insulating layer is provided with a first through hole at the first electrode, and the angle between a line connecting an upper edge and a lower edge of the first through hole and a top surface of the first electrode is 30° to 60°.

[0025] Preferably, on the contact surface between the first through hole and the first electrode, the diameter of the first through hole is D1, the diameter of the first electrode is D2, and D1 = (0.6-0.85) × D2.

[0026] Preferably, the pad layer includes a P-type pad and an N-type pad that are not electrically connected, the P-type pad and / or the N-type pad include a thinning area and a non-thinning area, the thickness of the thinning area is smaller than that of the non-thinning area, and the thinning area is used to thin the thickness of the pad layer in the area corresponding to the first electrode.

[0027] Preferably, the thinned area includes a plurality of independent circular areas, and the diameter of the circular area is greater than the diameter of the first electrode.

[0028] Preferably, a third electrode layer is further included between the second electrode layer and the pad layer.

[0029] Preferably, the third electrode layer is electrically connected or non-electrically connected to the pad layer.

[0030] Preferably, the third electrode layer is electrically connected or non-electrically connected to the second electrode layer.

[0031] Compared with the prior art, the present invention has the following beneficial effects:

[0032] (1) The light-emitting diode chip provided by the present invention reduces and limits the height of the first electrode, greatly reducing the height of the first electrode to a thickness of less than 1.2 μm, and the first electrode layer and / or the second electrode layer do not use metal Au, thereby avoiding a series of problems caused by the breakage of the insulating layer caused by the presence of gold particles in the prior art.

[0033] (2) The light-emitting diode chip provided by the present invention defines a specific structure of the first electrode layer and / or the second electrode layer without using a metal Au electrode, so that the chip also has excellent light-emitting performance.

[0034] (3) The light-emitting diode chip provided by the present invention optimizes the angle of the electrode side wall so as to achieve a better coating morphology of the first insulating layer.

[0035] (4) The light-emitting diode chip provided by the present invention reduces the height of the first electrode and improves the pad layer structure, making the entire chip flatter. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0037] Figure 1 It is a cross-sectional FIB image of a chip structure in the prior art;

[0038] Figure 2 A cross-sectional FIB image of another structure of a chip in the prior art;

[0039] Figure 3 A cross-sectional FIB image of another structure of a chip in the prior art;

[0040] Figure 4 A top view of a light emitting diode chip provided by an embodiment of the present invention;

[0041] Figure 5 A partial cross-sectional schematic diagram of a light emitting diode chip provided by an embodiment of the present invention;

[0042] Figure 6 A cross-sectional FIB image of an electrode structure provided by an embodiment of the present invention;

[0043] Figure 7 for Figure 6 A partial enlarged view of

[0044] Figure 8 is a schematic cross-sectional view of a first electrode and a first insulating layer;

[0045] Fig. 9 is a schematic structural diagram of a first electrode and a second electrode layer;

[0046] Fig.10 It is a plan view of the pad layer.

[0047] Reference numerals:

[0048] 100 - substrate; 210 - N-type semiconductor layer; 220 - active layer; 230 - P-type semiconductor layer;

[0049] 300-current blocking layer; 400-current spreading layer; 510-first electrode layer; 511-first P electrode; 512-first N electrode; 5101-first sublayer; 5102-second sublayer; 5103-third sublayer; 5104-fourth sublayer; 513-first through hole; 520-second electrode layer; 521-second P electrode; 522-second N electrode;

[0050] 600 - first insulating layer; 700 - second insulating layer; 800 - pad layer; 801 - thinning area; 802 - non-thinning area; 810 - P pad layer; 820 - N pad layer. DETAILED DESCRIPTION

[0051] The technical scheme of the present invention will be clearly and completely described below in conjunction with the accompanying drawings and specific embodiments, but it will be understood by those skilled in the art that the following described embodiments are part of embodiments of the present invention, rather than all embodiments, and are only used to illustrate the present invention, and should not be considered as limiting the scope of the present invention. Based on the embodiments in the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative work are within the scope of protection of the present invention. If specific conditions are not specified in the embodiments, they are carried out according to normal conditions or conditions recommended by the manufacturer. If the manufacturer is not specified in the reagents or instruments used, they are all conventional products that can be purchased commercially.

[0052] An embodiment of the present invention provides a light emitting diode chip, such as Figure 4 and Figure 5 As shown, it includes: a substrate 100, and an epitaxial structure unit sequentially arranged on the substrate 100 and an electrode structure unit connected to the electrode of the epitaxial structure unit, wherein the epitaxial structure unit at least includes an N-type semiconductor layer 210, an active layer 220, and a P-type semiconductor layer 230; the electrode structure unit at least includes a current spreading layer 400, a first electrode layer 510, a first insulating layer 600, a second electrode layer 520, a second insulating layer 700 and a pad layer 800 which are sequentially arranged.

[0053] It should be noted that the substrate 100 material includes at least one of Al2O3 (sapphire), GaAs, Si, SiC, GaN, GaP, InP, ZnO and Ge, and the sapphire transparent substrate is preferably used in the present invention; epitaxial structure units are sequentially formed on the substrate 100 by metal organic chemical vapor deposition, molecular beam epitaxy, or hydride vapor phase epitaxy, such as the N-type semiconductor layer 210, the active layer 220, and the P-type semiconductor layer 230 formed on the substrate 100 in sequence; wherein the active layer 220 is a single quantum well structure or a multi-quantum well structure, a quantum dot structure or a quantum wire structure; the N-type semiconductor layer 210 and the P-type semiconductor layer 230 are III-V group compound semiconductor materials, including at least Al x Ga y In (1-x-y) N or Al x Ga y In (1-x-y)P, wherein 0≤x≤1, 0≤y≤1, and 0≤x+y≤1, for example, the compound semiconductor may contain any one of GaN, AlN, AlGaN, GaInN, InN, AlGaInN, GaP, AlP, AlGaP, GaInP, InP, and AlGaInP.

[0054] After the epitaxial structure unit is formed, the electrode structure unit needs to be prepared on it. Before forming the electrode structure unit, the epitaxial structure unit needs to be etched with gold MESA and ISO, the epitaxial structure unit is independently divided according to the final chip size, and a MESA platform for depositing the N-type electrode structure is formed on each independently allocated epitaxial structure unit.

[0055] The electrode structure unit usually first prepares a current spreading layer 400, also known as a transparent conductive layer, whose materials include indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), aluminum zinc oxide (AZO), zinc tin oxide (ZTO), gallium zinc oxide (GZO), indium tungsten oxide (IWO), zinc oxide (ZnO) or indium zinc oxide (IZO).

[0056] Next, the first electrode layer 510 is prepared. The first electrode layer 510 includes a first P electrode 511 electrically connected to the P-type semiconductor layer, and a first N electrode 512 located on the MESA platform and electrically connected to the N-type semiconductor layer. For the uniformity of current distribution, the number of the first P electrode 511 and the first N electrode 512 is more than one, and they can be finger electrodes or dot electrodes. In the flip-chip DBR and / or ODR chip structure, the first N electrode 512 and the first P electrode 511 are relatively uniformly distributed on the epitaxial structure unit; usually, a current blocking layer 300 is also provided between the current expansion layer 400 and the P-type semiconductor layer 230 directly below the first P electrode 511. The shape of the current blocking layer 300 is similar to the shape of the first P electrode 511 to prevent the current from flowing along the shortest path. The material of the current blocking layer 300 is usually SiO2, with a thickness of 200nm to 500nm.

[0057] The first insulating layer 600 covers the first electrode layer 510 and is provided with a first through hole 513 exposing the first P electrode 511 and the first N electrode 512, and the second electrode layer 520 is electrically connected to the first electrode layer 510 through the through hole; specifically, the second electrode layer 520 includes a second P electrode 521 connected to the first P electrode 511 and a second N electrode 522 connected to the first N electrode 512, and the second N electrode 522 and the second P electrode 521 are insulated from each other; the second insulating layer 700 covers the second P electrode 521 and the second N electrode 522 and is provided with a second through hole exposing a portion of the second N electrode 522 and the second P electrode 521, and the pad layer 800 is electrically connected to the second electrode layer 520 through the second through hole. Similarly, the pad layer 800 includes an N pad layer 820 electrically connected to the second N electrode 522 and a P pad layer 810 electrically connected to the second P electrode 521.

[0058] The materials of the first insulating layer 600 and the second insulating layer 700 include SiO2, TiO2 and SiN x Preferably, the first insulating layer 600 is a DBR structure formed by SiO2 / TiO2, and the second insulating layer 700 is an insulating protection layer formed by SiO2.

[0059] The main purpose of the present invention is to reduce the total thickness of the electrode structure, reduce the use of precious metals, reduce production costs, and improve the reliability of the device. For example, the thickness of the first electrode is reduced, the thickness of the first electrode layer 510 is set to be less than 1.2μm, and the first electrode layer and the second electrode layer 520 are designed not to contain metal Au, so as to avoid the use of metal Au causing the thickness of the first electrode layer 510 to be too large, resulting in the insulation layer breaking at the corner of the electrode structure and chip failure. Here, not containing metal Au means not containing a single layer of metal Au, nor an alloy layer composed of metal Au and other metals.

[0060] In a preferred embodiment, the thickness of the first electrode layer 510 is For example Any value in or a range of values ​​consisting of any two point values. Figure 6 As shown, the thickness of the first electrode is reduced to It can be seen that the subsequent insulating layer and electrode layer are well coated without any breakage. Figure 7 As shown, it can be seen that the first electrode layer 510 is etched more smoothly after being thinned, and the second electrode layer 520 is well covered without any breakage, thereby ensuring the chip reliability.

[0061] In a preferred embodiment, in the first electrode layer 510, the structure of the first electrode is a truncated cone structure, and the angle between the side wall and the bottom surface of the truncated cone structure is 10° to 35°. Figure 8Taking the cross-sectional view of the first electrode through the center of the bottom surface of the truncated cone as an example, that is, θ1=10°~35°, including any point value among 10°, 15°, 20°, 25°, 30°, and 35° or a range value composed of any two point values.

[0062] In a preferred embodiment, without using metal Au as a wrapping layer, in order to optimize the light-emitting effect, the electrode structure of the first electrode layer 510 and / or the second electrode layer 520 includes, from bottom to top, a first sublayer 5101, a second sublayer 5102, a third sublayer 5103 and a fourth sublayer 5104, such as Fig. 9 As shown, the direction from bottom to top refers to extending from the substrate 100 to the electrode. Unless otherwise specified, "upward" in this application refers to extending from the substrate 100 to the electrode, and "downward" refers to extending from the electrode to the substrate 100.

[0063] Wherein, the first sublayer 5101 is an ohmic contact layer, including at least one of Cr, Ti, Al or Ag; more preferably Cr or Ti;

[0064] The second sub-layer 5102 is a reflective layer, including Al and / or Ag;

[0065] The third sublayer 5103 is a wrapping layer, including at least one of Ti / Pt, Ni / Pt and Ti / Ni;

[0066] The fourth sublayer 5104 is an adhesion layer, and includes Cr and / or Ti.

[0067] In a preferred embodiment, the thickness of the second electrode layer 520 is 1-3 μm, including but not limited to any point value among 1 μm, 2 μm and 3 μm, or a range consisting of any two point values.

[0068] The second electrode layer 520 includes an ohmic contact layer, a reflective layer, a wrapping layer, and an adhesion layer.

[0069] The ohmic contact layer includes at least one of Cr, Ti, Al or Ag; more preferably Cr or Ti; the reflective layer includes Al and / or Ag; the wrapping layer includes at least one of Ti / Al, Ti / Pt, Ni / Pt and Ti / Ni stacked structures; the thickness of the wrapping layer is 80% to 95% of the thickness of the second electrode layer 520, and the thicker wrapping layer has a stronger anti-puncture ability; the adhesion layer includes Cr and / or Ti.

[0070] In a preferred embodiment, the pad layer 800 includes a combination of one or more metal layers selected from Cr, Ni, Ti, Pt, Sn and Au, wherein the metal layer includes a single layer or an alloy layer; preferably, it includes at least one metal Au top layer.

[0071] In a preferred embodiment, the thickness of the metal Au top layer is less than or equal to

[0072] In a preferred embodiment, the first insulating layer 600 is provided with a first through hole 513 at the first electrode, and the angle between the line connecting the upper edge and the lower edge of the first through hole 513 and the top surface of the first electrode is as follows: Figure 8 θ2 = 30°~60°, for example, any point value among 30°, 35°, 40°, 45°, 50°, 55°, 60° or a range value consisting of any two point values.

[0073] In a preferred embodiment, on the contact surface between the first through hole 513 and the first electrode, the diameter of the first through hole 513 is D1, the diameter of the first electrode is D2, D1=(0.6~0.85)×D2, for example, D1=0.6D2, D1=0.7D2, D1=0.75D2, D1=0.8D2, D1=0.85D2.

[0074] After the thickness of the first electrode layer 510 is reduced, its bottom inclination angle θ1 decreases and the top surface area increases, the first through hole etching window provided becomes larger and the etching angle θ2 becomes smaller, that is, the surface height difference of the first insulating layer 600 becomes smaller and the surface is smoother, which provides a good platform for the subsequent deposition of the second electrode layer 520 and reduces the risk of the second electrode layer 520 breaking at the corners.

[0075] In a preferred embodiment, the pad layer 800 includes a P-type pad and an N-type pad electrically connected to the P-type semiconductor layer and the N-type semiconductor layer, the P-type pad and / or the N-type pad includes a thinning area 801 and a non-thinning area 802, the thickness of the thinning area 801 is smaller than that of the non-thinning area 802, and the thinning area 801 is used to thin the thickness of the pad layer 800 in the area corresponding to the first electrode in the first electrode layer, that is, the thinning area 801 is arranged above the first electrode.

[0076] In a preferred embodiment, the thinned area 801 includes a plurality of independent circular areas, and the diameter of the circular area is greater than the diameter of the first electrode.

[0077] In a preferred embodiment, the circular area can be a through hole, such as Fig.10 A schematic diagram of the surface structure of a preferred pad layer 800 is shown, in which a through hole is provided at a position corresponding to the first electrode, and the shape of the through hole is not limited, and can be circular or in other shapes.

[0078] The embodiment of the present application takes two layers of electrodes and a pad layer 800 as an example, but adding other functional electrode layers in between is also within the protection scope of the present application.

[0079] For example, a third electrode is further included between the second electrode layer 520 and the pad layer 800;

[0080] In a preferred embodiment, the third electrode layer is electrically connected or non-electrically connected to the pad layer 800;

[0081] In a preferred embodiment, the third electrode layer is electrically connected or non-electrically connected to the second electrode layer 520 .

[0082] In a preferred embodiment, the method for preparing the light emitting diode chip may adopt the following steps, but is not limited thereto, and may also be other methods that can realize the preparation of the chip, including:

[0083] S1, providing a substrate 100, and sequentially manufacturing an N-type semiconductor layer 210, a light-emitting layer and a P-type semiconductor layer 230 on the substrate;

[0084] S2, depositing SiO2 on the epitaxial wafer, preparing a CBL current blocking layer 300 by yellow light and etching, depositing an ITO film by magnetron sputtering or evaporation, first etching the ITO and then etching to form a step, and then deep etching to form an isolation groove;

[0085] S3, depositing the first electrode layer 510, then depositing the first insulating layer 600, etching the first through hole 513, depositing the second electrode layer 520, then depositing the second insulating layer 700, and then depositing the pad layer 800 to obtain the light emitting diode chip.

[0086] Although the present invention has been illustrated and described with specific embodiments, it should be appreciated that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit it. Those skilled in the art should understand that the technical solutions described in the above embodiments may be modified, or some or all of the technical features thereof may be replaced by equivalents without departing from the spirit and scope of the present invention. However, these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention. Therefore, this means that all such replacements and modifications within the scope of the present invention are included in the appended claims.

Claims

1. A light emitting diode chip, comprising: A substrate, and an epitaxial structure unit sequentially arranged on the substrate and an electrode structure unit connected to the electrode of the epitaxial structure unit, wherein the epitaxial structure unit at least includes an N-type semiconductor layer, an active layer, and a P-type semiconductor layer; the electrode structure unit at least includes a current spreading layer, a first electrode layer, a first insulating layer, a second electrode layer, a second insulating layer, and a pad layer sequentially arranged, characterized in that: The thickness of the first electrode layer is less than 1.2 μm; The first electrode layer and the second electrode layer do not contain metal Au; The pad layer includes a P-type pad and an N-type pad that are not electrically connected, the P-type pad and / or the N-type pad includes a thinning area and a non-thinning area, the thickness of the thinning area is smaller than that of the non-thinning area, and the thinning area is used to thin the thickness of the pad layer in the area corresponding to the first electrode; The first insulating layer is provided with a first through hole at the first electrode, and the angle between the line connecting the upper edge and the lower edge of the first through hole and the top surface of the first electrode is 30° to 60°; On the contact surface between the first through hole and the first electrode, the diameter of the first through hole is D1, the diameter of the first electrode is D2, and D1=(0.6-0.85)×D2; The second electrode layer includes an ohmic contact layer, a reflective layer, a wrapping layer and an adhesion layer. The ratio of the thickness of the wrapping layer in the second electrode layer to the thickness of the second electrode layer is 80% to 95%.

2. The light emitting diode chip according to claim 1, characterized in that: In the first electrode layer, the structure of the first electrode is a truncated cone structure, and the angle between the side wall and the bottom surface of the truncated cone structure is 10° to 35°; And / or, the thickness of the first electrode layer is 4KÅ~9KÅ.

3. The light emitting diode chip according to claim 1, characterized in that: The electrode structure of the first electrode layer includes, from bottom to top, a first sublayer, a second sublayer, a third sublayer and a fourth sublayer; Wherein, the first sublayer includes at least one of Cr, Ti, Al or Ag; The second sublayer comprises Al and / or Ag; The third sublayer includes at least one of TiPt, NiPt and TiNi; The fourth sublayer includes Cr and / or Ti.

4. The light emitting diode chip according to claim 3, characterized in that: The first sublayer is Cr or Ti.

5. The light emitting diode chip according to claim 1, characterized in that: The thickness of the second electrode layer is 1-3 μm.

6. The light emitting diode chip according to claim 1, characterized in that: The pad layer includes one or a combination of several metal layers selected from Cr, Ni, Ti, Pt, Sn and Au.

7. The light emitting diode chip according to claim 6, characterized in that: The pad layer includes a single-substance layer or an alloy layer; And / or, the pad layer includes at least one metal Au top layer.

8. The light emitting diode chip according to claim 7, characterized in that: The thickness of the metal Au top layer is less than or equal to 2KÅ.

9. The light emitting diode chip according to claim 1, characterized in that: The thinning area includes a plurality of independent circular areas, and the diameter of the circular area is greater than the diameter of the first electrode.

10. The light emitting diode chip according to any one of claims 1 to 9, characterized in that: A third electrode layer is further included between the second electrode layer and the pad layer.

11. The light emitting diode chip according to claim 10, characterized in that: The third electrode layer is electrically connected or non-electrically connected to the pad layer.

12. The light emitting diode chip according to claim 10, characterized in that: The third electrode layer is electrically connected or non-electrically connected to the second electrode layer.

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