SiC mosfet gate drive circuit with desaturation protection function

Abstract

The application relates to a SiC MOSFET gate drive circuit with a desaturation protection function, comprising an input receiving circuit, a first modulation sending circuit, a high-voltage isolation circuit, a first receiving amplification circuit, a first OOK demodulation circuit, an output buffer circuit, a second OOK demodulation circuit, a second receiving amplification circuit, a second modulation sending circuit, a high-precision desaturation protection circuit, a first OSC oscillator and a second OSC oscillator. The high-precision receiving amplification circuit adopted by the application adopts a multi-stage cascade structure to improve small-signal amplification capacity, and can adjust the common-mode voltage size, thereby improving the identification precision of a received signal and a common-mode working range; the OOK demodulation circuit adopts a multi-stage comparator structure to improve the OOK signal demodulation precision; the voltage variation slope of a SiC MOSFET V DS is detected to judge whether the state of the V DS voltage is in a safe interval, all abnormal changes of the V DS voltage can be dynamically monitored, the desaturation protection precision is improved, and finally the precision and reliability of the gate drive chip are greatly improved.

Description

Technical Field

[0001] This invention relates to a gate drive circuit for a SiC MOSFET device with a high-precision short-circuit protection module, belonging to the field of high-voltage drive chip technology. Background Technology

[0002] Compared to traditional silicon devices, silicon carbide (SiC) devices have emerged as viable candidates for next-generation low-loss semiconductors due to their low on-resistance and excellent high-temperature, high-frequency, and high-voltage performance. Furthermore, SiC allows designers to reduce the number of components, further simplifying designs. The low on-resistance of SiC devices helps significantly reduce device power consumption, thus facilitating the design of environmentally friendly products and systems that reduce CO2 emissions. SiC-based semiconductor devices can be applied in various industrial sectors, including automotive, charging equipment, portable power supplies, communication equipment, robotic arms, and aircraft, and their applications are continuously expanding and deepening.

[0003] Among the many device types implemented with SiC, SiC MOSFETs have become the most widely used representative devices. Currently, Si-based IGBTs are mainly used for voltages above 600V. IGBTs inject holes, which act as minority carriers, into the drift layer through conductivity modulation, generating tail currents during turn-off, resulting in significant switching losses. SiC devices have lower drift layer impedance than Si devices, eliminating the need for conductivity modulation to achieve high voltage withstand and low impedance using a high-frequency MOSFET structure. Therefore, the most significant advantage of SiC MOSFETs is that they do not theoretically generate the tail currents commonly seen in IGBTs. Even at voltage withstand values ​​above 1200V, SiC can employ fast MOSFET structures, reducing turn-off losses by approximately 90%, which is beneficial for energy saving and simplification and miniaturization of heat dissipation equipment. Furthermore, while the tail current of IGBTs increases with temperature, SiC MOSFETs are almost unaffected by temperature. Furthermore, the significant switching losses and resulting heat generation can cause the junction temperature (Tj) to exceed the rated value, so IGBTs are generally not suitable for use in high-frequency regions above 20kHz. However, SiC MOSFETs, due to their very small Eoff, can perform high-frequency switching. Therefore, replacing IGBTs with SiC MOSFETs can significantly reduce switching losses and achieve miniaturization of heat dissipation components. Compared to 600V–1200V Si MOSFETs, SiC MOSFETs have the advantages of smaller chip area (allowing for smaller packages) and very low body diode recovery losses. The dielectric breakdown field strength of SiC is 10 times that of Si, enabling high breakdown voltages with low impedance and thin drift layers. Therefore, for the same breakdown voltage, SiC can produce devices with lower standardized on-resistance (on-resistance per unit area).

[0004] The high-frequency characteristics of SiC MOSFETs present numerous challenges to the design of their gate drive circuits. Firstly, there are the requirements for higher switching speeds and lower delays; secondly, there is the need to overcome various non-ideal characteristics under high-frequency operating conditions. During the operation of a SiC MOSFET device, as V... DS As the voltage increases, the voltage difference between the gate and the silicon surface becomes too small to maintain the strong inversion at the silicon surface, resulting in channel pinch-off. The current then no longer follows the voltage. DS As voltage increases proportionally, SiC MOSFETs enter a desaturation state. Compared to silicon-based IGBTs, SiC MOSFETs have relatively poor short-circuit current withstand capability, making them more susceptible to thermal damage. Therefore, desaturation protection design for SiC MOSFETs becomes particularly important. Summary of the Invention

[0005] Based on existing technology, this invention provides a SiC MOSFET gate drive circuit with high-precision Desat detection and protection functions, thereby improving the service life and reliability of SiC MOSFETs.

[0006] The SiC MOSFET gate drive circuit with desaturation protection function provided by the present invention includes the following circuit structure: an input receiving circuit, a first modulation transmitting circuit, a first high-voltage isolation circuit, a first receiving amplification circuit, a first OOK demodulation circuit, an output buffer circuit, a second OOK demodulation circuit, a second receiving amplification circuit, a second high-voltage isolation circuit, a second modulation transmitting circuit, a high-precision desaturation protection circuit, a first OSC oscillator, and a second OSC oscillator.

[0007] The input receiving circuit, the first modulation transmitting circuit, the output buffer circuit, the second OOK demodulation circuit, the second receiving amplification circuit, and the first OSC oscillator constitute the transmitting end circuit of the driving circuit; the first receiving amplification circuit, the first OOK demodulation circuit, the high-precision desaturation protection circuit, the second modulation transmitting circuit, and the second OSC oscillator constitute the receiving end circuit of the driving circuit; the ground potential of all circuits inside the transmitting end circuit is connected to the transmitting end ground voltage Vgnd1, and the ground potential of all circuits inside the receiving end circuit is connected to the receiving end ground voltage Vgnd2; the first OSC oscillator is used to generate the clock CKd, and the second OSC oscillator is used to generate the clock CKp.

[0008] A high-voltage isolation circuit is used to isolate the transmitting circuit and the receiving circuit; the first high-voltage isolation circuit includes a positive transmitting capacitor Ctp and a positive receiving capacitor Crp connected in series, and a negative transmitting capacitor Ctn and a negative receiving capacitor Crn connected in series; the second high-voltage isolation circuit includes a positive transmitting capacitor Ctpp and a positive receiving capacitor Crpp connected in series, and a negative transmitting capacitor Ctnp and a negative receiving capacitor Crnp connected in series.

[0009] The input receiving circuit is connected to an external low-level logic input data IN, converted into input data Din, and connected to the first modulation transmitting circuit. The first modulation transmitting circuit modulates the input data Din with the clock CKd to obtain the differential transmission data TxP and TxN of the data channel. The differential transmission data TxP and TxN of the data channel are respectively connected to the left end of the positive transmitting capacitor Ctp and the left end of the negative transmitting capacitor Ctn. The right end of the positive transmitting capacitor Ctp and the right end of the negative transmitting capacitor Ctn are respectively connected to the left end of the positive receiving capacitor Crup and the left end of the negative receiving capacitor Crn. The right and negative terminals of capacitor Crup receive differential data RxP and RxN from the right terminal of capacitor Crn, which are connected to the first receiving amplifier circuit. The first receiving amplifier circuit processes the differential data RxP and RxN to obtain four differential transmission data signals Vo1p, Vo1n, Vo2p, and Vo2n, which are connected to the first OOK demodulation circuit. After demodulation, the received output data Dout is generated. The received output data Dout is finally output to the high-precision desaturation protection circuit. The high-precision desaturation protection circuit is also connected to the desaturation detection port Desat and the drain of the SiC MOSFET. The high-precision desaturation protection circuit generates an output drive signal GO with a large drive current and an error signal Flt_out based on the received output data Dout and Desat signal.

[0010] The error signal Flt_out is connected to the input data terminal of the second modulation and transmission circuit. The second modulation and transmission circuit modulates the clock CKp with the state of the error signal Flt_out to obtain the protection channel differential transmission data TxPp and TxNp. The protection channel differential transmission data TxPp and TxNp are respectively connected to the right end of the positive transmitting capacitor Ctpp and the right end of the negative transmitting capacitor Ctnp. The left end of the positive transmitting capacitor Ctpp and the left end of the negative transmitting capacitor Ctnp are respectively connected to the right end of the positive receiving capacitor Crpp and the right end of the negative receiving capacitor Cr. The left end of the positive terminal receiving capacitor Crpp and the left end of the negative terminal receiving capacitor Crnp generate the protection channel differential received data RxPp and RxNp. The protection channel differential received data RxPp and RxNp are connected to the second receiving amplifier circuit, generating four protection data differential signals Vo1pp, Vo1np, Vo2pp and Vo2np, which are connected to the second OOK demodulation circuit. After demodulation, the error buffer output signal Flt_buf is generated and connected to the output buffer circuit. After processing by the output buffer circuit, the final output error signal FLT is obtained.

[0011] Specifically, the first receiving amplifier circuit includes a 3-stage cascaded common-mode adjustable differential amplifier circuit;

[0012] The first-stage common-mode adjustable differential amplifier circuit includes: a PMOS transistor M21 and an NMOS transistor M23 connected in series through their drains; a PMOS transistor M22 and an NMOS transistor M24 connected in series through their drains; a capacitor C21 is connected between the gate and source of PMOS transistor M21; a bias resistor R21 is connected between the gate and drain of PMOS transistor M21; the drain of NMOS transistor M23 outputs the first-stage negative terminal output signal Vo11; the gate of NMOS transistor M23 is connected to the positive input terminal RxP of the receiving amplifier circuit; a capacitor C22 is connected between the gate and source of PMOS transistor M22; a bias resistor R22 is connected between the gate and drain of PMOS transistor M22; NMOS transistor M24... The drain of S-MOSFET M24 outputs the first-stage positive terminal signal Vo12. The gate of NMOS transistor M24 is connected to the negative input terminal RxN of the receiver amplifier circuit. The sources of PMOS transistors M21 and M22 are connected together and connected to the power supply VDD. The sources of NMOS transistors M23 and M24 are connected together and connected to the drains of NMOS transistors M25, M26, and M27. The gate of NMOS transistor M25 is connected to the bias voltage Vb1, providing the bias current required for the amplifier to operate normally. The gates of NMOS transistors M26 and M27 are connected to the common-mode adjustment signals C11 and C12, respectively.

[0013] The second-stage common-mode adjustable differential amplifier circuit includes: a PMOS transistor M31 and an NMOS transistor M33 connected in series through their drains; a PMOS transistor M32 and an NMOS transistor M34 connected in series through their drains; a capacitor C31 is connected between the gate and source of PMOS transistor M31; a bias resistor R31 is connected between the gate and drain of PMOS transistor M31; the drain of NMOS transistor M33 outputs the second-stage negative terminal output signal Vo21, and the gate of NMOS transistor M33 is connected to the first-stage positive terminal output signal Vo12; a capacitor C32 is connected between the gate and source of PMOS transistor M32; a bias resistor R32 is connected between the gate and drain of PMOS transistor M32; NMOS transistor M34... The drain of S-MOSFET M34 outputs the second-stage negative terminal signal Vo22, and the gate of NMOS transistor M34 is connected to the first-stage negative terminal output signal Vo11. The sources of PMOS transistors M31 and M32 are connected and connected to the power supply VDD. The sources of NMOS transistors M33 and M34 are connected and connected to ground. The drains of NMOS transistors M35, M36, and M37 are connected. The gate of NMOS transistor M35 is connected to the bias voltage Vb1, providing the bias current required for the amplifier to operate normally. The gates of NMOS transistors M36 and M37 are connected to the common-mode adjustment signals C11 and C12, respectively.

[0014] The third-stage common-mode adjustable differential amplifier circuit includes: a PMOS transistor M41 and an NMOS transistor M43 connected in series through their drains, and a PMOS transistor M42 and an NMOS transistor M44 connected in series through their drains; a capacitor C41 is connected between the gate and source of PMOS transistor M41, and the gate of PMOS transistor M41 is also connected to the upper end of resistor R41. The lower end of resistor R41 is connected to the upper end of resistor R42, serving as the first signal output terminal Vo1p of the receiving amplifier circuit; the lower end of resistor R42 is connected to the drain of PMOS transistor M41, serving as the third signal output terminal Vo2p of the receiving amplifier circuit; the gate of NMOS transistor M43 is connected to the positive terminal of the second stage output signal Vo22; a capacitor C42 is connected between the gate and source of PMOS transistor M42, and the gate of PMOS transistor M42 is also connected to the upper end of resistor R43, and resistor R44... The lower end of resistor 3 is connected to the upper end of resistor R44, serving as the second signal output terminal Vo1n of the receiving amplifier circuit; the lower end of resistor R44 is connected to the drain of PMOS transistor M42, serving as the fourth signal output terminal Vo2n of the receiving amplifier circuit; the gate of NMOS transistor M44 is connected to the negative terminal of the second stage to output signal Vo21; the source of PMOS transistor M41 is connected to the source of PMOS transistor M42 and connected to the power supply VDD; the source of NMOS transistor M43 is connected to the source of NMOS transistor M44 and connected to the drains of NMOS transistors M45, M46, and M47; the gate of NMOS transistor M45 is connected to the bias voltage Vb1, providing the bias current required for the amplifier to operate normally; the gates of NMOS transistors M46 and M47 are connected to the common-mode adjustment signals C11 and C12, respectively.

[0015] By changing the magnitudes of the common-mode adjustment signals C11 and C12, the bias current flowing through NMOS transistors M23 and M24 will change, and the output voltages of both the negative and positive output signals of the three-stage cascaded common-mode adjustable differential amplifier circuit will change simultaneously, thereby achieving adjustment of the output common-mode voltage; the second receiving amplifier circuit has the same circuit structure as the first receiving amplifier circuit.

[0016] Specifically, the first and second OOK demodulation circuits have the same structure, both being two-stage fully differential comparator amplifier circuits. The first-stage circuit includes a differential amplifier circuit composed of PMOS transistors M88, M89, M812, M813, M810, M811, M814, M815, and resistor R85. The second-stage comparator amplifier circuit is a three-stage comparator composed of PMOS transistors M801, M802, M803, M804, M805, M806, M809, M807, M808, M8010, resistor R801, and resistor R802.

[0017] The differential amplifier circuit internally includes: PMOS transistor M88 with its gate serving as the first signal input terminal; PMOS transistor M89 with its gate serving as the second signal input terminal; PMOS transistor M812 with its gate serving as the third signal input terminal; and PMOS transistor M813 with its gate serving as the fourth signal input terminal. The sources of PMOS transistors M88, M89, M812, and M813 are all connected to the power supply VDD. The drains of PMOS transistors M88 and M89 are connected and then connected to the source of NMOS transistor M810, serving as the positive output terminal V402 of the differential amplifier circuit. The drains of PMOS transistors M812 and M813 are connected... The source of NMOS transistor M814 is connected to the source of NMOS transistor M814 via resistor R85. The drain of NMOS transistor M814 serves as the negative output terminal V403 of the differential amplifier circuit. The drain of NMOS transistor M810 is connected to the drain of NMOS transistor M811, and the drain of NMOS transistor M814 is connected to the drain of NMOS transistor M815. The sources of NMOS transistors M811 and M815 share a common ground potential. NMOS transistors M810 and M811 form a common-source common-gate current source structure, as do NMOS transistors M814 and M815. The gates of NMOS transistors M810 and M814 are connected to the same bias voltage Vb81, and the gates of NMOS transistors M811 and M815 are connected to the same bias voltage Vb82.

[0018] The three-stage comparator internally includes: the sources of PMOS transistors M801, M804, and M809 are all connected to the power supply VDD; the gates of PMOS transistors M801, M804, and M809 are connected to the same bias voltage Vb81; the drain of PMOS transistor M801 is connected to the sources of PMOS transistors M802 and M803; the gate of PMOS transistor M802 is connected to the positive output terminal V402 of the differential amplifier circuit; the gate of PMOS transistor M803 is connected to the negative output terminal V403 of the differential amplifier circuit; the drain of PMOS transistor M802 is connected to the upper end of PMOS transistor M801 and the gate of PMOS transistor M805; and the drain of PMOS transistor M803... Connect the upper end of resistor R802 to the gate of PMOS transistor M806; the lower ends of resistor R801 and R802 share a common ground potential; the drain of PMOS transistor M804 is connected to the source of PMOS transistor M805 and the source of PMOS transistor M806; the drain of PMOS transistor M805 is connected to the drain of NMOS transistor M807, the gate of NMOS transistor M807, and the gate of NMOS transistor M808; the drain of PMOS transistor M806 is connected to the drain of NMOS transistor M808 and the gate of NMOS transistor M8010; the sources of NMOS transistors M807, M808, and M8010 share a common ground potential; the drain of PMOS transistor M809 is connected to the drain of NMOS transistor M8010, serving as the output of a three-stage comparator;

[0019] The input stage of the three-stage comparator consists of PMOS transistors M801, M802, and M803, resistors R801 and R802, PMOS transistors M804, M805, and M806, NMOS transistors M807 and M808, and PMOS transistors M809 and M8010.

[0020] Specifically, the high-precision desaturation protection circuit includes: an external interface circuit, a clock generation circuit, a voltage follower detection circuit, a comprehensive control logic circuit, a voltage detection circuit, an output drive circuit, a detection resistor Rd1, a detection resistor Rd2, and a detection capacitor Cd1;

[0021] The upper end of the sensing resistor Rd2 is connected to the desaturation detection port Desat and the drain of the SiC MOSFET, while the lower ends of the sensing resistor Rd1 and the sensing capacitor Cd1 are connected to the ground potential port. The connection point between the lower end of the sensing resistor Rd2 and the upper ends of the sensing resistor Rd1 and the sensing capacitor Cd1 generates a desaturation input signal Vdes, which is connected to the detection voltage input terminal of the voltage detection circuit. The voltage detection circuit detects the desaturation input signal Vdes generated by the voltage divider and filter of the Desat signal through the sensing resistors Rd1, Rd2, and Cd1, and outputs a desaturation sampling signal Vdesin under the control of the desaturation control clock Ckdes, which is connected to the voltage follower detection circuit. The voltage follower detection circuit, under the control of the sampling control clock Ckcs, the follower control clock Ckcom, and the desaturation control clock Ckdes, outputs a desaturation quantization signal Ddes based on the desaturation sampling signal Vdesin, which is connected to the integrated control logic circuit. The clock generation circuit generates the reference clock OSC and the sampling control clock Ckcs. The external interface circuit receives the signal Dout, converts it into an input drive signal Din2, and outputs it to the integrated control logic circuit. It also buffers the error signal Error from the integrated control logic circuit and outputs the error signal Flt_out. The integrated control logic circuit generates a power switch drive signal Dout2, an error signal Error, a control signal Ctrl, and a control signal Ctrl1 based on the states of the input drive signal Din2, the reference clock OSC, and the desaturation quantization signal Ddes. The power switch drive signal Dout2 is connected to the output drive circuit, the control signal Ctrl is connected to both the external interface circuit and the output drive circuit, the control signal Ctrl1 is connected to both the voltage follower detection circuit and the voltage detection circuit, and the error signal Error is connected to the external interface circuit. The output drive circuit generates the gate drive signal GO for the SiC MOSFET based on the power switch drive signal Dout2.

[0022] When the high-precision desaturation protection circuit starts working normally, the clock generation circuit first generates a default initial reference clock OSC, sampling control clock Ckcs, follower control clock Ckcom, and desaturation control clock Ckdes. Then, the integrated control logic circuit first outputs a control signal Ctrl to enable the external interface circuit and the output drive circuit. The external interface circuit starts receiving the signal Dout and converts it into the input drive signal Din2. Next, the integrated control logic circuit generates a power switch drive signal Dout2 based on the state of the input drive signal Din2, the reference clock OSC, and the desaturation quantization signal Ddes. The output drive circuit generates a gate drive signal GO based on the power switch drive signal Dout2. Finally, the integrated control logic circuit outputs a control signal Ctrl1 to enable the voltage follower detection circuit and the voltage detection circuit. The voltage detection circuit starts detecting the desaturation input signal Vdes and outputs a desaturation sampling signal Vdesin under the control of the desaturation control clock Ckdes. The voltage follower detection circuit generates a desaturation quantization signal Ddes based on the desaturation sampling signal Vdesin. The integrated control logic circuit determines the voltage signal Desat and SiC based on the state of the quantization signal Ddes. The MOSFET state is monitored, and in case of an abnormality, the state of the control signal Ctrl is changed, and an error signal Error is output to the external interface circuit. Finally, the external interface circuit outputs an error signal Flt_out to the second modulation and transmission circuit.

[0023] Specifically, the voltage detection circuit includes a sampling switch and a voltage integrator. The sampling switch samples the desaturation input signal Vdes under the control of the desaturation control clock Ckdes and outputs a sample-and-hold signal to the voltage integrator. The voltage integrator integrates the sample-and-hold signal based on the reference voltage Vref to obtain the desaturation sampling signal Vdesin.

[0024] Specifically, the voltage follower detection circuit includes: a high-performance sampling switch, a hold circuit, and a high-precision comparator; the desaturated sampling signal Vdesin is connected to the analog signal input terminal of the high-performance sampling switch, and the clock control terminal of the high-performance sampling switch is connected to the sampling control clock Ckcs; the first analog signal output terminal of the high-performance sampling switch is connected to the positive input terminal of the high-precision comparator, and the connection is controlled by the follower control clock Ckcom; the second analog signal output terminal of the high-performance sampling switch is connected to the signal input terminal of the hold circuit, and the connection is controlled by the desaturation control clock Ckdes; the analog signal output terminal of the hold circuit is connected to the negative input terminal of the high-precision comparator, and the connection is controlled by the follower control clock Ckcom; the data at the quantization output terminal of the high-precision comparator is the desaturated quantization signal Ddes, which is output to the integrated control logic circuit;

[0025] The voltage follower detection circuit operates as follows: In phase Ckcs, the high-performance sampling switch samples the desaturated sampling signal Vdesin. Assuming this is the Mth sampling iteration, the switch samples the voltage V. des (M); Ckcom phase, voltage V obtained from high-performance sampling switch des (M) and the voltage V held by the holding circuit in the previous clock cycle. des (M-1) enters the high-precision comparator, which compares the voltage V... des (M) and V des (M-1) is compared, and the output quantized data Ddes(M) is generated. Ddes(M) represents the desaturated quantized signal Ddes generated at the Mth sampling. A Ddes(M) value of 1 indicates that the Vdesin voltage is increasing, and a Ddes(M) value of 0 indicates the opposite; Ckdes phase, V des (M) enters the holding circuit for holding; where M is a natural number greater than 1, and the sampling control clock Ckcs, the follow control clock Ckcom and the desaturation control clock Ckdes are 3-phase non-overlapping clocks.

[0026] Specifically, the integrated control logic circuit includes: a counter, a control logic circuit, a reference data output circuit, an input serial register, a serial-to-parallel conversion circuit, a first buffer, a second buffer, a parallel register group, and error decision processing logic;

[0027] The counter generates a working control clock Ck_ctrl based on an external input reference clock OSC. The working control clock Ck_ctrl is simultaneously connected to the control clock inputs of the control logic circuit, the input serial register, the serial-to-parallel conversion circuit, the parallel register group, and the error decision handling logic. The control logic circuit generates control signals Ctrl and Ctrl1 based on the working control clock Ck_ctrl and the potential error signal Error_lat. Control signal Ctrl is connected to the control signal input of the first buffer, and control signal Ctrl1 is connected to the reference data output circuit, the input serial register, the serial-to-parallel conversion circuit, and the error decision handling logic. The first buffer, under the control of the control signal Ctrl, buffers the input drive signal Din2 and then outputs the power switch drive signal Dout2; the reference data output circuit, under the control of the control signal Ctrl1, outputs N-bit reference data Dref(N), which is connected to the error decision processing logic, where N is a natural number greater than 1; the input serial register, under the control of the working control clock Ck_ctrl and the control signal Ctrl1, receives the desaturation quantization signal Ddes in chronological order and outputs it to the serial / parallel conversion circuit in a first-in-first-out order; the serial / parallel conversion circuit... Under the control of the operating control clock Ck_ctrl and the control signal Ctrl1, the serially input desaturated quantization signal Ddes is converted into an N-bit desaturated status code Ds(N) output in parallel, and connected to the parallel register group. Under the control of the operating control clock Ck_ctrl, the parallel register group converts the N-bit desaturated status codes Ds(N) output in chronological order into K sets of parallel output N-bit desaturated status codes Ds(N)1~Ds(N)K, and connects them to the error decision handling logic; K is a natural number greater than 2. The error decision handling logic, under the control of the operating control clock Ck_ctrl and the control signal Ctrl1, processes the K sets of parallel output... The N-bit desaturation state codes Ds(N)1~Ds(N)K and the N-bit reference data Dref(N) are comprehensively processed to obtain the pre-output error signal Error_pre and the potential error signal Error_lat. The pre-output error signal Error_pre is connected to the second buffer, and the potential error signal Error_lat is connected to the control logic circuit. Under the control of the control signal Ctrl1, the second buffer buffers and drives the pre-output error signal Error_pre to output the error signal Error. The potential error signal Error_lat is output to the control logic circuit, and finally adjusts the state of the control signal Ctrl.

[0028] After the chip powers on, the counter starts working first. Once the counter is working normally, it outputs a working control clock Ck_ctrl based on the OSC signal, which is simultaneously input to the control logic circuit, input serial register, serial / parallel conversion circuit, parallel register group, and error decision handling logic. Next, the control logic circuit generates a control signal Ctrl based on the working control clock Ck_ctrl and enables the first buffer. The first buffer generates a power switch drive signal Dout2 based on the input drive signal Din2. After a certain delay, the control logic circuit generates a control signal Ctrl1 and enables the reference data output circuit, input serial register, serial / parallel conversion circuit, error decision handling logic, and the second buffer. Then, the reference data output circuit generates N-bit reference data Dref(N), and the input serial register receives the desaturated quantization signal Ddes sequentially according to the time sequence and outputs it to the serial / parallel converter in a first-in-first-out order. The serial-to-parallel conversion circuit converts the serially input desaturated quantization signal Ddes into an N-bit desaturated status code Ds(N) output in parallel. The parallel register group converts the N-bit desaturated status codes Ds(N) output in chronological order into K sets of parallel output N-bit desaturated status codes Ds(N)1~Ds(N)K. The error decision processing logic performs comprehensive decision processing on the K sets of parallel output N-bit desaturated status codes Ds(N)1~Ds(N)K and N-bit reference data Dref(N) to obtain the pre-output error signal Error_pre and the potential error signal Error_lat. The control logic circuit adjusts the state of the control signal Ctrl in real time according to the state of the potential error signal Error_lat, thereby controlling the operation of the external interface circuit and changing the characteristics of the input drive signal Din2, and finally changing the characteristics of the power switch drive signal Dout2 and the gate drive signal GO.

[0029] Specifically, the error decision handling logic includes: a coarse data weighting circuit, a fine data weighting circuit, K data weighting circuits, K summation data selection switches, K-1 subtractors, K-1 difference data selection switches, a first digital comparator, and a second digital comparator;

[0030] The coarse data weighting circuit performs weighted summation based on N-bit reference data Dref(N) to generate sum data Cot00, which is connected to the first digital comparator. The fine data weighting circuit performs weighted summation based on N-bit reference data Dref(N) to generate sum data Cot01, which is connected to the second digital comparator. Cot00 > Cot01.

[0031] K data weighting circuits perform weighted summation based on K sets of N-bit desaturation state codes Ds(N)1~Ds(N)K, generating K summation data respectively. These K summation data are then connected to the second comparison input Cot_s of a first digital comparator via K summation data selection switches, with only one switch active at any given time. The first comparison input of the first digital comparator is connected to the summation data Cot00. Any two adjacent summation data are subtracted using K-1 subtractors to obtain K-1 difference data. Each difference data point is connected to the second comparison input Cot_sn of the second digital comparator via K-1 difference data selection switches. Only one of the K-1 difference data selection switches can be turned on at any given time. The first comparison input of the second digital comparator is connected to the sum data Cot01. The second digital comparator compares the data at the Cot_sn input with the sum data Cot01 to obtain the potential error signal Error_lat. The first digital comparator compares the data at the Cot_s input with the sum data Cot00 to obtain the pre-output error signal Error_pre.

[0032] Compared with the prior art, the advantages of the present invention are:

[0033] (1) The present invention uses a high-precision receiving amplifier circuit and a multi-stage cascaded structure to improve the small signal amplification capability. In addition, the common-mode voltage can be adjusted to improve the identification accuracy of the received signal and the common-mode operating range.

[0034] (2) The OOK demodulation circuit of the present invention adopts a multi-stage comparator structure to improve the demodulation accuracy of the OOK signal;

[0035] (3) The high-precision desaturation protection circuit of the present invention detects the V of the SiC MOSFET. DS The slope of the voltage change is used to determine V DS Whether the voltage is within the safe range can be dynamically monitored. DS By mitigating all abnormal changes and improving the accuracy of Desat protection, the accuracy and reliability of the gate driver chip are significantly enhanced.

[0036] The technical solution of this invention can be applied to various power integrated systems based on SiC MOSFETs. Attached Figure Description

[0037] Figure 1 This is a block diagram of the SiC MOSFET gate drive circuit with desaturation protection function according to the present invention.

[0038] Figure 2 This is one embodiment of the receiving amplifier circuit of the present invention.

[0039] Figure 3This is one embodiment of the OOK demodulation circuit of the present invention.

[0040] Figure 4 This is one embodiment of the modulation and transmission circuit of the present invention.

[0041] Figure 5 This is a schematic diagram illustrating the desaturation protection principle of an existing SiC MOSFET.

[0042] Figure 6 This is a block diagram of the high-precision desaturation protection circuit structure of the present invention.

[0043] Figure 7 This is a block diagram of the voltage detection circuit structure of the present invention.

[0044] Figure 8 This is one embodiment of the voltage integrator circuit of the present invention.

[0045] Figure 9 This is a schematic diagram of the voltage follower detection circuit of the present invention.

[0046] Figure 10 This is an internal block diagram of the integrated control logic circuit of the present invention.

[0047] Figure 11 This is one embodiment of the error judgment handling logic of the present invention.

[0048] Figure 12 This is a block diagram illustrating the application of the present invention in a wide input range LLC resonant converter system. Detailed Implementation

[0049] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments.

[0050] like Figure 1 As shown, the SiC MOSFET gate drive circuit with desaturation protection function described in this invention includes: an input receiving circuit 1, a first modulation transmitting circuit 2, a first OSC oscillator 13, a first high-voltage isolation circuit 11, a first receiving amplification circuit 6, a first OOK demodulation circuit 7, an output buffer circuit 3, a second OOK demodulation circuit 4, a second receiving amplification circuit 5, a second modulation transmitting circuit 9, a second high-voltage isolation circuit 12, a high-precision desaturation protection circuit 8, and a second OSC oscillator 10.

[0051] The input receiving circuit 1, the first modulation transmitting circuit 2, the first OSC oscillator 13, the second OOK demodulation circuit 4, the second receiving amplification circuit 5, and the output buffer circuit 3 constitute the transmitting end circuit of the driving circuit. The first receiving amplification circuit 6, the first OOK demodulation circuit 7, the second modulation transmitting circuit 9, the high-precision desaturation protection circuit 8, and the second OSC oscillator 10 constitute the receiving end circuit of the driving circuit. The ground potential of all circuits inside the transmitting end circuit of the driving circuit is connected to the transmitting end ground voltage Vgnd1, and the ground potential of all circuits inside the receiving end circuit of the driving circuit is connected to the receiving end ground voltage Vgnd2.

[0052] The high-voltage isolation circuits (first high-voltage isolation circuit 11 and second high-voltage isolation circuit 12) are used to isolate the transmitting circuit and the receiving circuit of the driving circuit. The first high-voltage isolation circuit 11 includes a positive transmitting capacitor Ctp, a negative transmitting capacitor Ctn, a positive receiving capacitor Crp, and a negative receiving capacitor Crn. The second high-voltage isolation circuit 12 includes a positive transmitting capacitor Ctpp, a negative transmitting capacitor Ctnp, a positive receiving capacitor Crpp, and a negative receiving capacitor Crnp.

[0053] The first OSC oscillator (13) generates a clock CKd for use by the first modulation and transmission circuit 2. The second OSC oscillator (10) generates a clock CKp for use by the second modulation and transmission circuit 9.

[0054] The input receiving circuit 1 receives external low-level logic input data IN, processes it, and converts it into input data Din. Then, the input data Din enters the first modulation transmitting circuit 2, and is modulated with clock CKd to obtain the differential transmission data TxP and TxN for the data channel. The differential transmission data TxP and TxN are connected to the left ends of the positive transmitting capacitor Ctp and the negative transmitting capacitor Ctn, respectively; the right ends of the positive transmitting capacitor Ctp and the negative transmitting capacitor Ctn are connected to the left ends of the positive receiving capacitor Crp and the negative receiving capacitor Crn, respectively; the right ends of the positive receiving capacitor Crp and the negative receiving capacitor Crn are the differential reception data RxP and RxN for the data channel. The differential received data RxP and RxN from the data channel enter the first receiving amplifier circuit 6, and are processed to obtain four transmit data differential signals Vo1p, Vo1n, Vo2p, and Vo2n. Then, the four transmit data differential signals Vo1p, Vo1n, Vo2p, and Vo2n enter the first OOK demodulation circuit 7, and are demodulated to generate the receive output data Dout. Finally, the receive output data Dout enters the high-precision desaturation protection circuit 8, which is connected to the desaturation detection port Desat and the drain of the SiC MOSFET. The high-precision desaturation protection circuit 8 combines the Dout signal and the Desat signal to generate an output drive signal GO with a large drive current and an error signal Flt_out.

[0055] The second modulation and transmission circuit 9 modulates the clock CKp according to the state of the error signal Flt_out to obtain differential protection data PxP and PxN. The differential protection data PxP and PxN enter the second modulation and transmission circuit 9 to obtain protection channel differential transmission data TxPp and TxNp. The protection channel differential transmission data TxPp and TxNp are connected to the right ends of the positive transmitting capacitor Ctpp and the negative transmitting capacitor Ctnp, respectively. The left ends of the positive transmitting capacitor Ctpp and the negative transmitting capacitor Ctnp are connected to the right ends of the positive receiving capacitor Crpp and the negative receiving capacitor Crnp, respectively. The left ends of the positive receiving capacitor Crpp and the negative receiving capacitor Crnp are the protection channel differential receiving data RxPp and RxNp. The differential received data RxPp and RxNp of the protection channel enter the second receiving amplifier circuit 5, generating four protection data differential signals Vo1p, Vo1n, Vo2p and Vo2n; then the four protection data differential signals Vo1p, Vo1n, Vo2p and Vo2n enter the second OOK demodulation circuit 4, and after demodulation, an error buffer output signal Flt_buf is generated, and finally processed by the output buffer circuit 3 to obtain the output error signal FLT.

[0056] Figure 1The high and low voltage isolation on both sides of the gate driver chip is achieved by four sets of series-connected isolation capacitors. Capacitors Ctp and Crp form a P-terminal series isolation capacitor, and capacitors Ctn and Crn form an N-terminal series isolation capacitor. The upper plates of the two series isolation capacitors are connected by a bonding wire. Capacitors Ctpp and Crpp form a P-terminal protection series isolation capacitor, and capacitors Ctnp and Crnp form an N-terminal protection series isolation capacitor, also connected by a bonding wire. Typically, the withstand voltage of SiO2 is around 500V / µm. In a typical 0.18µm CMOS process, if the first metal layer M1 is used as the lower plate of the isolation capacitor and the sixth metal layer M6 is used as the upper plate, the total thickness of SiO2 between the metal layers is approximately 6-7µm. This means that the withstand voltage of a single isolation capacitor is approximately 3000V-3500V, and the withstand voltage of two isolation capacitors is approximately 6000V-7000V.

[0057] The implementation of input receiving circuit 1 typically includes an input ESD protection circuit and a Schmitt trigger connected in sequence. Input receiving circuit 1 not only transmits signals but also provides ESD protection for the internal circuitry of the chip, preventing damage from ESD-induced surges. The Schmitt trigger is used to identify whether the external input level is logic "0" or "1". Due to significant interference from external signals, the Schmitt trigger must have sufficient noise immunity.

[0058] Figure 2 This is a schematic diagram of the receiving amplifier circuit of the present invention, including a three-stage cascaded common-mode adjustable differential amplifier circuit: a first-stage common-mode adjustable differential amplifier circuit, a second-stage common-mode adjustable differential amplifier circuit, and a third-stage common-mode adjustable differential amplifier circuit. The circuit structure of the first receiving amplifier circuit 6 is the same as that of the second receiving amplifier circuit 5. For ease of explanation, Figure 2 The input and output signals of the first receiving amplifier circuit 6 are used for identification.

[0059] The left side of the first-stage common-mode adjustable differential amplifier circuit in the diagram includes a PMOS transistor M21 and an NMOS transistor M23 connected in series through their drains; a capacitor C21 is connected between the gate and source of PMOS transistor M21, and a bias resistor R21 is connected between its gate and drain; the drain of NMOS transistor M23 is connected to the negative terminal of the differential amplifier, output signal Vo11, and the gate of NMOS transistor M23 is connected to the positive input terminal RxP of the receiving amplifier circuit; the right side of the circuit includes a PMOS transistor M22 and an NMOS transistor M24 connected in series through their drains; the source of PMOS transistor M22 is connected to the power supply VDD, a capacitor C22 is connected between its gate and source, and a bias resistor R21 is connected between its gate and drain. Connect the bias resistor R22; the drain of NMOS transistor M24 is connected to the positive terminal of the differential amplifier output signal Vo12, and the gate of NMOS transistor M24 is connected to the negative input terminal RxN of the receiving amplifier circuit; the sources of PMOS transistors M21 and M22 are connected in parallel, and the sources of NMOS transistors M23 and M24 are connected in parallel; the sources of NMOS transistors M23 and M24 are connected to ground; the drains of NMOS transistors M25, M26, and M27 are connected; the gate of M25 is connected to the bias voltage Vb1, providing the bias current required for the normal operation of the amplifier; the gates of NMOS transistors M26 and M27 are connected to the common-mode adjustment signals C11 and C12, respectively.

[0060] The left side of the second-stage common-mode adjustable differential amplifier circuit includes a PMOS transistor M31 and an NMOS transistor M33 connected in series through their drains; a capacitor C31 is connected between the gate and source of PMOS transistor M31, and a bias resistor R31 is connected between its gate and drain; the drain of NMOS transistor M33 is the negative terminal of the second-stage common-mode adjustable differential amplifier circuit, outputting signal Vo21, and the gate of NMOS transistor M33 is connected to the positive output terminal Vo12 of the first-stage common-mode adjustable differential amplifier circuit; the right side of the circuit includes a PMOS transistor M32 and an NMOS transistor M34 connected in series through their drains; the source of PMOS transistor M32 is connected to the power supply VDD, a capacitor C32 is connected between its gate and source, and a bias resistor R31 is connected between its gate and drain. Resistor R32; The drain of NMOS transistor M34 is the positive terminal of the second-stage common-mode adjustable differential amplifier circuit, outputting signal Vo22. The gate of NMOS transistor M34 is connected to the negative output terminal Vo11 of the first-stage common-mode adjustable differential amplifier circuit. The sources of PMOS transistors M31 and M32 are connected in parallel, and the sources of NMOS transistors M33 and M34 are connected in parallel. The sources of NMOS transistors M33 and M34 are connected to ground. The drains of NMOS transistors M35, M36, and M37 are connected. The gate of NMOS transistor M35 is connected to the bias voltage Vb1, providing the bias current required for the amplifier to operate normally. The gates of NMOS transistors M36 and M37 are connected to the common-mode adjustment signals C11 and C12, respectively.

[0061] The left side of the third-stage common-mode adjustable differential amplifier circuit includes a PMOS transistor M41 and an NMOS transistor M43 connected in series through their drains. The source of the PMOS transistor M41 is connected to the power supply VDD, and a capacitor C41 is connected between the gate and source of the PMOS transistor M41. The gate of the PMOS transistor M41 is also connected to the upper end of a resistor R41, and the drain of the PMOS transistor M41 is also connected to the lower end of a resistor R42, serving as the third signal output terminal Vo2p of the receiving amplifier circuit. The lower end of resistor R41 and the upper end of resistor R42 are connected, serving as the first signal output terminal Vo1p of the receiving amplifier circuit. The drain of the NMOS transistor M43 is connected to the drain of the PMOS transistor M41, and the gate of the NMOS transistor M43 is connected to the positive output of the preceding common-mode adjustable amplifier circuit. The circuit includes a PMOS transistor M42 and an NMOS transistor M44 connected in series through their drains. The source of the PMOS transistor M42 is connected to the power supply VDD. A capacitor C42 is connected between the gate and source of the PMOS transistor M42. The gate of the PMOS transistor M42 is also connected to the upper end of a resistor R43, and the drain of the PMOS transistor M42 is also connected to the lower end of a resistor R44. The lower end of the resistor R43 and the upper end of the resistor R44 are connected and also serve as the second signal output terminal Vo1n of the receiving amplifier circuit. The drain of the NMOS transistor M44 is connected to the drain of the PMOS transistor M42 and also serves as the fourth signal output terminal Vo2n of the receiving amplifier circuit. The gate of the NMOS transistor M44 is connected to the negative output terminal Vo21 of the preceding common-mode adjustable amplifier circuit. The sources of PMOS transistors M41 and M42 are connected in parallel, and the sources of NMOS transistors M43 and M44 are connected in parallel. The sources of NMOS transistors M43 and M44 are connected to ground. The drains of NMOS transistors M45, M46, and M47 are also connected to ground. The gate of NMOS transistor M45 is connected to the bias voltage Vb1, providing the bias current required for the amplifier to operate normally. The gates of NMOS transistors M46 and M47 are connected to the common-mode adjustment signals C11 and C12, respectively.

[0062] By changing the magnitudes of the common-mode adjustment signals C11 and C12, the bias current flowing through NMOS transistors M23 and M24 will change, and the output voltages of both the negative and positive output signals of the 3-stage cascaded common-mode adjustable differential amplifier circuit will change simultaneously, thereby achieving adjustment of the output common-mode voltage.

[0063] Figure 3 This is a schematic diagram of the OOK demodulation circuit of the present invention. The circuit consists of two stages of fully differential comparator amplifiers. The first OOK demodulation circuit 7 and the second OOK demodulation circuit 4 have the same structure. For ease of explanation... Figure 3 The input and output signals of the first OOK demodulation circuit 7 are used for identification.

[0064] The preamplifier circuit is a differential amplifier (DDA) consisting of PMOS transistors M88, M89, M812, M813, NMOS transistors M810, M811, M814, and M815, and resistor R85. The post-amplifier circuit is a three-stage comparator consisting of PMOS transistors M801, M802, M803, M804, M805, M806, M809, NMOS transistors M807, M808, and M8010, and resistors R801 and R802.

[0065] The differential amplifier circuit internally includes: the gate of PMOS transistor M88 is the first signal input terminal of the differential amplifier circuit; the gate of PMOS transistor M89 is the second signal input terminal of the differential amplifier circuit; PMOS transistor M812 is the third signal input terminal of the differential amplifier circuit; and PMOS transistor M813 is the fourth signal input terminal of the differential amplifier circuit. The drains of PMOS transistors M88 and M89 are connected and connected to the drain of NMOS transistor M810, simultaneously serving as the positive output terminal V402 of the differential amplifier circuit. The drain of PMOS transistor M812 and P... The drain of MOSFET M813 is connected to the upper end of resistor R85; the lower end of resistor R85 is connected to the drain of NMOS transistor M814, and also serves as the negative output terminal V403 of the differential amplifier circuit; NMOS transistors M810 and M811 form a common-source common-gate current source structure, and NMOS transistors M814 and M815 form a common-source common-gate current source structure. The gates of NMOS transistors M810 and M814 are connected to the same bias voltage Vb81, and the gates of NMOS transistors M811 and M815 are connected to the same bias voltage Vb82.

[0066] The three-stage comparator internally includes: PMOS transistors M801, M802, and M803, resistors R801 and R802 forming the input stage of the three-stage comparator; PMOS transistors M804, M805, and M806, NMOS transistors M807 and M808 forming the amplification stage of the three-stage comparator; and PMOS transistors M809 and M8010 forming the output stage of the three-stage comparator. The output terminal of the output stage of the three-stage comparator is Dout.

[0067] For the second OOK demodulation circuit 4, the input signals are Vo1pp, Vo1np, Vo2pp and Vo2np, and the output is the error buffer output signal Flt_buf.

[0068] Figure 4 This is a schematic diagram of the modulation and transmission circuit structure of the present invention. The first modulation and transmission circuit 2 and the second modulation and transmission circuit 3 can adopt the same circuit structure. The signals in the diagram are labeled using the first modulation and transmission circuit 2 as an example. This circuit includes: a first digital multiplier 40, a second digital multiplier 41, an inverter inv401, an inverter inv402, an inverter inv403, an inverter inv404, and an inverter inv405. The first input terminal of the first digital multiplier 40 is connected to the OSC signal, the second input terminal is connected to the control signal set, the third input terminal is connected to the digital input signal Din, and the output terminal is connected to the input terminal of the inverter inv404. The first input of the second digital multiplier 41 is connected to the output of inverter inv401, the second input is connected to the control signal set, the third input is connected to the digital input signal Din, and the output is connected to the input of inverter inv402. The input of inverter inv401 is connected to the OSC signal, the output of inverter inv404 is connected to the input of inverter inv405, the output of inverter inv402 is connected to the input of inverter inv403, and the outputs of inverter inv405 and inverter inv403 are respectively the differential transmission data TxP and TxN.

[0069] Figure 4 The modulation and transmission circuit's differential transmission data TxP and TxN are controlled by the control signal set to determine their validity. Inverters inv402 and inv403 form one output buffer, and inverters inv404 and inv405 form another. When the Din signal is 0, both differential transmission data TxP and TxN are 0; when the Din signal is 1, the differential transmission data TxP and TxN are high-frequency square wave signals modulated by the OSC signal, and their high and low levels are completely opposite, forming an OOK signal.

[0070] When a positive voltage Vth greater than the threshold voltage Vth is applied to the gate of a SiC MOSFET GS If a positive voltage V is applied to the drain D at this time... DS Then, electrons in the source will continuously flow from the drain (D) to the source (S) under the influence of the electric field, and the current will increase linearly with the increase of the drain-source voltage. As V... DS As the voltage increases, the channel experiences pinch-off, and the current no longer follows V. DS The voltage increases proportionally, leading to desaturation. For example... Figure 5 As shown, during the time interval t1-t3, the MOSFET successively undergoes transitions through the turn-on, saturation, and deep linear regions, with the load current I... L V continues to remain at its maximum value. DSThe voltage remains at 0. After t4, when an abnormal phenomenon such as a short circuit occurs in the circuit, the MOSFET will undergo desaturation, at which point V DS The voltage will rise rapidly, and if no protective measures are taken, V DS The voltage will rise to the bus voltage VH, and the load current I L It is typically several times the rated current. An abnormal increase in power causes a rapid rise in junction temperature, and failure to shut down the device in time may burn it out. For the Desat protection design of SiC MOSFETs, the simplest method is to monitor the current I flowing through the SiC MOSFET. L I L If the current exceeds a certain threshold, the driver reports an error and shuts off the MOSFET switch. Another measure is to detect the VC of the SiC MOSFET device. DS The voltage desaturation detection circuit is preset with a saturation threshold voltage, such as 6V. Therefore, when V... DS When the voltage exceeds 6V, the driver chip reports an error and shuts down the MOSFET switch. The aforementioned Desat protection function uses a fixed saturation threshold voltage Vr for state comparison; if Vr exceeds this threshold, the driver will detect the voltage exceeding the threshold. DS If the situation is abnormal but has not reached the threshold Vr, the Desat protection function will not be triggered. However, at this time, the operating state of the SiC MOSFET device has already deviated significantly, the current has increased sharply, and the conduction loss has increased significantly. Therefore, this invention uses a high-precision desaturation protection circuit 8 to implement circuit protection.

[0071] like Figure 6 As shown, the high-precision desaturation protection circuit 8 proposed in this invention includes: an external interface circuit 61, a clock generation circuit 62, a voltage follower detection circuit 63, a comprehensive control logic circuit 64, a voltage detection circuit 65, an output drive circuit 66, a detection resistor Rd1, a detection resistor Rd2, and a detection capacitor Cd1.

[0072] The lower end of the detection resistor Rd2 is connected to the upper end of the detection resistor Rd1 and the upper end of the detection capacitor Cd1 to generate a desaturation input signal Vdes, which is then connected to the detection voltage input terminal of the voltage detection circuit 65. The upper end of the detection resistor Rd2 is connected to the desaturation detection port Desat and the drain of the SiC MOSFET M100 to be driven, while the lower ends of the detection resistor Rd1 and the lower ends of the detection capacitor Cd1 are connected to the ground potential port.

[0073] The voltage detection circuit 65 is used to detect the desaturation input signal Vdes generated by the desaturation detection port Desat signal through the voltage divider and filter of the detection resistor Rd1, the detection resistor Rd2 and the detection capacitor Cd1, and outputs the desaturation sampling signal Vdesin under the control of the desaturation control clock Ckdes.

[0074] The voltage follower detection circuit 63, under the control of the sampling control clock Ckcs, the follower control clock Ckcom, and the desaturation control clock Ckdes, generates a desaturation quantization signal Ddes based on the desaturation sampling signal Vdesin. The clock generation circuit 62 generates the reference clock OSC, the sampling control clock Ckcs, the follower control clock Ckcom, and the desaturation control clock Ckdes.

[0075] The integrated control logic circuit 64 generates a power switch drive signal Dout2, an error signal Error, a control signal Ctrl, and a control signal Ctrl1 based on the states of the input drive signal Din2, the reference clock OSC, and the desaturation quantization signal Ddes. The external interface circuit 61 receives the signal Dout and converts it into the input drive signal Din2; it also buffers the error signal Error and outputs the error signal Flt_out to the second modulation and transmission circuit 9. The output drive circuit 66 generates a gate drive signal GO based on the power switch drive signal Dout2.

[0076] Figure 6The circuit shown detects the state of the drain voltage signal Desat of the SiC MOSFET M100 at different times to determine whether the turn-on state of M100 is abnormal, thereby dynamically monitoring the states of Desat and M100 to achieve more accurate short-circuit protection. When the circuit is working normally, the clock generation circuit 62 first generates a set of default initial reference clock OSC, sampling control clock Ckcs, follower control clock Ckcom, and desaturation control clock Ckdes. Then, the integrated control logic circuit 64 first outputs the control signal Ctrl to enable the external interface circuit 61 and the output drive circuit 66. The external interface circuit 61 starts to receive the external input signal Dout and converts it into the input drive signal Din2. Then, the integrated control logic circuit 64 generates the power switch drive signal Dout2 based on the state of the input drive signal Din2, the reference clock OSC, and the desaturation quantization signal Ddes. The output drive circuit 66 generates the gate drive signal GO based on the power switch drive signal Dout2. Finally, the integrated control logic circuit 64 outputs the control signal Ctrl1, which activates the voltage follower detection circuit 63 and the voltage detection circuit 65. The voltage detection circuit 65 starts detecting the desaturation input signal Vdes and outputs the desaturation sampling signal Vdesin under the control of the desaturation control clock Ckdes. The voltage follower detection circuit 63 generates the desaturation quantization signal Ddes based on the desaturation sampling signal Vdesin. The integrated control logic circuit 64 determines the state of the voltage signals Desat and M100 based on the state of the quantization signal Ddes. In case of an abnormality, it changes the state of the control signal Ctrl and outputs an error signal Error to the external interface circuit 61. Finally, the external interface circuit 61 outputs the Flt_out signal.

[0077] Figure 7 In an embodiment of voltage detection circuit 65, the circuit includes a sampling switch 70 and a voltage integrator 71. The sampling switch 70 samples the desaturation input signal Vdes under the control of the desaturation control clock Ckdes to obtain a desaturation sample-and-hold signal Vdes_sh. The voltage integrator 71 then integrates and isolates the desaturation sample-and-hold signal Vdes_sh based on the reference voltage Vref to obtain a desaturation sampling signal Vdesin. Figure 7 The sampling switch 70 can be implemented using various existing voltage sampling switches.

[0078] Figure 8 for Figure 7One embodiment of the medium voltage integrator 71 circuit includes PMOS transistors M701, M702, M705, M706, M707, M708, NMOS transistors M709, M710, M711, M712, and M713, resistors R71 and R72, and capacitors C71 and C72.

[0079] Specifically, the gate of PMOS transistor M705 is connected to the reference voltage Vref; the gates of PMOS transistors M701 and M702 are connected to the bias voltage Vbc71; the gates of PMOS transistors M707 and M708 are connected to the bias voltage Vbc72; and the gates of NMOS transistors M710 and M709 are connected to the bias voltage Vbc73. The drain of PMOS transistor M701 is connected to the source of both PMOS transistors M705 and M706; the drain of PMOS transistor M705 is connected to the source of PMOS transistor M707; the drain of PMOS transistor M707 is connected to the drain of NMOS transistor M710; the source of NMOS transistor M710 is connected to the drain, gate, and gate of NMOS transistors M711 and M712; the drain of PMOS transistor M706 is connected to the source of PMOS transistor M708; the drain of PMOS transistor M708 is connected to the drain of NMOS transistor M709, the gate of NMOS transistor M713, and the upper end of resistor R72; the lower end of resistor R72 is connected to the upper end of capacitor C72; NM The source of OS transistor M709 is connected to the drain of NMOS transistor M712; the drain of PMOS transistor M702 is connected to the drain of NMOS transistor M713, and is also connected to the right end of capacitor C71, serving as the output terminal of the desaturation sampling signal Vdesin of the voltage integrator 71 circuit; the gate of NMOS transistor M706 is connected to the left end of capacitor C71 and the right end of resistor R71, and the left end of resistor R71 is connected to the desaturation sample-and-hold signal Vdes_sh; the sources of PMOS transistors M701 and M702 are simultaneously connected to the power supply voltage VDD; the sources of NMOS transistors M711, M712, and M713, and the lower end of capacitor C72 are all connected to ground potential.

[0080] Figure 8In this circuit, PMOS transistors M701, M702, M705, M706, M707, and M708, NMOS transistors M709, M710, M711, M712, and M713, along with resistor R72 and capacitor C72, constitute a two-stage cascode operational amplifier. This two-stage cascode operational amplifier, along with resistor R71 and capacitor C71, forms an integrator circuit. This integrator circuit integrates the desaturated sample-and-hold signal Vdes_sh based on the reference voltage Vref to obtain the desaturated sample signal Vdesin.

[0081] Figure 9 This is a schematic diagram of the voltage follower detection circuit 63 of the present invention. The voltage follower detection circuit 63 includes: a high-performance sampling switch 90, a hold circuit 91, and a high-precision comparator 93. The input desaturated sampling signal Vdesin is connected to the analog signal input terminal of the high-performance sampling switch 90. Under the control of the sampling control clock Ckcs, the high-performance sampling switch 90 samples the voltage of the input desaturated sampling signal Vdesin. The first analog signal output terminal of the high-performance sampling switch 90 is connected to the positive input terminal of the high-precision comparator 93 under the control of the follower control clock Ckcom. The second analog signal output terminal of the high-performance sampling switch 90 is connected to the signal input terminal of the hold circuit 91 under the control of the desaturation control clock Ckdes. The analog signal output terminal of the hold circuit 91 is connected to the negative input terminal of the high-precision comparator 93 under the control of the follower control clock Ckcom. The data from the quantization output terminal of the high-precision comparator 93 is output to the integrated control logic circuit 64.

[0082] In this invention, the reference clock OSC is further subdivided into a three-phase non-overlapping clock consisting of a sampling control clock Ckcs, a follower control clock Ckcom, and a desaturation control clock Ckdes. The simplified operation of the voltage follower detection circuit 63 is as follows: In the Ckcs phase, the high-performance sampling switch 90 samples the input desaturation sampling signal Vdesin. Assuming this is the Mth sampling, the switch samples the voltage V... cs (M); Ckcom phase, high-precision comparator 93 will sample the voltage V from the switch. cs (M) will hold the voltage V held by the holding circuit 91 for the previous clock cycle. cs (M-1) is compared, and the high-precision comparator 93 obtains the quantized data Ddes(M). The output Ddes(M) is 1, indicating that V cs The voltage increases, and the output Ddes(M) is 0, then the opposite occurs; Ckdt phase, V cs (M) will be held by holding circuit 91. Before the high-precision comparator 93 receives two valid adjacent switch sample voltages, the high-precision comparator 63 outputs the initial default voltage value.

[0083] The integrated control logic circuit 64 can obtain the changing trend of the desaturation sampling signal Vdesin by reading the quantization data Ddes(M). For example, if Ddes(M) is continuously 1, it means that the desaturation sampling signal Vdesin continues to rise, and the voltage signal Desat of the drain of the SiC MOSFET M100 to be driven continues to rise.

[0084] The accuracy of the above circuit depends on the performance of the hold circuit 91 and the high-precision comparator 93. Obviously, speed and accuracy are contradictory indicators. To improve accuracy, the frequency of the control clock can be reduced. Different application backgrounds have very different requirements for the speed and accuracy of the hold circuit 91 and the high-precision comparator 93, and different circuit structures need to be designed.

[0085] Figure 10 This is a block diagram of an embodiment of the integrated control logic circuit 64 of the present invention. The integrated control logic circuit 64 of the present invention includes: a counter 100, a control logic circuit 101, a reference data output circuit 102, an input serial register 103, a serial-to-parallel conversion circuit 104, a first buffer 105, a second buffer 106, a parallel register group 107, and an error decision processing logic 108.

[0086] The counter 100 generates a working control clock Ck_ctrl based on the external input reference clock OSC. The working control clock Ck_ctrl is simultaneously connected to the control clock input terminals of the control logic circuit 101, the input serial register 103, the serial / parallel conversion circuit 104, the parallel register group 107, and the error decision processing logic 108.

[0087] The control logic circuit 101 generates control signals Ctrl and Ctrl1 based on the operating control clock Ck_ctrl and the potential error signal Error_lat. Control signal Ctrl is connected to the control signal input terminal of the first buffer 105, and control signal Ctrl1 is connected to the control signal input terminals of the reference data output circuit 102, the input serial register 103, the serial-to-parallel conversion circuit 104, the error decision processing logic 108, and the second buffer 106. In addition to being used within the integrated control logic circuit, control signals Ctrl and Ctrl1 are also output to other circuit modules of the present invention.

[0088] The first buffer 105, under the control of the control signal Ctrl, buffers the input drive signal Din2 and then generates the power switch drive signal Dout2. The reference data output circuit 102, under the control of the control signal Ctrl1, generates N-bit reference data Dref(N). The input serial register 103, under the control of the working control clock Ck_ctrl and the control signal Ctrl1, sequentially receives the desaturation quantization signal Ddes according to the time sequence and outputs it to the serial / parallel conversion circuit 104 in a first-in-first-out order. The serial / parallel conversion circuit 104, under the control of the working control clock Ck_ctrl and the control signal Ctrl1, converts the serially input desaturation quantization signal Ddes into a parallel output N-bit desaturation status code Ds(N). The parallel register group 107, under the control of the working control clock Ck_ctrl, converts the N-bit desaturation status code Ds(N) output according to the time sequence into K groups of parallel output N-bit desaturation status codes Ds(N)1~Ds(N)K. The error decision processing logic 108, under the control of the working control clock Ck_ctrl and the control signal Ctrl1, performs comprehensive decision processing on the K sets of parallel output N-bit desaturation status codes Ds(N)1~Ds(N)K and N-bit reference data Dref(N) to obtain the pre-output error signal Error_pre and the potential error signal Error_lat. The second buffer 106, under the control of the control signal Ctrl1, buffers and drives the pre-output error signal Error_pre to obtain the error signal Error. The potential error signal Error_lat is output to the control logic circuit 101, and finally adjusts the state of the control signal Ctrl. Here, N is a natural number greater than 1, and K is a natural number greater than 2.

[0089] After the chip is powered on, the counter 100 in the integrated control logic circuit 64 of this invention starts working first. The counter 100 outputs a working control clock Ck_ctrl according to the OSC signal, and simultaneously inputs it to the control logic circuit 101, the input serial register 103, the serial / parallel conversion circuit 104, the parallel register group 107, and the error decision handling logic 108. Next, the control logic circuit 101 generates a control signal Ctrl according to the working control clock Ck_ctrl and enables the first buffer 105. The first buffer 105 generates a power switch drive signal Dout2 according to the input drive signal Din2. After a certain time delay, the control logic circuit 101 will generate a control signal Ctrl1 and enable the reference data output circuit 102, the input serial register 103, the serial / parallel conversion circuit 104, the error decision handling logic 108, and the second buffer 106. Then, the reference data output circuit 102 generates N-bit reference data Dref(N), and the input serial register 103 receives the desaturation quantization signal Ddes in chronological order and outputs it to the serial / parallel conversion circuit 104 in a first-in-first-out order. The serial / parallel conversion circuit 104 converts the serially input desaturation quantization signal Ddes into a parallel output N-bit desaturation status code Ds(N). The parallel register group 107 converts the N-bit desaturation status code Ds(N) output in chronological order into K groups of parallel output N-bit desaturation status codes Ds(N)1 to Ds(N)K. The error decision processing logic 108 performs comprehensive decision processing on the K groups of parallel output N-bit desaturation status codes Ds(N)1 to Ds(N)K and the N-bit reference data Dref(N) to obtain the pre-output error signal Error_pre and the potential error signal Error_lat. The control logic circuit 101 adjusts the state of the control signal Ctrl in real time according to the state of the potential error signal Error_lat, thereby controlling the external interface circuit of the present invention and changing the characteristics of the input drive signal Din2, and finally changing the characteristics of the power switch drive signal Dout2 and the gate drive signal GO, thus realizing the short-circuit protection function of SiC MOSFET.

[0090] In the above-described operation of the integrated control logic circuit 64 of this invention, the working control clock Ck_ctrl is typically a clock signal with a frequency not higher than OSC; the delay time for generating control signals Ctrl and Ctrl1 must be greater than a positive integer multiple of the period of the working control clock Ck_ctrl, and the specific duration can be set according to the application scenario. The control logic circuit 101 can be implemented in various ways, the most common being state machine control.

[0091] Figure 11 for Figure 10A block diagram of an embodiment of the error decision processing logic 108. The error decision processing logic 108 includes: a coarse data weighting circuit 111, a fine data weighting circuit 112, K data weighting circuits 1101 to 110K, K summation data selection switches S1 to SK, K-1 subtractors 1131 to 113K-1, K-1 difference data selection switches SN1 to SNK-1, a first digital comparator 114, and a second digital comparator 115.

[0092] The coarse data weighting circuit 111 and the fine data weighting circuit 112 generate summation data Cot00 with a larger value and summation data Cot01 with a smaller value, respectively, based on the N-bit reference data Dref(N).

[0093] K data weighting circuits 1101 to 110K generate K summation data Cot1 to CotK based on any one of the K sets of N-bit desaturation state codes Ds(N)1 to Ds(N)K. These K summation data Cot1 to CotK are connected to the left ends of K summation data selection switches S1 to SK. The right ends of the K summation data selection switches S1 to SK are connected together and then connected to the second comparison input Cot_s of the first digital comparator 114. The first comparison input of the first digital comparator 114 is connected to the larger summation data Cot00. Any two adjacent summation data from the K summation data Cot1 to CotK generated by the K sets of N-bit desaturation state codes Ds(N)1 to Ds(N)K are passed through K-1 subtractors 1131 to 1143. 13K-1 is subjected to subtraction processing to obtain K-1 subtraction data Not1 to NotK-1; the K-1 subtraction data Not1 to NotK-1 are respectively connected to the left end of the K-1 subtraction data selection switches SN1 to SNK-1; the right ends of the K-1 subtraction data selection switches SN1 to SNK-1 are connected together and connected to the second comparison input Cot_sn of the second digital comparator 115; the first comparison input of the second digital comparator 115 is connected to the smaller sum data Cot01; the second digital comparator 115 compares Cot_sn with the sum data Cot01 to obtain the potential error signal Error_lat; the first digital comparator 114 compares Cot_s with the sum data Cot00 to obtain the pre-output error signal Error_pre.

[0094] In the circuit described above, only one of the K summation data selection switches S1 to SK can be turned on at any given time, and the remaining K-1 summation data selection switches cannot be turned on simultaneously. Similarly, only one of the K-1 difference data selection switches SN1 to SNK-1 can be turned on at any given time, and the remaining K-2 difference data selection switches cannot be turned on simultaneously.

[0095] Figure 11 The main function of the circuit shown is to perform various comparisons between the values ​​of the K sets of N-bit desaturation state codes Ds(N)1~Ds(N)K and the values ​​of the N-bit reference data Dref(N), ultimately obtaining the pre-output error signal Error_pre and the potential error signal Error_lat. The pre-output error signal Error_pre is obtained by comparing the summed data Cot00 generated from the N-bit reference data Dref(N) through the coarse data weighting circuit 111 with any one of the K summed data Cot1~CotK generated from the K sets of N-bit desaturation state codes Ds(N)1~Ds(N)K. If the pre-output error signal Error_pre is abnormal, it indicates that the rise slope of the saturation sampling signal Vdesin is very large per unit time, and the drain voltage signal Desat of the driven SiC MOSFET is continuously rising with a slope exceeding the warning value, indicating a significant abnormality in the state of the SiC MOSFET device. The potential error signal Error_lat is obtained by comparing the summed data Cot01 generated from the N-bit reference data Dref(N) through the fine data weighting circuit 111 with any one of the K-1 difference data Not1 to NotK-1. The potential error signal Error_lat detects the difference between the rise slopes of the saturated sampling signal Vdesin voltage between different time periods, which can more subtly reflect the changes in the sampling signal Vdesin voltage, thereby more accurately detecting the changes in the drain voltage signal Desat of the driven SiC MOSFET device.

[0096] Review Figure 5 Given the waveform, existing Desat protection technology, after t4, uses a fixed reference voltage Vr and V DS The voltage is statically compared when V DS The Desat protection function is triggered when the voltage exceeds the reference voltage Vr. This protection technology cannot respond to V. DS Various V values ​​less than the reference voltage Vr DS Abnormal voltage fluctuations and current changes. The technical solution proposed in this invention detects V after t4. DS The slope of the voltage change is used to determine V DS Whether the voltage is within the safe range can be dynamically monitored. DS All abnormal changes can significantly improve the accuracy of Desat protection, ultimately greatly improving the short-circuit protection accuracy and reliability of the gate driver chip.

[0097] Figure 12This is a system block diagram illustrating the application of the present invention in a wide-input-range LLC resonant converter system. Renewable energy power generation is significantly affected by weather conditions, resulting in large fluctuations in its output voltage, thus exhibiting a wide output voltage range. To ensure efficient energy utilization, the cascaded LLC converter must possess wide gain and high efficiency characteristics. This paper addresses the issue of the narrow input voltage range in traditional frequency converter-controlled LLC resonant converters. Figure 12 This design employs a high-efficiency hybrid-mode fixed-frequency control LLC converter structure. Based on a traditional LLC converter, the two diodes in the secondary-side full-bridge rectifier bridge are replaced with switching transistors. When the input voltage is high, the converter operates in the same mode as traditional phase-shift control. Because the voltage gain variation range is small in this mode, the circulating current loss of the converter is reduced. When the input voltage is low, the converter charges the resonant inductor through the overlapping conduction of the secondary-side switching transistors, thereby widening the voltage gain range of the converter. Figure 12 As shown, the LLC resonant converter topology using the technical solution of this invention includes primary-side switches S1-S4 forming a full-bridge inverter unit, and diodes D1 and D2 and switches S5 and S6 forming a secondary-side full-bridge rectifier unit. Vin is the DC input voltage, Vo is the output voltage, T is a high-frequency transformer with a primary-to-secondary turns ratio of n:1, where n is a natural number greater than 1. The series resonant inductor Lr, the series resonant capacitor Cr, and the transformer's magnetizing inductance Lm form a resonant slot. Co is the output capacitor, and R is the load. When the input voltage is higher than the standard input voltage, the converter uses phase-shift control, increasing the primary-side phase shift angle θ to make the gain M < 1, denoted as Buck mode. When the input voltage is lower than or equal to the standard input voltage, the converter maintains the primary-side phase shift angle θ = 0 and increases the overlap conduction time of the secondary-side switches S5 and S6 to make the gain M ≥ 1, denoted as Boost mode.

[0098] To improve efficiency, Figure 12 The six switching transistors S1 to S6 can be implemented using SiC MOSFETs. The SiC MOSFET gate drive circuit proposed in this invention is used to drive and amplify the six switching drive signals output from the power controller to obtain the gate drive signals for S1, S2, S3, S4, S5, and S6. GD1, GD2, GD3, GD4, GD5, and GD6 are all SiC MOSFET gate drive circuits proposed in this invention. Figure 12The control topology of the power controller is also given. When Vin ≤ Vin_norm, Flag = 0, and the converter operates in Boost mode. The drive signal for the primary-side switch is a square wave signal with a duty cycle of 0.5 and a phase shift angle θ = 0. The converter adjusts the voltage gain by controlling the overlapping conduction time of the secondary-side switches S5 and S6 based on the output voltage feedback signal, thereby stabilizing the output voltage. When Vin > Vin_norm, Flag = 1, and the converter operates in Buck mode. In this mode, the converter adjusts the primary-side phase shift angle based on the output voltage feedback signal, thereby stabilizing the output voltage.

[0099] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A SiC MOSFET gate drive circuit with desaturation protection function, characterized in that, It includes an input receiving circuit (1), a first modulation transmitting circuit (2), a first high-voltage isolation circuit (11), a first receiving amplifier circuit (6), a first OOK demodulation circuit (7), an output buffer circuit (3), a second OOK demodulation circuit (4), a second receiving amplifier circuit (5), a second high-voltage isolation circuit (12), a second modulation transmitting circuit (9), a high-precision desaturation protection circuit (8), a first OSC oscillator (13), and a second OSC oscillator (10); The input receiving circuit (1), the first modulation transmitting circuit (2), the output buffer circuit (3), the second OOK demodulation circuit (4), the second receiving amplification circuit (5), and the first OSC oscillator (13) constitute the transmitting end circuit of the driving circuit; the first receiving amplification circuit (6), the first OOK demodulation circuit (7), the high-precision desaturation protection circuit (8), the second modulation transmitting circuit (9), and the second OSC oscillator (10) constitute the receiving end circuit of the driving circuit; the ground potential of all circuits inside the transmitting end circuit is connected to the transmitting end ground voltage Vgnd1, and the ground potential of all circuits inside the receiving end circuit is connected to the receiving end ground voltage Vgnd2; the first OSC oscillator (13) is used to generate the clock CKd, and the second OSC oscillator (10) is used to generate the clock CKp. The high-voltage isolation circuit is used to isolate the transmitting circuit and the receiving circuit; the first high-voltage isolation circuit (11) includes a positive transmitting capacitor Ctp and a positive receiving capacitor Crp connected in series, and a negative transmitting capacitor Ctn and a negative receiving capacitor Crn connected in series; the second high-voltage isolation circuit (12) includes a positive transmitting capacitor Ctpp and a positive receiving capacitor Crpp connected in series, and a negative transmitting capacitor Ctnp and a negative receiving capacitor Crnp connected in series. The input receiving circuit (1) is connected to an external low-level logic input data IN, which is converted into input data Din and connected to the first modulation transmitting circuit (2). The first modulation transmitting circuit (2) modulates the input data Din with the clock CKd to obtain the differential transmission data TxP and TxN of the data channel. The differential transmission data TxP and TxN of the data channel are respectively connected to the left end of the positive transmitting capacitor Ctp and the left end of the negative transmitting capacitor Ctn. The right end of the positive transmitting capacitor Ctp and the right end of the negative transmitting capacitor Ctn are respectively connected to the left end of the positive receiving capacitor Crup and the left end of the negative receiving capacitor Crn. The right end of rp and the right end of the negative end of the receiving capacitor Crn generate differential data RxP and RxN of the data channel, which are connected to the first receiving amplifier circuit (6); the first receiving amplifier circuit (6) processes the differential data RxP and RxN of the data channel to obtain four differential signals Vo1p, Vo1n, Vo2p and Vo2n of the transmitted data, which are connected to the first OOK demodulation circuit (7), and the received output data Dout is generated after demodulation; the received output data Dout is finally output to the high-precision desaturation protection circuit (8), which is also connected to the desaturation detection port Desat and the drain of the SiC MOSFET. The high-precision desaturation protection circuit (8) generates an output drive signal GO with a large drive current and an error signal Flt_out by combining the received output data Dout and the Desat signal. The error signal Flt_out is connected to the input data terminal of the second modulation and transmission circuit (9). The second modulation and transmission circuit (9) modulates the clock CKp according to the state of the error signal Flt_out to obtain the protection channel differential transmission data TxPp and TxNp. The protection channel differential transmission data TxPp and TxNp are respectively connected to the right end of the positive terminal transmission capacitor Ctpp and the right end of the negative terminal transmission capacitor Ctnp. The left end of the positive terminal transmission capacitor Ctpp and the left end of the negative terminal transmission capacitor Ctnp are respectively connected to the right end of the positive terminal receiving capacitor Crpp and the right end of the negative terminal receiving capacitor Crnp. The left end of the positive terminal receiving capacitor Crpp and the left end of the negative terminal receiving capacitor Crnp generate protection channel differential receiving data RxPp and RxNp; the protection channel differential receiving data RxPp and RxNp are connected to the second receiving amplifier circuit (5) to generate four protection data differential signals Vo1pp, Vo1np, Vo2pp and Vo2np, which are connected to the second OOK demodulation circuit (4). After demodulation, an error buffer output signal Flt_buf is generated and connected to the output buffer circuit (3). After processing by the output buffer circuit (3), the output error signal FLT is finally obtained.

2. The SiC MOSFET gate drive circuit with desaturation protection function according to claim 1, characterized in that, The first receiving amplifier circuit (6) includes a 3-stage cascaded common-mode adjustable differential amplifier circuit; The first-stage common-mode adjustable differential amplifier circuit includes: a PMOS transistor M21 and an NMOS transistor M23 connected in series through their drains, and a PMOS transistor M22 and an NMOS transistor M24 connected in series through their drains; a capacitor C21 is connected between the gate and source of the PMOS transistor M21, and a bias resistor R21 is connected between the gate and drain of the PMOS transistor M21; the drain of the NMOS transistor M23 outputs the first-stage negative terminal output signal Vo11, and the gate of the NMOS transistor M23 is connected to the positive input terminal RxP of the receiving amplifier circuit (6); a capacitor C22 is connected between the gate and source of the PMOS transistor M22, and a bias resistor R22 is connected between the gate and drain of the PMOS transistor M22; the NMOS transistor M24... The drain of S-channel transistor M24 outputs the first stage positive terminal output signal Vo12. The gate of NMOS transistor M24 is connected to the negative input terminal RxN of the receiving amplifier circuit (6). The sources of PMOS transistors M21 and M22 are connected and connected to the power supply VDD. The sources of NMOS transistors M23 and M24 are connected and connected to the drains of NMOS transistors M25, M26, and M27. The gate of NMOS transistor M25 is connected to the bias voltage Vb1, providing the bias current required for the normal operation of the amplifier. The gates of NMOS transistors M26 and M27 are connected to the common-mode adjustment signals C11 and C12, respectively. The second-stage common-mode adjustable differential amplifier circuit includes: a PMOS transistor M31 and an NMOS transistor M33 connected in series through their drains; a PMOS transistor M32 and an NMOS transistor M34 connected in series through their drains; a capacitor C31 is connected between the gate and source of PMOS transistor M31; a bias resistor R31 is connected between the gate and drain of PMOS transistor M31; the drain of NMOS transistor M33 outputs the second-stage negative terminal output signal Vo21, and the gate of NMOS transistor M33 is connected to the first-stage positive terminal output signal Vo12; a capacitor C32 is connected between the gate and source of PMOS transistor M32; a bias resistor R32 is connected between the gate and drain of PMOS transistor M32; NMOS transistor M34... The drain of S-MOSFET M34 outputs the second-stage negative terminal signal Vo22, and the gate of NMOS transistor M34 is connected to the first-stage negative terminal output signal Vo11. The sources of PMOS transistors M31 and M32 are connected and connected to the power supply VDD. The sources of NMOS transistors M33 and M34 are connected and connected to ground. The drains of NMOS transistors M35, M36, and M37 are connected. The gate of NMOS transistor M35 is connected to the bias voltage Vb1, providing the bias current required for the amplifier to operate normally. The gates of NMOS transistors M36 and M37 are connected to the common-mode adjustment signals C11 and C12, respectively. The third-stage common-mode adjustable differential amplifier circuit includes: a PMOS transistor M41 and an NMOS transistor M43 connected in series through their drains, and a PMOS transistor M42 and an NMOS transistor M44 connected in series through their drains; a capacitor C41 is connected between the gate and source of the PMOS transistor M41, and the gate of the PMOS transistor M41 is also connected to the upper end of a resistor R41, with the lower end of resistor R41 connected to the upper end of resistor R42, serving as the first signal output terminal Vo1p of the receiving amplifier circuit (6); the lower end of resistor R42 is connected to the drain of the PMOS transistor M41, serving as the third signal output terminal Vo2p of the receiving amplifier circuit (6); the gate of the NMOS transistor M43 is connected to the positive terminal output signal Vo22 of the second stage; a capacitor C42 is connected between the gate and source of the PMOS transistor M42, and the gate of the PMOS transistor M42 is also connected to the upper end of resistor R43, with resistor R41 connected to the upper end of resistor R42, with resistor R42 connected to the upper end of resistor R43, with resistor R42 connected to the upper end of resistor R43, with resistor R43 connected to the upper end of resistor R443, with resistor R4 ... The lower end of resistor R44 is connected to the upper end of resistor R44, serving as the second signal output terminal Vo1n of the receiving amplifier circuit (6); the lower end of resistor R44 is connected to the drain of PMOS transistor M42, serving as the fourth signal output terminal Vo2n of the receiving amplifier circuit (6); the gate of NMOS transistor M44 is connected to the negative terminal of the second stage to output signal Vo21; the source of PMOS transistor M41 is connected to the source of PMOS transistor M42, and connected to the power supply VDD; the source of NMOS transistor M43 is connected to the source of NMOS transistor M44, and connected to the drain of NMOS transistor M45, the drain of NMOS transistor M46, and the drain of NMOS transistor M47; the gate of NMOS transistor M45 is connected to the bias voltage Vb1, providing the bias current required for the normal operation of the amplifier; the gates of NMOS transistor M46 and NMOS transistor M47 are connected to the common-mode adjustment signals C11 and C12 respectively; By changing the magnitudes of the common-mode adjustment signals C11 and C12, the bias current flowing through NMOS transistors M23 and M24 will change, and the output voltages of the negative and positive output signals of the three-stage cascaded common-mode adjustable differential amplifier circuit will change simultaneously, thereby achieving adjustment of the output common-mode voltage; the second receiving amplifier circuit (5) has the same circuit structure as the first receiving amplifier circuit (6).

3. The SiC MOSFET gate drive circuit with desaturation protection function according to claim 1, characterized in that, The first OOK demodulation circuit (7) and the second OOK demodulation circuit (4) have the same structure, both being two-stage fully differential comparator amplifier circuits. The front-stage circuit includes a differential amplifier circuit composed of PMOS transistors M88, M89, M812, M813, M810, M811, M814, M815 and resistor R85. The rear-stage comparator amplifier circuit is a three-stage comparator composed of PMOS transistors M801, M802, M803, M804, M805, M806, M809, M807, M808, M8010, resistor R801 and resistor R802. The differential amplifier circuit internally includes: PMOS transistor M88 with its gate serving as the first signal input terminal; PMOS transistor M89 with its gate serving as the second signal input terminal; PMOS transistor M812 with its gate serving as the third signal input terminal; and PMOS transistor M813 with its gate serving as the fourth signal input terminal. The sources of PMOS transistors M88, M89, M812, and M813 are all connected to the power supply VDD. The drains of PMOS transistors M88 and M89 are connected and then connected to the source of NMOS transistor M810, serving as the positive output terminal V402 of the differential amplifier circuit. The drains of PMOS transistors M812 and M813 are connected... The source of NMOS transistor M814 is connected to the source of NMOS transistor M814 via resistor R85. The drain of NMOS transistor M814 serves as the negative output terminal V403 of the differential amplifier circuit. The drain of NMOS transistor M810 is connected to the drain of NMOS transistor M811, and the drain of NMOS transistor M814 is connected to the drain of NMOS transistor M815. The sources of NMOS transistors M811 and M815 share a common ground potential. NMOS transistors M810 and M811 form a common-source common-gate current source structure, as do NMOS transistors M814 and M815. The gates of NMOS transistors M810 and M814 are connected to the same bias voltage Vb81, and the gates of NMOS transistors M811 and M815 are connected to the same bias voltage Vb82. The three-stage comparator internally includes: the sources of PMOS transistors M801, M804, and M809 are all connected to the power supply VDD; the gates of PMOS transistors M801, M804, and M809 are connected to the same bias voltage Vb81; the drain of PMOS transistor M801 is connected to the sources of PMOS transistors M802 and M803; the gate of PMOS transistor M802 is connected to the positive output terminal V402 of the differential amplifier circuit; the gate of PMOS transistor M803 is connected to the negative output terminal V403 of the differential amplifier circuit; the drain of PMOS transistor M802 is connected to the upper end of PMOS transistor M801 and the gate of PMOS transistor M805; and the drain of PMOS transistor M803... Connect the upper end of resistor R802 to the gate of PMOS transistor M806; the lower ends of resistor R801 and R802 share a common ground potential; the drain of PMOS transistor M804 is connected to the source of PMOS transistor M805 and the source of PMOS transistor M806; the drain of PMOS transistor M805 is connected to the drain of NMOS transistor M807, the gate of NMOS transistor M807, and the gate of NMOS transistor M808; the drain of PMOS transistor M806 is connected to the drain of NMOS transistor M808 and the gate of NMOS transistor M8010; the sources of NMOS transistors M807, M808, and M8010 share a common ground potential; the drain of PMOS transistor M809 is connected to the drain of NMOS transistor M8010, serving as the output of a three-stage comparator; The input stage of the three-stage comparator consists of PMOS transistors M801, M802, and M803, resistors R801 and R802, PMOS transistors M804, M805, and M806, NMOS transistors M807 and M808, and PMOS transistors M809 and M8010.

4. The SiC MOSFET gate drive circuit with desaturation protection function according to claim 1, characterized in that, The high-precision desaturation protection circuit (8) includes: an external interface circuit (61), a clock generation circuit (62), a voltage follower detection circuit (63), a comprehensive control logic circuit (64), a voltage detection circuit (65), an output drive circuit (66), a detection resistor Rd1, a detection resistor Rd2, and a detection capacitor Cd1. The upper end of the sensing resistor Rd2 is connected to the desaturation detection port Desat and SiC. The drain of the MOSFET, the lower end of the sensing resistor Rd1, and the lower end of the sensing capacitor Cd1 are connected to the ground potential port; the connection point between the lower end of the sensing resistor Rd2 and the upper end of the sensing resistor Rd1 and the upper end of the sensing capacitor Cd1 generates a desaturation input signal Vdes, which is connected to the detection voltage input terminal of the voltage detection circuit (65); the voltage detection circuit (65) is used to detect the desaturation input signal Vdes generated by the voltage divider and filter of the Desat signal through the sensing resistor Rd1, the sensing resistor Rd2, and the sensing capacitor Cd1, and outputs a desaturation sampling signal Vdesin under the control of the desaturation control clock Ckdes, which is connected to the voltage follower detection circuit (63); the voltage follower detection circuit (63) outputs a desaturation quantization signal Ddes based on the desaturation sampling signal Vdesin under the control of the sampling control clock Ckcs, the follower control clock Ckcom, and the desaturation control clock Ckdes, which is connected to the integrated control logic circuit (64); the clock generation circuit (62) generates the reference clock OSC, the sampling control clock Ckcs, and the follower control clock Ckcom. The external interface circuit (61) receives the signal Dout and converts it into the input drive signal Din2, which is output to the integrated control logic circuit (64). On the other hand, it buffers the error signal Error from the integrated control logic circuit (64) and outputs the error signal Flt_out. The integrated control logic circuit (64) generates the power switch drive signal Dout2, the error signal Error, the control signal Ctrl, and the control signal Ctrl1 according to the state of the input drive signal Din2, the reference clock OSC, and the desaturation quantization signal Ddes. The power switch drive signal Dout2 is connected to the output drive circuit (66), the control signal Ctrl is connected to the external interface circuit (61) and the output drive circuit (66), the control signal Ctrl1 is connected to the voltage follower detection circuit (63) and the voltage detection circuit (65), and the error signal Error is connected to the external interface circuit (61). The output drive circuit (66) generates the gate drive signal GO of the SiC MOSFET according to the power switch drive signal Dout2.

5. The SiC MOSFET gate drive circuit with desaturation protection function according to claim 4, characterized in that, When the high-precision desaturation protection circuit (8) starts working normally, the clock generation circuit (62) first generates a set of default initial reference clock OSC, sampling control clock Ckcs, follower control clock Ckcom, and desaturation control clock Ckdes; then the integrated control logic circuit (64) first outputs the control signal Ctrl, turns on the external interface circuit (61) and the output drive circuit (66), the external interface circuit (61) starts to receive the signal Dout and converts it into the input drive signal Din2, and then the integrated control logic circuit (64) generates the power switch drive signal according to the state of the input drive signal Din2, the reference clock OSC, and the desaturation quantization signal Ddes. The output drive circuit (66) generates a gate drive signal GO based on the power switch drive signal Dout2; the integrated control logic circuit (64) outputs a control signal Ctrl1 to turn on the voltage follower detection circuit (63) and the voltage detection circuit (65). The voltage detection circuit (65) starts to detect the desaturation input signal Vdes and outputs a desaturation sampling signal Vdesin under the control of the desaturation control clock Ckdes. The voltage follower detection circuit (63) generates a desaturation quantization signal Ddes based on the desaturation sampling signal Vdesin. The integrated control logic circuit (64) judges the state of the voltage signal Desat and the SiC MOSFET based on the state of the quantization signal Ddes, and changes the state of the control signal Ctrl in case of an abnormality, and outputs an error signal Error to the external interface circuit (61). Finally, the external interface circuit (61) outputs an error signal Flt_out to the second modulation transmission circuit (9).

6. The SiC MOSFET gate drive circuit with desaturation protection function according to claim 4, characterized in that, The voltage detection circuit (65) includes a sampling switch (70) and a voltage integrator (71). The sampling switch (70) samples the desaturation input signal Vdes under the control of the desaturation control clock Ckdes and outputs a sample-and-hold signal to the voltage integrator (71). The voltage integrator (71) integrates the sample-and-hold signal based on the reference voltage Vref to obtain the desaturation sampling signal Vdesin.

7. The SiC MOSFET gate drive circuit with desaturation protection function according to claim 4, characterized in that, The voltage follower detection circuit (63) includes: a high-performance sampling switch (90), a hold circuit (91), and a high-precision comparator (93); the desaturation sampling signal Vdesin is connected to the analog signal input terminal of the high-performance sampling switch (90), and the clock control terminal of the high-performance sampling switch (90) is connected to the sampling control clock Ckcs; the first analog signal output terminal of the high-performance sampling switch (90) is connected to the positive input terminal of the high-precision comparator (93), and the connection is controlled by the follower control clock Ckcom; the second analog signal output terminal of the high-performance sampling switch (90) is connected to the signal input terminal of the hold circuit (91), and the connection is controlled by the desaturation control clock Ckdes; the analog signal output terminal of the hold circuit (91) is connected to the negative input terminal of the high-precision comparator (93), and the connection is controlled by the follower control clock Ckcom; the data of the quantization output terminal of the high-precision comparator (93) is the desaturation quantization signal Ddes, which is output to the integrated control logic circuit (64); The voltage follower detection circuit (63) operates as follows: In the Ckcs phase, the high-performance sampling switch (90) samples the desaturated sampling signal Vdesin. Assuming that this is the Mth sampling, the switch samples the voltage V. des (M); Ckcom phase, voltage V obtained from high-performance sampling switch (90) des (M) and the voltage V held by the holding circuit (91) in the previous clock cycle. des (M-1) enters the high-precision comparator (93), the high-precision comparator (93) compares the voltage V des (M) and V des (M-1) is compared, and the output quantized data Ddes(M) is generated. Ddes(M) represents the desaturated quantized signal Ddes generated at the Mth sampling. A Ddes(M) value of 1 indicates that the Vdesin voltage is increasing, and a Ddes(M) value of 0 indicates the opposite; Ckdes phase, V des (M) enters the holding circuit (91) for holding; where M is a natural number greater than 1, and the sampling control clock Ckcs, the follow control clock Ckcom and the desaturation control clock Ckdes are 3-phase non-overlapping clocks.

8. The SiC MOSFET gate drive circuit with desaturation protection function according to claim 4, characterized in that, The integrated control logic circuit (64) includes: a counter (100), a control logic circuit (101), a reference data output circuit (102), an input serial register (103), a serial-to-parallel conversion circuit (104), a first buffer (105), a second buffer (106), a parallel register group (107), and error decision processing logic (108); The counter (100) generates a working control clock Ck_ctrl based on an external input reference clock OSC. The working control clock Ck_ctrl is simultaneously connected to the control clock inputs of the control logic circuit (101), the input serial register (103), the serial-to-parallel conversion circuit (104), the parallel register group (107), and the error decision processing logic (108). The control logic circuit (101) generates control signals Ctrl and Ctrl1 based on the working control clock Ck_ctrl and the potential error signal Error_lat. The control signal Ctrl is connected to the control signal input of the first buffer (105), and the control signal Ctrl1 is connected to the reference data output circuit (…). 102), the input serial register (103), serial / parallel conversion circuit (104), error decision processing logic (108), and the control signal input terminals of the second buffer (106); the first buffer (105), under the control of the control signal Ctrl, buffers the input drive signal Din2 and then outputs the power switch drive signal Dout2; the reference data output circuit (102), under the control of the control signal Ctrl1, outputs N-bit reference data Dref(N), which is connected to the error decision processing logic (108), where N is a natural number greater than 1; the input serial register (103), under the control of the working control clock Ck_ctrl and the control signal Ctrl1, sequentially outputs data in chronological order. The serial-to-parallel conversion circuit (104) receives the desaturation quantization signal Ddes and outputs it to the serial-to-parallel conversion circuit (104) in a first-in-first-out order. Under the control of the working control clock Ck_ctrl and the control signal Ctrl1, the serial-input desaturation quantization signal Ddes is converted into an N-bit desaturation status code Ds(N) output in parallel and connected to the parallel register group (107). Under the control of the working control clock Ck_ctrl, the parallel register group (107) converts the N-bit desaturation status code Ds(N) output in chronological order into K sets of parallel output N-bit desaturation status codes Ds(N)1~Ds(N)K and connects them to the error decision processing logic (108). K is a natural number greater than 2. The error decision processing logic (108) performs comprehensive decision processing on the K groups of parallel output N-bit desaturation status codes Ds(N)1~Ds(N)K and N-bit reference data Dref(N) under the control of the working control clock Ck_ctrl and the control signal Ctrl1 to obtain the pre-output error signal Error_pre and the potential error signal Error_lat. The pre-output error signal Error_pre is connected to the second buffer (106), and the potential error signal Error_lat is connected to the control logic circuit (101). Under the control of the control signal Ctrl1, the second buffer (106) buffers the pre-output error signal Error_pre and drives the output error signal Error.The potential error signal Error_lat is output to the control logic circuit (101) and ultimately adjusts the state of the control signal Ctrl; After the chip is powered on, the counter (100) starts working first. After the counter (100) is working normally, it outputs the working control clock Ck_ctrl according to the OSC signal, and simultaneously inputs it to the control logic circuit (101), the input serial register (103), the serial / parallel conversion circuit (104), the parallel register group (107), and the error judgment processing logic (108). Then, the control logic circuit (101) generates the control signal Ctrl according to the working control clock Ck_ctrl and turns on the first buffer (105). The first buffer (105) generates the power switch drive signal Dout2 according to the input drive signal Din2. After a period of delay, the control logic circuit (101) will generate the control signal Ctrl1 and turn on the reference data output circuit (102), the input serial register (103), the serial / parallel conversion circuit (104), the error judgment processing logic (108), and the second buffer (106). Then, the reference data output circuit (102) generates N bits of reference data Dref(N), which are input to the serial register (103) in chronological order. The serial input desaturation quantization signal Ddes is received sequentially and output to the serial-to-parallel conversion circuit (104) in a first-in-first-out order. The serial-to-parallel conversion circuit (104) converts the serial input desaturation quantization signal Ddes into a parallel output N-bit desaturation status code Ds(N). The parallel register group (107) converts the N-bit desaturation status code Ds(N) output in chronological order into K sets of parallel output N-bit desaturation status codes Ds(N)1~Ds(N)K. The error decision processing logic (108) performs comprehensive decision processing on the K sets of parallel output N-bit desaturation status codes Ds(N)1~Ds(N)K and N-bit reference data Dref(N) to obtain the pre-output error signal Error_pre and the potential error signal Error_lat. The control logic circuit (101) adjusts the state of the control signal Ctrl in real time according to the state of the potential error signal Error_lat, thereby controlling the operation of the external interface circuit (1) and changing the characteristics of the input drive signal Din2, and finally changing the characteristics of the power switch drive signal Dout2 and the gate drive signal GO.

9. The SiC MOSFET gate drive circuit with desaturation protection function according to claim 8, characterized in that, The error decision processing logic (108) includes: a coarse data weighting circuit (111), a fine data weighting circuit (112), K data weighting circuits, K summation data selection switches, K-1 subtractors, K-1 difference data selection switches, a first digital comparator (114), and a second digital comparator (115); The coarse data weighting circuit (111) performs weighted summation based on N-bit reference data Dref(N) to generate sum data Cot00, which is connected to the first digital comparator (114). The fine data weighting circuit (112) performs weighted summation based on N-bit reference data Dref(N) to generate sum data Cot01, which is connected to the second digital comparator (115). Cot00 > Cot01. K data weighting circuits perform weighted summation based on K groups of N-bit desaturation state codes Ds(N)1~Ds(N)K, generating K summation data respectively. These K summation data are connected to the second comparison input Cot_s of the first digital comparator (114) via K summation data selection switches, with only one switch active at any given time. The first comparison input of the first digital comparator (114) is connected to the summation data Cot00. Any two adjacent data points from the K summation data are subtracted using K-1 subtractors to obtain K-1 difference data points. The data is connected to the second comparison input Cot_sn of the second digital comparator (115) via K-1 difference data selection switches. Only one of the K-1 difference data selection switches can be turned on at any time. The first comparison input of the second digital comparator (115) is connected to the sum data Cot01. The second digital comparator (115) compares the data at the Cot_sn terminal with the sum data Cot01 to obtain the potential error signal Error_lat. The first digital comparator (114) compares the data at the Cot_s terminal with the sum data Cot00 to obtain the pre-output error signal Error_pre.

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