A multi-phase clock generation circuit
By adopting a distributed and modular clock generation method, the layout design is simplified, power consumption is reduced, and clock jitter is improved. This solves the problems of high layout design difficulty and high power consumption of traditional clock generation circuits in high-speed communication, and achieves more efficient multi-phase clock generation.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- JOYWELL SEMICON (SHANGHAI) CO LTD
- Filing Date
- 2023-02-13
- Publication Date
- 2026-06-16
AI Technical Summary
Traditional clock generation circuits require complex clock synchronization and reset modules when generating multiple phase clocks, resulting in difficult layout design, high power consumption, and severe clock jitter, making it difficult to meet the requirements of high-speed communication.
A distributed, modular clock generation method is adopted. Through a master clock generator, frequency divider and sub-clock generation module, phase shift and logic operations are performed using synchronous timing circuits and gate circuits to generate multi-phase clocks, which simplifies the layout design and reduces power consumption.
It reduces the difficulty of distributing high-speed clocks in the physical layer, reduces parasitic effects, improves clock jitter, enhances circuit matching and simplifies layout design, and reduces power consumption.
Smart Images
Figure CN116015254B_ABST
Abstract
Description
Technical Field
[0001] This invention generally relates to the field of integrated circuit technology, and in particular to a multi-phase clock generation circuit. Background Technology
[0002] With the development of communication technology, the amount of data generated per unit time is increasing, and the required communication speed is also getting faster. Therefore, high-speed analog-to-digital converters (ADCs) are becoming increasingly important. For sampling rates of 32GS / s or 64GS / s, clock-interleaved ADCs are a relatively common architecture. Clock-interleaving circuits require complex clock generation circuits to create the interleaving of multiple clock phases. Functionally, the relative order of the phases is essential for the clock generation circuit. Furthermore, low power consumption and low clock jitter are also necessary performance characteristics. However, for many traditional clock generation methods that use frequency dividers to generate multiple phases, a necessary module is the clock synchronization and reset module to ensure that the clock is synchronized from the source, without any glitches, and that the phase relationship is completely determined. (Refer to...) Figure 1 The clock generation circuit shown uses clock synchronization reset and frequency divider. Summary of the Invention
[0003] The purpose of this invention is to provide a multi-phase clock generation circuit that employs a distributed and modular clock generation method, which simplifies the layout and reduces phase error.
[0004] This application discloses a multi-phase clock generation circuit, including:
[0005] The master clock generator is used to generate the first-level source clock.
[0006] The first frequency divider is used to receive the first-stage source clock and generate the first-stage phase information;
[0007] A second frequency divider is used to receive the first-stage phase information output by the first frequency divider and output the second-stage phase information; and
[0008] Several sub-clock generation modules, each sub-clock generation module includes:
[0009] The first-level sampling clock generation unit consists of several sub-clock generation modules whose first-level sampling clock generation units are connected in sequence. The first first-level sampling clock generation unit is connected to the first frequency divider. Each first-level sampling clock generation unit receives the first-level phase information and the first-level source clock output by the previous first-level sampling clock generation unit and outputs the phase-shifted first-level phase information to the next first-level sampling clock generation unit. Each first-level sampling clock generation unit generates a first-level sampling clock and generates a second-level source clock.
[0010] Several second-level sampling clock generation units are connected in sequence. The first second-level sampling clock generation unit of the first sub-clock generation module is connected to the second frequency divider. The first second-level sampling clock generation unit of the remaining sub-clock generation modules is connected to the last second-level sampling clock generation unit of the previous sub-clock generation module. Each second-level sampling clock generation unit receives the second-level phase information and the second-level source clock output by the previous second-level sampling clock generation unit and outputs the phase-shifted second-level phase information to the next second-level sampling clock generation unit. Each second-level sampling clock generation unit generates a second-level sampling clock.
[0011] In a preferred embodiment, the first-level sampling clock generation unit includes: a first-level synchronous timing circuit, a first-level gate circuit, and a logic circuit. The first-level synchronous timing circuit receives the first-level source clock and the first-level phase information, performs phase shifting on the first-level phase information, and outputs it to the first-level gate circuit, the logic circuit, and the next first-level synchronous timing circuit. The first-level gate circuit performs logical operations on the first-level source clock and the phase-shifted first-level phase information and outputs the first-level sampling clock. The logic circuit adjusts the duty cycle of the phase-shifted first-level phase information and generates a second-level source clock.
[0012] In a preferred embodiment, the first-stage synchronization timing circuit is phase-shifted by 180° to the phase information of the first-stage phase and to the phase corresponding to the period of the first-stage source clock.
[0013] In a preferred embodiment, the first-stage gate circuit performs an AND logic operation on the first-stage source clock and the phase-shifted first-stage phase information.
[0014] In a preferred embodiment, the second-stage sampling clock generation unit includes: a second-stage synchronous timing circuit and a second-stage gate circuit. The second-stage synchronous timing circuit receives the second-stage source clock and the second-stage phase information, performs phase shifting on the second-stage phase information, and outputs it to the second-stage gate circuit and the next second-stage synchronous timing circuit. The second-stage gate circuit performs logical operations on the second-stage source clock and the phase-shifted second-stage phase information and outputs the second-stage sampling clock.
[0015] In a preferred embodiment, the second-stage gate circuit performs an AND logic operation on the first-stage source clock and the phase-shifted first-stage phase information.
[0016] Compared with the prior art, the multi-phase clock generation circuit of the present invention has the following advantages:
[0017] This invention avoids distributing too many high-speed clocks in the physical layer, reducing the difficulty of parasitic and layout design. It also reduces power consumption and improves jitter. Furthermore, modular physical blocks improve matching and layout.
[0018] This specification contains numerous technical features distributed across various technical solutions. Listing all possible combinations of these features (i.e., technical solutions) would make the specification excessively lengthy. To avoid this problem, the various technical features disclosed in the above-described invention, the various embodiments and examples below, and the various technical features disclosed in the accompanying drawings can be freely combined to form various new technical solutions (all of which should be considered as described in this specification), unless such a combination of technical features is technically infeasible. For example, one example discloses feature A+B+C, and another example discloses feature A+B+D+E. Features C and D are equivalent technical means that serve the same function, and technically only one needs to be used; they cannot be used simultaneously. Feature E can technically be combined with feature C. Therefore, the solution A+B+C+D should not be considered as described because it is technically infeasible, while the solution A+B+C+E should be considered as described. Attached Figure Description
[0019] Non-limiting and non-exhaustive embodiments of this application are described with reference to the following figures, wherein, unless otherwise stated, the same reference numerals refer to the same parts in the various figures.
[0020] Figure 1 A schematic diagram of a multi-phase clock generation circuit in one embodiment of this application is shown.
[0021] Figure 2 A schematic diagram of a sub-clock generation module in one embodiment of this application is shown.
[0022] Figure 3 A schematic diagram of a sub-clock generation module is shown in another embodiment of this application.
[0023] Explanation of reference numerals in the attached figures:
[0024] 101 - Master Clock Generator;
[0025] 102 - First frequency divider;
[0026] 103 - Second frequency divider;
[0027] 103 - First latch circuit;
[0028] 104.1~104.N - Several sub-clock generation modules;
[0029] 105,201 - First-stage sampling clock generation unit;
[0030] 106.1~106.M, 202.1~202.M - Several second-level sampling clock generation units;
[0031] 203 - First-stage synchronous timing circuit;
[0032] 204 - First-level gate circuit;
[0033] 205 - Logic Circuit;
[0034] 206 - Second-stage synchronous timing circuit;
[0035] 207 - Second-stage gate circuit. Detailed Implementation
[0036] In the following description, many technical details are presented to help the reader better understand this application. However, those skilled in the art will understand that the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments.
[0037] Explanation of some terms:
[0038] A frequency divider is an electronic circuit that makes the output signal frequency an integer part of the input signal frequency. For any Nth-order frequency divider, with the input signal unchanged, the output signal can have a phase of 2π / N. This phenomenon is inherent to the frequency division operation and is independent of the specific circuit of the frequency divider; it is called the multi-valued output phase of the frequency divider.
[0039] Logic circuits are circuits that transmit and process discrete signals, using binary principles to implement logical operations and manipulations of digital signals.
[0040] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.
[0041] This application discloses a multi-phase clock generation circuit. Figure 1 A schematic diagram of a multi-phase clock generation circuit in one embodiment is shown. The multi-phase clock generation circuit includes a master clock generator 101, a first frequency divider 102, a second frequency divider 103, and several sub-clock generation modules 104.1 to 104.N. The master clock generator 101 is used to generate a first-stage source clock (1... st The first frequency divider 102 is used to receive the first-stage source clock and generate the first-stage phase information (1). stPhase info). The second frequency divider 103 is used to receive the first-level phase information output by the first frequency divider 102 and output the second-level phase information (2). nd Phase info).
[0042] Each sub-clock generation module 104.1 to 104.N includes a first-level sampling clock generation unit 105 and several second-level sampling clock generation units 106.1 to 106.M, for example, M = 4 in this embodiment. It should be understood that the number of second-level sampling clock generation units 106 can depend on the overall structure of the ADC. The first-level sampling clock generation units 105.1 to 105.N of the several sub-clock generation modules 104.1 to 104.N are connected in sequence. The first first-level sampling clock generation unit 105.1 is connected to the first frequency divider 102. Each first-level sampling clock generation unit 105 receives the first-level phase information and the first-level source clock output by the previous first-level sampling clock generation unit 105 and outputs the phase-shifted first-level sampling clock to the next first-level sampling clock generation unit 105. Each first-level sampling clock generation unit 105.1 to 105.N generates a first-level sampling clock (1 st sampling clock), and generate a second-level source clock (2 nd A number of second-level sampling clock generation units 106.1 to 106.M are connected in sequence. The first second-level sampling clock generation unit 106.1 of the first sub-clock generation module 104.1 is connected to the second frequency divider 103. The first second-level sampling clock generation unit 106.1 of the remaining sub-clock generation modules 104.2 to 104.N is connected to the last second-level sampling clock generation unit 106.M of the previous sub-clock generation module. Each second-level sampling clock generation unit 106 receives the second-level phase information and the second-level source clock output from the previous second-level sampling clock generation unit and outputs the phase-shifted second-level phase information to the next second-level sampling clock generation unit. Each second-level sampling clock generation unit 106.1 to 106.M generates a second-level sampling clock (2). nd (sampling clock).
[0043] In one embodiment, the division ratio of the first frequency divider 102 depends on the first-stage sampling clock generation unit 105 and the first-stage source clock 1. st The frequency relationship of the sampling source clock. For example, if the first-stage sampling clock generation unit 105 has 32 units, then the first-stage sampling clock 1... st The sampling clock period is 32T, and the first-stage source clock is 1.st The sampling source clock has a period of 8T, which depends on the design of the master clock. Therefore, the first frequency divider 102 is a quarter frequency divider.
[0044] In one embodiment, the division ratio of the second frequency divider 103 depends on the second-stage sampling clock generation unit 106 and the first-stage sampling clock 1. st The frequency relationship of the sampling clock. For example, if the first-stage sampling clock generation unit 105 has 32 units and the second-stage sampling clock generation unit 106 has 128 units, then the first-stage sampling clock 1... st The sampling clock period is 32T, and the second-stage sampling clock is 2. nd The sampling clock period is 128T, so the second frequency divider 103 is a quarter frequency divider.
[0045] Figure 2 A schematic diagram of a sub-clock generation module in one embodiment is shown, which can be an example of sub-clock generation modules 104.1 to 104.N. The sub-clock generation module includes a first-level sampling clock generation unit 201 and several second-level sampling clock generation units 202.1 to 202.M. The first-level sampling clock generation unit 201 includes a first-level synchronization timing circuit 203, a first-level gate circuit 204, and a logic circuit 205. The first-level synchronization timing circuit 203 receives the first-level source clock and the first-level phase information, performs a phase shift on the first-level phase information, and outputs it to the first-level gate circuit 204, the logic circuit 205, and the next first-level synchronization timing circuit. The first-level gate circuit 204 performs logical operations on the first-level source clock and the phase-shifted first-level phase information and outputs the first-level sampling clock. The logic circuit 205 adjusts the duty cycle of the phase-shifted first-level phase information and generates the second-level source clock. In one embodiment, the first-level synchronization timing circuit 203 shifts the phase of the first-level phase information by 180° and the phase corresponding to the period of the first-level source clock. In one embodiment, the first-stage gate circuit 204 performs an AND logic operation on the first-stage source clock and the phase-shifted first-stage phase information.
[0046] Continue to refer to Figure 2As shown, the second-stage sampling clock generation units 202.1 to 202.M include: a second-stage synchronization timing circuit 206 and a second-stage gate circuit 207. The second-stage synchronization timing circuit 206 receives the second-stage source clock and the second-stage phase information, performs a phase shift on the second-stage phase information, and outputs it to the second-stage gate circuit 207 and the next second-stage synchronization timing circuit. The second-stage gate circuit 207 performs logical operations on the second-stage source clock and the phase-shifted second-stage phase information and outputs the second-stage sampling clock. In one embodiment, the second-stage gate circuit 207 performs an AND logical operation on the first-stage source clock and the phase-shifted first-stage phase information.
[0047] Figure 3 A schematic diagram of a sub-clock generation module in another embodiment is shown, which may be an example of sub-clock generation modules 104.1 to 104.N. The sub-clock generation module includes a first-level sampling clock generation unit 301 and several second-level sampling clock generation units 302.1 to 302.M. Figure 3 The illustrated embodiments and Figure 2 The difference in the embodiments is that the first-stage sampling clock generation unit 301 may not include Figure 2 The first-stage gate circuit 204 shown can be included in the first-stage synchronous timing circuit 203.
[0048] To better understand the technical solution in this specification, a specific example is provided below. The details listed in this example are mainly for ease of understanding and are not intended to limit the scope of protection of this application.
[0049] Clock design has become a major challenge for ultra-high-speed ADCs. Almost every ultra-high-speed ADC uses time-interleaving structures and hierarchical sampling schemes to alleviate the difficulties of data path design. Hierarchical sampling schemes require complex multi-stage, multi-phase clocks and complex physical clock distribution. Traditionally, all these multi-stage, multi-phase clocks are generated in a centralized location and then distributed together to each sub-ADC (sub-ADC).
[0050] This patent discloses a novel method for a distributed clock generation scheme. Figure 1 The overall structure of this patent is shown. We use a simple master clock generator to send a high-speed clock to each sub-ADC and process all the necessary multiphase clocks within the SUBADC. The master clock generator transmits the phase information to a first-stage divider, and the first-stage divider passes the phase information to a second-stage divider. The outputs of these two dividers send the first-stage and second-stage phase information to the sub-ADCs, generating the required sampling clock within each sub-ADC.
[0051] Using this new architecture, we can gain the following benefits: First, we can avoid distributing too many high-speed clocks in the physical layer, which will reduce the difficulty of parasitic and layout design. As a result, power consumption will be reduced and jitter improved. Second, modular physical blocks improve matching and layout. Furthermore, as long as the timing of the first-stage synchronization circuit is met, the timing of subsequent stages is replicated, making it easier to meet the timing requirements of the circuit. Last but not least, it has the potential to expand the application of future ADCs at higher speeds.
[0052] Figure 2 and Figure 3 A simplified diagram of local clock generation in a SUBADC is shown. The first-level sampling clock generation receives the high-speed first-level sampling source clock and first-level phase information from the top layer. We retime the phase information and synchronize it to the current SUBADC phase. We connect this retimed clock to the first-level sampling switch and specific logic to generate the second-level sampling source clock. Furthermore, this clock is sent to the next first-level sampling clock generation module and used as the phase information input. One difference here is that the transmitted phase is shifted by 180 degrees, so that the next sampling phase will be far from the current phase. As a result, it avoids interaction between two adjacent samples, as the sampling phases are separated by this phase shift. The second-level sampling source clock is then sent to the second-level sampling clock generation module. The number of second-level sampling clock generation modules is determined by the overall ADC architecture. Within the second-level sampling clock generation module, we use a similar strategy to the first-level sampling clock generation module. The second-level sampling source clock is used to retime the second-level phase information and send it to the next second-level sampling clock generation module. The retimed clock is also further processed to generate the second-level sampling clock. Figure 2 and Figure 3 The difference lies in whether we further process the retiming first-level phase information before sending it to the first-level sampling switch, based on the first-level sampling source clock and the first-level phase information frequency.
[0053] It should be noted that in this patent application, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one" does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. In this patent application, if it refers to performing an action according to an element, it means performing the action at least according to that element, including two cases: performing the action only according to that element, and performing the action according to that element and other elements. Expressions such as "multiple," "repeatedly," and "various" include two, two times, two kinds, and more than two, more than two times, and more than two kinds.
[0054] All references to this specification are considered to be incorporated integrally into the disclosure of this application so that they can serve as the basis for modifications if necessary. Furthermore, it should be understood that the above descriptions are merely preferred embodiments of this specification and are not intended to limit the scope of protection of this specification. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of one or more embodiments of this specification should be included within the scope of protection of one or more embodiments of this specification.
[0055] In some cases, the actions or steps described in the claims can be performed in a different order than that shown in the embodiments and still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require a specific or sequential order to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.
Claims
1. A multi-phase clock generation circuit, characterized in that, include: The master clock generator is used to generate the first-level source clock. The first frequency divider is used to receive the first-stage source clock and generate the first-stage phase information; The second frequency divider is used to receive the first-level phase information output by the first frequency divider and output the second-level phase information. as well as Several sub-clock generation modules, each sub-clock generation module includes: The first-level sampling clock generation unit consists of several sub-clock generation modules whose first-level sampling clock generation units are connected in sequence. The first first-level sampling clock generation unit is connected to the first frequency divider. Each first-level sampling clock generation unit receives the first-level phase information and the first-level source clock output by the previous first-level sampling clock generation unit and outputs the phase-shifted first-level phase information to the next first-level sampling clock generation unit. Each first-level sampling clock generation unit generates a first-level sampling clock and generates a second-level source clock. Several second-level sampling clock generation units are connected in sequence. The first second-level sampling clock generation unit of the first sub-clock generation module is connected to the second frequency divider. The first second-level sampling clock generation unit of the remaining sub-clock generation modules is connected to the last second-level sampling clock generation unit of the previous sub-clock generation module. Each second-level sampling clock generation unit receives the second-level phase information and the second-level source clock output by the previous second-level sampling clock generation unit and outputs the phase-shifted second-level phase information to the next second-level sampling clock generation unit. Each second-level sampling clock generation unit generates a second-level sampling clock.
2. The multi-phase clock generation circuit according to claim 1, characterized in that, The first-level sampling clock generation unit includes: a first-level synchronous timing circuit, a first-level gate circuit, and a logic circuit. The first-level synchronous timing circuit receives the first-level source clock and the first-level phase information, performs phase shifting on the first-level phase information, and outputs it to the first-level gate circuit, the logic circuit, and the next first-level synchronous timing circuit. The first-level gate circuit performs logical operations on the first-level source clock and the phase-shifted first-level phase information and outputs the first-level sampling clock. The logic circuit adjusts the duty cycle of the phase-shifted first-level phase information and generates the second-level source clock.
3. The multi-phase clock generation circuit according to claim 2, characterized in that, The first-stage synchronous timing circuit has a phase offset of 180° for the first-stage phase information and a phase corresponding to the period of the first-stage source clock.
4. The multi-phase clock generation circuit according to claim 2, characterized in that, The first-stage gate circuit performs an AND logic operation on the first-stage source clock and the phase information of the first stage after phase shifting.
5. The multi-phase clock generation circuit according to claim 1, characterized in that, The second-level sampling clock generation unit includes a second-level synchronous timing circuit and a second-level gate circuit. The second-level synchronous timing circuit receives the second-level source clock and the second-level phase information, performs phase shifting on the second-level phase information, and outputs it to the second-level gate circuit and the next second-level synchronous timing circuit. The second-level gate circuit performs logical operations on the second-level source clock and the phase-shifted second-level phase information and outputs the second-level sampling clock.
6. The multi-phase clock generation circuit according to claim 5, characterized in that, The second-stage gate circuit performs an AND logic operation on the first-stage source clock and the phase information of the first stage after phase shifting.