An ADC digital controller

Abstract

The application discloses an ADC digital controller, which comprises an ADC control module, a task scheduling module, a single sampling conversion task module, a mapping module, a bus interface module and a data register, wherein the single sampling conversion task module is configured with the trigger, the ADC analog-digital conversion channel and the priority of each single sampling conversion task during initialization, and after receiving the trigger, the single sampling conversion task corresponding to the trigger is delivered to the task scheduling module; in the task scheduling module, the single sampling conversion tasks are sent to the ADC control module in sequence according to the priority to form a task sequence, the ADC control module controls the external connected ADC analog-digital converter to perform analog-digital conversion, and the mapping module informs the external DMA to access the mapping module through the bus to indirectly carry data. The application can realize a theoretical infinite number of sequence numbers, the sequences can be interrupted at will, and a limited number of sequences can realize the injection demand of various complex situations.

Description

Technical Field

[0001] This application belongs to the field of analog-to-digital conversion technology, and in particular relates to an ADC digital controller. Background Technology

[0002] An ADC (Analog to Digital Converter) is a converter used to convert analog signals into digital signals. An ADC digital controller is a control device that controls the ADC to perform analog-to-digital conversion and outputs the converted digital signal.

[0003] In traditional ADC digital controllers, various technical solutions exist for sequence logic, channel injection, and data storage and DMA (Direct Memory Access) transfer. For example, in terms of sequence logic, one solution assumes the ADC has n different external channels. The user selects i channels (i <= n) from these n channels, and the digital controller automatically arranges these i channels into a sequence in ascending or descending order. However, in this solution, each external channel can only appear once in the sequence, and the order of the external channels is fixed, determined by their channel numbers and cannot be changed. Another solution requires the user to first configure a sequence of length i, then select one of the n different external channels at position 1 of this sequence, configuring them sequentially until position i is completed, resulting in a sequence of length i. Although this solution allows configuring two or even four sequences, the total length of all sequences that can be configured simultaneously is usually still n times the number of external channels, and the maximum length of each sequence is fixed at (n / number of sequences), with a fixed order between multiple sequences.

[0004] For example, in channel injection, one approach is to configure the injection sequence, and then, when the injection is triggered, insert the injection sequence into the normal sequence according to the injection position. This approach has a fixed injection position, is not flexible enough, and only has one injection sequence, which cannot handle more complex multi-injection scenarios.

[0005] Regarding data storage and DMA transfer, existing technologies using multiple registers currently lack a solution for flexible DMA data transfer; they can only transfer data by simply incrementing, decrementing, or keeping the address constant. Summary of the Invention

[0006] The purpose of this application is to provide an ADC digital controller that overcomes the problems of rigidity and limited applicability in the existing technology in terms of sequence logic, injection logic, and storage logic, so as to improve the flexibility of ADC conversion.

[0007] To achieve the above objectives, the technical solution of this application is as follows:

[0008] An ADC digital controller includes: an ADC control module, a task scheduling module, a single-sampling conversion task module, a mapping module, a bus interface module, and a data register, wherein:

[0009] The bus interface module connects to an external bus, receives configuration information, and distributes it to each module to complete the initialization of each module.

[0010] Upon receiving a trigger, the single-sample conversion task module will pass the corresponding single-sample conversion task to the task scheduling module.

[0011] After receiving a single sampling conversion task, the task scheduling module forms a task sequence according to the priority of the single sampling conversion tasks, and sends the single sampling conversion tasks to the ADC control module in the order of arrangement.

[0012] After receiving a single-sample conversion task, the ADC control module parses the single-sample conversion task and controls the externally connected ADC analog-to-digital converter to perform analog-to-digital conversion and then stores the converted digital signal into a data register.

[0013] The mapping module is used to determine whether the data register's transfer flag is enabled during the initialization phase. If so, it sets the transfer flag corresponding to the data register that needs to be transferred, and when the DMA request setting of the data register is set, it notifies the external DMA to indirectly transfer data through the bus access mapping module.

[0014] Furthermore, the initialization of the single-sample conversion task module includes:

[0015] Configure the triggering, ADC analog-to-digital conversion channel, and priority of each single sampling conversion task one by one until the total number of single sampling conversion tasks that need to be configured is reached.

[0016] Furthermore, the initialization of the mapping module includes:

[0017] Configure whether the DMA-moved flag is enabled for each data register;

[0018] Configure the DMA request bit in the last data register of the data to be moved.

[0019] Furthermore, the task scheduling module is also used to inject the received single sampling conversion task into the existing task sequence according to the priority of the single sampling conversion task after receiving it.

[0020] Furthermore, the ADC digital controller also includes a hardware trigger module, which is connected to the single-sampling conversion task module, receives an external hardware trigger signal, and activates the single-sampling conversion task corresponding to the hardware trigger signal.

[0021] This application proposes an ADC digital controller where the sequence is composed of single-sampling conversion tasks. These single-sampling conversion tasks, configured on the same trigger, automatically form a sequence according to priority. Each single-sampling conversion task can independently select an external channel. This retains the advantages of existing sequence logic (external channels can be placed at any position in the sequence) while overcoming the limitations on the number of sequences and channels within a sequence. Furthermore, with software triggering, a theoretically unlimited number of sequences can be achieved. The sequences generated by this ADC digital controller only have a priority relationship, unlike other designs with strict sequential logic control. Therefore, sequences can be arbitrarily interrupted and inserted to achieve injection functionality; the unlimited number of sequences can meet injection requirements in various complex situations. For modes with multiple data registers storing data, the digital controller has a data mapping module to flexibly control which data registers are moved when cooperating with DMA data transfer. This technical solution is more flexible and efficient than existing ADC controllers on the market, and possesses hardware automation capabilities for more complex scenarios. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the ADC digital controller of this application.

[0023] Figure 2 This is the sequence logic configuration diagram for this application.

[0024] Figure 3 This is a schematic diagram of the data storage logic in this application. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0026] This application provides an ADC digital controller, such as Figure 1 As shown, it includes: an ADC control module, a task scheduling module, a single-sampling conversion task module, a mapping module, a bus interface module, and a data register, wherein:

[0027] The bus interface module connects to an external bus, receives configuration information, and sends it to each module to complete the initialization of each module.

[0028] Upon receiving a trigger, the single-sample conversion task module will pass the corresponding single-sample conversion task to the task scheduling module.

[0029] After receiving a single sampling conversion task, the task scheduling module forms a task sequence according to the priority of the single sampling conversion tasks, and sends the single sampling conversion tasks to the ADC control module in the order of arrangement.

[0030] After receiving a single sampling conversion task, the ADC control module parses the single sampling conversion task and controls the externally connected ADC analog-to-digital converter to perform analog-to-digital conversion and then stores the converted digital signal into a data register.

[0031] The mapping module is used to determine whether the data register being moved is enabled during the initialization phase. If so, it sets the data register to be moved corresponding to the data register to be moved, and when the DMA request setting of the data register is set, it notifies the external DMA to indirectly move the data through the bus access mapping module.

[0032] Specifically, the ADC digital controller of this application is used to control the ADC analog-to-digital conversion module to perform analog-to-digital conversion and provide the converted digital signal to the master device equipped with the ADC digital controller of this application. The master device has a processor and a DMA (Direct Memory Access) module. The user's software program is usually executed by the processor of the master device, while the configuration of the ADC digital controller is initiated by the processor, which accesses the ADC digital controller through the bus and performs read and write operations on the bus interface module. The bus interface module then passes the processor's configuration information to other modules to complete the configuration initialization.

[0033] The initialization descriptions of the various modules involved are as follows:

[0034] The initialization of the single-sample conversion task module mainly involves configuring each single-sample conversion task that needs to be configured within the module. For example, if the single-sample conversion task module has m configurable single-sample conversion tasks, but the user's application environment only needs to use n of them, then the initialization of the single-sample conversion task module involves configuring n single-sample conversion tasks, including:

[0035] Configure the triggering, ADC analog-to-digital conversion channel, and priority of each single sampling conversion task one by one until the total number of single sampling conversion tasks that need to be configured is reached.

[0036] like Figure 2As shown, the task sequence generation of this ADC digital controller consists of three layers: the top layer is the trigger, the middle layer is the single-sampling conversion task, and the bottom layer is the external channel (i.e., the ADC analog-to-digital conversion channel). Users need to configure the correspondence between each layer to generate a complete task sequence.

[0037] In an ADC digital controller, there are n single-sampling conversion tasks that need to be configured. One of these tasks, designated as 'i', is selected. Then, its underlying information (one of multiple external channels) is configured for task i. Finally, its top-level information (one of multiple triggers) is configured for task i. In this embodiment, the sequence number of the single-sampling conversion task is used as the priority. During configuration, the external channel with the smallest sequence number is assigned to the task with the highest priority. After configuring all n single-sampling conversion tasks, all single-sampling conversion tasks corresponding to a single trigger can be obtained. These tasks can then be arranged into a task sequence according to their priority.

[0038] For example, Figure 2 In the sequence, the single-sample conversion tasks corresponding to trigger 1 include single-sample conversion tasks 3, 4, 5, 6, and 7. If the sequence number of a single-sample conversion task corresponds to its priority, then the task sequence is single-sample conversion tasks 3, 4, 5, 6, and 7, with smaller sequence numbers indicating higher priority. Each single-sample conversion task has its corresponding external channel; for example, the external channel for single-sample conversion task 3 is external channel 3. These details will not be elaborated here.

[0039] Similarly, the single-sample conversion task corresponding to trigger 3 includes single-sample conversion tasks 1 and 2, forming a task sequence.

[0040] It should be noted that the sequence in the prior art is a queue of one or more external channels arranged in a certain order. When the ADC starts working, it samples and converts the voltage values ​​on the external channels in the order of the sequence. However, this application introduces a single sampling conversion task as an intermediate layer, corresponding to different external channels or triggers, thereby generating multiple task sequences corresponding to different triggers. This allows for the selection and execution of multiple task sequences based on the trigger.

[0041] It can be seen that this multi-sequence logic, composed of multiple single-sample transformation tasks, not only retains the advantages of existing schemes but also has unique advantages: the upper limit of the sequence is determined by the number of triggers, which can be flexibly configured according to requirements during hardware implementation. If combined with software triggers, theoretically an unlimited number of software sequences can be implemented. The single-sample transformation tasks available for all sequences are also flexibly configured according to requirements during hardware implementation. Furthermore, the number of single-sample transformation tasks within each sequence (i.e., the sequence length) has no other additional limitations and can be flexibly allocated.

[0042] In addition, during the initialization phase, the ADC control module is configured, including the power-on process for the ADC analog-to-digital conversion module, the working time of each stage during operation can also be adjusted, and some other information for controlling the status of the ADC analog-to-digital conversion module. This is a relatively mature technology in this field, and will not be elaborated here.

[0043] The initialization of the mapping module mainly involves configuring the flag bits of each data register, including: enabling or disabling the DMA transfer flag bit of each data register; and configuring the DMA request bit bit of the last data register in the data to be transferred.

[0044] In one specific embodiment, the ADC digital controller of this application further includes a hardware trigger module, which is connected to the single-sampling conversion task module, receives an external hardware trigger signal, and activates the single-sampling conversion task corresponding to the hardware trigger signal.

[0045] It should be noted that, in addition to hardware triggering, software triggering is also possible. Hardware triggering is initiated by other hardware components, processed by the hardware triggering module, and then fed into the single-sample conversion task module. Software triggering is initiated by the processor and delivered to the single-sample conversion task module via the bus and bus interface module. That is, the triggering corresponding to the single-sample conversion task in this application can originate from the processor's software triggering or from the hardware triggering module's hardware triggering. This application is not limited to any specific triggering method. Regardless of the triggering method, upon receiving the trigger, the single-sample conversion task corresponding to the trigger signal is activated and sent to the task scheduling module.

[0046] Upon receiving a trigger, the single-sample transformation task module adds all single-sample transformation tasks configured for that trigger to the task scheduler module. The task scheduler module then processes all added single-sample transformation tasks sequentially according to their priority, forming a task sequence.

[0047] Specifically, after receiving tasks, the task scheduling module processes them sequentially according to priority. When N tasks are received in a single trigger, they are arranged into a sequence according to priority. If a new task arrives during the processing of this sequence, an injection function is implemented, and the tasks are reordered according to priority. Finally, the task scheduling module assigns the highest priority task to the ADC control module for execution, deletes the highest priority task, and reorders the remaining tasks. After receiving a task, the ADC control module parses the task's details and controls the ADC analog-to-digital conversion module to begin operation. After completing one task, it notifies the task scheduling module to send the next task; otherwise, it remains idle. Each time the ADC analog-to-digital conversion module completes a sampling conversion, it generates a voltage value, which is stored in the corresponding data register.

[0048] In typical applications, to improve the efficiency of processor program execution, the data generated by the ADC is processed by the DMA. The ADC digital controller communicates with the DMA through separate request and response lines, and then the DMA completes the data transfer processing through the bus, that is, the DMA directly moves the data in the data register.

[0049] This application proposes a mapping module to indirectly move data within data registers. During mapping module initialization, the user configures the DMA move flag for each data register via the bus, and then configures the DMA request set bit for the last data register among the data to be moved. This configuration information is initiated by the processor during program execution and stored in the bus interface module after passing through the bus. The mapping module can directly obtain this configuration information from the bus interface module during operation.

[0050] It's important to note that the DMA transfer flag for each data register needs to be enabled or disabled. If enabled, it can be set to 1 later; otherwise, it cannot be set. The DMA request flag for the last data register in the data to be transferred should be set to 1, indicating that this is the last data register in the data to be transferred.

[0051] The ADC digital controller completes the initialization process and waits for a trigger to begin operation. The hardware trigger module receives the hardware trigger and activates N single-sample conversion tasks. These tasks are then passed to the task scheduling module to form a task sequence, which is distributed to the ADC control module to begin operation. After completing a single-sample conversion task, the ADC analog-to-digital conversion module generates the corresponding external channel voltage value and places this data into the data register of the corresponding single-sample conversion task. At this point, the mapping module makes a determination based on whether the DMA-transferred flag enable bit of the data register was enabled during the initialization phase. If enabled, it indicates that the data register contains data that needs to be transferred by DMA. The DMA-transferred flag bit corresponding to this data register is then set, for example, to 1, indicating that the data in this data register needs to be transferred.

[0052] The mapping module also initiates a data transfer request to the DMA via the DMA request and acknowledge lines, notifying the DMA that it can indirectly transfer data through the bus access mapping module. Upon receiving the request, the DMA will perform a read access to the mapping module to transfer the data. At this time, the mapping module will place the data from all the data registers with the transfer flags set into the mapping module and the bus interface in order of priority, awaiting DMA read access.

[0053] The specific operation is as follows: Figure 3 As shown, the ADC digital controller of this application starts working after waiting for a hardware trigger or a user software trigger. The ADC analog-to-digital conversion module completes the single sampling conversion task i and generates data i, which is then stored in the corresponding data register i.

[0054] The mapping module then begins to determine whether the data register i is being moved flag is enabled. If it is enabled, it proceeds to the next step; otherwise, it returns to continue completing other single-sample conversion tasks in the task sequence.

[0055] When the data register i's move flag is enabled, the mapping module sets the move flag of data register i, and then checks whether the DMA request bit of data register i is set. If it is set, it indicates that the task sequence is complete and this is the last data; otherwise, it returns to continue completing other single-sample conversion tasks in the task sequence. When the DMA request bit of the data register is set, this is the last data register, and the mapping module sends a request to the DMA module, notifying the DMA to indirectly move data through the bus access to the mapping module. The DMA module responds by reading the data from the mapping module. The mapping module iterates through all data registers, placing the data of all data registers i with the move flag set in priority order onto the mapping module and the bus interface, awaiting DMA read access. After the data is read, the move flag bit of the corresponding data register is cleared.

[0056] This application makes data transfer more flexible by individually marking each data register, allowing only data relevant to the current task sequence to be transferred. Using a data mapping module in conjunction with DMA allows for the specification of any data to be transferred, without restrictions such as address contiguousness.

[0057] In another specific embodiment, the task scheduling module is further configured to, upon receiving a single sampling conversion task, inject the received single sampling conversion task into the existing task sequence according to the priority of the single sampling conversion task.

[0058] Specifically, the single-sample transformation task module can be configured with multiple sequences, and the single-sample transformation tasks within each sequence are fixed. When a single-sample transformation task of a certain sequence is working within the task scheduler module, the injection sequence is triggered, thus forming an injection. The injection logic is formed by each single-sample transformation task itself based on its priority.

[0059] For example, the following three situations:

[0060] 1. The injection sequence has high real-time requirements and needs to be processed immediately. Therefore, the single sampling transformation task within the injection sequence should have a higher priority than that within the normal sequence. When an injection occurs, the task scheduler can switch to the injection sequence in a timely manner, regardless of the current state of the normal sequence.

[0061] 2. If the injection sequence needs to be sampled and transformed only after sampling is completed at a specific point, then the highest priority of the single sampling and transformation task in the injection sequence should be placed after the priority of that specific point to achieve injection arrangement at that specific point.

[0062] 3. Ordinary sequences have high real-time requirements and need to be processed periodically. Therefore, the single-sample transformation tasks within the injected sequence should use a lower priority than those within the ordinary sequence. When an injection occurs, regardless of the current state of the ordinary sequence, the task scheduler will process all the single-sample transformation tasks within the ordinary sequence before processing the injected sequence.

[0063] In other words, using a task scheduler module to allocate work allows for work allocation to be performed solely at the task level, bypassing the sequence hierarchy. Since work allocation occurs at the task level, this application's technical solution does not limit the number of sequences at the sequence hierarchy; it also does not limit the nature of the sequences at the sequence hierarchy, meaning each sequence can be a regular sequence or an injected sequence. Because work allocation occurs at the task level, each injection action is influenced by fixed task priorities and trigger order, allowing for flexible handling of non-periodic or sporadic injection scenarios in addition to periodic injection.

[0064] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. An ADC digital controller, characterized in that, The ADC digital controller includes: an ADC control module, a task scheduling module, a single-sampling conversion task module, a mapping module, a bus interface module, and a data register, wherein: The bus interface module connects to an external bus, receives configuration information, and sends it to each module to complete the initialization of each module. Upon receiving a trigger, the single-sample conversion task module will pass the corresponding single-sample conversion task to the task scheduling module. After receiving a single sampling conversion task, the task scheduling module forms a task sequence according to the priority of the single sampling conversion tasks, and sends the single sampling conversion tasks to the ADC control module in the order of arrangement. After receiving a single-sample conversion task, the ADC control module parses the single-sample conversion task and controls the externally connected ADC analog-to-digital converter to perform analog-to-digital conversion and then stores the converted digital signal into a data register. The mapping module is used to determine whether the data register's transfer flag is enabled during the initialization phase. If so, it sets the transfer flag corresponding to the data register that needs to be transferred, and when the DMA request setting of the data register is set, it notifies the external DMA to indirectly transfer data through the bus access mapping module.

2. The ADC digital controller according to claim 1, characterized in that, The initialization of the single-sample conversion task module includes: Configure the triggering, ADC analog-to-digital conversion channel, and priority of each single sampling conversion task one by one until the total number of single sampling conversion tasks that need to be configured is reached.

3. The ADC digital controller according to claim 1, characterized in that, The initialization of the mapping module includes: Configure whether the DMA-moved flag is enabled for each data register; Configure the DMA request bit in the last data register of the data to be moved.

4. The ADC digital controller according to claim 1, characterized in that, The task scheduling module is also used to inject the received single sampling conversion task into the existing task sequence according to the priority of the single sampling conversion task after receiving it.

5. The ADC digital controller according to claim 1, characterized in that, The ADC digital controller also includes a hardware trigger module, which is connected to the single-sampling conversion task module, receives an external hardware trigger signal, and activates the single-sampling conversion task corresponding to the hardware trigger signal.

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