An analog output module

Abstract

This application discloses an analog output module applied in the field of analog output. The single-channel DAC of this application is connected to the input interface of a MUX, and the multiple output interfaces of the MUX are respectively connected to multiple sample-and-hold units. In practical applications, because the single-channel DAC of this solution only has one output, after the MUX outputs the first channel, there is no source to maintain the stable output voltage of the first channel when switching to the second channel. Even with compensation, the accuracy may not meet requirements. Therefore, this application uses sample-and-hold units to provide a stable output voltage. Multiple sample-and-hold units are connected one-to-one with multiple V&I circuits. This application uses a single-channel DAC to achieve multi-channel AO output. Compared to parallel output of multiple DACs, the single-channel DAC time-division output + sample-and-hold design results in a lower module cost.

Description

Technical Field

[0001] This application relates to the field of analog output, and in particular to an analog output module. Background Technology

[0002] Currently, most analog output modules (AO modules) used in industry to control regulating valves are 4-20mA current-type output modules, which are implemented using a digital to analog converter (DAC) + voltage-to-current (V&I) circuit. For multi-channel output modules, multiple DACs + multiple V&I circuits are used. Figure 1 This is a block diagram of a current-output type analog output module; such as... Figure 1 As shown, the microcontroller unit (MCU) configures the registers inside the multi-channel DAC through the digital interface between the MCU and the multi-channel DAC, so as to provide different voltage values ​​to different output channels of the multi-channel DAC as needed. The V&I circuit completes the voltage to current conversion, thereby realizing the control of the opening of the regulating valve.

[0003] However, the DAC uses multiple parallel voltage outputs, which results in high module costs.

[0004] Therefore, how to reduce the cost of analog output circuits is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] The purpose of this application is to provide an analog output module to reduce the cost of analog output circuits.

[0006] To address the aforementioned technical problems, this application provides an analog output module, comprising: a single-channel DAC, a sample-and-hold circuit, and multiple V&I circuits; wherein the sample-and-hold circuit includes a MUX and multiple sample-and-hold units;

[0007] The single-channel DAC is connected to the input interface of the MUX, and the multiple output interfaces of the MUX are respectively connected to multiple sample-and-hold units;

[0008] Each of the sample-and-hold units is connected to one of the V&I circuits; the sample-and-hold units are used to provide a stable output voltage.

[0009] Preferably, the sample-and-hold unit includes a holding circuit and a buffer circuit;

[0010] The holding circuit is used to provide a stable output voltage, and the buffer circuit is used to provide buffering for the holding circuit.

[0011] Preferably, the holding circuit includes: a first resistor and a holding capacitor;

[0012] The first end of the first resistor is connected to one of the output interfaces of the MUX, the second end of the first resistor is connected to the first end of the holding capacitor, and the second end of the holding capacitor is grounded.

[0013] The second end of the first resistor and the first end of the holding capacitor are also connected to the buffer circuit.

[0014] Preferably, the buffer circuit includes: an input resistor, an operational amplifier, a feedback capacitor, and a feedback resistor;

[0015] The first end of the input resistor is connected to the second end of the first resistor and the first end of the holding capacitor;

[0016] The second terminal of the input resistor is connected to the positive terminal of the input terminal of the operational amplifier, and the negative terminal of the input terminal of the operational amplifier is connected to the first terminal of the feedback capacitor and the first terminal of the feedback resistor.

[0017] The second end of the feedback capacitor and the second end of the feedback resistor are connected to the output terminal of the operational amplifier, and the output terminal of the operational amplifier is connected to the corresponding V&I circuit.

[0018] Preferably, the buffer circuit further includes a filter;

[0019] The output of the operational amplifier is connected to the corresponding V&I circuit through the filter.

[0020] Preferably, the filter includes a filter resistor and a filter capacitor;

[0021] The output terminal of the operational amplifier is connected to the first terminal of the filter resistor, the second terminal of the filter resistor is connected to the first terminal of the filter capacitor, and the second terminal of the filter capacitor is grounded.

[0022] The second end of the filter resistor and the first end of the filter capacitor are connected to the corresponding V&I circuit.

[0023] Preferably, the offset of the operational amplifier is less than a first preset value.

[0024] Preferably, the single-channel DAC, the sample-and-hold circuit, and the V&I circuit share the same power supply.

[0025] Preferably, the single-channel DAC cyclically controls multiple output interfaces of the MUX in a preset order.

[0026] Preferably, the MUX further includes a backup output interface; if the normal output interface of the MUX fails, it switches to the backup output interface.

[0027] This application provides an analog output module that reduces the cost of analog output modules. The analog output module includes a single-channel DAC, a sample-and-hold circuit, and multiple V&I circuits; the sample-and-hold circuit includes a MUX and multiple sample-and-hold units. The single-channel DAC is connected to the input interface of the MUX, and the multiple output interfaces of the MUX are respectively connected to the multiple sample-and-hold units. In practical applications, because the single-channel DAC in this solution only has one output, after the MUX outputs the first channel, there is no source to maintain the stable output voltage of the first channel when switching to the second channel. Even with compensation, the accuracy may not meet the requirements. Therefore, this application uses sample-and-hold units to provide a stable output voltage. Multiple sample-and-hold units are connected one-to-one with multiple V&I circuits. This application uses a single-channel DAC to achieve multi-channel AO output. Compared to parallel output of multiple DACs, the single-channel DAC time-division output + sample-and-hold design results in a lower module cost. Attached Figure Description

[0028] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1 This is a schematic diagram of the current current output type analog output module.

[0030] Figure 2 A schematic block diagram of the analog output module provided in the embodiments of this application;

[0031] Figure 3 A channel output timing diagram for a sample-and-hold implementation provided in this application embodiment;

[0032] Figure 4 This is a schematic diagram of a sample-and-hold circuit provided in an embodiment of this application. Detailed Implementation

[0033] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0034] The core of this application is to provide an analog output module to reduce the cost of analog output circuits.

[0035] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0036] To reduce the cost of analog output circuits, this application uses a single DAC to achieve multi-channel AO output. Channel switching allows the single DAC to charge the voltage sample-and-hold circuits of different channels. The sample-and-hold (S&H) circuit then charges, discharges, and holds the input voltage of the V&I circuit. Figure 2 A schematic block diagram of the analog output module provided in the embodiments of this application; as shown Figure 2 As shown, the analog output module provided in this application includes a single-channel DAC1, a sample-and-hold circuit 2, and multiple V&I circuits 3. The sample-and-hold circuit 2 includes a multiplexer (MUX) and multiple sample-and-hold units. The single-channel DAC1 is connected to the input interface of the MUX, and the multiple output interfaces of the MUX are respectively connected to the multiple sample-and-hold units. Each sample-and-hold unit is connected to a corresponding V&I circuit 3; the sample-and-hold units are used to provide a stable output voltage.

[0037] The main idea of ​​the method for implementing multi-channel AO output using a single-channel DAC in this application embodiment is a single-channel DAC + MUX + sample-and-hold circuit. A multi-select analog switch MUX charges the multi-channel sample-and-hold circuit using the single-channel DAC. When the analog switch MUX switches to another channel, the sample-and-hold circuit must ensure the stability of the input voltage of the V&I circuit, i.e., ensure the stability of the output current of the analog output module. In the multi-select analog output module, the MCU scans all channels (or any number of channels, depending on user configuration) one by one by updating the output of the single-channel DAC to obtain the desired channel output value, and then switches the MUX channel to connect to the desired output. Each channel passes through an S&H cycle (reference...). Figure 3Meanwhile, the value of a single-channel DAC can change continuously, resulting in different input voltages for each V&I circuit. When a channel is disconnected from the output of a single-channel DAC, the sample-and-hold circuit of each output channel can maintain its original value. It should be noted that the solution provided in this application is merely one example and does not limit other solutions. For example, the sample-and-hold unit may include a hold circuit and a buffer circuit. The hold circuit provides a stable output voltage, and the buffer circuit provides buffering for the hold circuit. The hold circuit may include a first resistor and a hold capacitor. The first end of the first resistor is connected to one of the output interfaces of the MUX, the second end of the first resistor is connected to the first end of the hold capacitor, the second end of the hold capacitor is grounded, and the second end of the first resistor and the first end of the hold capacitor are also connected to the buffer circuit. The buffer circuit includes an input resistor, an operational amplifier, a feedback capacitor, and a feedback resistor. The first terminal of the input resistor is connected to the second terminal of the first resistor and the first terminal of the holding capacitor. The second terminal of the input resistor is connected to the positive terminal of the operational amplifier's input. The negative terminal of the operational amplifier's input is connected to the first terminal of the feedback capacitor and the first terminal of the feedback resistor. The second terminal of the feedback capacitor and the second terminal of the feedback resistor are connected to the output terminal of the operational amplifier. The output terminal of the operational amplifier is connected to the corresponding V&I circuit. In one embodiment, the buffer circuit may further include a filter, which consists of a filter resistor and a filter capacitor. The output terminal of the operational amplifier is connected to the first terminal of the filter resistor, the second terminal of the filter resistor is connected to the first terminal of the filter capacitor, the second terminal of the filter capacitor is grounded, and the second terminal of the filter resistor and the first terminal of the filter capacitor are connected to the corresponding V&I circuit. The above scheme does not limit this application; the following describes practical application scenarios.

[0038] Figure 3 This application provides a sampling and holding implementation channel output timing diagram. The sampling and holding implementation process is as follows: MUX_EN is the MUX enable pin; a low level disables it, and a high level enables it. After enabling, the MUX input and output are connected; after disabling, the MUX input and output are disconnected. MUX_SEL is the MUX channel selection pin; different combinations of levels on the channel selection pin enable the selection of the MUX channel. MCU->DAC refers to the MCU sending data (code value) to the DAC; DAC_OUT refers to the DAC receiving data (code value) from the MCU and converting it into a voltage output. Figure 3 As shown, the channel scan cycle operation is as follows:

[0039] 1. At time T1, the MUX_EN pin of the multiplexer is given a low level to enable the output and prevent output jitter.

[0040] 2. From time T1 to T2, the MCU sends the corresponding DAC code value to the DAC via the MCU->DAC communication link; simultaneously, it controls the MUX_SEL pin of the MUX to achieve channel selection. (Since MUX_EN is low, there is no output to the line after channel selection.)

[0041] 3. The DAC output register is configured starting at time T2, and the DAC output is updated using the new value obtained from the MCU. The time interval from T2 to T3 is reserved for DAC conversion. During this period, the DAC completes the conversion of code value to voltage and the new voltage value enters a stable state.

[0042] 4. At time T3, the MUX_EN pin of the multiplexer goes high, turning on the MUX and connecting the sample-and-hold circuit to the DAC output. From T3 to T4, the sample-and-hold circuit is charged and discharged, i.e., sampled and refreshed. It's important to note that the sample-and-hold circuit discharges when the voltage is higher than the DAC output voltage and charges when it's lower than the DAC code value. Due to the presence of the DAC output voltage source, rapid charging and discharging of the sample-and-hold circuit is achieved, and the T3-T4 time period is very short.

[0043] 5. At time T4, the MUX is turned off to begin updating the next channel; the sample-and-hold circuit will maintain a stable output value until the MUX cycles back to that channel. It's important to note that a stable output value means the output value changes very little, meeting the channel's output accuracy requirements.

[0044] Figure 4 This is a schematic diagram of a sample-and-hold circuit provided in an embodiment of this application; as shown below. Figure 4 As shown, the sample-and-hold circuit consists of a MUX switch, an output holding circuit, and a buffer circuit for driving the output. To reduce leakage current in the sample-and-hold circuit, the MUX should be selected with low leakage current when open. To reduce the error introduced by the buffer circuit, a low-offset precision operational amplifier is used. For ease of theoretical analysis, the multiplexer MUX is equivalent to a pure switching section MUX and RC sections Rmux1, Rmux2, Cmux1, and Cmux2. Rmux1 is the on-resistance of the multiplexer, and Cmux1 and Cmux2 are the parasitic capacitances of the multiplexer. When the MUX is closed, the sample-and-hold circuit is charged and discharged through Rmux1, Cmux2, the first resistor Rh, and the holding capacitor Ch (path 1 in the figure). When the MUX is open, the first capacitor Ch and Cmux2 are discharged through two paths: the first resistor Rh, Rmux1, Rmux2, and Rin (paths 2 and 3 in the figure). By properly selecting Rmux1, Rmux2, the first resistor Rh, and the input resistor Rin, the voltage deviation caused by leakage current can be reduced.

[0045] An operational amplifier (active voltage follower or unity-gain amplifier) ​​is used to buffer the holding capacitor Ch and provide load drive capability. The input resistor Rin and feedback resistor Rf help match the input impedance to the op-amp and reduce the input bias current (though this is minimal, as the amplifier's bias current is already low). The feedback capacitor Cf helps maintain the stability of the unity-gain buffer. The filter resistor Ro matches the output circuit impedance, and the filter resistor Ro and filter capacitor CL form a filter to filter out high-frequency interference jitter, making the voltage entering the VI circuit more stable. The modules provided in the embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only for helping to understand the method and core ideas of this application; at the same time, for those skilled in the art, there will be changes in specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

[0046] This application provides an analog output module that reduces the cost of analog output modules. The analog output module includes a single-channel DAC, a sample-and-hold circuit, and multiple V&I circuits; the sample-and-hold circuit includes a MUX and multiple sample-and-hold units. The single-channel DAC is connected to the input interface of the MUX, and the multiple output interfaces of the MUX are respectively connected to the multiple sample-and-hold units. In practical applications, because the single-channel DAC in this solution only has one output, after the MUX outputs the first channel, there is no source to maintain the stable output voltage of the first channel when switching to the second channel. Even with compensation, the accuracy may not meet the requirements. Therefore, this application uses sample-and-hold units to provide a stable output voltage. Multiple sample-and-hold units are connected one-to-one with multiple V&I circuits. This application uses a single-channel DAC to achieve multi-channel AO output. Compared to parallel output of multiple DACs, the single-channel DAC time-division output + sample-and-hold design results in a lower module cost.

[0047] As described in the above embodiments, the sample-and-hold circuit consists of a MUX and a sample-and-hold unit, which in turn consists of a hold circuit and a buffer circuit for driving the output. To reduce leakage current in the sample-and-hold circuit, the MUX should be selected with low leakage current when open-circuited. To reduce the error introduced by the buffer circuit, a low-offset precision operational amplifier is used. For ease of theoretical analysis, the multiplexer MUX is equivalent to a pure switching section MUX and its internal RC sections Rmux1, Rmux2, Cmux1, and Cmux2. Appropriate selection of Rmux1, Rmux2, the first resistor Rh, and the input resistor Rin can reduce voltage offset caused by leakage current. The hold circuit provides a stable output voltage, and the buffer circuit provides buffering for the hold circuit. In practical applications, the specific circuit structure of the hold circuit and the buffer circuit is not limited. The hold circuit may include a first resistor and a hold capacitor. The first end of the first resistor is connected to one of the output terminals of the MUX, the second end of the first resistor is connected to the first end of the hold capacitor, the second end of the hold capacitor is grounded, and the second end of the first resistor and the first end of the hold capacitor are also connected to the buffer circuit. A buffer circuit may include an input resistor, an operational amplifier, a feedback capacitor, and a feedback resistor. The first terminal of the input resistor is connected to the second terminal of a first resistor and the first terminal of a holding capacitor. The second terminal of the input resistor is connected to the positive terminal of the operational amplifier's input. The negative terminal of the operational amplifier's input is connected to the first terminal of the feedback capacitor and the first terminal of the feedback resistor. The second terminals of the feedback capacitor and the second terminal of the feedback resistor are connected to the output terminal of the operational amplifier. The output terminal of the operational amplifier is connected to the corresponding V&I circuit. For highly capacitive loads, the feedback resistor helps maintain the stability of the buffer circuit.

[0048] The buffer circuit also includes a filter, through which the output of the operational amplifier is connected to the corresponding V&I circuit. The filter includes a filter resistor and a filter capacitor. The output of the operational amplifier is connected to the first terminal of the filter resistor, the second terminal of the filter resistor is connected to the first terminal of the filter capacitor, the second terminal of the filter capacitor is grounded, and the second terminal of the filter resistor and the first terminal of the filter capacitor are connected to the corresponding V&I circuit. For the specific circuit structure of this embodiment, please refer to [reference needed]. Figure 4 .

[0049] Additionally, the buffer circuit may introduce errors. Therefore, the offset of the operational amplifier can be selected. To reduce the errors introduced by the buffer circuit, a low-offset precision operational amplifier is used. Specifically, a first preset value can be set. When selecting the operational amplifier, it is necessary to ensure that the offset of the operational amplifier is less than the first preset value. To reduce leakage current in the sample-and-hold circuit, the MUX should be selected with low leakage current when the circuit is open.

[0050] In practical applications, to save costs, multiple components can use the same power supply. For example... Figure 4As shown, the single-channel DAC, sample-and-hold circuit, and V&I circuit in the analog output module share the same power supply.

[0051] In practice, a single DAC can cyclically control multiple output interfaces of the MUX in a preset order, facilitating control of these interfaces by the single DAC and simplifying the control scheme. Additionally, the MUX can be configured with backup output interfaces; if a normal output interface of the MUX fails, it can switch to the backup interface, thus ensuring the normal operation of the analog output module.

[0052] Here is also a specific operation method for the channel scan cycle (this method is not limited to actual applications):

[0053] 1. First, disable the output enable of the MUX to avoid output jitter during DAC updates.

[0054] 2. The MCU sends the voltage code value to be output to the DAC, and at the same time selects the output channel of the MUX.

[0055] 3. The DAC updates the configuration output register with the new value obtained from the MCU, reserving time for the DAC to complete voltage conversion and voltage stabilization.

[0056] 4. Enable the output of the MUX to output the new voltage to the channel and charge and discharge the sample-and-hold circuit.

[0057] 5. Based on the RC charging constant, allow sufficient time for RC charging and discharging. After charging and discharging is complete, turn off the MUX and start updating the next channel. Until the MUX cycles to the same channel again, the sample-and-hold circuit will keep the output value stable.

[0058] The analog output module provided in this application has been described in detail above. The various embodiments in the specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.

[0059] It should also be noted that, in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the aforementioned element.

Claims

1. An analog output module, characterized in that, include: A single-channel DAC, a sample-and-hold circuit, and multiple V&I circuits; wherein the sample-and-hold circuit includes a MUX and multiple sample-and-hold units; The single-channel DAC is connected to the input interface of the MUX, and the multiple output interfaces of the MUX are respectively connected to multiple sample-and-hold units; Each of the sample-and-hold units is connected to one of the V&I circuits; the sample-and-hold units are used to provide a stable output voltage. The sample-and-hold unit includes a holding circuit and a buffer circuit; The holding circuit is used to provide a stable output voltage, and the buffer circuit is used to provide buffering for the holding circuit; The buffer circuit includes: an input resistor, an operational amplifier, a feedback capacitor, and a feedback resistor; The first end of the input resistor is connected to the second end of the first resistor in the holding circuit and the first end of the holding capacitor in the holding circuit. The second terminal of the input resistor is connected to the positive terminal of the input terminal of the operational amplifier, and the negative terminal of the input terminal of the operational amplifier is connected to the first terminal of the feedback capacitor and the first terminal of the feedback resistor. The second end of the feedback capacitor and the second end of the feedback resistor are connected to the output terminal of the operational amplifier, and the output terminal of the operational amplifier is connected to the corresponding V&I circuit. It also includes: the MUX as a multi-select analog switch, used to enable a single DAC to charge multiple sample-and-hold circuits; when the analog switch is switched to other channels, the sample-and-hold circuit must ensure that the input voltage of the V&I circuit is stable.

2. The analog output module according to claim 1, characterized in that, The holding circuit includes: a first resistor and a holding capacitor; The first end of the first resistor is connected to one of the output interfaces of the MUX, the second end of the first resistor is connected to the first end of the holding capacitor, and the second end of the holding capacitor is grounded. The second end of the first resistor and the first end of the holding capacitor are also connected to the buffer circuit.

3. The analog output module according to claim 1, characterized in that, The buffer circuit also includes: a filter; The output of the operational amplifier is connected to the corresponding V&I circuit through the filter.

4. The analog output module according to claim 3, characterized in that, The filter includes a filter resistor and a filter capacitor; The output terminal of the operational amplifier is connected to the first terminal of the filter resistor, the second terminal of the filter resistor is connected to the first terminal of the filter capacitor, and the second terminal of the filter capacitor is grounded. The second end of the filter resistor and the first end of the filter capacitor are connected to the corresponding V&I circuit.

5. The analog output module according to claim 1, characterized in that, The offset of the operational amplifier is less than a first preset value.

6. The analog output module according to claim 1, characterized in that, The single-channel DAC, the sample-and-hold circuit, and the V&I circuit share the same power supply.

7. The analog output module according to claim 1, characterized in that, The single-channel DAC cyclically controls multiple output interfaces of the MUX in a preset order.

8. The analog output module according to claim 1, characterized in that, The MUX also includes a backup output interface; if the normal output interface of the MUX fails, it will switch to the backup output interface.

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