An entropy decoding decoder suitable for HEVC and its optimization method

Abstract

The present invention discloses an entropy decoding decoder optimization method suitable for HEVC. According to the characteristics of different syntax elements, multiple conventional arithmetic decoders are grouped and parallelized to form a five-way output device, thereby realizing the parallel calculation of multiple bins in a single-cycle clock, achieving parallel calculation of entropy decoding at the circuit level, and having good versatility. The steps of parallelizing multiple conventional arithmetic decoders are as follows: obtaining the bin currently undergoing conventional arithmetic decoding, and outputting the corresponding conventional arithmetic decoder drive signal when the current bitstream pointer points to the syntax element required by the corresponding module. For the renormalization operation in the conventional arithmetic unit, the conventional arithmetic unit input is clipped to the upper 5 bits of the current 8-bit bitstream, and the ivlCurrRange interval size comparison is improved to a shift judgment selector.

Description

Technical Field

[0001] The present invention relates to the technical field of video decoding, and in particular to an entropy decoding decoder suitable for HEVC and an optimization method thereof. Background Art

[0002] H.265 / HEVC is a new generation of video codec standard that replaces H.264 / AVC. Its coding efficiency is much better than the previous standard. Compared with H.264 / AVC, the video compression standard H.265 / HEVC can achieve a lower bit rate at the same image quality, that is, a higher compression ratio [1]. Context-Adaptive Binary Arthmetic Coding (CABAC) is an entropy coding scheme supported by H.265 / HEVC. CABAC has an extremely high data compression rate among entropy coding schemes. Compared with another entropy coding scheme, Context-Adaptive Variable Length Coding (CAVLC), CABAC can save 10%-15% of the bit rate at the same coding quality.

[0003] In CABAC, maintaining and updating context modeling requires a lot of computation and access to internal storage devices. During the decoding process, a syntax element requires the previous syntax element to determine the context address. When each binVal is decoded, the decoding process needs to check whether the stream has been changed or remains in the same syntax element. Therefore, the decoding process has more dependencies than the encoding process. At the same time, in the standard entropy decoding process, due to the existence of the bitstream pointer (binIdx), the entropy decoding process is too serial, which takes a long decoding time. As a result, the CABAC module becomes the throughput bottleneck of the video decoder. Therefore, it is necessary to design a highly parallel, high-throughput hardware structure to address the above problems.

[0004] Currently, CABAC decoders can be divided into three categories: pipeline-based temporal parallelism expansion, single-cycle multi-bit decoding, prediction-based decoding, and subinterval reordering-based decoding. Pipelining can expand temporal parallelism, but the high data dependency between bitstreams makes the feedback loop too serial, resulting in excessive clock redundancy in the pipeline architecture. Adding additional decoding logic can increase the number of decoded output bits per cycle, but the clock rate is low. Decoding through prediction can save the hardware overhead of pre-storing decoding information, but it introduces additional critical path delay and a high prediction error penalty, resulting in lower throughput. Some scholars have proposed CABAC decoders using multi-bin decoding, improving arithmetic coding (subinterval reordering) and shortening the critical path. However, front-end bitstream control is prone to performance bottlenecks. After using subinterval reordering, the encoder and decoder must be used simultaneously to ensure codec consistency, making it less practical. Furthermore, in their research of the prior art, the inventors found that existing CABAC implementations in HEVC decoding methods still suffer from unstable throughput, excessive data loop serialization, and high hardware overhead, making it difficult to meet the real-time decoding requirements of various software and hardware platforms. Summary of the Invention

[0005] In view of the shortcomings of the existing technology, the present invention proposes an entropy decoding decoder suitable for HEVC and an optimization method thereof. By grouping syntax elements for parallel processing, the use and access times of internal registers are reduced, the critical path is optimized, and the throughput of the CABAC decoder is increased. In addition, no special configuration is required at the encoding end, and the proposed structure has good versatility.

[0006] In order to solve the above technical problems, the technical solution of the present invention is:

[0007] A method for optimizing entropy decoding for HEVC is proposed. Based on the characteristics of different syntax elements, multiple conventional arithmetic decoders are grouped and parallelized to form a five-way output device. This allows for parallel computation of multiple bins in a single clock cycle, achieving parallel computation of entropy decoding at the circuit level and achieving high versatility.

[0008] The steps of operating multiple conventional arithmetic decoders in parallel are: obtaining a bin currently undergoing conventional arithmetic decoding, and outputting a corresponding conventional arithmetic decoder driving signal when a current bitstream pointer points to a syntax element required by a corresponding module.

[0009] Among them, for the renormalization operation in the conventional arithmetic unit, the conventional arithmetic unit input is cut into the upper 5 bits of the current 8-bit bit stream, and the size comparison of the ivlCurrRange interval range is improved to a shift judgment selector.

[0010] Furthermore, the corresponding decoding type is selected according to the context model index CtxIdx value corresponding to the current bin to be decoded, and the decoding type includes three types: conventional arithmetic decoding, bypass decoding, and termination decoding; according to the aforementioned corresponding decoding type, a conventional arithmetic decoder, a bypass decoder or a termination decoder is selected for decoding operation.

[0011] Furthermore, context model reading and updating are performed within different groups of modules, depending on the type of syntax element requiring conventional arithmetic decoding. The decoding calculation module is instantiated separately within the module. In the initial steps of conventional arithmetic decoding, each group must perform probability state transitions and read probability intervals through table lookups. State transition data is irregular, so to improve throughput, a LUT is used during hardware design to pre-store the values ​​that need to be updated.

[0012] The present invention also provides an entropy decoding decoder suitable for HEVC, comprising a conventional arithmetic decoding engine grouping parallel unit, which is used to group multiple conventional arithmetic decoding engines in parallel to form a conventional arithmetic decoder, wherein one conventional arithmetic decoder is responsible for conventional arithmetic decoding of one bin, so that the conventional arithmetic decoder can perform parallel conventional arithmetic decoding of multiple syntax elements within one clock cycle;

[0013] The conventional arithmetic decoding parallel module further includes a context information acquisition and update module and a renormalization module.

[0014] The context information collection and updating module is used to obtain the bin currently undergoing conventional arithmetic decoding, determine whether the value decoded by the current bin is MPS or LPS, and output a binary decoding value binVal.

[0015] The renormalization module is used to keep the current ivlCurrRange interval range value always less than 256, and iterate and calculate multiple times to update the ivlCurrRange and ivlOffset values.

[0016] Furthermore, it also includes a decoding type judgment unit, that is, a syntax element state machine, which is configured to: select a corresponding decoding type according to the context model index CtxIdx value corresponding to the current bin to be decoded, and the decoding type includes three types: conventional arithmetic decoding, bypass decoding, and termination decoding; and

[0017] According to the corresponding decoding type mentioned above, a conventional arithmetic decoder, a bypass decoder or a termination decoder is selected respectively.

[0018] The present invention has the following characteristics and beneficial effects:

[0019] The above technical solution is used to group multiple conventional arithmetic decoding engines into a five-way output device according to the characteristics of different syntax elements, thereby realizing the parallel calculation of multiple bins in a single-cycle clock, achieving parallel calculation of entropy decoding at the circuit level, and having good versatility.

[0020] While reducing the critical path, the throughput of the CABAC decoding module is increased and the clock cycle redundancy caused by data is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0022] Figure 1 A schematic diagram of the CABAC parallel architecture provided by an embodiment of the present invention.

[0023] Figure 2 This is the algorithm architecture diagram of CABAC under the H.265 / HEVC standard.

[0024] Figure 3 Flowchart of the decoding operation for a conventional arithmetic decoding engine to decode a bin.

[0025] Figure 4 A two-dimensional lookup table built for CABAC.

[0026] Figure 5 A schematic diagram of parallel grouping of a conventional arithmetic decoding engine provided by an embodiment of the present invention.

[0027] Figure 6 This is a flowchart of the bypass decoding engine provided by an embodiment of the present invention.

[0028] Figure 7 This is a flowchart of the operation of the termination decoding engine provided by an embodiment of the present invention.

[0029] Figure 8 This is a simulation verification diagram in an embodiment of the present invention.

[0030] Figure 9 The resource consumption required for the hardware implementation provided by the embodiment of the present invention. DETAILED DESCRIPTION

[0031] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features therein may be combined with each other.

[0032] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, features defined as "first", "second", etc. may explicitly or implicitly include one or more of the features. In the description of the present invention, unless otherwise specified, "multiple" means two or more.

[0033] In the description of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they may refer to fixed connections, detachable connections, or integral connections; mechanical connections or electrical connections; direct connections or indirect connections through an intermediate medium; and internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0034] During the decoding process, most syntax elements require the previous syntax elements to determine the context address, such as the state transition and context model update during arithmetic decoding. When each binVal is decoded, the decoding process needs to check whether the stream has been changed or remains in the same syntax element. Therefore, the decoding process has more dependencies than the encoding process. At the same time, in the standard entropy decoding process, due to the existence of binIdx (bitstream pointer), the serial program of the entropy decoding process is too high, which takes a long decoding time. In order to solve the problems existing in the CABAC entropy decoding algorithm, a multi-path parallel CABAC decoding process is proposed in this work, such as Figure 1 As shown, while reducing the critical path, the throughput of the CABAC decoding module is increased and the clock cycle redundancy caused by data is reduced.

[0035] Through analysis Figure 2 The algorithm flow chart of conventional arithmetic decoding in the figure can abstract the input and output of the conventional arithmetic decoding module. The input information includes the current Range, the current pStateIdx, the current Offset and the current MPS. The output information includes the updated Range, Offset, pStateIdx and MPS, as well as the solved binVal. Figure 3There is no obvious pattern in the interval state corresponding values ​​in the lookup table, so the data in this table is directly input for reading.

[0036] On the other hand, for parameters related to SAO, the number of ctxTable parameters is small, while the number of residual syntax element parameters is large. The conventional CABAC decoding module is designed here according to decode_decision, decode_bypass, and decode_terminate, and different decoding modes are carried out in three parallel paths. At the same time, the bitstream input is input serially according to the bitstream pointer. This will cause the throughput to drop instantly when decoding to a larger contextmodel bit width, and the stability of the decoded data output cannot be guaranteed.

[0037] Based on the above reasons, the present invention divides the conventional arithmetic decoding (decode_decision) with the highest operation ratio in CABAC decoding into 5 paths according to the different bit widths of the required context models. Figure 5 As shown in the figure, they are SAO, CU, pred, residual, and sig. Enable signals are transmitted through the module containing the syntax element to drive the corresponding conventional arithmetic decoding module. The advantage of this grouped parallel approach is that it drives multiple modules to run simultaneously, reducing the high serialization and data dependency of CABAC decoding, reducing unnecessary waiting in the hardware module, and shortening the critical path during parameter transfer.

[0038] Furthermore, the input rbsp of the conventional arithmetic decoding module is the upper 5 bits. Combined with the judgment of the renormalization part, the structure of the bit stream is read left-shifted and padded, so the input discards the lower 3 bits. In the process of updating the state probability interval, the most important step is to transfer the state and read ivlLpsRange through the table lookup. Because the data in the lookup table has no pattern and cannot be logically deduced, two LUTs are used in the design to store the values ​​that need to be updated. In the renormalization process, by optimizing the original comparison size, it is improved to a bit-by-bit judgment selector structure. When ivlCurrRange[8] is equal to 1, ivlCurrRange must be greater than 256. The number of paths required for judgment in the hardware circuit is reduced, which improves the throughput. Combined with the ivlOffset in the next step, the left shift is performed and the rbsp is padded.

[0039] Furthermore, the input of the bypass decoding module is 1 bit, and the interval value remains unchanged during the entire bypass decoding process. First, the ivlOffset offset is shifted left by 1 bit, and 1 bit is read from the bitstream to fill the position. Then, a judgment is made and the binary syntax element value and the updated ivlOffset are output. The algorithm flow chart and hardware implementation architecture are shown as follows: Figure 7As shown, the technical solution provided in this embodiment is simulated, and the simulation verification results are as follows Figure 8 shown.

[0040] In this embodiment, the entropy decoding process of a bin has the following steps: obtaining the context model index value corresponding to the current bin to be decoded, selecting the corresponding decoding type according to the index value, and the decoding type includes three types: conventional arithmetic decoding, bypass decoding and termination decoding; according to the aforementioned corresponding decoding types, selecting the conventional arithmetic decoding engine, bypass decoding engine and planting decoding engine to perform decoding operations.

[0041] Specifically, you can first determine whether BypassFlag is equal to 1. When BypassFlag is equal to 1, it is determined to be the bypass arithmetic decoding type, and the bypass decoding engine is triggered to perform bypass arithmetic decoding; otherwise, continue to determine whether CtxIdx is equal to 276. When CtxIdx is equal to 1, it is determined to be the terminator arithmetic decoding type, and the terminator decoding engine is triggered to perform terminator arithmetic decoding; otherwise, it is determined to be the conventional arithmetic decoding type, and the conventional decoding engine is triggered to perform DecodeDecision(ctxIdx) parsing.

[0042] This embodiment provides an entropy decoding decoder optimization method applicable to HEVC, such as Figure 1 shown.

[0043] The complete CABAC decoder is generally designed as a three-stage pipeline. First, the bit stream in the first-stage pipeline passes through the syntax element state machine, and by parsing the different data paths that different syntax elements need to pass through, it outputs the enable signal required by each decoding module; the context state machine in the second-stage pipeline establishes a specific context index register by judging the enable signal received by the previous-stage pipeline. The corresponding syntax elements and initialization information are stored in the context model memory together, which is also the place where the context update model is stored in the subsequent decoding process. This module sends the prepared enable signal, context model and slicedata to the stateselector; the third-stage pipeline is the decoding part of the decoder. After decoding the binary syntax element value binVal, it is passed into the module where the syntax element is located for denormalization (De-Binarization, DB).

[0044] Slicedata is a unit in the video encoding process, where a video frame is composed of several non-overlapping slices. This decoder decodes slices. The entropy decoding described in this embodiment is to obtain the additional information required for the slice to perform the subsequent decoding steps (output during the encoding stage through entropy coding with extremely high data dependency and compression rate).

[0045] In order to verify the proposed entropy decoding group multi-way parallel pipeline structure, implementation and performance evaluation verification were carried out based on FPGA. The circuit structure was designed using VerilogHDL, synthesized on the xc7z035ffg676-2 chip, simulated using Modelsim, and compared with the results in the HM16.19 test platform. The results are consistent, proving the correctness of the design in this paper.

[0046] First, the enable signal for the corresponding syntax element group is pulled high, driving the decoding module to work and output the updated interval value and offset. After the regular arithmetic decoding process is completed, the enable signal is pulled low again, and the enable signal for bypass decoding is pulled high to output the updated offset. In this design, the update of the offset and interval value is delayed by one clock cycle.

[0047] The resources occupied by the present invention are as follows Figure 9 As shown, this design increases the number of syntax elements output per cycle while reducing on-board resources.

[0048] The embodiments of the present invention are described in detail above with reference to the accompanying drawings, but the present invention is not limited to the described embodiments. It will be apparent to those skilled in the art that various changes, modifications, substitutions, and variations of these embodiments, including components, without departing from the principles and spirit of the present invention are still within the scope of protection of the present invention.

Claims

1. An entropy decoding decoder suitable for HEVC, characterized in that include The syntax element state machine is configured to: select a corresponding decoding type according to the context model index number CtxIdx value corresponding to the current bin to be decoded; The context selector and context state machine are configured to: identify the enable signal received by the previous pipeline level to establish a specific context index register. The corresponding syntax elements and initialization information are stored in the context model memory, which is also where the context update model is stored during the subsequent decoding process. This module sends the prepared enable signal, context model and slice data to the state selector to select a specific data path; A multi-way parallel debinarization decoder configured as follows: 5-way conventional arithmetic decoders, wherein the 5-way conventional arithmetic decoders are connected to context modeling storage buffers of different depths and bit widths; A bypass decoder specifies the number of bits of the code stream input according to the characteristics of the original algorithm, and reads the bit stream for discrimination through its discrimination module. The original size comparator in the discrimination module is replaced by a multi-way state selector. The 1-way termination decoder specifies a specific number of code stream input bits according to the characteristics of the original algorithm, and reads the bit stream for discrimination through its discrimination module. The original size comparator in the discrimination module is replaced by a multi-way state selector.

2. The entropy decoding decoder suitable for HEVC according to claim 1, characterized in that The decoding types include bypass decoding, termination decoding and conventional arithmetic decoding, and the bypass decoding, termination decoding and conventional arithmetic decoding respectively select a bypass decoder, a terminator decoder and a conventional decoder to perform decoding operations.

3. The entropy decoding decoder optimization method applicable to HEVC according to claim 1 or 2, characterized in that: The steps include: S1. The bitstream passes through the syntax element state machine, which parses the different data paths required for different syntax elements and outputs the enable signals required for each decoding; S2. The context state machine determines the enable signal output in step S1, establishes a specific context index register, stores the corresponding syntax elements and initialization information in the context model memory, and sends the prepared enable signal, context model memory, and slice data to the state selector. S3. The state selector calls a specific conventional decoder among the five conventional arithmetic decoders according to the received enable signal, and groups the grammatical elements into five groups according to different types, so that the five conventional arithmetic decoders output multiple bins in one cycle. S4. Select the corresponding decoding type according to the context model index number CtxIdx value corresponding to the current bin to be decoded S5. Decode the binary syntax element value binVal and pass it to the decoder where the syntax element is located for denormalization.

4. The entropy decoding decoder optimization method applicable to HEVC according to claim 3, characterized in that In step S2, a plurality of state selectors are set.

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