Semiconductor structure and method of manufacturing the same

Abstract

The application provides a semiconductor structure and a preparation method thereof, relates to the technical field of semiconductors, and aims to solve the technical problem of large contact resistance of a contact plug. The preparation method comprises the following steps: forming a conductive layer on a substrate; forming a first mask layer on the conductive layer, wherein the first mask layer has a plurality of first mask patterns; forming a second mask layer on the first mask layer in an isolation region; etching the first mask layer in an array region by taking the second mask layer as a mask, so that the first mask patterns in the array region are formed into second mask patterns; etching the conductive layer by taking the first mask patterns and the second mask patterns as masks, so that the conductive layer in the array region and the isolation region forms a plurality of spaced conductive structures; wherein the characteristic size of the conductive structure in the array region is smaller than the characteristic size of the conductive structure in the isolation region in a second direction; and forming a first contact plug on the conductive structure in the isolation region. The application can reduce the contact resistance of the first contact plug.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor manufacturing, and in particular to a semiconductor structure and a preparation method thereof. BACKGROUND

[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor memory device, which includes a plurality of repeated memory cells. Each memory cell usually includes a transistor and a capacitor, the gate of the transistor is connected with a word line (WL), the drain is connected with a bit line (BL), and the source is connected with the capacitor.

[0003] With the continuous development of semiconductor chips, the critical dimension of the semiconductor chips is continuously reduced, and the critical dimension of the cross section of the device formed by the array region and the isolation region in the DRAM is also continuously reduced. For example, when a contact plug is made in the isolation region to contact the end of the bit line, a trench is usually first made to expose the bit line, and a conductive material is filled in the trench to form the contact plug, so that the bit line is electrically connected to an external device through the contact plug.

[0004] However, in the related art, as the critical dimension of the bit line and other structures is continuously reduced, the trench for exposing the bit line in the shallow trench isolation region is prone to over-etching or even perforation, and the contact resistance of the contact plug prepared in the trench is large. SUMMARY

[0005] In view of the above problems, the embodiments of the present application provide a semiconductor structure and a preparation method thereof, which can avoid the phenomenon of over-etching or even perforation when the trench is made, and can reduce the contact resistance of the contact plug formed in the semiconductor structure, thereby improving the reliability of the electrical performance of the semiconductor structure.

[0006] In order to achieve the above purpose, the embodiments of the present application provide the following technical solutions:

[0007] The first aspect of the embodiments of the present application provides a preparation method of a semiconductor structure, comprising:

[0008] providing a substrate, and forming a conductive layer on the substrate, the substrate having an array region, an isolation region and a peripheral circuit region, the isolation region being located between the array region and the peripheral circuit region;

[0009] forming a first mask layer on the conductive layer, the first mask layer corresponding to the array region and the isolation region having a plurality of first mask patterns, each first mask pattern extending along a first direction;

[0010] forming a second mask layer on the first mask layer of the isolation region, and etching the first mask layer of the array region with the second mask layer as a mask, so that the first mask pattern in the first mask layer of the array region is formed into a second mask pattern;

[0011] etching the conductive layer by using the first mask pattern and the second mask pattern, so that the conductive layer reserved in the isolation region and the array region is formed into a plurality of spaced conductive structures; the feature size of the conductive structure in the array region in a second direction is smaller than the feature size of the conductive structure in the isolation region in the second direction, and the conductive structure in the isolation region is connected with the conductive structure in the array region corresponding to the same extension direction, wherein the first direction and the second direction are perpendicular to each other;

[0012] forming a first contact plug on the conductive structure in the isolation region.

[0013] As an optional embodiment, in the step of forming a first mask layer on the conductive layer, the first mask layer corresponding to the array region and the isolation region has a plurality of first mask patterns, specifically comprising:

[0014] adopting one of an atomic layer deposition process, a chemical vapor deposition process, and a physical vapor deposition process to form a first initial mask base layer on the conductive layer;

[0015] forming a first mask pattern layer on the first initial mask base layer corresponding to the array region and the isolation region;

[0016] patterning the first mask pattern layer to form a plurality of first mask patterns, and the first initial mask base layer and the first mask pattern layer jointly form the first mask layer; wherein the feature size of the first mask pattern in the second direction is a first size.

[0017] As an optional embodiment, in the step of etching the first mask layer of the array region with the second mask layer as a mask, comprising:

[0018] adopting a wet etching or dry etching process to etch each of the first mask patterns in the array region with the second mask layer as a mask, so that the first mask pattern is formed into a second mask pattern, wherein the feature size of the second mask pattern in the second direction is a second size;

[0019] wherein the second size is smaller than the first size.

[0020] As an optional implementation, in the step of etching the conductive layer by using the first mask pattern and the second mask pattern to form the conductive layer remained in the array region and the isolation region into a plurality of spaced conductive structures, the step comprises:

[0021] The conductive layer in the array region is etched by using the first mask pattern as a mask, and the conductive layer in the isolation region is etched by using the second mask pattern as a mask, so as to form conductive structures in the array region and the isolation region synchronously.

[0022] As an optional implementation, in the step of forming the first contact plug on the conductive structure in the isolation region, the step comprises:

[0023] A dielectric layer is formed between adjacent conductive structures and on the conductive structures.

[0024] The dielectric layer on the conductive structure in the isolation region is removed to form a first trench, and the first trench exposes the surface of the conductive structure.

[0025] The conductive material in the first trench is filled to form a first contact plug in contact with the conductive structure.

[0026] As an optional implementation, in the step of forming the second mask layer on the first mask layer in the isolation region, the step further comprises:

[0027] A second mask layer is formed in the peripheral circuit region synchronously.

[0028] As an optional implementation, the method further comprises:

[0029] The first contact plug is formed on the conductive structure in the isolation region, and a second contact plug is formed in the peripheral circuit region synchronously.

[0030] The peripheral circuit region comprises a transistor, the transistor comprises a source / drain, and the second contact plug is electrically connected with the source / drain.

[0031] As an optional implementation, in the step of forming the first contact plug on the conductive structure in the isolation region and forming the second contact plug in the peripheral circuit region synchronously, the step comprises:

[0032] A dielectric layer is formed on the conductive structure in the isolation region and on the peripheral circuit region synchronously.

[0033] simultaneously removing the dielectric layer on the source / drain in the peripheral circuit region to form a second trench, the second trench exposing a surface of the source / drain;

[0034] simultaneously filling the second trench with conductive material to form the conductive material in the second trench into a second contact plug electrically connected with the source / drain.

[0035] As an optional implementation, in the step of forming the conductive layer on the substrate, specifically includes:

[0036] forming a first conductive layer on the substrate;

[0037] forming a second conductive layer on the first conductive layer;

[0038] forming a third conductive layer on the second conductive layer, the first conductive layer, the second conductive layer and the third conductive layer collectively forming the conductive layer.

[0039] As an optional implementation, after etching the first mask layer of the array region to form the first mask pattern in the first mask layer of the array region into a second mask pattern, further includes:

[0040] removing part of the second mask layer of the isolation region close to the array region, and retaining the second mask layer of the isolation region close to the peripheral circuit region, wherein the region corresponding to the isolation region where the second mask layer is removed forms a first region, and the region corresponding to the isolation region where the second mask layer is retained forms a second region.

[0041] As an optional implementation, after the conductive structure is formed in the array region and the isolation region, and before the first contact plug is formed on the conductive structure in the isolation region, further includes:

[0042] removing the first mask layer of the array region and the isolation region.

[0043] The second aspect of the embodiments of the present application further provides a semiconductor structure, comprising:

[0044] a substrate, the substrate having an array region, an isolation region and a peripheral circuit region, the isolation region being between the array region and the peripheral circuit region;

[0045] a plurality of conductive structures, the plurality of conductive structures are respectively arranged in the array region and the isolation region in a spaced manner, and the conductive structures extend along a first direction; a feature size of the conductive structures in the array region in a second direction is smaller than a feature size of the conductive structures in the isolation region in the second direction, and the conductive structures in the isolation region are connected with the conductive structures in the array region corresponding thereto in the same extending direction; wherein the second direction is perpendicular to the first direction;

[0046] a first contact plug located on the conductive structures in the isolation region.

[0047] As an optional implementation, a feature size of the first contact plug in the isolation region in the second direction is not less than the feature size of the conductive structures in the isolation region in the second direction.

[0048] In the semiconductor structure and the preparation method thereof provided by the embodiments of the present application, a plurality of first mask patterns are formed in the array region and the isolation region in a spaced manner along the second direction, then the first mask patterns in the array region are continuously etched to form second mask patterns, so that the feature size of the second mask patterns in the second direction is smaller than the feature size of the first mask patterns in the second direction, and the conductive layer on the substrate is etched by using the first mask patterns and the second mask patterns, so that the conductive layer remaining in the array region and the isolation region is formed into a plurality of spaced conductive structures, thereby making the feature size of the conductive structures in the isolation region in the second direction larger than the feature size of the conductive structures in the array region in the second direction, and the conductive structures in the isolation region are connected with the conductive structures in the array region corresponding thereto in the same extending direction, and the first contact plug is formed on the conductive structures in the isolation region. In this way, while meeting the miniaturization of the semiconductor structure, the phenomenon of perforation or over-etching of the trench corresponding to the first contact plug during etching can be avoided, the contact resistance of the first contact plug is reduced, and thus the reliability of the electrical performance of the semiconductor structure can be improved.

[0049] In addition to the technical problems solved by the embodiments of the present application described above, the technical features constituting the technical solutions and the beneficial effects brought by these technical features, other technical problems solved by the semiconductor structure and the preparation method thereof provided by the embodiments of the present application, other technical features included in the technical solutions and the beneficial effects brought by these technical features will be further described in detail in the specific embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0050] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the accompanying drawings needed to be used in the embodiments or prior art description will be briefly introduced as follows. Obviously, the accompanying drawings in the following description are some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained based on these drawings without creative labor.

[0051] Figure 1 A top view of a semiconductor structure according to an embodiment of the present application;

[0052] Figure 2 A cross-sectional view of a semiconductor structure according to an embodiment of the present application, in which a trench is formed in the isolation region;

[0053] Figure 3 A cross-sectional view of a semiconductor structure according to an embodiment of the present application, in which a contact plug is formed in the trench;

[0054] Figure 4 A flow chart of a method for manufacturing a semiconductor structure according to another embodiment of the present application;

[0055] Figure 5 A top view of a semiconductor structure according to another embodiment of the present application, in which a gate is formed in the peripheral circuit region;

[0056] Figure 6 A cross-sectional view of a semiconductor structure according to another embodiment of the present application, in which a gate is formed in the peripheral circuit region; Figure 5 A cross-sectional view of a semiconductor structure according to another embodiment of the present application, in which a gate is formed in the peripheral circuit region;

[0057] Figure 7 A top view of a semiconductor structure according to another embodiment of the present application, in which a first mask pattern is formed during manufacturing;

[0058] Figure 8 A cross-sectional view of a semiconductor structure according to another embodiment of the present application, in which a first mask pattern is formed during manufacturing;

[0059] Figure 9 A top view of a semiconductor structure according to another embodiment of the present application, in which a second mask pattern is formed during manufacturing;

[0060] Figure 10 A cross-sectional view of a semiconductor structure according to another embodiment of the present application, in which a second mask pattern is formed during manufacturing;

[0061] Figure 11 A top view of a semiconductor structure according to another embodiment of the present application, in which a first mask layer of the isolation region is removed during manufacturing;

[0062] Figure 12A cross-sectional view of a semiconductor structure provided for another embodiment of the present application during a process of removing a first mask layer of the isolation region;

[0063] Figure 13 A cross-sectional view of a semiconductor structure provided for another embodiment of the present application during a process of forming the conductive structure;

[0064] Figure 14 A cross-sectional view of a semiconductor structure provided for another embodiment of the present application during a process of forming the conductive structure;

[0065] Figure 15 A top view of a semiconductor structure provided for another embodiment of the present application during a process of forming the first trench and the second trench;

[0066] Figure 16 A cross-sectional view of a semiconductor structure provided for another embodiment of the present application during a process of forming the first trench and the second trench;

[0067] Figure 17 A cross-sectional view of a semiconductor structure provided for another embodiment of the present application during a process of forming the first trench and the second trench;

[0068] Reference Signs:

[0069] 100 - substrate; 10 - trench; 11 - slit; 12 - bit line;

[0070] 20 - contact plug; 110 - conductive layer; 111 - first conductive layer;

[0071] 112 - second conductive layer; 113 - third conductive layer; 114 - insulating layer;

[0072] 120 - first mask layer; 121 - first mask pattern; 122 - second mask pattern;

[0073] 130 - second mask layer; 140 - conductive structure; 150 - dielectric layer;

[0074] 151 - first trench; 152 - second trench; 160 - first contact plug;

[0075] 170 - second contact plug; 180 - gate. DETAILED DESCRIPTION

[0076] The inventors of the present application found in practical research that a dynamic random access memory (DRAM) includes a plurality of repeated memory cells, each of which generally includes a capacitor and a transistor, a gate of the transistor being connected with a word line (WL), a drain being connected with a bit line (BL), and a source being connected with the capacitor. A voltage signal on the word line can control the opening or closing of the transistor, and then data information stored in the capacitor is read through the bit line or the data information is written into the capacitor through the bit line for storage. The word line is connected with a word line driver through a contact plug in a peripheral circuit region of the memory cell, so as to facilitate the word line driver to input a voltage signal into the word line.

[0077] Figure 1 A top view of a semiconductor structure according to an embodiment of the present application; Figure 2 A cross-sectional view of a semiconductor structure according to an embodiment of the present application, in which a trench is formed in an isolation region; Figure 3 A cross-sectional view of a semiconductor structure according to an embodiment of the present application, in which a contact plug is formed in the trench.

[0078] Please refer to Figure 1 As shown in the figure, the current semiconductor structure generally has a substrate 100, the substrate 100 has a word line (not shown in the figure) and a bit line 12 arranged in sequence, the word line and the bit line 12 are arranged alternately, and the bit line 12 can extend along the first direction in the figure, and a plurality of bit lines 12 are arranged in the second direction. Figure 1

[0079] The substrate 100 includes an array region, an isolation region and a peripheral circuit region, and the isolation region is located between the array region and the peripheral circuit region. The isolation region can include a first region and a second region, the first region is arranged close to the array region, and the second region is arranged close to the peripheral circuit region. For the convenience of description, in the embodiments of the present application, the array region is represented by I, the first region in the isolation region is represented by II, the second region is represented by III, and the peripheral circuit region is represented by IV. Figure 1 As shown in the figure, the bit line 12 made on the substrate extends from the array region to at least the first region in the isolation region, and a contact plug is made on the part of the bit line 12 in the isolation region to realize the electrical connection between the bit line 12 and other devices. Since the part of the bit line 12 in the same extension direction is made by the same process, i.e. the part of the bit line 12 in the array region and the part of the bit line 12 in the isolation region are made by the same process, and the feature size of the part of the bit line 12 in the array region is the same as that of the part of the bit line 12 in the isolation region, i.e. the width of the part of the bit line 12 in the array region in the second direction is equal to that of the part of the bit line 12 in the isolation region in the second direction. ​

[0080] However, with the continuous development of semiconductor chips, the critical dimension thereof is continuously reduced, for example, as shown in Figure 1 The width of the bit line 12 formed by the array region and the isolation region in the second direction is also continuously reduced. When the contact plug 20 in contact with the bit line 12 is manufactured, the trench 10 exposing the bit line is usually manufactured first, and then the conductive material is filled in the trench 10 to form the contact plug 20, as shown in Figure 2 and Figure 3 When the trench 10 is manufactured, more of the medium layer filled between the adjacent bit lines 12 is exposed on both sides of the bit line 12. In the process of etching the trench 10, over-etching is prone to occur on both sides of the bit line 12 due to the large etching rate of the medium layer, thereby forming the slit 11 on both sides of the bit line, as shown in Figure 2 The electric field at the slit 11 is large, and under the large electric field, even perforation may occur between the adjacent bit lines 12. In addition, with the reduction of the width of the bit line 12 in the second direction, the contact resistance of the contact plug 20 in contact with the bit line 12 is large.

[0081] To solve the above problems, the embodiments of the present application provide a semiconductor structure and a preparation method thereof. A plurality of first mask patterns are formed in the array region and the isolation region along the second direction, respectively. Then, the first mask pattern in the array region is continuously etched to form a second mask pattern, so that the feature size of the second mask pattern in the second direction is smaller than that of the first mask pattern in the second direction. The conductive layer on the substrate is etched by using the first mask pattern and the second mask pattern, so that the conductive layer remaining in the array region and the isolation region is formed into a plurality of spaced conductive structures. Thus, the feature size of the conductive structure in the isolation region in the second direction is larger than that of the conductive structure in the array region in the second direction, the conductive structure in the isolation region is connected with the conductive structure in the array region corresponding thereto in the same extension direction, and the first contact plug is formed on the conductive structure in the isolation region. In this way, the miniaturization of the semiconductor structure is met, the feature size of the conductive structure in the isolation region in the second direction is increased, the over-etching or perforation phenomenon caused by the fast etching speed of the exposed part on both sides of the conductive structure in the isolation region during the manufacture of the first contact plug is reduced, and the contact resistance of the first contact plug is reduced, thereby improving the reliability of the electrical performance of the semiconductor structure.

[0082] In order to make the above objectives, characteristics and advantages of the embodiments of the present application more apparent, clearly and completely, the technical solutions in the embodiments of the present application will be described in detail below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of the present application.

[0083] Figure 4 A flowchart of a preparation method of a semiconductor structure provided by another embodiment of the present application is shown in FIG. 6; Figure 5 A top view of a semiconductor structure in which a gate is formed in a peripheral circuit region provided by another embodiment of the present application is shown in FIG. 7; Figure 6 A top view of a semiconductor structure in which a gate is formed in a peripheral circuit region provided by another embodiment of the present application is shown in FIG. 7; Figure 5 A cross-sectional view of the semiconductor structure at A-A in FIG. 7 is shown in FIG. 8; Figure 7 A top view of a semiconductor structure in which a first mask pattern is formed in a preparation process provided by another embodiment of the present application is shown in FIG. 9; Figure 8 A cross-sectional view of a semiconductor structure in which a first mask pattern is formed in a preparation process provided by another embodiment of the present application is shown in FIG. 10; Figure 9 A top view of a semiconductor structure in which a second mask pattern is formed in a preparation process provided by another embodiment of the present application is shown in FIG. 11; Figure 10 A cross-sectional view of a semiconductor structure in which a second mask pattern is formed in a preparation process provided by another embodiment of the present application is shown in FIG. 12; Figure 11 A top view of a semiconductor structure in which a first mask layer of an isolation region is removed in a preparation process provided by another embodiment of the present application is shown in FIG. 13;

[0084] Figure 12 A cross-sectional view of a semiconductor structure in which a first mask layer of an isolation region is removed in a preparation process provided by another embodiment of the present application is shown in FIG. 14; Figure 13 A cross-sectional view of a semiconductor structure in which a conductive structure is formed in a preparation process provided by another embodiment of the present application is shown in FIG. 15; Figure 14 A cross-sectional view of a semiconductor structure in which a dielectric layer is formed on the conductive structure provided by another embodiment of the present application is shown in FIG. 16; Figure 15 A top view of a semiconductor structure in which a first trench and a second trench are formed in a preparation process provided by another embodiment of the present application is shown in FIG. 17; Figure 16 A cross-sectional view of a semiconductor structure in which a first trench and a second trench are formed in a preparation process provided by another embodiment of the present application is shown in FIG. 18; Figure 17 A cross-sectional view of a semiconductor structure in which a first contact plug and a second contact plug are respectively formed in the first trench and the second trench provided by another embodiment of the present application is shown in FIG. 19.

[0085] Please refer to Figure 4As shown, the embodiment of the present application provides a preparation method of a semiconductor structure, which comprises:

[0086] Step S101: providing a substrate, and forming a conductive layer on the substrate, the substrate having an array region, an isolation region and a peripheral circuit region, the isolation region being located between the array region and the peripheral circuit region.

[0087] Please refer to Figure 5 and Figure 6 As shown, the substrate 100 can provide a structural basis for subsequent structures and processes, and the material of the substrate 100 can include any one or more of silicon, germanium, silicon germanium, silicon carbide, a silicon-on-insulator substrate and a germanium-on-insulator substrate. In the embodiment, at least part of the substrate is a silicon substrate, and the silicon material can be monocrystalline silicon. The substrate can be prepared by a chemical vapor deposition (CVD) method.

[0088] The array region can be formed with capacitors, bit lines, word lines and the like, and the word lines and bit lines in the array region also extend into the isolation region. The peripheral circuit region can be formed with peripheral circuits, such as transistors, which include gates 180 and source / drain electrodes. In subsequent processes, a first contact plug is formed on the bit line in the isolation region, so that the bit line is electrically connected to the drain electrode in the transistor through the first contact plug.

[0089] In some embodiments, the step of forming the conductive layer 110 on the substrate 100 specifically comprises:

[0090] The first conductive layer 111, the second conductive layer 112 and the third conductive layer 113 can be sequentially formed on the substrate 100 by a CVD process or an atomic layer deposition (ALD) process, and the first conductive layer 111, the second conductive layer 112 and the third conductive layer 113 collectively form the conductive layer 110, wherein the first conductive layer 111, the second conductive layer 112 and the third conductive layer 113 are sequentially stacked from bottom to top along the thickness direction of the substrate 100.

[0091] Taking the preparation of a bit line as an example, the first conductive layer 111 can be a bit line contact layer, the second conductive layer 112 can be a bit line barrier layer, and the third conductive layer 113 can be a bit line conductive layer. It can be understood that the bit line contact layer can be electrically connected to the source region or the drain region of an active region in the substrate, and the material of the bit line contact layer can be polysilicon or the like; the material of the bit line barrier layer can include but is not limited to titanium nitride, so as to prevent the conductive material in the bit line conductive layer from diffusing into the substrate, while also having conductive capability; the bit line conductive layer can include but is not limited to tungsten or other conductive materials.

[0092] In addition, in order to realize electrical isolation between the conductive layer 110 and other devices in the semiconductor structure, in the embodiment of the present application, the conductive layer 110 can further be provided with an insulating layer 114, and the material of the insulating layer 114 can be silicon nitride or other insulating materials, so as to realize electrical isolation between the bit line conductive layer and other devices on the substrate through the insulating layer.

[0093] The isolation region can be divided into a first region and a second region, wherein the first region is arranged close to the array region, and the second region is arranged close to the peripheral circuit region.

[0094] For the convenience of description, in the embodiment of the present application, the array region can be represented by I, the first region in the isolation region is represented by II, the second region is represented by III, and the peripheral circuit region is represented by IV.

[0095] After the conductive layer 110 is formed on the substrate 100, the conductive layer 110 in the second region and part of the conductive layer 110 in the peripheral circuit region can be removed, and the conductive layer 110 remaining in the peripheral circuit region is formed as a gate electrode 180 of a transistor, as shown in Figure 5 and Figure 6 .

[0096] Step S102: forming a first mask layer on the conductive layer, and the first mask layer corresponding to the array region and the isolation region has a plurality of first mask patterns, and each first mask pattern extends along a first direction.

[0097] Please refer to Figure 7 and Figure 8 , in some embodiments, the first mask layer 120 can include a first initial mask base layer and a first mask pattern layer formed on the first initial mask base layer, that is, the first mask pattern layer is arranged on the side of the first initial mask base layer away from the substrate 100, wherein the first mask pattern layer includes a plurality of first mask patterns 121, and exemplarily, the first mask pattern 121 can be a plurality of column bodies arranged at intervals along a second direction.

[0098] In some embodiments, forming the first mask layer 120 on the conductive layer 110 can include: forming a first initial mask base layer on the conductive layer 110, and forming a first initial mask pattern layer on the first initial mask base layer corresponding to the array region and the isolation region; the first mask pattern layer can be patterned by exposure, development and the like to form a plurality of first mask patterns 121.

[0099] The first initial mask base layer and the first mask pattern layer can be formed by CVD process, ALD process or physical vapor deposition process. The material of the first initial mask base layer can be silicon oxynitride, and the first initial mask pattern layer can be photoresist, which can be an organic compound sensitive to light (for example, ultraviolet light), such as polyvinyl alcohol silicate.

[0100] For ease of description, a feature size of the first mask pattern 121 in the second direction (e.g. a width of the first mask pattern 121 in the second direction) can be represented by a first size.

[0101] In addition, the first initial mask base layer is formed on the conductive layer 110 of the array region and the isolation region, and simultaneously formed on the peripheral circuit region, where the first initial mask base layer can be a single layer or multiple layers, which can be set according to actual needs, and is not specifically limited here.

[0102] Step S103: Form a second mask layer on the first mask layer of the isolation region, and etch the first mask layer of the array region with the second mask layer as a mask, so that the first mask pattern in the first mask layer of the array region is formed into a second mask pattern.

[0103] Please refer to Figure 9 and Figure 10 The second mask layer 130 can be formed on the first mask layer 120 of the isolation region by a CVD process, an ALD process or a physical vapor deposition process, and the second mask layer 130 is formed on the first mask layer 120 of the isolation region at the same time, and the second mask layer 130 is formed on the peripheral circuit region, that is, the second mask layer 130 covers the isolation region and the peripheral circuit region. The first mask pattern 121 of the array region is etched with the second mask layer 130 as a mask by a wet etching process or a dry etching process, so that the first mask pattern 121 is formed into a second mask pattern 122, as shown in Figure 10 The feature size of the second mask pattern 122 in the second direction (e.g. the width of the cross section of the second mask pattern 122 in the second direction) is a second size, and the second size is smaller than the first size.

[0104] It can be understood that the first mask pattern 121 of the array region is etched with the second mask layer 130 as a mask to reduce the feature size of the first mask pattern 121 in the second direction. For example, when the first mask pattern 121 is a column, the second mask pattern 122 is also a column, and the width of the cross section of the column corresponding to the second mask pattern 122 in the second direction (the second size) is smaller than the width of the cross section of the column corresponding to the first mask pattern 121 in the second direction (the first size), so that the feature sizes of the conductive structures 140 formed by the first mask pattern 121 and the second mask pattern 122 in the subsequent process are different.

[0105] Step S104: etching the conductive layer by using the first mask pattern and the second mask pattern, so as to form the conductive layer remained in the array region and the isolation region into a plurality of spaced conductive structures; the feature size of the conductive structure in the array region in the second direction is smaller than the feature size of the conductive structure in the isolation region in the second direction, and the conductive structure in the isolation region is connected with the conductive structure in the array region corresponding thereto in the same extension direction, wherein the first direction and the second direction are perpendicular to each other.

[0106] It can be understood that, as the critical dimension of the semiconductor chip and other structures is continuously reduced, the integration of the array region is higher and higher, and the critical dimension of each structure is smaller and smaller, thus leading to the increase of the difficulty of the process technology. In the embodiment of the present application, the conductive structure 140 formed in the isolation region is connected with the conductive structure 140 in the array region corresponding thereto in the same extension direction, and the electrical connection between the first contact plug 160 formed in the isolation region in the subsequent process and the external electrical device is realized, so that the integration of the semiconductor structure can be improved while the difficulty of the process technology of the semiconductor structure is reduced.

[0107] In the specific implementation, please refer to Figure 11 and Figure 12 After the first mask pattern 121 in the array region is etched into the second mask pattern 122 by taking the second mask layer 130 as a mask, the second mask layer 130 in the first region of the isolation region is removed to expose the first mask pattern 121 in the first region, and the conductive layer 110 corresponding to the array region and the isolation region is etched by using the second mask pattern 122 in the array region and the first mask pattern 121 in the first region of the isolation region as masks respectively through the etching process, so as to retain the conductive layer 110 covered by the first mask pattern 121 and the second mask pattern 122, so that the conductive layer 110 covered by the first mask pattern 121 in the isolation region is formed into the conductive structure 140 of the isolation region, and the conductive layer 110 covered by the second mask pattern 122 in the array region is formed into the conductive structure 140 of the array region, as shown in Figure 13 , and the feature size of the conductive structure 140 in the array region in the second direction is smaller than the feature size of the conductive structure 140 in the isolation region in the second direction, and the conductive structure 140 in the isolation region is connected with the conductive structure 140 in the array region corresponding thereto in the same extension direction, that is, taking the conductive structure 140 as a bit line as an example, the feature size of the part of the bit line in the array region in the second direction is smaller than the feature size of the part of the bit line in the isolation region in the second direction, and the first contact plug 160 is formed on the conductive structure 140 in the isolation region in the subsequent process; wherein the first direction and the second direction are perpendicular to each other.

[0108] For example, the etching process includes but is not limited to wet etching or dry etching.

[0109] Since the feature size of the first mask pattern 121 is different from the feature size of the second mask pattern 122 in the second direction, when the conductive layer is etched by using the first mask pattern 121 and the second mask pattern 122, the etching amount of the conductive layer to be etched in the array region is different from the etching amount of the conductive layer to be etched in the isolation region. In order to make the conductive structures 140 in the array region and the isolation region be formed synchronously, in the embodiment of the present application, the conductive layer 110 is etched by using the first mask pattern 121 and the second mask pattern 122, so that the conductive layer 110 reserved in the array region and the isolation region is formed into a plurality of spaced conductive structures 140, specifically including:

[0110] The conductive layer 110 in the array region is etched by using the first etching selection ratio, and the conductive layer 110 in the isolation region is etched by using the second etching selection ratio, so as to form the conductive structures 140 in the array region and the isolation region synchronously. Since the feature size of the first mask pattern 121 is greater than the feature size of the second mask pattern 122, the feature size of the conductive structure 140 formed in the array region in the second direction is smaller than the feature size of the conductive structure 140 formed in the isolation region in the second direction.

[0111] It can be understood that the first etching selection ratio can be different from the second etching selection ratio. Since the feature size of the conductive structure 140 in the array region is smaller than the feature size of the conductive structure 140 in the isolation region, the etching amount of the conductive layer 110 to be etched in the array region is greater than the etching amount of the conductive layer 110 to be etched in the isolation region. Therefore, the second etching selection ratio can be smaller than the first etching selection ratio, that is, in the embodiment of the present application, the etching selection ratio of the array region and the isolation region when etching the conductive layer 110 can be adjusted respectively to meet the case that the etching amount of the conductive layer 110 in the array region and the etching amount of the conductive layer 110 in the isolation region to be etched are different, so that the conductive structure 140 in the array region and the conductive structure 140 in the isolation region are formed synchronously, thereby improving the reliability of the conductive structure 140 in the preparation process.

[0112] Step S105: forming a first contact plug on the conductive structure in the isolation region.

[0113] In some embodiments, the first contact plug 160 is formed on the conductive structure 140 in the isolation region, specifically including:

[0114] After the plurality of conductive structures 140 are formed in the array region and the isolation region, a dielectric layer 150 is formed between adjacent conductive structures 140 and on the conductive structures 140, such as Figure 14The surface of the medium layer 150 is formed as a flat surface; the medium layer 150 on each conductive structure 140 in the isolation region is removed to form a first trench 151, the first trench 151 exposes the surface of the conductive structure 140, in particular, the first trench 151 exposes the surface of the conductive layer (for example, the third conductive layer) of the conductive structure 140; and the conductive material is filled in the first trench 151, the conductive material in the first trench 151 is formed as a first contact plug 160 in contact with the conductive structure 140. The conductive material includes but is not limited to tungsten and the like.

[0115] In some embodiments, the removing the medium layer 150 on each conductive structure 140 in the isolation region to form the first trench 151 specifically includes: forming a third mask layer on the medium layer 150, and patterning the third mask layer to expose the surface of the medium layer 150 corresponding to the conductive structure 140 in the isolation region by the patterned third mask layer, and etching the exposed medium layer 150 in the isolation region to form the first trench 151 by taking the patterned third mask layer as a mask, wherein the first trench 151 exposes the surface of the conductive structure 140, and the first contact plug 160 is formed in the first trench 151 by CVD, ALD or the like process.

[0116] In addition, the patterned third mask layer also exposes the surface of the medium layer 150 corresponding to the source / drain of the transistor in the peripheral circuit region, so that the medium layer 150 of the peripheral circuit region can be etched synchronously to form a second trench 152 exposing the source / drain while etching to form the first trench 151, as shown in Figure 15 and Figure 16 The surface of the medium layer 150 is formed as a flat surface; the medium layer 150 on each conductive structure 140 in the isolation region is removed to form a first trench 151, the first trench 151 exposes the surface of the conductive structure 140, in particular, the first trench 151 exposes the surface of the conductive layer (for example, the third conductive layer) of the conductive structure 140; and the conductive material is filled in the first trench 151, the conductive material in the first trench 151 is formed as a first contact plug 160 in contact with the conductive structure 140. The conductive material includes but is not limited to tungsten and the like. Figure 17

[0117] In addition, after the conductive structure 140 is formed in the array region and the isolation region, and before the first contact plug 160 is formed on the conductive structure 140 in the isolation region, the first mask layer 120 in the array region and the isolation region is also removed.

[0118] ​In the above scheme, the first mask patterns are formed in the array region and the isolation region, respectively, and then the first mask patterns in the array region are etched to form second mask patterns, so that the feature size of the second mask patterns in the second direction is smaller than that of the first mask patterns in the second direction. The conductive layer on the substrate is etched by using the first mask patterns and the second mask patterns, so that the conductive layer remaining in the array region and the isolation region forms a plurality of spaced conductive structures. Thus, the feature size of the conductive structure in the isolation region in the second direction is larger than that of the conductive structure in the array region in the second direction, and the conductive structure in the isolation region is connected to the corresponding conductive structure in the array region in the same extension direction, and the first contact plug is formed on the conductive structure in the isolation region. In this way, while meeting the miniaturization of the semiconductor structure, the feature size of the conductive structure in the isolation region in the second direction is increased, and the phenomenon of over-etching or even perforation caused by fast etching speed of the exposed parts on both sides of the conductive structure in the isolation region during preparation of the first contact plug is reduced. In addition, by increasing the feature size of the conductive structure in the isolation region, the contact resistance of the first contact plug can be reduced, thereby improving the reliability of the electrical performance of the semiconductor structure.

[0119] Please continue to refer to Figure 17 As shown in FIG. 1, the semiconductor structure provided by the embodiment of the present application includes a substrate 100, and the substrate 100 has an array region, an isolation region and a peripheral circuit region. The isolation region is located between the array region and the peripheral circuit region, i.e., the array region and the isolation region are arranged adjacently, and the isolation region and the peripheral circuit region are arranged adjacently.

[0120] In some embodiments, the array region and the isolation region are respectively provided with a plurality of conductive structures 140 extending in a first direction, and the plurality of conductive structures 140 can be arranged spaced apart in a second direction, wherein the first direction is perpendicular to the second direction.

[0121] In addition, the feature size of the conductive structure 140 in the array region in the second direction is smaller than that of the conductive structure 140 in the isolation region in the second direction, and the conductive structure 140 in the isolation region is connected to the corresponding conductive structure 140 in the array region in the same extension direction. A first contact plug 160 is arranged on the conductive structure 140 in the isolation region and is in contact with the conductive structure 140 in the isolation region, so that the conductive structure 140 in the array region is electrically connected to an external electrical device through the conductive structure 140 in the isolation region and the first contact plug 160.

[0122] The array region can be provided with a capacitor and a conductive structure 140, and the conductive structure 140 can be a bit line, a word line or the like. In the present application, the conductive structure 140 is taken as an example of a bit line.

[0123] In addition, the feature size of the conductive structure 140 in the second direction can be the width dimension of the cross section of the conductive structure 140 perpendicular to the extension direction of the conductive structure 140 in the second direction. In the subsequent description, the feature size of the conductive structure 140 refers to the width dimension of the cross section of the conductive structure 140 perpendicular to the extension direction of the conductive structure 140 in the second direction.

[0124] In some embodiments, the peripheral circuit region can be provided with a peripheral circuit, for example, a transistor including a gate 180 and a source / drain, and a second contact plug 170 can be disposed on the source / drain to contact and connect the source / drain, so as to realize electrical connection between the transistor and other components.

[0125] In the above scheme, by making the feature size of the conductive structure 140 in the second direction of the isolation region greater than the feature size of the conductive structure 140 in the second direction of the array region, and connecting the conductive structure 140 of the isolation region and the conductive structure 140 of the array region corresponding to the same extension direction, and forming a first contact plug 160 on the conductive structure 140 of the isolation region, so that the conductive structure 140 of the array region is electrically connected between the external electronic components through the conductive structure 140 of the isolation region and the first contact plug 160, in this way, while meeting the miniaturization of the semiconductor structure, the feature size of the conductive structure 140 of the isolation region in the second direction is increased, and the phenomenon of over-etching or even perforation caused by fast etching speed of the exposed part on both sides of the conductive structure of the isolation region when preparing the first contact plug 160 is reduced. In addition, by increasing the feature size of the conductive structure of the isolation region, the contact resistance of the first contact plug can be reduced, thereby improving the reliability of the electrical performance of the semiconductor structure.

[0126] In some optional embodiments, the feature size of the conductive structure 140 of the array region in the second direction is 0.5-0.8 times the feature size of the conductive structure 140 of the isolation region in the second direction, for example, the feature size of the conductive structure 140 of the array region in the second direction is 0.5 times, 0.6 times, 0.7 times or 0.8 times the feature size of the conductive structure 140 of the isolation region in the second direction, and the specific value can be adaptively designed according to actual needs, which is not limited here.

[0127] In some optional embodiments, the feature size of the first contact plug 160 of the isolation region in the second direction is not less than the feature size of the conductive structure 140 of the isolation region in the second direction, in this way, while meeting the miniaturization of the semiconductor structure, the contact resistance of the first contact plug 160 is reduced, thereby improving the reliability of the electrical performance of the semiconductor structure.

[0128] In the semiconductor structure and the preparation method thereof provided by the embodiments of the present application, a plurality of first mask patterns are formed in the array region and the isolation region in the second direction, then the first mask patterns in the array region are etched to form second mask patterns, so that the feature size of the second mask patterns in the second direction is smaller than that of the first mask patterns in the second direction, and the conductive layer on the substrate is etched by using the first mask patterns and the second mask patterns, so that the conductive layer reserved in the array region and the isolation region is formed into a plurality of spaced conductive structures, thereby making the feature size of the conductive structure in the isolation region in the second direction larger than that of the conductive structure in the array region in the second direction, and the conductive structure in the isolation region is connected with the conductive structure in the array region corresponding to it in the same extension direction, and the first contact plug is formed on the conductive structure in the isolation region. In this way, the feature size of the conductive structure in the isolation region in the second direction is increased while the miniaturization of the semiconductor structure is met, and the phenomenon of over-etching or even perforation caused by the fast etching speed of the exposed parts on both sides of the conductive structure in the isolation region when the first contact plug is prepared is reduced. In addition, by increasing the feature size of the conductive structure in the isolation region, the contact resistance of the first contact plug can be reduced, thereby improving the reliability of the electrical performance of the semiconductor structure.

[0129] In the description of the present specification, each embodiment or implementation is described in a progressive manner, and each embodiment focuses on the difference from other embodiments. The same or similar parts between embodiments can be referred to each other.

[0130] In the description of the present specification, the description of the terms "one embodiment", "some embodiments", "exemplary embodiment", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the present specification, the exemplary description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0131] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement to part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, and a conductive layer is formed on the substrate, the substrate having an array region, an isolation region, and a peripheral circuit region, the isolation region being located between the array region and the peripheral circuit region; A first mask layer is formed on the conductive layer. The first mask layer corresponding to the array region and the isolation region has a plurality of first mask patterns, and each first mask pattern extends along a first direction. A second mask layer is formed on the first mask layer in the isolation region, and the first mask layer in the array region is etched using the second mask layer as a mask, so that the first mask pattern in the first mask layer of the array region is formed as the second mask pattern; The conductive layer is etched using the first mask pattern and the second mask pattern to form a plurality of spaced conductive structures in the conductive layer retained in the isolation region and the array region; the feature size of the conductive structure in the array region in the second direction is smaller than the feature size of the conductive structure in the isolation region in the second direction, and the conductive structure in the isolation region is connected to the conductive structure in the array region corresponding to it in the same extension direction, wherein the first direction and the second direction are perpendicular to each other; A first contact plug is formed on the conductive structure of the isolation zone.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, The step of forming a first mask layer on the conductive layer, wherein the first mask layer corresponding to the array region and the isolation region has multiple first mask patterns, specifically includes: A first initial mask base layer is formed on the conductive layer using one of atomic layer deposition, chemical vapor deposition, or physical vapor deposition processes. A first mask pattern layer is formed on the first initial mask base layer corresponding to the array region and the isolation region; The first mask pattern layer is patterned to form a plurality of first mask patterns, wherein the first initial mask base layer and the first mask pattern layer together form the first mask layer; wherein the feature size of the first mask pattern in the second direction is a first size.

3. The method for preparing a semiconductor structure according to claim 2, characterized in that, The step of etching the first mask layer of the array region using the second mask layer as a mask includes: Using the second mask layer as a mask, each of the first mask patterns in the array region is etched using a wet etching or dry etching process, so that the first mask pattern is formed into a second mask pattern, wherein the feature size of the second mask pattern in the second direction is the second size; The second dimension is smaller than the first dimension.

4. The method for preparing a semiconductor structure according to any one of claims 1-3, characterized in that, The step of etching the conductive layer using the first mask pattern and the second mask pattern to form the conductive layer retained in the array region and the isolation region into a plurality of spaced conductive structures includes: Using the first mask pattern as a mask, the conductive layer of the array region is etched; simultaneously, using the second mask pattern as a mask, the conductive layer of the isolation region is etched, so as to synchronously form conductive structures in the array region and the isolation region respectively.

5. The method for preparing a semiconductor structure according to claim 4, characterized in that, The step of forming the first contact plug on the conductive structure of the isolation region specifically includes: A dielectric layer is formed between adjacent conductive structures and on the conductive structures; The dielectric layer on each of the conductive structures in the isolation region is removed to form a first trench, the first trench exposing the surface of the conductive structure; The first trench is filled with conductive material, and the conductive material in the first trench is formed as a first contact plug that contacts and connects with the conductive structure.

6. The method for preparing a semiconductor structure according to any one of claims 1-3, characterized in that, While forming a second mask layer on the first mask layer in the isolation area, the method also includes: A second mask layer is simultaneously formed in the peripheral circuit area.

7. The method for preparing a semiconductor structure according to claim 5, characterized in that, Also includes: While forming the first contact plug on the conductive structure of the isolation zone, a second contact plug is simultaneously formed in the peripheral circuit zone; The peripheral circuit area includes a transistor, the transistor having a source and a drain, and the second contact plug being electrically connected to the source and drain.

8. The method for preparing a semiconductor structure according to claim 7, characterized in that, The step of simultaneously forming a first contact plug on the conductive structure of the isolation region and a second contact plug in the peripheral circuit region includes: While forming dielectric layers between adjacent conductive structures and on the conductive structures, a dielectric layer is simultaneously formed on the peripheral circuit region. While removing the dielectric layer on each of the conductive structures in the isolation region to form a first trench, the dielectric layer on the source / drain in the peripheral circuit region is simultaneously removed to form a second trench, the second trench exposing the surface of the source / drain; While filling the first trench with conductive material, simultaneously fill the second trench with conductive material, so that the conductive material in the second trench forms a second contact plug electrically connected to the source / drain electrode.

9. The method for preparing a semiconductor structure according to any one of claims 1-3, characterized in that, The step of forming a conductive layer on the substrate specifically includes: A first conductive layer is formed on the substrate; A second conductive layer is formed on the first conductive layer; A third conductive layer is formed on the second conductive layer, and the first conductive layer, the second conductive layer and the third conductive layer together form the conductive layer.

10. The method for preparing a semiconductor structure according to claim 6, characterized in that, After etching the first mask layer of the array region to form the first mask pattern in the first mask layer of the array region as the second mask pattern, the method further includes: The second mask layer on the side of the isolation region closest to the array region is removed, while the second mask layer on the side of the isolation region closest to the peripheral circuit region is retained. The region corresponding to the isolation region with the second mask layer removed is formed as a first region, and the region corresponding to the isolation region with the second mask layer retained is formed as a second region.

11. The method for preparing a semiconductor structure according to claim 10, characterized in that, After the conductive structures are formed in both the array region and the isolation region, and before the first contact plug is formed on the conductive structure in the isolation region, the method further includes: Remove the first mask layer from the array region and the isolation region.

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