Detection device

Abstract

The detection device has a pixel in which a photoelectric conversion element is connected to the gate electrode of a first transistor; has a reset period for resetting the gate electrode of the first transistor, an exposure period for exposing the photoelectric conversion element, and a readout period for reading a voltage accompanying the exposure of the photoelectric conversion element; during the reset period, a first voltage is read out during a first period in which a reset voltage is supplied to the gate electrode of the first transistor, a second voltage is read out during a second period after supply of the reset voltage to the gate electrode of the first transistor is stopped, and a third voltage is read out during a fourth period as the above-mentioned readout period after a third period as the exposure period; a difference between the first voltage and the second voltage is output as PUF-ID data; and a difference between the third voltage and the second voltage is output as detection data.

Description

Technical Field

[0001] The invention relates to a detection device and a driving method of the detection device. Background Art

[0002] In recent years, imitation, pirated or counterfeit products have become a problem with electronic components having semiconductor integrated circuits, electronic devices having the electronic components, or systems using the electronic components. For example, in order to prevent the manufacture of imitation, pirated or counterfeit products of the electronic components, the electronic devices, or systems using the electronic components, one of the countermeasures against these problems is to adopt encryption technology using a secret key.

[0003] Furthermore, as another countermeasure to these problems, Patent Documents 1 and 2 disclose solid-state imaging devices capable of generating imaging data using PUF (Physical Unclonable Function).

[0004] Prior art literature

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent Application Publication No. 2019-180003

[0007] Patent Document 2: International Publication No. 2016 / 167076 Summary of the invention

[0008] Problems to be solved by the invention

[0009] One of the objects of the present invention is to provide a detection device capable of generating image data using PUF in order to suppress the production of counterfeit, pirated or forged products.

[0010] Means used to solve problems

[0011] The detection device has at least one pixel in which the first electrode of the photoelectric conversion element is connected to the gate electrode of the first transistor connected between the power line and the readout signal line; and has: during a reset period, the gate electrode of the first transistor is reset; during an exposure period, the photoelectric conversion element is exposed; and during a readout period, the voltage accompanying the exposure of the photoelectric conversion element is read out; during the reset period, during a first period in which the reset voltage is supplied to the gate electrode of the first transistor, the first voltage is read out from the readout signal line; during a second period after the supply of the reset voltage to the gate electrode of the first transistor is stopped, the second voltage is read out from the readout signal line; after a third period as the exposure period, during a fourth period as the above-mentioned readout period, the third voltage is read out from the readout signal line; the difference between the first voltage and the second voltage is output as PUF-ID data; and the difference between the third voltage and the second voltage is output as detection data. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 It is a plan view showing the structure of a detection device according to one embodiment of the present invention.

[0013] Figure 2 It is a plan view showing the structure of a detection device according to one embodiment of the present invention.

[0014] Figure 3 : is a circuit diagram showing a pixel circuit according to one embodiment of the present invention.

[0015] Figure 4 This is a timing chart showing a method for driving the detection device according to one embodiment of the present invention.

[0016] Figure 5 Yes means Figure 4 A schematic diagram showing the operation state of a pixel at the timing shown.

[0017] Figure 6 Yes means Figure 4 A schematic diagram showing the operation state of a pixel at the timing shown.

[0018] Figure 7 Yes means Figure 4 A schematic diagram showing the operation state of a pixel at the timing shown.

[0019] Figure 8 Yes means Figure 4 A schematic diagram showing the operation state of a pixel at the timing shown.

[0020] Fig. 9 It is a plan view showing the structure of a detection device according to one embodiment of the present invention.

[0021] Fig.10 : is a circuit diagram showing a pixel circuit according to one embodiment of the present invention.

[0022] Fig.11 This is a timing chart showing a method for driving the detection device according to one embodiment of the present invention.

[0023] Fig.12 Yes means Fig.11 A schematic diagram showing the operation state of a pixel at the timing shown.

[0024] Fig.13 Yes means Fig.11 A schematic diagram showing the operation state of a pixel at the timing shown.

[0025] Fig.14 Yes means Fig.11 A schematic diagram showing the operation state of a pixel at the timing shown.

[0026] Fig.15 Yes means Fig.11 A schematic diagram showing the operation state of a pixel at the timing shown.

[0027] Fig.16 This is a flowchart showing a driving method of the detection device using one embodiment of the present invention. DETAILED DESCRIPTION

[0028] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings, etc. However, the present invention can be implemented in many different forms, and is not limited to the description of the embodiments illustrated below. In addition, the accompanying drawings schematically show the width, thickness, shape, structure, etc. of each part compared to the actual form in order to make the description clearer, but this is only an example and does not limit the interpretation of the present invention. In addition, the characters "1st" and "2nd" attached to each element are convenient identifiers used to distinguish each element, and do not have any further meaning unless otherwise specified.

[0029] The detection device includes a device for detecting biometric information such as fingerprints, and a solid-state imaging device. Examples of solid-state imaging devices include CMOS (Complementary Metal Oxide Semiconductor) image sensors, CCD (Charge Coupled Device) image sensors, and the like. A solid-state imaging device according to one embodiment of the present invention is, for example, a CMOS image sensor. In this specification, a solid-state imaging device is used as an example for explanation, but the content of the present invention is not limited to a solid-state imaging device, and can of course be applied to detection devices such as fingerprint sensors for detecting biometric information. In addition, when the present invention is applied to detection devices such as fingerprint sensors, the imaging data described later may also be referred to as detection data.

[0030] <1. First Implementation Method>

[0031] <1-1. Configuration of Solid-State Imaging Device 100 >

[0032] Figure 1 and Figure 2 1 is a schematic plan view showing the structure of a solid-state imaging device 100 according to an embodiment of the present invention. The structure of the solid-state imaging device 100 according to an embodiment of the present invention is not limited to Figure 1 and Figure 2 The structure shown.

[0033] like Figure 1 As shown, the solid-state imaging device 100 includes a power supply circuit 200, a drive timing control circuit 300, a row selection circuit 400, a pixel portion 504, a readout circuit 600, and a signal processing circuit 700. The pixel portion 504 includes a plurality of pixels 502 for capturing an image of a subject.

[0034] The plurality of pixels 502 are arranged in a matrix in the x direction and the y direction intersecting the x direction. The plurality of pixels 502 each have a plurality of transistors ( Figure 3 ), multiple capacitor elements ( Figure 3 ), and light receiving element ( Figure 3 ), details will be described later. In one embodiment of the present invention, for example, the x direction is referred to as the first direction, and the y direction is referred to as the second direction. In addition, in one embodiment of the present invention, the light receiving element is represented as an example of a photoelectric conversion element that generates a photoelectromotive force, but one embodiment of the present invention is not limited to this example. In one embodiment of the present invention, a photodiode (Photo Diode, PD) is represented as a specific example of a photoelectric conversion element.

[0035] The power supply circuit 200 is electrically connected to the drive timing control circuit 300, the signal processing circuit 700, the readout circuit 600, and the row selection circuit 400. The power supply circuit 200 includes a logic circuit (not shown) and a voltage generation circuit (not shown). The power supply circuit 200 generates a signal or a power supply voltage using the logic circuit and the voltage generation circuit, and supplies the generated signal, power supply voltage, or power to the drive timing control circuit 300, the signal processing circuit 700, the readout circuit 600, and the row selection circuit 400.

[0036] The drive timing control circuit 300 is electrically connected to the signal processing circuit 700, the readout circuit 600, and the row selection circuit 400. The drive timing control circuit 300 generates, for example, timing signals required for signal processing by the signal processing circuit 700, the readout circuit 600, and the row selection circuit 400, and supplies the timing signals to the signal processing circuit 700, the readout circuit 600, and the row selection circuit 400. Regarding the timing control signal, for example, a clock signal and a start pulse for controlling row selection of the row selection circuit 400 are generated, and the generated signals are supplied to the row selection circuit 400.

[0037] The row selection circuit 400 is, for example, arranged at a position adjacent to the pixel portion 504 in the x direction. The row selection circuit 400 is, for example, connected to the reset signal line 412 ( Figure 3 )、scanning signal line 410( Figure 3 )、Bias voltage supply line 418( Figure 3 ), the reference potential line PVSS, and the first drive power line PVDD1. The scanning signal line 410 is connected to a plurality of pixels 502 arranged in the same row.

[0038] The readout circuit 600 is connected to the signal processing circuit 700. The readout circuit 600 is arranged, for example, at a position adjacent to the pixel portion 504 in the y direction. The readout circuit 600 is connected to the plurality of readout signal lines 420 ( Figure 3 ), the second driving power line PVDD2 ( Figure 3 The readout signal line 420 is connected to a plurality of pixels 502 arranged in the same column.

[0039] The readout circuit 600 includes, for example, an AD converter (not shown) and a horizontal transfer scanning circuit (not shown). The AD converter outputs the output signal OUT(n) ( Figure 4 ) is converted into a digital signal. The digital signal is transmitted to the horizontal transfer scanning circuit. The horizontal transfer scanning circuit reads out the digital signal in each column in sequence. The horizontal transfer scanning circuit can read out the output signal OUT(n) corresponding to each of the plurality of pixels 502 connected to the row selected by the row selection circuit 400 as a digital signal. The readout circuit 600 receives the output signal OUT(n) as input and outputs the digital signal.

[0040] The signal processing circuit 700 has a PUF-ID extraction circuit 710 and an image processing circuit 720. The PUF-ID extraction circuit 710 generates an identifier (ID) inherent to the solid-state imaging device 100, namely, a PUF-ID, using multiple digital signals output from the readout circuit 600, for example. The image processing circuit 720 performs image processing such as gamma correction and noise removal on the multiple digital signals output from the readout circuit 600 to generate image data. The image data is, for example, imaging data of the photographed subject. In addition, although omitted in the figure, the signal processing circuit 700, the PUF-ID extraction circuit 710 and the image processing circuit 720 respectively have an operation processing circuit and a storage circuit. In one embodiment of the present invention, the operation processing circuit is, for example, a processor, a CPU, etc., and the storage circuit is, for example, a volatile memory or a non-volatile memory.

[0041] like Figure 2 As shown, the row selection circuit 400 supplies a reset signal RG(n), a scan signal SG(n), a bias voltage supply signal VB, a reference potential VSS, and a first drive voltage VPP1 to a plurality of pixels 502 (pixel circuits 120) located in the nth row in the pixel portion 504 in common. The readout circuit 600 supplies a second drive voltage VPP2 to the pixel circuits 120 of a plurality of pixels 502 located in the mth column in the pixel portion 504. In one embodiment of the present invention, the plurality of pixels 502 are arranged, for example, in the x direction (first direction) in m pieces and in the y direction (second direction) in n pieces. The numerical value m and the numerical value n are natural numbers, respectively. For example, the pixels 502 arranged in 3 rows and 5 columns are referred to as the pixels 502 in 3 rows and 5 columns or the pixels 502 in the coordinates (3, 5).

[0042] A plurality of pixels 502 may include a plurality of sub-pixels respectively. For example, one pixel 502 may have three sub-pixels, and each of the three sub-pixels has a pixel circuit 120. The three sub-pixels may have color filters of different colors from each other. For example, the first sub-pixel of the three pixels has a red color filter, the second sub-pixel has a green color filter, and the third sub-pixel has a blue color filter. In addition, it may be that the three pixels 502 are taken as one unit, and the three pixels have color filters of different colors from each other. For example, the first pixel of the three pixels has a red color filter, the second pixel has a green color filter, and the third pixel has a blue color filter. The structure of pixels and sub-pixels is not limited to the example shown here. For example, a pixel 502 may have more than four sub-pixels having color filters of different colors from each other, or more than four pixels 502 having color filters of different colors from each other may be taken as one unit. The solid-state imaging device 100 according to one embodiment of the present invention includes four or more pixels or sub-pixels having color filters of mutually different colors, and can generate imaging data with high color reproducibility of an object.

[0043] In the solid-state imaging device 100 according to one embodiment of the present invention, the arrangement of the plurality of pixels 502 is shown as an example of a stripe arrangement. The arrangement of the plurality of pixels 502 is not limited and may be appropriately determined based on the application or specification of the solid-state imaging device 100, for example.

[0044] In addition, the signals, power, voltage, and power serving as the basis of each signal, power, voltage, and power may be supplied from an external circuit (not shown) to the power supply circuit 200, the drive timing control circuit 300, and the signal processing circuit 700. A desired signal, a desired power, a desired voltage, and a desired power processed in the power supply circuit 200, the drive timing control circuit 300, and the signal processing circuit 700 based on each signal, power, voltage, and power may be supplied to the row selection circuit 400, the pixel portion 504, and the readout circuit 600.

[0045] <1-2. Structure of pixel 502>

[0046] Figure 3 1 is a circuit diagram showing a pixel circuit 120 according to an embodiment of the present invention. Each of the plurality of pixels 502 includes a plurality of transistors, capacitors, and photoelectric conversion elements constituting the pixel circuit 120 . Figure 3 express Figure 2 The pixels 502 of n rows and m columns shown are components of the pixel circuit 120 . Figure 3 The structure of the pixel circuit 120 shown in the figure is an example, and the structure of the pixel circuit 120 is not limited to Figure 3 The structure shown. Figure 1 and Figure 2 The same or similar structures are omitted from description here.

[0047] like Figure 3 As shown, the pixel circuit 120 includes, for example, a reset transistor Mrst (first switch), a drive transistor Msf (second switch), a selection transistor Msw (third switch), a load transistor Mcc (fourth switch), a photoelectric conversion element PD, a first capacitor SC1, a second capacitor SC2, a third capacitor SC3, and a fourth capacitor SC4. These transistors each have a gate electrode (first electrode), a pair of electrodes consisting of a source electrode and a drain electrode (a pair of electrodes consisting of a second electrode and a third electrode). These capacitors each have a pair of electrodes (first electrode, second electrode). In addition, depending on the voltage applied to the source electrode and the drain electrode, the function of each electrode as a source and the function as a drain can be replaced.

[0048] The driving transistor Msf, the selection transistor Msw and the load transistor Mcc constitute a source follower 121. The source follower 121 is a so-called drain grounding circuit, which allows current to flow from the second driving power line PVDD2 to the reference potential line PVSS, and outputs an output signal OUT(n) corresponding to the voltage supplied to the gate electrode 620 (first electrode 620) of the driving transistor Msf.

[0049] As power sources for driving the pixel 502, a first driving voltage VPP1 is supplied from the first driving power line PVDD1, a second driving voltage VPP2 is supplied from the second driving power line PVDD2, a reference voltage VSS is supplied from the reference potential line PVSS, and a common voltage is supplied from the common potential line VCOM. The first driving power line PVDD1 is the first driving power line 414, the second driving power line PVDD2 is the second driving power line 428, and the reference potential line PVSS is the reference potential line 424. The common potential line VCOM is connected to the common electrode 422.

[0050] In one embodiment of the present invention, the first driving power line PVDD1, the second driving power line PVDD2, the reference potential line PVSS and the common potential line VCOM are commonly provided for a plurality of pixels 502, but the first driving power line PVDD1, the second driving power line PVDD2, the reference potential line PVSS and the common potential line VCOM may not be commonly provided for a plurality of pixels 502. The first driving voltage VPP1 may be the same as or substantially the same as the second driving voltage VPP2, or may be smaller than the second driving voltage VPP2. The first driving voltage VPP1 is a constant voltage, which is a voltage that can reset or initialize the pixel 502 by supplying a constant voltage to the node nodeA. The common voltage may be the same as or substantially the same as the reference voltage VSS, or may be smaller than the reference voltage VSS. The common voltage is a constant voltage, which is a voltage that can suppress the variation of the common electrode 422.

[0051] In addition, in one embodiment of the present invention, an example is shown in which the bias voltage supply signal VB, the reference potential line PVSS, and the first driving power line PVDD1 are provided in the row selection circuit 400, and the bias voltage Vbias, the reference voltage VSS, and the first driving voltage VPP1 are supplied to the plurality of pixels 502 from the row selection circuit 400, but the present invention is not limited to this example. The bias voltage supply signal VB, the reference potential line PVSS, and the first driving power line PVDD1 may also be provided in the readout circuit 600, or a part of the bias voltage supply signal VB, the reference potential line PVSS, and the first driving power line PVDD1 may be provided in the row selection circuit 400, and the remaining part may be provided in the readout circuit 600. An example is shown in which the second driving power line PVDD2 is provided in the readout circuit 600, and the second driving voltage VPP2 is supplied to the plurality of pixels 502 from the readout circuit 600, but the present invention is not limited to this example. The second driving power line PVDD2 may also be provided in the row selection circuit 400. The bias voltage supply signal VB, the reference potential line PVSS, the first driving power line PVDD1, and the second driving power line PVDD2 may be provided in the power circuit 200, and the bias voltage Vbias, the reference voltage VSS, the first driving voltage VPP1, and the second driving voltage VPP2 may be supplied to the plurality of pixels 502 from the power circuit 200. In addition, although not shown in the figure, for example, the common potential line VCOM is provided in the power circuit 200, and the common voltage is supplied to the common electrode 422 of the plurality of pixels 502 from the power circuit 200, but the present invention is not limited to this example. The common potential line VCOM may also be provided in the power circuit 200, and the common voltage may be supplied to the common electrode 422 of the plurality of pixels 502 from the power circuit 200 via the row selection circuit 400 or the readout circuit 600. In the solid-state imaging device 100 according to one embodiment of the present invention, the arrangement of the power lines and the like may be appropriately changed according to the application, specifications, and the like.

[0052] The reset transistor Mrst supplies the first drive voltage VPP1 to the node nodeA based on the reset signal RG(n), and sets the pixel 502 to a reset state or an initialization state. The node nodeA is connected to the gate electrode 620 (first electrode 620) of the drive transistor Msf, the first electrode of the photoelectric conversion element PD, the second electrode of the first capacitor, and the second electrode of the second capacitor.

[0053] The driving transistor Msf adjusts the current flowing in the source follower 121 of the pixel 502 in the reset state or the initialization state by using the input first driving voltage VPP1. In addition, the driving transistor Msf adjusts the current flowing in the source follower 121 by using the photoelectric electromotive force generated by the photoelectric conversion element PD based on the received light as the pixel 502 is exposed. In addition, in one embodiment of the present invention, the exposure of the pixel 502 can also be renamed as the pixel 502 receiving light and exposing the pixel 502, and the light receiving of the photoelectric conversion element PD can also be renamed as the exposure of the photoelectric conversion element PD and exposing the photoelectric conversion element PD.

[0054] The selection transistor Msw controls whether to drive the source follower 121 based on the scanning signal SG(n). That is, the selection transistor Msw controls whether current flows through the source follower 121 based on the scanning signal SG(n).

[0055] The load transistor Mcc controls whether to make a constant current flow from the second drive power line PVDD2 to the reference potential line PVSS based on the bias voltage supply signal VB. When the bias voltage Vbias is input to the load transistor Mcc, the load transistor Mcc becomes conductive, and makes a constant current flow from the second drive power line PVDD2 to the reference potential line PVSS. That is, the load transistor Mcc becomes a constant current source.

[0056] The first capacitor SC1 is provided between the gate electrode (first electrode) of the reset transistor Mrst and the source electrode or drain electrode (second electrode or third electrode) of the reset transistor Mrst. In addition, the first capacitor SC1 is provided between the reset signal line 412 and the node nodeA. The capacitance value of the first capacitor SC1 is the capacitance value Cgs (Mrst). The third capacitor SC3 is provided between the gate electrode 620 (first electrode 620) of the drive transistor Msf and the source electrode or drain electrode (third electrode 630) of the drive transistor Msf. In addition, the third capacitor SC3 is provided between the node nodeA and the second drive power supply line 428. The capacitance value of the third capacitor SC3 is the capacitance value Cgd (Msf). The fourth capacitor SC4 is provided between the gate electrode 620 (first electrode 620) of the drive transistor Msf and the source electrode or drain electrode (second electrode 610) of the drive transistor Msf. The capacitance value of the fourth capacitor SC4 is the capacitance value Cgs (Msf). The first capacitor SC1, the third capacitor SC3, and the fourth capacitor SC4 are, for example, parasitic capacitances and additional capacitances between each transistor and wiring, etc. The first capacitor SC1, the third capacitor SC3, and the fourth capacitor SC4 can hold a charge corresponding to the first drive voltage VPP1 supplied to the node nodeA, or a charge corresponding to the photoelectric electromotive force generated by the photoelectric conversion element PD based on the received light.

[0057] The second capacitor SC2 holds a charge corresponding to the first drive voltage VPP1 supplied to the node nodeA. In addition, the second capacitor SC2 holds a charge corresponding to the photoelectric electromotive force generated by the photoelectric conversion element PD based on the received light. The capacitance value of the second capacitor SC2 is the capacitance value Cdiode. The solid-state imaging device 100 according to one embodiment of the present invention has the second capacitor SC2, so that the discharge of the charge corresponding to the first drive voltage VPP1 can be suppressed, and the reset state or the initialization state of the pixel 502 can be maintained. In addition, the solid-state imaging device 100 according to one embodiment of the present invention has the second capacitor SC2, so that the discharge of the charge corresponding to the photoelectric electromotive force can be suppressed, and the exposure state of the pixel 502 can be maintained. As a result, the solid-state imaging device 100 according to one embodiment of the present invention can keep each voltage in the reset state, the initialization state, and the exposure state constant, so that the PUF-ID that can better suppress the manufacture of counterfeit products can be stably generated, and the imaging data of the subject can be stably generated, and the imaging data with the PUF-ID that can suppress counterfeiting can be stably generated.

[0058] The gate electrode (first electrode) of the reset transistor Mrst is electrically connected to the reset signal line 412. The reset signal line 412 is supplied with a reset signal RG(n). The conductive state and non-conductive state of the reset transistor Mrst are controlled by the signal supplied to the reset signal line 412. When the signal supplied to the reset signal line 412 is a high (High, H) level, the reset transistor Mrst becomes conductive. When the signal supplied to the reset signal line 412 is a low (Low, L) level, the reset transistor Mrst becomes non-conductive. The source electrode (second electrode) of the reset transistor Mrst is electrically connected to the first drive power line 414. The first drive power line 414 is supplied with the first drive voltage VPP1. The drain electrode (third electrode) of the reset transistor Mrst is connected to the node nodeA. In addition, in one embodiment of the present invention, the high level can be the first drive voltage VPP1 or the second drive voltage VPP2, and the low level can be the reference voltage VSS or the common voltage.

[0059] The gate electrode (first electrode) of the selection transistor Msw is electrically connected to the scanning signal line 410. The scanning signal SG(n) is supplied to the scanning signal line 410. The conducting state and the non-conducting state of the selection transistor Msw are controlled by the signal supplied to the scanning signal SG(n). When the signal supplied to the scanning signal SG(n) is at a high level, the selection transistor Msw becomes conducting. When the signal supplied to the scanning signal SG(n) is at a low level, the selection transistor Msw becomes non-conducting. The source electrode (second electrode) of the selection transistor Msw is electrically connected to the readout signal line 420 and the drain electrode (third electrode) of the load transistor Mcc. The readout signal line 420 is supplied with the output signal OUT(n).

[0060] The gate electrode (first electrode) of the load transistor Mcc is electrically connected to the bias voltage supply line 418. The bias voltage supply line 418 is supplied with a bias voltage supply signal VB. The conduction state and the non-conduction state of the load transistor Mcc are controlled by the voltage supplied to the bias voltage supply signal VB. When the voltage supplied to the bias voltage supply signal VB is the bias voltage Vbias, the load transistor Mcc becomes conductive and a constant current flows through the load transistor Mcc. When the voltage supplied to the bias voltage supply signal VB is a low level, the load transistor Mcc becomes non-conductive. The source electrode (second electrode) of the load transistor Mcc is electrically connected to the reference potential line 424.

[0061] The first electrode of the photoelectric conversion element PD is electrically connected to the node nodeA, and the second electrode of the photoelectric conversion element PD is electrically connected to the common electrode 422. The common electrode 422 is supplied with a common voltage from the common potential line VCOM.

[0062] The first electrode of the first capacitor SC1 is electrically connected to the gate electrode (first electrode) of the reset transistor Mrst. The second electrode of the first capacitor SC1 is electrically connected to the drain electrode (third electrode) of the reset transistor Mrst and the node nodeA. The first electrode of the second capacitor SC2 is electrically connected to the node nodeA. The second electrode of the second capacitor SC2 is electrically connected to the common electrode 422.

[0063] The first electrode of the third capacitor SC3 is electrically connected to the gate electrode 620 (first electrode 620) of the driving transistor Msf and the node nodeA. The second electrode of the third capacitor SC3 is electrically connected to the drain electrode 630 (third electrode 630) of the driving transistor Msf and the second driving power line 428. The second driving power line 428 is supplied with the second driving voltage VPP2. The first electrode of the fourth capacitor SC4 is electrically connected to the gate electrode 620 (first electrode 620) of the driving transistor Msf and the node nodeA. The second electrode of the fourth capacitor SC4 is electrically connected to the source electrode 610 (second electrode 610) of the driving transistor Msf.

[0064] In one embodiment of the present invention, the conduction state indicates that the source electrode and the drain electrode of the transistor are conductive and the transistor is in an on state. In addition, in one embodiment of the present invention, the non-conduction state indicates that the source electrode and the drain electrode of the transistor are not conductive and the transistor is in an off state. In addition, in each transistor, the source electrode and the drain electrode are switched according to the voltage of each electrode. In addition, those skilled in the art can easily understand that even if the transistor is in an off state, a current flows slightly, such as a leakage current.

[0065] In one embodiment of the present invention, each transistor has a Group 14 element such as silicon or germanium in the channel region. In addition, each transistor may also contain an oxide having semiconductor properties in the channel region. For example, the channel region of each transistor may have low temperature polysilicon (LTPS) or an oxide semiconductor containing indium (In), gallium (Ga), zinc (Zn) and oxygen (O). The solid-state imaging device 100 of one embodiment of the present invention preferably appropriately adapts the structure of the transistor, the connection of the holding capacitor, the voltage of the power supply, etc. according to the application and specifications.

[0066] In one embodiment of the present invention, a portion of transistors may be shared between adjacent pixels. For example, the reset transistor Mrst may be provided with one for each row, may be provided in one row selection circuit 400 for each row, may be provided with one for multiple rows, or may be provided in one row selection circuit 400 for multiple rows.

[0067] <1-3. Method of Driving Solid-State Imaging Device 100 >

[0068] Figure 4 1 is a schematic diagram showing a timing chart of the solid-state imaging device 100 according to one embodiment of the present invention. Figures 5 to 8 Yes means Figure 4 Schematic diagram of the operation state of the pixel 502 at the timing shown. Figures 4 to 8 The driving method shown is an example of a driving method of the solid-state imaging device 100 according to an embodiment of the present invention, and the driving method of the solid-state imaging device 100 is not limited to the driving method of the solid-state imaging device 100. Figures 4 to 8 The driving method shown. Figure 1 to Figure 3 The same or similar structures are omitted from description here.

[0069] For example, the row selection circuit 400 selects each pixel from the plurality of pixels 502 in the first row to the plurality of pixels 502 in the final row for each row. For each selected row, the photoelectric conversion element PD corresponding to each pixel converts the light received by each pixel 502 into an analog signal (photoelectromotive force). Each analog signal after photoelectric conversion for each row is output from each pixel. The AD converter included in the readout circuit 600 converts the analog signal output for each row into a digital signal. The horizontal transfer scanning circuit included in the readout circuit 600 sends the digital signal converted for each row to the signal processing circuit 700 for each row. The PUF-ID extraction circuit 710 included in the signal processing circuit 700 receives the digital signal converted for each row, and generates the PUF-ID inherent to the solid-state imaging device 100 using the digital signal converted for each row. In addition, the image processing circuit 720 included in the signal processing circuit 700 receives the digital signal converted for each row, and generates the imaging data of the subject using the digital signal converted for each row. Furthermore, the signal processing circuit 700 combines the data of the PUF-ID inherent to the solid-state imaging device 100 with the imaging data of the object, and generates imaging data having the PUF-ID that can suppress forgery.

[0070] Here, a driving method of the solid-state imaging device 100 for driving a plurality of pixels 502 electrically connected to the n-th row scanning signal line 410 will be described. Figure 4 As shown, the driving method of the solid-state imaging device 100 includes a reset period, an exposure period, an imaging data acquisition period, and a blank period. Figure 4 As an example, a timing chart for driving a plurality of pixels 502 electrically connected to the n-th row scanning signal line 410 is shown. Figures 5 to 8 Indicates the operating state of the pixel 502 at the nth row and the mth column. Figure 4 In the driving method shown, the driving of the plurality of pixels 502 in the first row to the plurality of pixels 502 in the final row is repeatedly performed, and the digital signal converted for each row is processed by the signal processing circuit 700. That is, Figure 4The driving method shown is repeatedly performed in each of the plurality of pixels 502, and the digital signal converted for each row is processed by the signal processing circuit 700. The signal processing circuit 700 can generate the PUF-ID data inherent in the solid-state imaging device 100 and the imaging data of the object, and generate the imaging data with the PUF-ID that can suppress forgery by using the PUF-ID data inherent in the solid-state imaging device 100 and the imaging data of the object.

[0071] <1-3-1. Reset period>

[0072] The reset period is a period during which the node nodeA of the pixel 502 is reset and the pixel 502 is set to a reset state or an initialization state. Figure 4 As shown, the reset period has a first period T1 and a second period T2. The first period T1 is a period in which the first voltage V(t1) is obtained. The first voltage V(t1) is an output signal OUT(n) corresponding to the voltage of the node nodeA. The second period T2 is a period in which the second voltage V(t2) is obtained. The second voltage V(t2) is an output signal OUT(n) corresponding to the voltage drop of the voltage of the node nodeA. In one embodiment of the present invention, the state of the pixel 502 in the first period T1 is sometimes referred to as the first reset state or the first initialization state, and the state of the pixel 502 in the second period T2 is sometimes referred to as the second reset state or the second initialization state. In addition, the first reset state or the first initialization state, the second reset state or the second initialization state in the reset period are sometimes referred to as reset state or initialization state. In addition, the reset period is also a period in which the first voltage V(t1) is obtained in the first period T1 and the second voltage V(t2) is obtained in the second period T2, and the details are described later.

[0073] First, use Figure 4 and Figure 5 The driving method in the first period T1 is described below. Figure 4As shown, at time t11, the reset signal RG(n) changes from a low level to a high level, and the reset signal RG(n) is supplied with a high level. In addition, at time t11, the selection signal SG(n) changes from a low level to a high level, and the selection signal SG(n) is supplied with a high level. Although not shown in the figure, when the solid-state imaging device 100 starts driving, the bias voltage supply signal VB changes from a low level or a reference voltage VSS to a bias voltage Vbias, and the bias voltage supply signal VB is supplied with a bias voltage Vbias. When the reset transistor Mrst becomes conductive, the first drive voltage VPP1 is supplied from the first drive power line 414 to the node nodeA. As a result, the voltage of the node nodeA gradually increases from the low level at time t11, and becomes the first drive voltage VPP1 at time t1. That is, when the reset transistor Mrst becomes conductive, the reset transistor Mrst supplies the first drive voltage VPP1 from the first drive power line 414 to the node nodeA (the gate electrode 620 of the drive transistor Msf). In one embodiment of the present invention, the first driving power line PVDD1 and the first driving power line 414 may be referred to as reset voltage lines, and the first driving voltage VPP1 may be referred to as a reset voltage.

[0074] Therefore, if Figure 5 As shown, the reset transistor Mrst, the selection transistor Msw and the load transistor Mcc are in the on state.

[0075] Here, when the solid-state imaging device 100 starts driving, the reference voltage VSS is supplied to the second electrode 610 of the driving transistor Msf from the reference potential line PVSS, and the second driving voltage VPP2 is supplied to the third electrode 630 of the driving transistor Msf from the second driving power line 428. Figure 5 As shown, a voltage equivalent to VPP1-VSS is applied between the gate electrode 620 (first electrode 620) of the driving transistor Msf and the second electrode 610 of the driving transistor Msf, and a voltage equivalent to VPP2-VSS is applied between the third electrode 630 of the driving transistor Msf and the second electrode 610 of the driving transistor Msf. As a result, the driving transistor Msf becomes conductive, and the source follower 121 causes a current to flow from the second driving power supply line PVDD2 to the reference potential line PVSS. Then, the source follower 121 supplies a voltage equivalent to the threshold voltage Vth(Msf) of the driving transistor Msf between the gate electrode 620 (first electrode 620) of the driving transistor Msf and the second electrode 610 of the driving transistor Msf. That is, the voltage VPP1-Vth(Msf) is supplied to the second electrode 610 of the driving transistor Msf. As a result, the pixel 502 (source follower 121 ) outputs an output signal OUT(n) corresponding to the voltage VPP1 −Vth(Msf) supplied to the second electrode 610 of the driving transistor Msf.

[0076] like Figure 5 As shown, the output signal OUT(n) is supplied with the second drive voltage VPP2 from the second drive power supply line 428. As a result, the voltage of the output signal OUT(n) gradually increases from the low level at time t11, and becomes the first voltage V(t1) at time t1. The first voltage V(t1) is supplied to the readout signal line 420. The readout circuit 600 reads the first voltage V(t1) supplied to the readout signal line 420. In addition, the readout circuit 600 may also convert the first voltage V(t1) into a digital signal and send the digital signal to the signal processing circuit 700, and the signal processing circuit 700 may also receive the digital signal of the first voltage V(t1). As described above, in the driving method of the solid-state imaging device 100 according to one embodiment of the present invention, the first period T1 is a period for obtaining the first voltage V(t1).

[0077] Next, use Figure 4 and Figure 6 The driving method in the second period T2 is described below. Figure 4 As shown, at time t21, the reset signal RG(n) changes from high level to low level, and the reset signal RG(n) is supplied with low level. In addition, at time t21, the selection signal SG(n) maintains high level. Although not shown in the figure, the bias voltage supply signal VB maintains the bias voltage Vbias.

[0078] Therefore, if Figure 6 As shown, the reset transistor Mrst becomes non-conductive, and the selection transistor Msw and the load transistor Mcc maintain the conductive state.

[0079] like Figure 6 As shown in FIG. 1 , as the reset transistor Mrst changes from the conducting state to the non-conducting state, the first driving voltage VPP1 is no longer supplied from the first driving power line 414 to the node nodeA. That is, when the reset transistor Mrst becomes non-conducting, the reset transistor Mrst stops supplying the first driving voltage VPP1 from the first driving power line 414 to the node nodeA (gate electrode 620 of the driving transistor Msf). Figure 4 and Figure 6 As shown in FIG. 1 , as the reset transistor Mrst changes from the conducting state to the non-conducting state, for example, the voltage of the node nodeA decreases through the first capacitor SC1, the second capacitor SC2, the third capacitor SC3, and the fourth capacitor SC4 provided between the reset transistor Mrst and the node nodeA. That is, the voltage of the node nodeA gradually decreases from the first drive voltage VPP1 at time t21 to become the voltage Vm.

[0080] Here, a voltage corresponding to the threshold voltage Vth(Msf) of the driving transistor Msf is supplied between the gate electrode 620 (first electrode 620) of the driving transistor Msf and the second electrode 610 of the driving transistor Msf. That is, a voltage corresponding to Vm-Vth(Msf) is supplied to the second electrode 610 of the driving transistor Msf. As a result, the pixel 502 (source follower 121) outputs an output signal OUT(n) corresponding to the voltage Vm-Vth(Msf) supplied to the second electrode 610 of the driving transistor Msf.

[0081] like Figure 6 As shown, the second driving voltage VPP2 is supplied from the second driving power line 428 to the output signal OUT(n). As a result, the voltage of the output signal OUT(n) gradually decreases from the low level at time t21, and becomes the second voltage V(t2) at time t2. The second voltage V(t2) is supplied to the readout signal line 420. The readout circuit 600 reads the second voltage V(t2) supplied to the readout signal line 420. In addition, the readout circuit 600 can also convert the second voltage V(t2) into a digital signal and send the digital signal to the signal processing circuit 700, and the signal processing circuit 700 can also receive the digital signal of the second voltage V(t2). As described above, in the driving method of the solid-state imaging device 100 according to one embodiment of the present invention, the second period T2 is a period for obtaining the second voltage V(t2).

[0082] During the reset period, the voltage Vm is supplied to the node nodeA, and the voltage of the node nodeA is maintained at the voltage Vm. As a result, the pixel 502 is reset or initialized, and the state of the pixel 502 becomes a second reset state or a second initialized state.

[0083] For example, between time t2 and time t31 during the reset period, the signal processing circuit 700 may also generate a voltage (V(t1)-V(t2)) obtained by subtracting the second voltage V(t2) from the first voltage V(t1) using the digital signal of the first voltage V(t1) and the digital signal of the second voltage V(t2). The second voltage V(t2) is smaller than the first voltage V(t1), and the difference between the first voltage V(t1) and the second voltage V(t2) is the voltage (V(t1)-V(t2)).

[0084] Here, the voltage (V(t1)-V(t2)) obtained by subtracting the second voltage V(t2) from the first voltage V(t1) is the voltage change amount accompanied by the so-called feed-through, which is caused by the instantaneous change in the voltage of the drain electrode of the reset transistor Mrst (i.e., the voltage of the node nodeA) due to the coupling of the gate electrode of the reset transistor Mrst and the first capacitor element SC1 at the moment when the voltage of the gate electrode of the reset transistor Mrst changes. In one embodiment of the present invention, V(t1)-V(t2) is referred to as the feed-through voltage. The feed-through voltage is expressed by the formula 1 shown below. ΔVg is the change in the voltage of the gate electrode of the reset transistor Mrst. The PUF-ID extraction circuit 710 included in the signal processing circuit 700 generates PUF-ID data inherent to the solid-state imaging device 100 using the feed-through voltage. PUF-ID data can also be generated during the reset period.

[0085] [Formula 1]

[0086]

[0087] <1-3-2. Exposure Period>

[0088] The exposure period is a period during which the pixel 502 is set to an exposure state. That is, the exposure period is a period during which the solid-state imaging device 100 adjusts the current flowing through the source follower 121 using the photoelectric electromotive force generated by the photoelectric conversion element PD based on the received light as the pixel 502 is exposed. Figure 4 As shown, the exposure period has a third period T3.

[0089] use Figure 4 and Figure 7 The driving method in the third period T3 is described below. Figure 4 As shown, during the period from time t31 to time t41, the reset signal RG(n) maintains a low level. In addition, at time t31, the selection signal SG(n) changes from a high level to a low level, and a low level is supplied to the selection signal SG(n). The selection signal SG(n) maintains a low level until time t41. Although not shown in the figure, during the period from time t31 to time t41, the bias voltage supply signal VB maintains a bias voltage Vbias.

[0090] Therefore, if Figure 7 As shown, during the period from time t31 to time t41, the reset transistor Mrst and the selection transistor Msw are in a non-conductive state, and the load transistor Mcc is in a conductive state.

[0091] As the pixel 502 is exposed, the photoelectric conversion element PD generates a photoelectromotive force based on the received light. As a result, during the period from time t31 to time t41, a current flows from the node nodeA to the common electrode 422, and the voltage of the node nodeA gradually decreases from the voltage Vm. In addition, during the period from time t31 to time t41, the selection transistor Msw is in a non-conductive state and the load transistor Mcc is in a conductive state, so a current flows from the readout signal line 420 to the reference potential line PVSS, and the voltage of the output signal OUT(n) becomes the reference voltage VSS.

[0092] <1-3-3. Image Data Acquisition Period>

[0093] The image data acquisition period is a period in which the pixel 502 is set to a state in which image data can be acquired and image data of the subject is acquired. The image data is generated using the second voltage V(t2) and the third voltage V(t3), which will be described in detail later. Figure 4 As shown, the imaging data acquisition period has a fourth period T4.

[0094] use Figure 4 and Figure 8 , the driving method in the fourth period T4 is described. Figure 4 As shown, between time t41 and time t51, the reset signal RG(n) maintains a low level. In addition, at time t41, the selection signal SG(n) changes from a low level to a high level, and a high level is supplied to the selection signal SG(n). The selection signal SG(n) maintains a high level until time t51. Although not shown in the figure, between time t41 and time t51, the bias voltage supply signal VB maintains a bias voltage Vbias.

[0095] Therefore, if Figure 8 As shown, between time t41 and time t51, the reset transistor Mrst is in a non-conductive state, and the selection transistor Msw and the load transistor Mcc are in a conductive state.

[0096] Between time t41 and time t51, as the pixel 502 is exposed, the photoelectric conversion element PD generates a photoelectromotive force based on the received light. As a result, from time t31 to the period from time t41 to time t51, the current also continues to flow from the node nodeA to the common electrode 422, and the voltage of the node nodeA gradually decreases. In addition, since the selection transistor Msw and the load transistor Mcc are in the on state between time t41 and time t51, the source follower 121 causes the current to flow from the second drive power line PVDD2 to the reference potential line PVSS. As a result, the pixel 502 outputs an output signal OUT(n) corresponding to the voltage supplied to the gate electrode 620 (first electrode 620) of the drive transistor Msf.

[0097] like Figure 4 As shown, the voltage of the node nodeA gradually decreases and becomes the voltage Vn at time t3. In addition, the voltage of the output signal OUT(n) gradually increases from the reference voltage VSS at time t41. At time t3, the voltage of the output signal OUT(n) becomes the third voltage V(t3) corresponding to the voltage Vn of the node nodeA. The third voltage V(t3) is supplied to the readout signal line 420. The readout circuit 600 reads the third voltage V(t3) supplied to the readout signal line 420. In addition, the readout circuit 600 can also convert the third voltage V(t3) into a digital signal and send the digital signal to the signal processing circuit 700, and the signal processing circuit 700 can also receive the digital signal of the third voltage V(t3). As described above, in the driving method of the solid-state imaging device 100 of one embodiment of the present invention, the fourth period T4 is also a period for obtaining the third voltage V(t3).

[0098] For example, between time t3 and time t51 during the period of acquiring imaging data, the signal processing circuit 700 may also generate data (V(t2)-V(t3)) obtained by subtracting the third voltage V(t3) from the second voltage V(t2) using the digital signal of the second voltage V(t2) and the digital signal of the third voltage V(t3). The image processing circuit 720 included in the signal processing circuit 700 generates imaging data of the subject using the data (V(t2)-V(t3)) obtained by subtracting the third voltage V(t3) from the second voltage V(t2). The third voltage V(t2) is smaller than the second voltage V(t2), and the difference between the second voltage V(t2) and the third voltage V(t3) is the voltage (V(t2)-V(t3)). The imaging data of the subject may also be generated during the period of acquiring imaging data.

[0099] <1-3-4. Blank period>

[0100] During a blank period, for example, the PUF-ID extraction circuit 710 included in the signal processing circuit 700 generates PUF-ID data inherent to the solid-state imaging device 100 using a digital signal corresponding to the feed-through voltage after transformation for each row. Furthermore, during a blank period, for example, the image processing circuit 720 included in the signal processing circuit 700 generates imaging data of the subject using a digital signal obtained by subtracting the third voltage V(t3) from the second voltage V(t2) after transformation for each row (V(t2) - V(t3)). Furthermore, during a blank period, for example, the signal processing circuit 700 synthesizes the PUF-ID data inherent to the solid-state imaging device 100 with the imaging data of the subject to generate imaging data having PUF-ID data that can suppress forgery. Figure 4As shown in FIG. 1 , the blanking period includes a fifth period T5. In addition, in the blanking period, for example, the pixel 502 is in the same state as the exposure state.

[0101] use Figure 4 The driving method in the fifth period T5 is described below. Figure 4 As shown, between time t51 and time t61, the reset signal RG(n) maintains a low level. In addition, at time t51, the selection signal SG(n) changes from a high level to a low level, and a low level is supplied to the selection signal SG(n). The selection signal SG(n) maintains a low level until time t61. Although not shown in the figure, between time t51 and time t61, the bias voltage supply signal VB maintains a bias voltage Vbias.

[0102] Thus, between time t51 and time t61, as in the exposure period, the photoelectric conversion element PD continues to receive light, and current flows from the node nodeA to the common electrode 422, and the voltage of the node nodeA gradually decreases. In addition, between time t51 and time t61, the selection transistor Msw is in a non-conductive state, and the load transistor Mcc is in a conductive state, so that current flows from the readout signal line 420 to the reference potential line PVSS, and the voltage of the output signal OUT(n) becomes the reference voltage VSS.

[0103] In a driving method of a solid-state imaging device 100 according to an embodiment of the present invention, for example, the coordinates of a pixel 502 are used as an input signal (challenge), and data of a feedthrough voltage corresponding to the challenge of a plurality of pixels 502 are extracted, and PUF-ID data (response) is generated using the data of the plurality of feedthrough voltages. In addition, in a driving method of a solid-state imaging device 100 according to an embodiment of the present invention, imaging data of a subject is generated using data (V(t2)-V(t3)) obtained by subtracting a third voltage V(t3) from a second voltage V(t2). The imaging data of the subject may be generated after the PUF-ID data (response) is generated, or the PUF-ID data (response) may be generated after the imaging data of the subject is generated. In a driving method of a solid-state imaging device 100 according to an embodiment of the present invention, the PUF-ID data is synthesized with the imaging data of the subject to generate imaging data having the PUF-ID data.

[0104] By using the driving method of the solid-state imaging device 100 according to one embodiment of the present invention, it is possible to obtain two data, namely, the inherent PUF-ID data based on the feedthrough voltage of the pixel 502 of the solid-state imaging device 100 and the image data of the object imaged by the solid-state imaging device 100, in a series of driving. In addition, by using the driving method of the solid-state imaging device 100 according to one embodiment of the present invention, it is possible to synthesize the inherent PUF-ID data based on the feedthrough voltage with the image data of the object imaged by the solid-state imaging device 100. Since the inherent PUF-ID data is the ID data inherent to the solid-state imaging device 100, by using the driving method of the solid-state imaging device 100 according to one embodiment of the present invention, it is possible to use the PUF-ID data and the image data obtained in a series of driving to prove that the image data is the data imaged by the solid-state imaging device 100, and it is possible to prevent the imitation of the image data, and further, it is possible to suppress the production of imitation, pirated or counterfeit products.

[0105] In addition, since the inherent ID generated by the photoelectric conversion element PD using the photoelectromotive force or current (bright current or dark current) may change depending on the environment such as the bright place, the dark place, the temperature, etc., it is difficult to use it as an inherent ID. On the other hand, in the driving method of the solid-state imaging device 100 of one embodiment of the present invention, instead of using the data during the exposure period when the pixel 502 is in the exposure state, that is, the photoelectric conversion element PD receives light, the PUF-ID data is generated using the feed-through voltage when the pixel 502 is in the reset state. As a result, the solid-state imaging device 100 can generate PUF-ID data that suppresses the influence of light. Therefore, by using the driving method of the solid-state imaging device 100 of one embodiment of the present invention, using the PUF-ID data and the imaging data obtained in a series of drives, it can be less susceptible to the influence of the environment, and then it can be proved that the imaging data is the data captured by the solid-state imaging device 100, and it can prevent the imitation of the imaging data, and then it can suppress the production of counterfeit, pirated or forged products.

[0106] <2. Second Implementation Method>

[0107] <2-1. Configuration of Solid-State Imaging Device 100B>

[0108] Fig. 9 1 is a schematic plan view showing the structure of a solid-state imaging device 100B according to an embodiment of the present invention. The structure of the solid-state imaging device 100B according to an embodiment of the present invention is obtained by adding a structure for transmitting a signal TX(n) to the structure of the solid-state imaging device 100. Therefore, in the second embodiment, the structure related to the transmission signal TX(n) is mainly described. The structure of the solid-state imaging device 100B according to an embodiment of the present invention is not limited to Fig. 9The description of the same or similar structures as those in the first embodiment will be omitted here.

[0109] like Fig. 9 As shown, the row selection circuit 400B has the structure of the row selection circuit 400 and further supplies a transmission signal TX(n) in common to each of the plurality of pixels 502 (pixel circuits 120 ) located in the n-th row in the pixel portion 504 .

[0110] <2-2. Structure of pixel 502>

[0111] Fig.10 1 is a circuit diagram showing a pixel circuit 120B according to an embodiment of the present invention. Each of the plurality of pixels 502 includes a plurality of transistors, capacitors, and photoelectric conversion elements constituting the pixel circuit 120B. Fig.10 express Fig. 9 1 and 2 are components of the pixel circuit 120B of the pixel 502 with n rows and m columns shown in FIG. The structure of the pixel circuit 120B is a structure in which a transmission signal TX(n), a transmission transistor Mtrg, and a fifth capacitor SC5 are added to the structure of the solid-state imaging device 100. Therefore, the structure related to the transmission signal TX(n), the transmission transistor Mtrg, and the fifth capacitor SC5 will be mainly described here. Fig.10 The structure of the pixel circuit 120B shown in the figure is an example, and the structure of the pixel circuit 120B is not limited to Fig.10 The description of the same or similar structures as those in the first embodiment will be omitted here.

[0112] like Fig.10 As shown, the pixel circuit 120B has, for example, a transfer transistor Mtrg (fifth switch) in addition to the structure of the pixel circuit 120. The transfer transistor Mtrg (fifth switch) also has a gate electrode (first electrode) and a pair of electrodes consisting of a source electrode and a drain electrode (a pair of electrodes consisting of a second electrode and a third electrode) like other transistors. Depending on the voltage applied to the source electrode and the drain electrode, the function of each electrode as a source and the function as a drain can be switched.

[0113] The transmission transistor Mtrg selects connection or non-connection between the node nodeA and the first electrode of the photoelectric conversion element PD based on the transmission signal TX(n). As a result, the transmission transistor Mtrg adjusts the voltage of the node nodeA using the photoelectric electromotive force generated by the photoelectric conversion element PD based on the received light as the pixel 502 is exposed. In one embodiment of the present invention, the photoelectric electromotive force generated by the photoelectric conversion element PD based on the received light can also be referred to as the voltage generated by the exposure of the photoelectric conversion element.

[0114] The gate electrode (first electrode) of the transmission transistor Mtrg is electrically connected to the transmission signal line 416. The transmission signal TX(n) is supplied to the transmission signal line 416. The conduction state and the non-conduction state of the transmission transistor Mtrg are controlled according to the signal supplied to the transmission signal line 416. When the signal supplied to the transmission signal line 416 is at a high level, the transmission transistor Mtrg becomes a conduction state. When the signal supplied to the transmission signal line 416 is at a low level, the transmission transistor Mtrg becomes a non-conduction state. The source electrode (second electrode) of the transmission transistor Mtrg is electrically connected to the first electrode of the photoelectric conversion element PD. The drain electrode (third electrode) of the transmission transistor Mtrg and the second electrode of the fifth capacitor are connected to the node nodeA. The first electrode of the fifth capacitor is connected to the gate electrode (first electrode) of the transmission transistor Mtrg. The fifth capacitor SC5 has a pair of electrodes (first electrode, second electrode) in the same manner as the first capacitor to the fourth capacitor. In addition, the fifth capacitor SC5 is, for example, a parasitic capacitor and an additional capacitor between the node nodeA and the gate electrode (first electrode) of the transfer transistor Mtrg, and the capacitance value of the fifth capacitor SC5 is the capacitance value Cgd (Mtrg). The fifth capacitor SC5 can hold a charge corresponding to the first drive voltage VPP1 supplied to the node nodeA, or a charge corresponding to the photoelectric electromotive force generated by the photoelectric conversion element PD based on the received light.

[0115] <2-3. Method of Driving Solid-State Imaging Device 100B>

[0116] Fig.11 1 is a schematic diagram showing a timing chart of the solid-state imaging device 100B according to one embodiment of the present invention. Figure 12 to Figure 15 Yes means Fig.11 Schematic diagram of the operation state of the pixel 502 at the timing shown. Figure 11 to Figure 15 The driving method shown is an example of a driving method of the solid-state imaging device 100B according to an embodiment of the present invention, and the driving method of the solid-state imaging device 100B is not limited to the driving method of the solid-state imaging device 100B. Figure 11 to Figure 15 Regarding the first embodiment and Fig.10 The same or similar structures are omitted from description here.

[0117] <2-3-1. Reset period>

[0118] like Figure 11 to Figure 13 As shown in FIG. 1 , during the reset period, the transmission signal TX(n) is supplied with a low level. Fig.12 and Fig.13As shown, the transfer transistor Mtrg is in a non-conductive state. In the reset period, the description other than that related to the transfer signal TX(n) and the transfer transistor Mtrg is the same as that of the first embodiment, and thus the description is omitted here.

[0119] In the solid-state imaging device 100B of the second embodiment, the feed-through voltage (voltage V(t1)-V(t2)) becomes the following formula 2. In formula 2, ΔVg is the change in the voltage of the gate electrode of the reset transistor Mrst, and CallnodeA is the sum of the capacitances added to the node nodeA. The sum of the capacitances added to the node nodeA includes the capacitance value Cgs(Mrst), the capacitance value Cdiode, the capacitance value Cgd(Msf), the capacitance value Cgs(Msf), the capacitance value Cgd(Mtrg), the capacitance value corresponding to the capacitance between the node nodeA side of the transmission transistor Mtrg and the first electrode side of the photoelectric conversion element PD (omitted in the figure), other additional capacitance values ​​and parasitic capacitance values.

[0120] [Formula 2]

[0121]

[0122] <2-3-2. Exposure Period>

[0123] As in the first embodiment, the exposure period in the second embodiment is also a period in which the pixel 502 is set to an exposure state. That is, the exposure period is a period in which the solid-state imaging device 100B adjusts the current flowing through the source follower 121 using the photoelectric electromotive force generated by the photoelectric conversion element PD based on the received light as the pixel 502 is exposed. Fig.11 As shown, the exposure period has a third period T3.

[0124] use Fig.11 and Fig.14 , the driving method in the third period T3 is described. Fig.11 As shown, between time t31 and time t41, the reset signal RG(n) maintains a low level, and the selection signal SG(n) maintains a high level. In addition, at time t31, the transmission signal TX(n) changes from a low level to a high level, and a high level is supplied to the transmission signal TX(n). The transmission signal TX(n) maintains a high level until time t41. Although not shown in the figure, between time t31 and time t41, the bias voltage supply signal VB maintains a bias voltage Vbias.

[0125] Therefore, if Fig.14 As shown, between time t31 and time t41, the reset transistor Mrst is in a non-conductive state, and the selection transistor Msw, the transfer transistor Mtrg, and the load transistor Mcc are in a conductive state.

[0126] As the pixel 502 is exposed, the photoelectric conversion element PD generates a photoelectromotive force based on the received light. As a result, between time t31 and time t41, a current flows from the node nodeA to the common electrode 422, and the voltage of the node nodeA gradually decreases from the voltage Vm at time t31 to the voltage Vn at time t41. That is, the transfer transistor Mtrg supplies the voltage generated by the exposure of the photoelectric conversion element to the node nodeA (the gate electrode 620 of the drive transistor Msf). In addition, between time t31 and time t41, since the selection transistor Msw and the load transistor Mcc are in the on state, the source follower 121 causes the current to flow from the second drive power line PVDD2 to the reference potential line PVSS. As a result, the pixel 502 outputs an output signal OUT(n) corresponding to the voltage supplied to the gate electrode 620 (first electrode 620) of the drive transistor Msf.

[0127] like Fig.11 As shown, the voltage of the output signal OUT(n) changes from the second voltage V(t2) at time t31 to the third voltage V(t3) corresponding to the voltage Vn of the node nodeA at time t41 in a manner following the decrease in the voltage of the node nodeA. The third voltage V(t3) is supplied to the read signal line 420. That is, the voltage of the output signal OUT(n) becomes the third voltage V(t3) corresponding to the voltage Vn of the node nodeA.

[0128] <2-3-3. Image Data Acquisition Period>

[0129] As in the first embodiment, in the second embodiment, the image data acquisition period is also a period in which the pixel 502 is set to the image data acquisition state and the image data of the subject is acquired. The image data is generated using the second voltage V(t2) and the third voltage V(t3), which will be described in detail later. Fig.11 As shown, the imaging data acquisition period has a fourth period T4.

[0130] use Fig.11 and Fig.15 The driving method in the fourth period T4 is described below. Fig.11 As shown, between time t41 and time t51, the reset signal RG(n) maintains a low level, and the selection signal SG(n) maintains a high level. In addition, at time t41, the transmission signal TX(n) changes from a high level to a low level, and a low level is supplied to the transmission signal TX(n). The transmission signal TX(n) maintains a low level until time t41. Although not shown in the figure, between time t41 and time t51, the bias voltage supply signal VB maintains a bias voltage Vbias.

[0131] Therefore, if Fig.15 As shown, between time t41 and time t51, the reset transistor Mrst and the transfer transistor Mtrg are in a non-conductive state, and the selection transistor Msw and the load transistor Mcc are in a conductive state.

[0132] Between time t41 and time t51, current does not flow from node nodeA to common electrode 422, so the voltage of node nodeA maintains voltage Vn. In addition, between time t41 and time t51, selection transistor Msw and load transistor Mcc are in the on state, so source follower 121 allows current to continue to flow from second drive power line PVDD2 to reference potential line PVSS. As a result, pixel 502 maintains output signal OUT(n) corresponding to the voltage (voltage Vn of node nodeA) supplied to gate electrode 620 (first electrode 620) of drive transistor Msf, i.e., third voltage V(t3).

[0133] As in the first embodiment, in the second embodiment, the readout circuit 600 also reads the third voltage V(t3) supplied to the readout signal line 420. In addition, the readout circuit 600 may convert the third voltage V(t3) into a digital signal and send it to the signal processing circuit 700, and the signal processing circuit 700 may receive the digital signal of the third voltage V(t3). As described above, in the driving method of the solid-state imaging device 100 according to one embodiment of the present invention, the fourth period T4 is also a period for obtaining the third voltage V(t3).

[0134] Similar to the first embodiment, in the second embodiment, for example, the signal processing circuit 700 may generate data (V(t2)-V(t3)) obtained by subtracting the third voltage V(t3) from the second voltage V(t2) using the digital signal of the second voltage V(t2) and the digital signal of the third voltage V(t3) during the acquisition of the imaging data. The image processing circuit 720 included in the signal processing circuit 700 generates imaging data of the subject using the data (V(t2)-V(t3)) obtained by subtracting the third voltage V(t3) from the second voltage V(t2).

[0135] <2-3-4. Blank period>

[0136] Similar to the first embodiment, in the second embodiment, also during the blank period, for example, the PUF-ID extraction circuit 710 included in the signal processing circuit 700 generates PUF-ID data inherent to the solid-state imaging device 100 using a digital signal corresponding to the feed-through voltage after transformation for each row. Furthermore, during the blank period, for example, the image processing circuit 720 included in the signal processing circuit 700 generates imaging data of the subject using a digital signal obtained by subtracting the third voltage V(t3) from the second voltage V(t2) after transformation for each row (V(t2) - V(t3)). Furthermore, during the blank period, for example, the signal processing circuit 700 synthesizes the PUF-ID data inherent to the solid-state imaging device 100 with the imaging data of the subject to generate imaging data having PUF-ID data that can suppress forgery. Fig.11 As shown, the blank period has a fifth period T5.

[0137] use Fig.11 The driving method in the fifth period T5 is described below. Fig.11 As shown, between time t51 and time t61, the reset signal RG(n) and the transmission signal TX(n) maintain a low level. In addition, at time t51, the selection signal SG(n) changes from a high level to a low level, and a low level is supplied to the selection signal SG(n). The selection signal SG(n) maintains a low level until time t61. Although not shown in the figure, between time t51 and time t61, the bias voltage supply signal VB maintains a bias voltage Vbias.

[0138] Therefore, between time t51 and time t61, current does not flow from node nodeA to common electrode 422, so the voltage of node nodeA maintains voltage Vn. In addition, between time t51 and time t61, selection transistor Msw is in a non-conductive state and load transistor Mcc is in a conductive state, so current flows from read signal line 420 to reference potential line PVSS, and the voltage of output signal OUT(n) becomes reference voltage VSS.

[0139] In the driving method of the solid-state imaging device 100B according to an embodiment of the present invention, similarly to the driving method of the solid-state imaging device 100, the solid-state imaging device 100B can extract the data of the feed-through voltage corresponding to the challenge of the plurality of pixels 502, generate PUF-ID data (response) using the data of the plurality of feed-through voltages, and generate the imaging data of the subject using the data (V(t2)-V(t3)) obtained by subtracting the third voltage V(t3) from the second voltage V(t2). As a result, in the driving method of the solid-state imaging device 100B according to an embodiment of the present invention, similarly to the driving method of the solid-state imaging device 100, the PUF-ID data and the imaging data of the subject can be synthesized to generate imaging data having the PUF-ID data.

[0140] The driving method of the solid-state imaging device 100B according to one embodiment of the present invention can obtain the same operational effects as the driving method of the solid-state imaging device 100 according to one embodiment of the present invention.

[0141] <2. Third Implementation Method>

[0142] Fig.16 100 or 100B according to an embodiment of the present invention. The driving method of the solid-state imaging device 100 or 100B according to an embodiment of the present invention is not limited to the following. Fig.16 The description of the same or similar structures as those of the first embodiment or the second embodiment will be omitted here.

[0143] like Fig.16 As shown, for example, a user starts imaging using the solid-state imaging device 100 or 100B. The drive timing control circuit 300 sends a challenge to the row selection circuit 400 , the readout circuit 600 , and the signal processing circuit 700 .

[0144] When the plurality of pixels 502 receive the challenge and each signal, the plurality of pixels 502 obtain the first voltage V(t1) in step S31. That is, the first voltage V(t1) is supplied to the output signal OUT. The plurality of pixels 502 execute step S31 in the first period T1. In addition, for example, the readout circuit 600 receives the first voltage V(t1) and converts it into a digital signal for each row, and sends the plurality of first voltages V(t1) converted into digital signals to the signal processing circuit 700 for each row. The signal processing circuit 700 stores the plurality of first voltages V(t1) converted into digital signals in, for example, a storage circuit.

[0145] Next, in step S33, the plurality of pixels 502 respectively obtain the second voltage V(t2). That is, the second voltage V(t2) is supplied to the output signal OUT. The plurality of pixels 502 respectively perform step S33 in the second period T2. In addition, for example, the readout circuit 600 receives the second voltage V(t2), converts it into a digital signal for each row, and sends the plurality of second voltages V(t2) converted into digital signals to the signal processing circuit 700 for each row. The signal processing circuit 700 stores the plurality of second voltages V(t2) converted into digital signals, for example, in a storage circuit.

[0146] Next, the solid-state imaging device 100 or the solid-state imaging device 100B performs the processing between step S33 and step S47 in parallel. That is, the solid-state imaging device 100 or the solid-state imaging device 100B performs the processing after step S37 and the processing after step 41 in parallel. In step S37, the signal processing circuit 700 calculates the feed-through voltage obtained by subtracting the second voltage V(t2) from the first voltage V(t1). In step S41, the plurality of pixels 502 respectively obtain the third voltage V(t3). The solid-state imaging device 100 or 100B performs step S37 and step 41, for example, in the fourth period T4.

[0147] In step S37, the signal processing circuit 700 reads out the plurality of first voltages V(t1) and the plurality of second voltages V(t2) stored in the storage circuit. In addition, the signal processing circuit 700 calculates a plurality of feed-through voltages obtained by subtracting the second voltage V(t2) from the first voltage V(t1) using the plurality of first voltages V(t1) and the plurality of second voltages V(t2). The first voltage V(t1), the second voltage V(t2), and the feed-through voltage are digital signals.

[0148] Next, in step S39 , the signal processing circuit 700 sends the plurality of feed-through voltages to the PUF-ID extraction circuit 710 , and the PUF-ID extraction circuit 710 generates PUF-ID data unique to the solid-state imaging device 100 or 100B using the plurality of feed-through voltages.

[0149] In step S41, the plurality of pixels 502 respectively obtain the third voltage V(t3). That is, the plurality of pixels 502 respectively supply the third voltage V(t3) to the output signal OUT. In addition, for example, the readout circuit 600 receives the third voltage V(t3) from the plurality of pixels 502 respectively and converts it into a digital signal for each row, and sends the plurality of third voltages V(t3) converted into digital signals to the signal processing circuit 700 for each row. The signal processing circuit 700 stores the plurality of third voltages V(t3) converted into digital signals, for example, in a storage circuit.

[0150] In step S43, the signal processing circuit 700 reads out the plurality of second voltages V(t2) and the plurality of third voltages V(t3) stored in the storage circuit. In addition, the signal processing circuit 700 generates a plurality of data obtained by subtracting the third voltage V(t3) from the second voltage V(t2) using the plurality of second voltages V(t2) and the plurality of second voltages V(t3). The third voltage V(t3) is a digital signal.

[0151] Next, in step S45, the signal processing circuit 700 sends the generated multiple data obtained by subtracting the third voltage V(t3) from the second voltage V(t2) to the image processing circuit 720. The image processing circuit 720 generates imaging data using the multiple data obtained by subtracting the third voltage V(t3) from the second voltage V(t2).

[0152] In addition, step S45 may be executed after step S39 , or step S45 may be executed after step S39 .

[0153] Next, in step S47 , the image processing circuit 720 selects whether to combine the generated PUF-ID data with the generated imaging data. The solid-state imaging device 100 or 100B may execute step S47 in the fourth period T4 or in the fifth period T5 , for example.

[0154] If the image processing circuit 720 chooses to synthesize the generated PUF-ID data inherent to the solid-state imaging device 100 or 100B with the generated imaging data (yes), then in step S49, the image processing circuit 720 synthesizes the generated PUF-ID data inherent to the solid-state imaging device 100 or 100B with the generated imaging data to generate imaging data with PUF-ID data that can suppress forgery. In addition, the image processing circuit 720 sends the generated imaging data with PUF-ID data that can suppress forgery, for example, to a host (omitted in the figure) or a display device (omitted in the figure). The driving method of the solid-state imaging device 100 or 100B according to one embodiment of the present invention ends.

[0155] If the image processing circuit 720 chooses not to synthesize the generated PUF-ID data inherent to the solid-state imaging device 100 or 100B with the generated imaging data (No), then in step S51, the image processing circuit 720 outputs the generated PUF-ID data inherent to the solid-state imaging device 100 or 100B and the generated imaging data separately. The image processing circuit 720 may output the generated imaging data after outputting the generated PUF-ID data inherent to the solid-state imaging device 100 or 100B, or may output the generated imaging data and output the generated PUF-ID data inherent to the solid-state imaging device 100 or 100B. The image processing circuit 720 sends the generated PUF-ID data inherent to the solid-state imaging device 100 or 100B and the generated imaging data, for example, to a host (not shown). The driving method of the solid-state imaging device 100 or 100B according to one embodiment of the present invention ends.

[0156] For example, the host saves the generated image data with PUF-ID data that can suppress forgery, the generated PUF-ID data inherent to the solid-state imaging device 100 or the solid-state imaging device 100B, or the generated image data to a data storage device. In addition, for example, the display device displays the generated image data with PUF-ID data that can suppress forgery.

[0157] As described above, by utilizing the driving method of the solid-state imaging device 100 according to one embodiment of the present invention, it is possible to utilize the PUF-ID data and imaging data obtained in a series of drives to prove that the imaging data is data captured by the solid-state imaging device 100, and to prevent the imaging data from being imitated, thereby suppressing the production of counterfeit, pirated or forged products.

[0158] In addition, the solid-state imaging device 100 may also be electrically connected to a host (not shown). The solid-state imaging device 100 may also be connected to the host through two-way communication via a wireless network, for example. The host is, for example, a computer that provides an application or program to the solid-state imaging device 100 via a wireless network. For example, in the case where a request related to the provision of an application is made from the solid-state imaging device 100 to the host, the host provides the installation file of the application to the solid-state imaging device 100. The user can install the application in the solid-state imaging device 100 and use the application installed in the solid-state imaging device 100. For example, if a request for the provision of an application or program related to the acquisition of imaging data or the acquisition of a PUF-ID is made from the user or the solid-state imaging device 100, the host provides the installation file or program of the application to the solid-state imaging device 100. Thus, the user can install the application in the solid-state imaging device 100, and by utilizing the application installed in the solid-state imaging device 100, can utilize the driving method of the solid-state imaging device 100, and in a series of driving of the solid-state imaging device 100, execute a program for generating and outputting PUF-ID data using the feed-through voltage inherent in the solid-state imaging device 100 and a program for generating and outputting imaging data.

[0159] The embodiments or parts of the embodiments described as the embodiments of the present invention can be implemented in combination as appropriate unless they are contradictory to each other.

[0160] Even if other effects different from the effects brought about by the above-mentioned embodiments are obvious from the description of this specification or can be easily predicted by a person skilled in the art, they should of course be regarded as brought about by the present invention.

[0161] Description of symbols

[0162] 100: solid-state imaging device; 100B: solid-state imaging device; 120: pixel circuit; 120B: pixel circuit; 121: source follower; 200: power supply circuit; 300: drive timing control circuit; 400: row selection circuit; 400B: row selection circuit; 410: scanning signal line; 412: reset signal line; 414: first drive power supply line; 416: transmission signal line; 418: bias voltage supply line; 420 : readout signal line; 422: common electrode; 424: reference potential line; 428: second driving power line; 502: pixel; 504: pixel unit; 600: readout circuit; 610: second electrode; 610: source electrode; 620: first electrode; 620: gate electrode; 630: third electrode; 630: drain electrode; 700: signal processing circuit; 710: PUF-ID extraction circuit; 720: image processing circuit.

Claims

1. A detection device, characterized in that: having at least one pixel in which a first electrode of a photoelectric conversion element is connected to a gate electrode of a first transistor connected between a power supply line and a readout signal line; have: During the reset period, the gate electrode of the first transistor is reset; During the exposure period, the photoelectric conversion element is exposed; as well as During the readout period, the voltage accompanying the exposure of the above-mentioned photoelectric conversion element is read out; During the above reset period, reading a first voltage from the readout signal line during a first period in which a reset voltage is supplied to the gate electrode of the first transistor; reading a second voltage from the readout signal line during a second period after supply of the reset voltage to the gate electrode of the first transistor is stopped; After the third period as the exposure period, a third voltage is read from the readout signal line in a fourth period as the readout period; outputting the difference between the first voltage and the second voltage as identification data inherent to the detection device; The difference between the third voltage and the second voltage is output as detection data.

2. The detection device according to claim 1, characterized in that having a plurality of pixels including at least one pixel mentioned above; The first voltage, the second voltage, and the third voltage are read out in each of the plurality of pixels.

3. The detection device according to claim 1, characterized in that: A second transistor connected between a reset voltage line and a gate electrode of the first transistor; Setting the second transistor to an on state; The reset voltage is supplied to the gate electrode of the first transistor from the reset voltage line.

4. The detection device according to claim 3, characterized in that: a third transistor connected between the electrode of the pair of electrodes of the first transistor that is not connected to the power supply line and the readout signal line; Setting the third transistor to an on state; The first voltage, the second voltage, and the third voltage are read out.

5. The detection device according to claim 4, characterized in that: A fourth transistor connected between the readout signal line and the reference potential line; supplying a bias voltage to the gate electrode of the fourth transistor; Setting the fourth transistor to an on state; A constant current is allowed to flow between a pair of electrodes of the fourth transistor.

6. The detection device according to claim 5, characterized in that: The first transistor, the third transistor and the fourth transistor constitute a source follower; Setting the first transistor, the third transistor and the fourth transistor to an on state; A current is caused to flow between the power supply line and the read signal line.

7. The detection device according to claim 6, characterized in that: A fifth transistor connected between the gate electrode of the first transistor and the first electrode of the photoelectric conversion element; During the third period above, Setting the fifth transistor to an on state; A voltage generated by exposure of the photoelectric conversion element is supplied to the gate electrode of the first transistor.

8. The detection device according to claim 1, characterized in that: The difference between the first voltage and the second voltage is a feed-through voltage.

9. The detection device according to claim 1, characterized in that: After generating the identification data inherent to the detection device, the detection data is generated.

10. The detection device according to claim 1, characterized in that: The second voltage is lower than the first voltage, and the third voltage is lower than the second voltage.

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