A module verification method based on multi-channel secondary cache

Abstract

The application discloses a module verification method based on a multi-channel secondary cache, which comprises the following steps: a stimulus generator sends a current control signal to a multi-channel secondary cache and a monitor; the multi-channel secondary cache adopts at least two output channels to simultaneously send data to each receiving channel in a current clock cycle according to the current control signal, determines an actual output channel corresponding to each receiving channel in the current clock cycle from the at least two output channels, and stores the data sent by the actual output channel; an arbitration signal of each receiving channel in the current clock cycle is generated and sent to the monitor, and the data received by the receiving channel in the current clock cycle is output to a comparator; the monitor acquires the data sent to the receiving channel in the current clock cycle from the at least two output channels and sends the data to the comparator, and verifies the arbitration signal of the receiving channel in the current clock cycle; and the comparator verifies the data output by the receiving channel in the current clock cycle according to the received data.

Description

TECHNICAL FIELD

[0001] The application belongs to the chip verification technical field, and particularly relates to a module verification method based on a multi-channel secondary cache. BACKGROUND

[0002] In the chip field, the design of a chip has many links, and the most time-consuming links are two processes of design and verification. The efficiency of chip verification will determine whether the chip can be delivered on time. In the background of global chip shortage, timely delivery of chips is undoubtedly very important for major chip manufacturers.

[0003] At present, the industry lacks an efficient verification method for how to verify a multi-channel secondary cache module, and the development process of a chip containing a multi-channel secondary cache module is greatly prolonged, which is a difficult problem faced by chip enterprises.

[0004] Compared with an ordinary few-channel secondary cache, each additional channel means that the number of sent stimuli will increase exponentially, which will bring great challenges to our verification environment. If the secondary cache itself also has an arbitration mechanism on the basis of the multi-channel, the above-mentioned scenario will become more complex. The traditional verification scheme compares the data of the secondary cache and checks the arbitration mechanism of the secondary cache in the same environment. The increase of one channel not only needs to consider whether the data reception can be successfully completed, but also needs to consider whether the arbitration mechanism is updated to process the increased data amount. Each increase of one channel needs to complete the two things at the same time, which hinders the progress. This not only greatly improves the complexity of the verification environment, but also consumes a lot of manpower and material resources, and due to the too complex test scenario, the completeness of the module verification cannot be guaranteed. SUMMARY

[0005] In order to solve the above problems in the related art, the application provides a module verification method based on a multi-channel secondary cache. The technical problems to be solved by the application are realized by the following technical scheme:

[0006] The application provides a module verification method based on a multi-channel secondary cache, applied to a verification platform, comprising:

[0007] The stimulus generator sends a current control signal to the multi-channel secondary cache and the monitor; the current control signal contains at least two output channels, at least one receiving channel and data of each output channel;

[0008] In response to the current control signal, in a current clock cycle, the multi-channel secondary cache simultaneously sends the data to each receiving channel via the at least two output channels respectively, determines the actual output channel corresponding to each receiving channel in the current clock cycle from the at least two output channels, and stores the data sent by the actual output channel of the receiving channel;

[0009] The multi-channel secondary cache generates an arbitration signal of each receiving channel in a current clock cycle and sends the arbitration signal to a monitor, and outputs the data received by the receiving channel in the current clock cycle to an operation comparator;

[0010] The monitor obtains the data sent to the receiving channel in the current clock cycle from the at least two output channels and sends the data to the operation comparator, verifies the arbitration signal of the receiving channel in the current clock cycle according to the current control signal, and when the verification is passed, continues to receive and verify the arbitration signal of the receiving channel in the next clock cycle, and when the arbitration signal of the receiving channel received is not verified or the last arbitration signal of the receiving channel is verified, ends the current verification.

[0011] The operation comparator verifies the data output by the receiving channel in the current clock cycle according to the received data, and when the verification is passed, verifies the data output by the receiving channel in the next clock cycle, and when the verification is not passed or the data output by the receiving channel in the last clock cycle is verified, ends the current verification.

[0012] The application has the following beneficial technical effects:

[0013] The module verification method based on the multi-channel secondary cache provided by the application can divide the test into two parts, i.e., an arbitration mechanism and a data completeness check, each part has a respective verification environment, and the two parts are no longer dependent on and influence each other, thereby improving the verification efficiency, reducing the manpower cost and time cost required during verification.

[0014] The application will be further described in detail below with reference to the drawings and embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0015] Figure 1 An optional flowchart of the module verification method based on the multi-channel secondary cache provided by the embodiment of the application;

[0016] Figure 2 A frame schematic diagram of an exemplary verification platform provided by the embodiment of the application;

[0017] Figure 3 A flowchart of the verification of the arbitration signal by the Monitor provided by the embodiment of the application. DETAILED DESCRIPTION

[0018] The application will be described in further detail below with reference to specific embodiments. The embodiments of the application described are not meant to be limiting and that the application will be described with reference to specific embodiments.

[0019] In the description of the application, the terms "first", "second", "third", etc. are used only for descriptive purposes and do not connote or imply a relative importance or an implied order of precedence. Thus, a feature described as a "first", "second", etc. feature can implicitly or explicitly include one or more of the same feature. In the description of the application, the term "plurality" means two or more, unless specifically indicated otherwise.

[0020] In the description of the application, the terms "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" and the like, are intended to mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. The appearances of the phrases "in one embodiment", "in some embodiments", "an example", "a specific example", or "some examples" in various places in the specification are not necessarily referring to the same embodiment or example of the application. Furthermore, the particular features, structures, materials, or characteristics can be combined in any suitable manner in one or more embodiments or examples. It will also be appreciated by those of skill in the art that one or more applications described herein can include, consist essentially of, or consist of, any of the described embodiments, features, structures, materials, or characteristics, in combination with one another or in combination with other

[0021] Although the application herein has been described with reference to particular embodiments thereof, those skilled in the art will be able to appreciate that many other variations of the application can be practiced under the general principles described herein. For example, other object shapes, sizes, and materials can be used. Other variations can be made to the application in light of the above detailed description. In the claims, the use of the term "including" does not mean that other components or steps are excluded. In the claims, the use of the indefinite article "a" or "an" does not exclude a plurality. A single processor or other unit can implement several of the functions recited in the claims. Measures recited in mutually different dependent claims do not preclude combination of these measures in a single claim.

[0022] Figure 1 is an optional flowchart of the module verification method based on the multi-channel secondary cache provided by the embodiments of the application, as shown in Figure 1 The method comprises the following steps:

[0023] S101, the excitation generator sends a current control signal to the multi-channel secondary cache and the monitor; the current control signal comprises at least two output channels, at least one receiving channel, and data of each output channel.

[0024] The module verification method based on the multi-channel secondary cache provided by the application can be applied to a verification platform, such as Figure 2As shown, the verification platform can include: a Driver (excitation generator), a DUT (multi-channel secondary cache), a Monitor (monitor), a Model (arithmetic unit, i.e., a virtual component generated using Systemverilog and having the same function as the multi-channel secondary cache to be tested according to the function of the multi-channel secondary cache to be tested), and a Scoreboard (comparator); wherein the Model (arithmetic unit) and the Scoreboard (comparator) can be collectively referred to as an arithmetic comparator. As shown in Figure 2 As shown, data transmission can be performed between corresponding components, and TLM2.0 communication can be performed between the components, and the transmission of information between the components relies on transactions. The Driver, the DUT, the Monitor, the Model, and the Scoreboard can each be a software module. The verification platform can verify the arbitration mechanism of the DUT (multi-channel secondary cache) through the Driver and the Monitor, and verify the data completeness of the multi-channel secondary cache through the Driver, the DUT, the Monitor, the Model, and the Scoreboard.

[0025] Here, the verification platform can be constructed from bottom to top based on the UVW verification component tree structure.

[0026] Here, different control signals can be sent by the excitation generator by calling different test files, and different control signals can be sent by the excitation generator each time by simultaneously calling multiple test files. The test file can include a specified output channel, a specified receiving channel corresponding to the specified output channel, and a specified data type (for example, 64 bits or 256 bits, etc.), i.e., for indicating that the specified output channel of the multi-channel secondary cache sends what type of data to the specified receiving channel.

[0027] Here, the current control signal can be a control signal generated by calling a certain test file; and different control signals can be generated each time when a test file is called. The current control signal can include the addresses of at least two output channels, the address of at least one receiving channel, and the data to be sent by each output channel.

[0028] Here, the following method can be used to batch call test files through scripts: first, a TEST variable can be added to the Makefile, and the value of the TEST variable is specified as the file name of each test file; then, the file name can be added when sending a verification command to the verification platform, and the Makefile file can find the test file to be run this time according to the externally input file name.

[0029] Here, the multi-channel secondary cache includes a plurality of output channels and a plurality of receiving channels, each receiving channel being a memory ram.

[0030] S102, in response to the current control signal, in the current clock cycle, the multi-channel secondary cache simultaneously sends data to each receiving channel using at least two output channels, and determines the actual output channel corresponding to each receiving channel in the current clock cycle from the at least two output channels, and stores the data sent by the actual output channel of the receiving channel.

[0031] In the embodiment of the application, the multi-channel secondary cache itself stores preset arbitration information, which can be a preset arbitration operation function; the multi-channel secondary cache selects an actual output channel for each receiving channel from the at least two output channels in each clock cycle using the preset arbitration operation function, so that each receiving channel (for example, receiving channel A) can receive and store the data sent by the actual output channel in the corresponding clock cycle.

[0032] S103, the multi-channel secondary cache generates an arbitration signal for each receiving channel in the current clock cycle and sends it to the monitor, and outputs the data received by the receiving channel in the current clock cycle to the operation comparator.

[0033] In the embodiment of the application, when each receiving channel of the multi-channel secondary cache receives the data sent by the at least two output channels in the current clock cycle, the multi-channel secondary cache generates an arbitration signal for receiving channel A in the current clock cycle.

[0034] Specifically, for receiving channel A, when the current clock cycle is the first clock cycle in which the current control signal is received, the multi-channel secondary cache generates an arbitration signal for representing that the at least two output channels simultaneously send data to receiving channel A; the arbitration signal contains the addresses of the at least two output channels and the address of receiving channel A. When the current clock cycle is the Nth clock cycle in which the current control signal is received, the multi-channel secondary cache generates an arbitration signal for representing that the at least one output channel simultaneously sends data to receiving channel A; the arbitration signal contains the address of the at least one output channel and the address of receiving channel A; N is an integer greater than or equal to 2.

[0035] S104, the monitor obtains the data sent to the receiving channel in the current clock cycle from the at least two output channels and sends it to the operation comparator, verifies the arbitration signal of the receiving channel in the current clock cycle according to the current control signal, and when the verification is passed, continues to receive and verify the arbitration signal of the receiving channel in the next clock cycle, and when the received arbitration signal of the receiving channel is not verified or the last arbitration signal of the receiving channel is verified, the current verification is ended.

[0036] Here, the monitor contains a plurality of first queues corresponding to the plurality of output channels of the multi-channel secondary cache, for example, Figure 2 a plurality of queue_a contained in the Monitor; and further contains a plurality of second queues corresponding to the plurality of receiving channels of the multi-channel secondary cache, for example, Figure 2 a plurality of queue_d contained in the Monitor.

[0037] Here, the monitor stores the same preset arbitration information as the multi-channel secondary cache, and the monitor can verify the arbitration signal generated by the receiving channel A of the multi-channel secondary cache according to the preset arbitration information and the control information.

[0038] Here, the monitor can obtain the data to be sent to the receiving channel A by each output channel in the current clock cycle from the at least two output channels of the multi-channel secondary cache when receiving the prompt signal sent by the excitation generator in the current clock cycle, and then store the data to be sent by each output channel in the at least two output channels in the corresponding second queue.

[0039] In some embodiments, the verification of the arbitration signal of the receiving channel in the current clock cycle according to the current control signal in S104, when the verification is passed, continue to receive and verify the arbitration signal of the receiving channel in the next clock cycle, until the received arbitration signal of the receiving channel is not passed or the last arbitration signal of the receiving channel is passed, end the current verification, which can be implemented as:

[0040] S1041, when the current clock cycle is the first clock cycle in which the current control signal is received, at least two output channels are obtained according to the current control signal.

[0041] Specifically, when the current clock cycle is the first clock cycle in which the current control signal is received, the at least two output channels can be obtained from the current control signal, and at least two first queues corresponding to the at least two output channels can be determined from the plurality of first queues contained in the monitor, and then the address of the receiving channel A can be obtained from the control signal, and the address of the receiving channel A can be used as the first address of the at least two first queues.

[0042] S1042, when the at least two output channels obtained match the output channels contained in the arbitration signal of the receiving channel in the current clock cycle, it is indicated that the arbitration signal of the receiving channel in the current clock cycle is verified.

[0043] Specifically, the address of the output channel and the address of the receiving channel contained in the arbitration signal of the receiving channel A in the current clock cycle can be determined, and the arbitration signal of the receiving channel A in the current clock cycle is verified when the address of the receiving channel contained in the arbitration signal of the receiving channel A in the current clock cycle is the same as the first address of the first queue of the at least two first queues.

[0044] S1043, according to the at least two output channels and the preset arbitration information, the output channel that sends data to the receiving channel in the next clock cycle is determined, and the expected channel in the next clock cycle is obtained.

[0045] Specifically, the expected sending channel of the receiving channel A in the current clock cycle can be determined according to the preset arbitration information and the output channel contained in the arbitration signal of the receiving channel A in the current clock cycle, and the first address of the first queue corresponding to the expected sending channel in the at least two first queues is deleted, so that at least one first queue with the first address being the address of the receiving channel A is obtained. The output channel corresponding to the at least one first queue is the expected channel of the receiving channel A in the next clock cycle.

[0046] S1044, when the arbitration signal of the receiving channel in the next clock cycle is received, the expected channel in the next clock cycle is used to verify the arbitration signal of the receiving channel in the next clock cycle, and when the verification is passed, the arbitration signal of the receiving channel in the next clock cycle is continuously received and verified, and when the verification of the received arbitration signal of the receiving channel is not passed or the verification of the last arbitration signal of the receiving channel is passed, the current verification is ended.

[0047] Here, the principle of using the expected channel in the next clock cycle to verify the arbitration signal of the receiving channel in the next clock cycle can be: comparing the expected channel in the next clock cycle with the output channel contained in the arbitration signal of the receiving channel in the next clock cycle to obtain a comparison result; when the comparison result indicates that the expected channel in the next clock cycle is consistent with the output channel contained in the arbitration signal of the receiving channel in the next clock cycle, the verification is passed; when the comparison result indicates that the expected channel in the next clock cycle is inconsistent with the output channel contained in the arbitration signal of the receiving channel in the next clock cycle, the verification fails.

[0048] Specifically, when the arbitration signal of the receiving channel A in the next clock cycle is received, the address of the output channel and the address of the receiving channel contained in the arbitration signal of the receiving channel A in the next clock cycle are determined. When the address of the receiving channel contained in the arbitration signal of the receiving channel A in the next clock cycle is the same as the first address of at least one first queue, it indicates that the arbitration signal of the receiving channel A in the next clock cycle has been verified. After that, the receiving channel A arbitration signal in the next clock cycle can continue to be received and verified until the verification of the received arbitration signal of the receiving channel A fails or the verification of the last arbitration signal of the receiving channel A passes, at which point the current verification ends.

[0049] For example, Figure 3 A flowchart for the Monitor to verify the arbitration signal, and in Figure 3 In this context, the control signals include the addresses of output channel 1 and output channel 2, and the address of receive channel 1. For example... Figure 3 As shown, the Monitor first obtains the current control signal from the Driver, and determines the first queue 1 corresponding to output channel 1 and the first queue 2 corresponding to output channel 2 from the multiple first queues it contains, and uses the address of receiving channel 1 as the starting address of the first queue 1 and the first queue 2. When the Monitor receives the arbitration signal for the current clock cycle of receive channel 1 sent by the DUT, it records the addresses of the output channel and the receive channel contained in the arbitration signal. It then locates the first queue corresponding to the recorded output channel and checks if the starting address of the first queue matches the recorded receive channel address. If the starting address of the first queue is not the recorded receive channel address, the verification of the arbitration signal for the current clock cycle of receive channel 1 fails, indicating an error in the arbitration mechanism of receive channel 1 in the multi-channel L2 buffer. If the starting addresses of the first queues all match the recorded receive channel addresses, the Monitor determines, based on its own arbitration information, which output channel data receive channel 1 should receive in the current clock cycle. If the determined output channel is output channel 1, the Monitor deletes the starting address of the first queue 1 corresponding to output channel 1. At this point, the starting address of the first queue 2 corresponding to output channel 2 becomes the address of receive channel 1, and the Monitor waits for the next clock cycle. When the next clock cycle arrives, the Monitor verifies the arbitration signal for the next clock cycle of receive channel 1 based on the starting address of the first queue 2, continuing this process until the current verification ends.

[0050] Here, the next clock cycle is the clock cycle following the next clock cycle. The verification principle for the arbitration signal of the receiving channel A in the next clock cycle is the same as that in S1041 to S1044 above.

[0051] Here, the number of clock cycles can be the same as the number of output channels sending data to the receiving channel A at the same time in the current control signal.

[0052] Here, the end of the current verification means the end of the verification of the multi-channel secondary cache according to the current control signal; and then, the next verification of the multi-channel secondary cache can be continued according to the next control signal sent by the stimulus generator until the verification is stopped when the stimulus generator no longer sends the control signal.

[0053] S105, the operation comparator verifies the data output by the receiving channel in the current clock cycle according to the received data, and when the verification is passed, verifies the data output by the receiving channel in the next clock cycle, and when the verification is failed or the verification of the data output by the receiving channel in the last clock cycle is passed, ends the current verification.

[0054] Here, the operation comparator includes an operation device and a comparator, wherein the operation device performs operation processing on the data sent by at least two output channels to the receiving channel in the current clock cycle to obtain operation data; and the comparator verifies the data output by the receiving channel in the current clock cycle using the operation data, and when the verification is passed, verifies the data output by the receiving channel in the next clock cycle, and when the verification is failed or the verification of the data output by the receiving channel in the last clock cycle is passed, ends the current verification.

[0055] Here, since the multi-channel secondary cache will store the received data after some processing, the data output by the multi-channel secondary cache to the comparator is processed by the multi-channel secondary cache; and the data obtained by the monitor from the output end of the multi-channel secondary cache is not processed by the multi-channel secondary cache, so the operation device needs to perform the same processing on the data obtained by the monitor from the output end of the multi-channel secondary cache as the multi-channel secondary cache, and then send the obtained processed data to the comparator, and the comparator verifies the data sent by the multi-channel secondary cache using the processed data.

[0056] Here, the principle of the comparator verifying the data output by the receiving channel A in the current clock cycle using the operation data sent by the operation device is as follows:

[0057] The comparator compares the operation data with the data output by the receiving channel A in the current clock cycle to obtain a comparison result; when the comparison result indicates that the operation data contains the data output by the receiving channel A in the current clock cycle, it means that the verification is passed; and when the comparison result indicates that the operation data does not contain the data output by the receiving channel A in the current clock cycle, it means that the verification is failed.

[0058] In some embodiments, the verification platform further comprises a function coverage statistic, and the component can also be a software module. Correspondingly, when verification is performed using the verification platform, the following steps are further included:

[0059] S201, the excitation generator sends the current control signal to the function coverage statistic.

[0060] Here, S201 can be performed simultaneously with S101, or before or after S101.

[0061] S202, the function coverage statistic determines at least two output channels and a receiving channel in the current control signal as current verified channels.

[0062] S203, the function coverage statistic updates the preset to-be-verified channels according to the current verified channels, obtains current to-be-verified channels, and when the next control signal sent by the excitation generator is received, determines the next verified channels, updates the current to-be-verified channels according to the next verified channels, obtains the next to-be-verified channels, and outputs the to-be-verified channels corresponding to the verification stop when the verification stops.

[0063] Here, the preset to-be-verified channels can be to-be-verified receiving channels and output channels of the multi-channel second-level cache, and the preset to-be-verified channels can be preset channels contained in multiple warehouses of different types, for example, the multiple warehouses of different types can be traversal warehouses and random warehouses, wherein each channel contained in the traversal warehouse needs to be verified, and when any channel contained in the random warehouse is verified, all channels contained in the random warehouse can be considered as being verified; and each warehouse can include at least one channel.

[0064] Here, when the function coverage statistic obtains the at least two output channels and the at least one receiving channel from the current control signal, the at least two output channels and the at least one receiving channel can be searched from each warehouse. If the at least two output channels or the at least one receiving channel are located in a traversal warehouse, the at least two output channels or the at least one receiving channel contained in the traversal warehouse are marked as verified, and the remaining unmarked channels in the traversal warehouse, unmarked channels in other traversal warehouses, and channels contained in other random warehouses are new to-be-verified channels (i.e., updated to-be-verified channels). If the at least two output channels or the at least one receiving channel are located in a random warehouse, all channels contained in the random warehouse are marked as verified, and unmarked channels in other traversal warehouses and channels contained in other random warehouses are new to-be-verified channels (i.e., updated to-be-verified channels).

[0065] Here, the verification stop can refer to the end of the current secondary verification of the multi-channel secondary cache according to the current control signal, or can refer to the failure of the arbitration signal or the data verification of the received channel output, or can refer to that the excitation generator no longer sends the control signal.

[0066] The embodiment of the present application can divide the test into two parts, i.e., the arbitration mechanism and the data integrity check, each part has a respective verification environment, and the two parts of verification no longer depend on and affect each other, thereby improving the verification efficiency, reducing the manpower cost and time cost required during verification.

[0067] In general, according to the characteristics of the secondary cache, the present application strips the secondary cache function, divides the comparison of data integrity and the arbitration function between channels into two parts to build a verification environment, increases the feasibility of the verification plan, avoids the mutual conflict and influence of the data integrity comparison and the arbitration mechanism verification environment, avoids generating a complex use case, splits the complex test scene into two simple parts, is beneficial to generate a more complete excitation, completes the verification of the multi-channel secondary cache, and uses the Makefile script and the UVM language characteristics to simultaneously run multiple test files, uses the script file to run each test file multiple times, and generates content to ensure randomness, thereby guaranteeing the completeness of the verification.

[0068] The above is a further detailed description of the present application in combination with a specific preferred embodiment, and the specific implementation of the present application cannot be limited to these descriptions. For ordinary skilled persons in the technical field to which the present application belongs, a number of simple deductions or replacements can be made without departing from the concept of the present application, and all of them should be regarded as falling within the protection scope of the present application.

Claims

1. A module verification method based on multi-channel secondary cache, applied to a verification platform, characterized in that, include: The excitation generator sends a current control signal to the multi-channel L2 buffer and the monitor; the current control signal includes at least two output channels, at least one receive channel, and data for each output channel. In response to the current control signal, within the current clock cycle, the multi-channel secondary buffer simultaneously transmits the data to each receiving channel using the at least two output channels, and determines the actual output channel corresponding to each receiving channel within the current clock cycle from the at least two output channels, and stores the data transmitted by the actual output channel of that receiving channel; wherein, the multi-channel secondary buffer uses a preset arbitration function to select one actual output channel from the at least two output channels for each receiving channel within each clock cycle; The multi-channel secondary buffer generates an arbitration signal for each receiving channel in the current clock cycle and sends it to the monitor, outputting the data received by that receiving channel in the current clock cycle to the arithmetic comparator; The monitor acquires the data sent to the receiving channel in the current clock cycle from the at least two output channels and sends it to the arithmetic comparator. It verifies the arbitration signal of the receiving channel in the current clock cycle according to the current control signal. When the verification is successful, it continues to receive and verify the arbitration signal of the receiving channel in the next clock cycle until the verification of the received arbitration signal of the receiving channel fails or the verification of the last arbitration signal of the receiving channel is successful, at which point the current verification ends. The arithmetic comparator verifies the data output by the receiving channel in the current clock cycle based on the received data. If the verification is successful, it verifies the data output by the receiving channel in the next clock cycle until the verification fails or the data output by the receiving channel in the last clock cycle is verified, at which point the current verification ends.

2. The module verification method based on multi-channel secondary cache according to claim 1, characterized in that, The multi-channel secondary buffer generates arbitration signals for each receive channel within the current clock cycle, including: When the current clock cycle is the first clock cycle in which the current control signal is received, the multi-channel secondary buffer generates an arbitration signal to characterize that the at least two output channels are simultaneously sending data to the receiving channel; the arbitration signal contains the addresses of the at least two output channels and the address of the receiving channel; When the current clock cycle is the Nth clock cycle since the current control signal was received, the multi-channel secondary buffer generates an arbitration signal to characterize that at least one output channel is simultaneously sending data to the receiving channel; the arbitration signal contains the address of the at least one output channel and the address of the receiving channel; N is an integer greater than or equal to 2.

3. The module verification method based on multi-channel secondary cache according to claim 2, characterized in that, The actual output channel is determined by the multi-channel secondary cache based on preset arbitration information; The step of verifying the arbitration signal of the receiving channel in the current clock cycle according to the current control signal, and continuing to receive and verify the arbitration signal of the receiving channel in the next clock cycle when the verification is successful, until the verification of the received arbitration signal of the receiving channel fails or the verification of the last arbitration signal of the receiving channel is successful, and then ending the current verification, includes: When the current clock cycle is the first clock cycle in which the current control signal is received, the at least two output channels are obtained according to the current control signal; When the obtained at least two output channels match the output channels included in the arbitration signal of the receiving channel in the current clock cycle, it indicates that the arbitration signal of the receiving channel in the current clock cycle has been verified. Based on the obtained at least two output channels and the preset arbitration information, determine the output channel that simultaneously sends data to the receiving channel in the next clock cycle, and obtain the expected channel in the next clock cycle. When an arbitration signal for the receiving channel is received in the next clock cycle, the expected channel for the next clock cycle is used to verify the arbitration signal for the receiving channel in the next clock cycle. If the verification is successful, the receiving channel continues to receive and verify the arbitration signal for the receiving channel in the next clock cycle until the verification of the received arbitration signal for the receiving channel fails or the verification of the last arbitration signal for the receiving channel passes, at which point the current verification ends.

4. The module verification method based on multi-channel secondary cache according to claim 3, characterized in that, The step of verifying the arbitration signal of the received channel in the next clock cycle using the expected channel in the next clock cycle includes: The expected channel in the next clock cycle is compared with the output channel contained in the arbitration signal of the received channel in the next clock cycle to obtain the comparison result; The verification is considered successful when the comparison result indicates that the expected channel in the next clock cycle is consistent with the output channel contained in the arbitration signal of the received channel in the next clock cycle. The verification fails when the comparison result indicates that the expected channel in the next clock cycle is inconsistent with the output channel contained in the arbitration signal of the received channel in the next clock cycle.

5. The module verification method based on multi-channel secondary cache according to claim 2, characterized in that, The actual output channel is determined by the multi-channel secondary cache based on preset arbitration information; the monitor contains multiple first queues that correspond one-to-one with the multiple output channels of the multi-channel secondary cache; the current control signal contains the addresses of at least two output channels and the address of at least one receiving channel; The step of verifying the arbitration signal of the receiving channel in the current clock cycle according to the current control signal, and continuing to receive and verify the arbitration signal of the receiving channel in the next clock cycle when the verification is successful, until the verification of the received arbitration signal of the receiving channel fails or the verification of the last arbitration signal of the receiving channel is successful, and then ending the current verification, includes: When the current clock cycle is the first clock cycle in which the current control signal is received, the address of the receiving channel in the control signal is used as the first address of the at least two first queues that correspond one-to-one with the at least two output channels. Determine the address of the output channel and the address of the receiving channel contained in the arbitration signal of the receiving channel within the current clock cycle; If the address of the receiving channel contained in the arbitration signal of the receiving channel during the current clock cycle is the same as the first address of the at least two first queues, it indicates that the arbitration signal of the receiving channel during the current clock cycle has been verified. Based on the preset arbitration information and the output channel contained in the arbitration signal of the receiving channel in the current clock cycle, the expected transmission channel of the receiving channel in the current clock cycle is determined, and the first address of the first queue corresponding to the expected transmission channel in the at least two first queues is deleted to obtain at least one first queue whose first address is the address of the receiving channel. When the arbitration signal of the receiving channel is received in the next clock cycle, the address of the output channel and the address of the receiving channel contained in the arbitration signal of the receiving channel in the next clock cycle are determined. When the address of the receiving channel contained in the arbitration signal of the receiving channel in the next clock cycle is the same as the first address of the at least one first queue, it indicates that the arbitration signal of the receiving channel in the next clock cycle has been verified. The receiving and verification of the arbitration signal of the receiving channel in the next clock cycle continues until the verification of the received arbitration signal of the receiving channel fails or the verification of the last arbitration signal of the receiving channel passes, at which point the current verification ends.

6. The module verification method based on multi-channel secondary cache according to claim 1, characterized in that, The arithmetic comparator includes: an arithmetic unit and a comparator; The comparator verifies the data output by the receiving channel within the current clock cycle based on the received data. If the verification passes, it verifies the data output by the receiving channel in the next clock cycle, until the verification fails or the data output by the receiving channel in the last clock cycle passes the verification, at which point the current verification ends. This includes: The arithmetic unit processes the data sent to the receiving channel by the at least two output channels within the current clock cycle to obtain processed data. The comparator uses the computational data to verify the data output by the receiving channel in the current clock cycle. If the verification is successful, it verifies the data output by the receiving channel in the next clock cycle until the verification fails or the data output by the receiving channel in the last clock cycle is verified, at which point the current verification ends.

7. The module verification method based on multi-channel secondary cache according to claim 6, characterized in that, The comparator uses the calculated data to verify the data output by the receiving channel within the current clock cycle, including: The comparator compares the processed data with the data output by the receiving channel in the current clock cycle to obtain a comparison result; The verification is successful when the comparison result indicates that the calculated data includes the data output by the receiving channel within the current clock cycle. If the comparison result indicates that the calculated data does not contain the data output by the receiving channel within the current clock cycle, the verification fails.

8. The module verification method based on multi-channel secondary cache according to claim 1, characterized in that, The method further includes: The excitation generator sends the current control signal to the function coverage statistician; The function coverage statistician determines the at least two output channels and the receiving channel in the current control signal as currently verified channels; The function coverage statistician updates the preset channels to be verified based on the currently verified channels to obtain the current channels to be verified. When it receives the next control signal sent by the excitation generator, it determines the next verified channel and updates the current channels to be verified based on the next verified channel to obtain the next channels to be verified. This process continues until verification stops, at which point it outputs the channel to be verified corresponding to the point when verification stops.

9. The module verification method based on multi-channel secondary cache according to claim 1, characterized in that, The monitor includes multiple second queues that correspond one-to-one with the multiple receive channels of the multi-channel secondary buffer; after the monitor obtains the data sent to the receive channel in the current clock cycle from the at least two output channels, it stores the data sent by each of the at least two output channels into the corresponding second queue.

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