An FPGA that realizes data transmission through a built-in edge module

Abstract

The present application discloses an FPGA that realizes data transmission through a built-in edge module, relating to the technical field of FPGAs. This FPGA has a built-in edge module, and the read port of each resource module connected to the edge module in the FPGA is simultaneously connected to the winding architecture and the edge module, and / or the write port is simultaneously connected to the winding architecture and the edge module; the edge module includes a read-write controller and a cache unit. The read-write controller simultaneously reads data from the read ports of multiple resource modules and temporarily stores the data in the cache unit, or the read-write controller simultaneously writes the data temporarily stored in the cache unit into the write ports of multiple resource modules. This FPGA can simultaneously perform data reading and writing on multiple resource modules through the built-in edge module, thereby realizing high-speed and high-bandwidth data transmission and improving the performance of the FPGA.

Description

Technical Field

[0001] The present invention relates to the field of FPGAs, and in particular to an FPGA that realizes data transmission through an embedded edge module. Background Art

[0002] An FPGA (Field Programmable Gate Array) internally contains a large number of resource modules such as CLBs, BRAMs, DSPs, and IOBs. These resource modules achieve signal interconnection through a wiring architecture to implement the required user design. In recent years, in fields such as artificial intelligence applications and communication signal processing, higher performance requirements have been put forward for the computing power and speed of FPGAs. How to achieve high-speed data transmission has become a technical focus in the development of high-capacity FPGAs. Summary of the Invention

[0003] In view of the above problems and technical requirements, the applicant of the present application proposes an FPGA that realizes data transmission through an embedded edge module. The technical solution of the present application is as follows:

[0004] An FPGA that realizes data transmission through an embedded edge module, the FPGA is embedded with an edge module connected to a plurality of resource modules within the FPGA, and the read port of each resource module is simultaneously connected to the wiring architecture and the edge module and / or the write port is simultaneously connected to the wiring architecture and the edge module;

[0005] The edge module includes a read-write controller and a cache unit. The read-write controller simultaneously reads data from the read ports of a plurality of resource modules and temporarily stores the data in the cache unit, or the read-write controller simultaneously writes the data temporarily stored in the cache unit into the write ports of a plurality of resource modules.

[0006] A further technical solution thereof is that the cache unit embedded in the edge module includes a plurality of read cache units and at least one write cache unit. The data simultaneously read by the read-write controller from the read ports of a plurality of resource modules are respectively temporarily stored in each read cache unit, and each read cache unit is used to temporarily store the data read from the read port of one resource module; the data simultaneously written by the read-write controller to the write ports of a plurality of resource modules comes from one or more write cache units, and the data in each write cache unit is simultaneously written into the write ports of one or more resource modules.

[0007] A further technical solution thereof is that the resource module connected to the edge module has both a read port and a write port at the same time, and the read-write controller simultaneously reads data from the read port of the same resource module and writes data to the write port of the resource module.

[0008] A further technical solution is that each read cache unit built in the edge module is respectively connected to the read ports of multiple resource modules. Each read port of a resource module is respectively connected to the corresponding read cache unit through a tri-state selector. The read-write controller controls the on / off of each tri-state selector and reads data from one of the read ports of the resource modules connected to the read cache unit each time; each write cache unit built in the edge module is respectively connected to the write ports of multiple resource modules. The read-write controller writes the data in one write cache unit into all the write ports of the connected resource modules or into the write ports of some of the connected resource modules each time.

[0009] A further technical solution is that each read cache unit built in the edge module is simultaneously connected to each write cache unit. The data written by the read-write controller to the write port of any first resource module is the data read by the read-write controller from the read port of another second resource module. The read-write controller reads the data from the read port of the second resource module and temporarily stores it in the read cache unit connected to the read port of the second resource module. The read-write controller controls to write the data in the read cache unit connected to the read port of the second resource module into the write cache unit connected to the write port of the first resource module, and then writes the data in the write cache unit connected to the first resource module into the write port of the first resource module.

[0010] A further technical solution is that the data written by the read-write controller to the write ports of multiple first resource modules simultaneously is the data read by the read-write controller from the read ports of one or more other second resource modules; the data read from the read port of each second resource module is written into the write ports of one or more first resource modules.

[0011] A further technical solution is that the resource modules connected to the edge module are arranged in an array structure. The same read cache unit is connected to the read ports of multiple resource modules in the same column, and the same write cache unit is connected to the write ports of multiple resource modules in the same column;

[0012] The read-write controller reads data from the read ports of multiple second resource modules in the same row simultaneously, or the read-write controller writes data to the write ports of multiple first resource modules in the same row simultaneously.

[0013] A further technical solution is that the cache unit of the edge module is also connected to the off-chip read-write port of the FPGA. The data read by the read-write controller from the read port of the resource module and temporarily stored in the read cache unit is transmitted to the outside of the FPGA through the off-chip read-write port, or the data written by the read-write controller to the write port of the resource module is the data that is transmitted from the outside of the FPGA through the off-chip read-write port and temporarily stored in the write cache unit; the off-chip read-write port of the FPGA is a high-speed serial port and / or a DDR IO port.

[0014] A further technical solution is that the edge module is simultaneously connected to multiple off-chip read / write ports, and the read / write controller simultaneously transmits the data temporarily stored in multiple read buffer units to the outside of the FPGA via the multiple off-chip read / write ports respectively. Alternatively, the read / write controller simultaneously writes the data input from the outside of the FPGA into multiple write buffer units through the multiple off-chip read / write ports.

[0015] A further technical solution is that the buffer unit built in the edge module is a FIFO, and the read / write speed of the off-chip read / write port for the buffer unit matches the read / write speed of the read / write controller for the resource module.

[0016] A further technical solution is that the edge module further includes a read / write signal generation circuit. The read / write signal generation circuit is connected to the read / write control port of the resource module. The read / write controller generates a read / write control signal through the read / write signal generation circuit and sends it to the read / write control port of the resource module, and reads data from the read ports of multiple resource modules or simultaneously writes data to the write ports of multiple resource modules according to the read / write control signal.

[0017] A further technical solution is that the edge module includes a read / write signal generation circuit, and the read / write signal generation circuit is connected to the read / write control ports of all resource modules; or the edge module includes multiple read / write signal generation circuits, each read / write signal generation circuit is connected to the read / write control port of one or more resource modules, and each read / write signal generation circuit sends a read / write control signal to the read / write control port of the connected resource module.

[0018] A further technical solution is that the resource module connected to the edge module is a BRAM module, and the read / write control port of each BRAM module includes a read address port, a read enable port, a write address port, and a write enable port;

[0019] The read / write signal generation circuit built in the edge module includes a read address generator, a read enable generator, a write address generator, and a write enable generator. The read address generator is connected to the read address port of the BRAM module, the read enable generator is connected to the read enable port of the BRAM module, the write address generator is connected to the write address port of the BRAM module, and the write enable generator is connected to the write enable port of the BRAM module;

[0020] The read / write control signal generated by the read / write signal generation circuit includes the read address generated by the read address generator, the read enable generated by the read enable generator, the write address generated by the write address generator, and the write enable generated by the write enable generator.

[0021] Its further technical solution is that multiple BRAM modules connected to the edge module at the same time form a full-chip storage array. The read-write controller in the edge module provides corresponding read enable and write enable to each BRAM module through the read-write signal generation circuit according to the obtained full-chip enable signal. The read-write controller in the edge module provides corresponding read address and write address to each BRAM module through the read-write signal generation circuit according to the obtained full-chip enable signal and full-chip address signal.

[0022] The beneficial technical effects of this application are:

[0023] This application discloses an FPGA that realizes data transmission through an embedded edge module. The FPGA can read and write data to multiple resource modules simultaneously through the embedded edge module, thereby realizing high-speed and high-bandwidth data transmission and improving the performance of the FPGA.

[0024] Using the embedded edge module can not only realize efficient data transmission between different resource modules within the FPGA, but also realize efficient data transmission inside and outside the FPGA. Moreover, the implementation cost of the edge module is relatively low, making it suitable for various applications involving large amounts of data processing. Description of the Drawings

[0025] Figure 1 is a schematic connection diagram of the edge module and the resource module in an embodiment of this application.

[0026] Figure 2 is a schematic connection diagram of the edge module, the resource module and the off-chip read-write port in an embodiment of this application.

[0027] Figure 3 is a schematic connection diagram of the edge module and the BRAM module in an embodiment of this application.

[0028] Figure 4 is a schematic connection diagram of the edge module and the BRAM module in another embodiment of this application. Detailed Embodiments

[0029] The following further describes the detailed embodiments of this application with reference to the drawings.

[0030] This application discloses an FPGA that realizes data transmission through an embedded edge module. Please refer to Figure 1 , this FPGA, like a conventional FPGA, has a large number of resource modules such as CLB, BRAM, DSP, and IOB embedded. These resource modules are generally arranged in an array structure. In addition, this FPGA also additionally embeds an edge module through hardware resources. The newly added edge module is connected to multiple original resource modules within the FPGA. This edge module is generally embedded at the bottom of the array formed by the resource modules, with a relatively low manufacturing cost.

[0031] In a conventional FPGA, the read port RD and / or write port WD of each resource module are connected to the interconnection resource module INT to access the routing architecture, so that data transmission and communication between two resource modules can be achieved by connecting to the read port or write port of other resource modules via the routing architecture. Based on this, in the FPGA of the present application, while retaining the data path between the resource module and the routing architecture, the resource module is further connected to the newly added edge module. That is, the read port RD of a resource module is simultaneously connected to the routing architecture and the edge module, and / or the write port WD of a resource module is simultaneously connected to the routing architecture and the edge module, enabling the resource module to implement data transmission and communication with other resource modules via the routing architecture as in the traditional method, and also enabling data transmission and communication with other resource modules connected to the edge module via the edge module. As Figure 1 shown, the write port WD of the resource module is generally connected to the interconnection resource module INT and the edge module through a multiplexer. That is, the write port WD of the resource module is connected to the output end of a multiplexer, one input end of the multiplexer is connected to the interconnection resource module INT, and the other input end is connected to the edge module. By controlling the gating state of the multiplexer, a path can be formed between the write port WD of the resource module and the interconnection resource module INT or a path can be formed between the write port WD and the edge module.

[0032] In actual implementation, a resource module may only have its read port RD connected to the edge module, or only have its write port WD connected to the edge module, or, as Figures 1 - 4 shown in the example, both the read port RD and the write port WD of a resource module are connected to the edge module.

[0033] The edge module includes a read / write controller and a cache unit. The connection between the resource module and the edge module is as follows: the read port RD and / or write port WD of the resource module are connected to the cache unit in the edge module. As Figures 1 - 4 shown, Figures 1 - 4 the read / write controller in the edge module is not shown in both cases.

[0034] The read-write controller reads data from the read ports of multiple resource modules simultaneously and temporarily stores it in the cache unit, or the read-write controller writes the data temporarily stored in the cache unit to the write ports of multiple resource modules simultaneously. That is, by using the newly added edge module in this application, read or write operations can be performed on multiple resource modules at one time, thereby increasing the data bit width of a single read or write and enabling high-speed data transfer within the PFGA. For example, if each resource module has 32-bit data, according to the conventional method, data is read from one resource module at a time, and the data bit width of a single read is 32 bits. In the FPGA of this application, the edge module can be used to read data from 6 resource modules simultaneously, and the data bit width of a single read is 192 bits, which can make the data bit width of a single read very large, and the same is true for write operations.

[0035] To avoid interference between the data of read and write operations, the cache unit built in the edge module includes several read cache units and at least one write cache unit. Each read cache unit is connected to the read port RD of the corresponding resource module, and each write cache unit is connected to the write port WD of the corresponding resource module. The data read by the read-write controller from the read ports of multiple resource modules simultaneously is temporarily stored in each read cache unit respectively, and each read cache unit is used to temporarily store the data read from the read port of one resource module. The data written by the read-write controller to the write ports of multiple resource modules simultaneously comes from one or more write cache units, and the data in each write cache unit is written to the write ports of one or more resource modules simultaneously.

[0036] Based on this, when the read port RD and the write port WD of a resource module are both connected to the edge module, the read-write controller can read data from the read port of this resource module and write data to the write port of this resource module simultaneously, that is, the read and write operations on the same resource module are carried out simultaneously and do not affect each other.

[0037] Since the data read by the read-write controller from the read ports of multiple resource modules simultaneously needs to be temporarily stored in different read cache units, in one embodiment, each read cache unit is only connected to the read port of one resource module, and this condition can always be met. Or in another embodiment, to improve the reusability of the read cache unit, one read cache unit is connected to the read ports of multiple resource modules simultaneously. The read port of each resource module is connected to the corresponding read cache unit through a tri-state selector respectively. The read-write controller controls the on-off of each tri-state selector and reads data from one of the resource modules connected to one read cache unit each time. The read-write controller does not perform simultaneous reading on multiple resource modules connected to the same read cache unit.

[0038] Based on the inherent characteristic that the resource modules inside the FPGA are arranged in an array structure, when one read cache unit is connected to the read ports RD of multiple resource modules, in one embodiment, a relatively common structure is, for exampleFigure 1 As shown, each read cache unit is simultaneously connected to the read ports RD of multiple resource modules located in the same column, and different read cache units are connected to resource modules in different columns. When the read-write controller reads data from the read ports RD of multiple resource modules simultaneously, these multiple resource modules are located in different columns, and data is read from only one resource module in one column each time. For example, in Figure 1 , the resource modules connected to the edge module form an array structure of M rows and N columns. Then the edge module includes N read cache units, which are respectively written as read cache unit 1 to read cache unit N. Read cache unit 1 is connected to the read ports RD of M resource modules in the first column, and read cache unit N is connected to the read ports RD of M resource modules in the Nth column, and so on. The read-write controller can control to read data from the resource module <2,1> in the first column and the second row and temporarily store it in read cache unit 1, and simultaneously read data from the resource module <M,N> in the Nth column and the Mth row and temporarily store it in read cache unit N.

[0039] Regardless of whether a read cache unit is connected to one or multiple resource modules, when the read-write controller reads data from the connected resource modules each time, it can read data from the resource modules connected to all read cache units simultaneously, or can read data from the resource modules connected to some read cache units simultaneously. In actual implementation, it can also read data from the resource modules connected to only one read cache unit. For example, in Figure 1 , assuming N = 40, the read-write controller can simultaneously read data from 40 resource modules and temporarily store them in 40 read cache units respectively, and these 40 resource modules are located in different columns. Or, the read controller can only read data from 20 resource modules simultaneously and temporarily store them in 20 read cache units respectively, and these 20 resource modules are located in different columns. Or it can also read data from only one resource module in one column and temporarily store it in one read cache unit.

[0040] The read-write controller can write the data in one write cache unit into the write ports of one or multiple resource modules at a single time, and the written data is the same. Therefore, in one embodiment, one write cache unit is only connected to the write port WD of one resource module. Or in another embodiment, one write cache unit is simultaneously connected to the write ports WD of multiple resource modules. Similar to the read cache unit, based on the characteristics of the array structure of the resource modules inside the FPGA, when one write cache unit is connected to multiple resource modules, in one embodiment, more commonly, each write cache unit is simultaneously connected to the write ports WD of multiple resource modules located in the same column, and different write cache units are connected to resource modules in different columns. For example, in Figure 1In the [system], the resource modules connected to the edge module form an array structure of M rows and N columns. The edge module includes N write buffer units, which are respectively written as write buffer unit 1 to write buffer unit N. Write buffer unit 1 is connected to the write ports WD of the M resource modules in the first column, write buffer unit N is connected to the write ports WD of the M resource modules in the Nth column, and so on for the others. Each time, the read-write controller writes the data in one write buffer unit to the write ports of all the resource modules connected to it or to the write ports of some of the resource modules connected to it. For example, in Figure 1 it is possible to write the data in write buffer unit 1 to all M resource modules in the first column at the same time, or only write the data in write buffer unit 1 to 5 of the M resource modules in the first column at the same time.

[0041] When the edge module includes multiple write buffer units, in one embodiment, the read-write controller simultaneously writes the data in all write buffer units to the resource modules connected to them respectively. For example, Figure 1 in the edge 5 module includes N write buffer units, the read-write controller writes the data in the N write buffer units to the resource modules in N columns respectively. The data in each write buffer unit can be written to one or more resource modules in the same column. For example, the data in write buffer unit 1 can be written to the resource module in the 5th row and the 10th row of the first column, and at the same time, the data in write buffer unit 2 can be written to the resource modules in the 1st row, the 2nd row, and the 2nd row of the second column,... the data in write buffer unit N is written to all M resource modules in the Nth column.

[0042] Or in another embodiment, the read-write controller simultaneously writes the data in some write buffer units to the write ports of the resource modules connected to them respectively. For example, also in Figure 1 the read-write controller only writes the data in write buffer unit 1 to the resource modules in the first column, and at the same time writes the data in write buffer unit 2 to the resource modules in the second column, without writing data to the resource modules in other columns.

[0043] In one embodiment, each read buffer unit built in the edge module is simultaneously connected to each write buffer unit. For example, Figure 1 in [the system], read buffer unit 1 is respectively connected to N write buffer units, read buffer unit 2 is respectively connected to N write buffer units, and so on for the others, so that the data in any one read buffer unit can be written to any one write buffer unit. Based on this structure, the read-write controller sends data to any first resource module

[0044] The data written to the write port of the block is the data read as 0 by the read-write controller from the read port of other second resource modules. When implementing this function: The read-write controller first reads the data from the read port of the second resource module and temporarily stores it in the read buffer unit connected to the read port of the second resource module. Then, the read-write controller controls to write the data in the read buffer unit connected to the read port of the second resource module into the write buffer unit connected to the write port of the first resource module, and then writes the data in the write buffer unit connected to the write port of the first resource module

[0045] into the write port of the first resource module. In this scenario, the first resource module and the second resource module 5 can be located in the same column or in different columns. The edge module can be used to implement data transmission between the first resource module and the second resource module at any position. It should be noted that in Figures 2 - 4 the embodiment, the read buffer unit and the write buffer unit also have a similar relationship in this embodiment, but Figures 2 - 4 it is not shown again for simplicity in

[0046] For example, in Figure 1 , the first resource module is the resource module <15,10> located in row 15 and column 10, and the second resource module is the resource module <25,10> located in row 25 and column 10. Then, the read-write controller reads the data from the read port RD of the resource module <25,10> and temporarily stores it in the read buffer unit 10, and then controls to write the data in the read buffer unit 10 into the write buffer unit 10, and then writes the data in the write buffer unit 10 into the write port WD of the resource module <15,10>.

[0047] Another example is in Figure 1 , the first resource module is the resource module <15,10> located in row 15 and column 10, and the second resource module is the resource module <17,1> located in row 17 and column 1. Then, the read-write controller reads the data from the read port RD of the resource module <17,1> and temporarily stores it in the read buffer unit 1, and then controls to write the data in the read buffer unit 1 into the write buffer unit 10, and then writes the data in the write buffer unit 10 into the write port WD of the resource module <15,10>.

[0048] On this basis, the data written by the read-write controller to the write ports of multiple first resource modules at the same time is the data read by the read-write controller from the read ports of one or more other second resource modules. The data read from the read port of each second resource module is written to the write ports of one or more first resource modules. When writing the data read from the read port of one second resource module to the write ports of multiple first resource modules, the write ports of these multiple first resource modules can be connected to the same write buffer unit or to different write buffer units. The specific implementation process is the same as that of the above embodiment.

[0049] For example, in Figure 1 Figure 1 , the second resource module is the resource module <17,1> located at the 17th row and the 1st column. The multiple first resource modules include the resource module <15,10> located at the 15th row and the 10th column, the resource module <16,10> located at the 16th row and the 10th column, and the resource module <17,10> located at the 17th row and the 10th column. Then, the read-write controller reads data from the read port RD of the resource module <17,1> and temporarily stores it in the read buffer unit 1, and then controls to write the data in the read buffer unit 1 into the write buffer unit 10, and then writes the data in the write buffer unit 10 into the write ports of the resource module <15,10>, the resource module <16,10>, and the resource module <17,10> simultaneously. In this embodiment, these three first resource modules are all written with the data read from the resource module <17,1> and are connected to the same write buffer unit 10.

[0050] For another example, in Figure 1 Figure 1 , the second resource module is the resource module <17,1> located at the 17th row and the 1st column. The multiple first resource modules include the resource module <15,10> located at the 15th row and the 10th column, the resource module <16,10> located at the 16th row and the 10th column, and the resource module <2,2> located at the 2nd row and the 2nd column. Then, the read-write controller reads data from the read port RD of the resource module <17,1> and temporarily stores it in the read buffer unit 1, controls to write the data in the read buffer unit 1 into the write buffer unit 10 and the write buffer unit 2, and then writes the data in the write buffer unit 10 into the write ports of the resource module <15,10> and the resource module <16,10> simultaneously, and writes the data in the write buffer unit 2 into the write port of the resource module <2,2> simultaneously. In this example, these three first resource modules are all written with the data read from the resource module <17,1> but are connected to different write buffer units.

[0051] For another example, in Figure 1 Figure 1 , the second resource module includes the resource module <17,1> located at the 17th row and the 1st column and the resource module <17,2> located at the 17th row and the 2nd column. The first resource module includes the resource module <19,1> located at the 19th row and the 1st column and the resource module <19,2> located at the 19th row and the 2nd column.

[0052] The read-write controller reads data from the read port RD of the resource module <17,1> and temporarily stores it in the read buffer unit 1, and simultaneously reads data from the read port RD of the resource module <17,2> and temporarily stores it in the read buffer unit 2.

[0053] Then it controls to write the data in the read buffer unit 1 into the write buffer unit 1, write the data in the read buffer unit 2 into the write buffer unit 2. Then it writes the data in the write buffer unit 1 into the resource module <19,1>

[0054] Meanwhile, the data in the write cache unit 2 is written into the resource module <19, 2>. In this example, data is written into two first resource modules simultaneously, and the written data comes from different second resource modules.

[0055] In another embodiment, the read-write controller reads data from the read ports of multiple second resource modules located in the same row simultaneously, or the read-write controller writes data to the write ports of multiple first resource modules located in the same row simultaneously. That is, by using the edge module, data of an entire row can be read from the resource modules of the array structure and then written into another row. The read-write process implemented in this embodiment has very important practical application significance.

[0056] In addition to enabling efficient data transmission within the FPGA through the above various embodiments, please refer to Figure 2 , the cache unit of this edge module is also connected to the off-chip read-write port of the FPGA. The data read from the read port of the resource module 5 by the read-write controller and temporarily stored in the read cache unit is transmitted to the outside of the FPGA via the off-chip read-write port. Thus, the data of the resource module at a specific location in the FPGA can be read out and transmitted to the outside of the FPGA.

[0057] Alternatively, the data written by the read-write controller to the write port of the resource module is input from the outside of the FPGA via the off-chip read-write port and temporarily stored in the write cache unit. Thus, the data outside the FPGA can be written into the resource module at a specific location within the FPGA.

[0058] The off-chip read-write port of the FPGA is a high-speed serial port and / or a DDR IO port. Figure 2 Taking the high-speed transceiver GTH as an example for the high-speed serial port. In addition, the edge module is connected to multiple off-chip read-write ports simultaneously. The read-write controller transmits the data in multiple read cache units to the outside of the FPGA via multiple off-chip read-write ports simultaneously, or

[0059] the read-write controller writes the data input from the outside of the FPGA into multiple write caches

[0060] units through multiple off-chip read-write ports simultaneously, thereby realizing large-bandwidth data transmission between the inside and outside of the FPGA. For example Figure 2 , each write 5 cache unit is respectively connected to a GTH, and each read cache unit is respectively connected to a GTH. Then in this embodiment, the cache unit built in the edge module is implemented by using a FIFO to make the read-write speed of the off-chip read-write port for the cache unit match the read-write speed of the read-write controller for the resource module.

[0061] The resource module connected to the edge module in this application can be various resource modules within the FPGA. Considering that for certain types of resource modules, when reading and writing to the resource module, it is often necessary to provide read and write control signals to the read and write control ports of resource module 0. For example, for the BRAM module, it is necessary to provide a read address and a read enable, or provide a write address and a write enable. Therefore, in one embodiment, the edge module further includes a read and write signal generation circuit. The read and write signal generation circuit is connected to the read and write control ports of the resource module. The read and write controller generates read and write control signals through the read and write signal generation circuit and sends them to the read and write control ports of the resource module, and reads data from the read ports RD of multiple resource modules or writes data to the write ports WD of multiple resource modules simultaneously according to the read and write control signals.

[0062] In one embodiment, all the resource modules connected to the edge module share a read and write signal generation circuit, and the read and write signal generation circuit is connected to the read and write control ports of all the resource modules. Or the edge module includes multiple read and write signal generation circuits, each read and write signal generation circuit is connected to the read and write control ports of one or more resource modules, and each read and write signal generation circuit sends read and write control signals to the read and write control ports of the connected resource modules. Based on the array layout architecture of the resource module, in one embodiment, a more common approach is that the edge module includes multiple read and write signal generation circuits, each read and write signal generation circuit corresponds to a column of resource modules, and each read and write signal generation circuit is connected to the read and write control ports of multiple resource modules in the same column.

[0063] This application mainly uses the edge module to achieve simultaneous reading and writing of multiple resource modules to improve data transmission efficiency. Therefore, the resource modules connected to the edge module are usually resource modules with large data transmission requirements, such as BRMA modules, registers, signal points, etc. More commonly, in one embodiment, the resource module connected to the edge module in the FPGA is a BRAM module, and multiple BRAM modules can be read and written simultaneously through the edge module.

[0064] The read and write control ports of each BRAM module include a write address port WA, a write enable port WEN, a read address port RA, and a read enable port REN. Therefore, when the resource module connected to the edge module is a BRAM module, each read and write signal generation circuit built in the edge module includes a read address generator, a read enable generator, a write address generator, and a write enable generator. The read address generator is connected to the write address port WA of the BRAM module, the read enable generator is connected to the write enable port WEN of the BRAM module, the write address generator is connected to the read address port RA of the BRAM module, and the write enable generator is connected to the read enable port REN of the BRAM module. In one embodiment, the circuit structure when each read and write signal generation circuit is connected to a column of BRAM modules is as Figure 3As shown, when the resource modules form an array structure of M rows and N columns, the edge module includes read / write signal generation circuits 1 to read / write signal generation circuits N, which are respectively used to connect N columns of resource modules. In another embodiment, the read / write signal generation circuits are connected to all BRAM modules, and the circuit structure is as Figure 4 shown.

[0065] Then, the read / write control signals generated by each read / write signal generation circuit include the read address generated by the read address generator, the read enable generated by the read enable generator, the write address generated by the write address generator, and the write enable generated by the write enable generator. The edge module provides a read enable of effective level and a read address to a specific BRAM module through the read / write signal generation circuit, and the read / write controller reads the data in the read address from the read port RD of the BRAM module with the read enable. Alternatively, the edge module provides a write enable of effective level and a write address to a specific BRAM module through the read / write signal generation circuit, and the read / write controller writes data to the

[0066] write port WD of the write address of the BRAM module with the write enable. Based on the structure that the read ports RD of the BRAM modules in the same column are all connected to the same read buffer unit, only one BRAM module in each column receives a read enable of effective level at a time. However, multiple BRAM modules in the same column can receive a write enable of effective level, so as to write the same data to multiple BRAM modules. The read / write operations for the same BRAM module are independent, and the same BRAM module can be enabled for reading and writing at the same time.

[0067] At the same time, multiple BRAM modules connected to the edge module can form a whole-chip storage array. The read / write controller in the edge module 0 reads and writes the whole-chip storage array according to the obtained whole-chip enable signal and whole-chip address signal, that is, the read / write controller in the edge module provides corresponding read enables and write enables to each BRAM module through the read / write signal generation circuit according to the obtained whole-chip enable signal, and the read / write controller in the edge module provides corresponding read addresses and write addresses to each BRAM module through the read / write signal generation circuit according to the obtained whole-chip enable signal and whole-chip address signal.

Claims

1. An FPGA that realizes data transmission through a built-in edge module, characterized in that The FPGA additionally builds an edge module through hardware resources. The newly added edge module is connected to multiple resource modules within the FPGA. The read port and / or write port of each resource module is connected to an interconnection resource module to access the routing architecture. On the basis of retaining the data path between the resource module and the routing architecture, the resource module is further connected to the newly added edge module, so that the read port of each resource module is simultaneously connected to the routing architecture and the edge module and / or the write port is simultaneously connected to the routing architecture and the edge module, enabling the resource module to achieve data transmission and communication with other resource modules via the routing architecture, or to achieve data transmission and communication with other resource modules connected to the edge module via the edge module; The edge module includes a read-write controller and a cache unit. The read-write controller simultaneously reads data from the read ports of multiple resource modules and temporarily stores the data in the cache unit, or the read-write controller simultaneously writes the data temporarily stored in the cache unit into the write ports of multiple resource modules; The cache unit built in the edge module includes a number of read cache units and at least one write cache unit. The data read by the read-write controller simultaneously from the read ports of multiple resource modules is temporarily stored in each read cache unit respectively. Each read cache unit is used to temporarily store the data read from the read port of one resource module; the data written by the read-write controller simultaneously into the write ports of multiple resource modules comes from one or more write cache units, and the data in each write cache unit is simultaneously written into the write ports of one or more resource modules; Each read cache unit built in the edge module is simultaneously connected to each write cache unit. The data written by the read-write controller into the write port of any first resource module is the data read by the read-write controller from the read port of other second resource modules. The read-write controller reads the data from the read port of the second resource module and temporarily stores the data in the read cache unit connected to the read port of the second resource module. The read-write controller controls to write the data in the read cache unit connected to the read port of the second resource module into the write cache unit connected to the write port of the first resource module, and then writes the data in the write cache unit connected to the first resource module into the write port of the first resource module.

2. The FPGA according to claim 1, wherein The resource module connected to the edge module has both a read port and a write port at the same time. The read-write controller simultaneously reads data from the read port of the same resource module and writes data into the write port of the resource module.

3. The FPGA according to claim 1, wherein Each read cache unit built in the edge module is respectively connected to the read ports of multiple resource modules. The read port of each resource module is respectively connected to the corresponding read cache unit through a tri-state selector. The read-write controller controls the on / off of each tri-state selector and reads data from the read port of one of the resource modules connected to the read cache unit each time; each write cache unit built in the edge module is respectively connected to the write ports of multiple resource modules. The read-write controller writes the data in one write cache unit into the write ports of all the resource modules connected thereto or into the write ports of some of the resource modules connected thereto each time.

4. The FPGA according to claim 1, wherein The data written by the read-write controller to the write ports of multiple first resource modules at the same time is the data read by the read-write controller from the read ports of one or more other second resource modules; The data read from the read port of each second resource module is written to the write ports of one or more first resource modules.

5. The FPGA according to claim 4, wherein The resource modules connected to the edge module are arranged in an array structure. The same read cache unit is connected to the read ports of multiple resource modules in the same column, and the same write cache unit is connected to the write ports of multiple resource modules in the same column; The read-write controller reads data from the read ports of multiple second resource modules in the same row at the same time, or the read-write controller writes data to the write ports of multiple first resource modules in the same row at the same time.

6. The FPGA according to claim 1, wherein The cache unit of the edge module is also connected to the off-chip read-write port of the FPGA. The data read by the read-write controller from the read port of the resource module and temporarily stored in the read cache unit is transmitted to the outside of the FPGA through the off-chip read-write port. Alternatively, the data written by the read-write controller to the write port of the resource module is transmitted from the outside of the FPGA through the off-chip read-write port and temporarily stored in the write cache unit; the off-chip read-write port of the FPGA is a high-speed serial port and / or a DDR IO port.

7. The FPGA according to claim 5, wherein The edge module is connected to multiple off-chip read-write ports at the same time. The read-write controller transmits the data temporarily stored in multiple read cache units to the outside of the FPGA through multiple off-chip read-write ports at the same time, or the read-write controller writes the data input from the outside of the FPGA to multiple write cache units through multiple off-chip read-write ports at the same time.

8. The FPGA according to claim 5, wherein The cache unit built in the edge module is a FIFO, and the read-write speed of the off-chip read-write port for the cache unit matches the read-write speed of the read-write controller for the resource module.

9. The FPGA according to claim 1, wherein The edge module further includes a read-write signal generation circuit. The read-write signal generation circuit is connected to the read-write control ports of the resource modules. The read-write controller generates read-write control signals through the read-write signal generation circuit and sends them to the read-write control ports of the resource modules, and reads data from the read ports of multiple resource modules or writes data to the write ports of multiple resource modules at the same time according to the read-write control signals.

10. The FPGA according to claim 9, wherein The edge module includes one read-write signal generation circuit, and the read-write signal generation circuit is connected to the read-write control ports of all resource modules; or the edge module includes multiple read-write signal generation circuits, each read-write signal generation circuit is connected to the read-write control ports of one or more resource modules, and each read-write signal generation circuit sends read-write control signals to the read-write control ports of the connected resource modules.

11. The FPGA according to claim 9, wherein The resource modules connected to the edge module are BRAM modules. The read-write control ports of each BRAM module include a read address port, a read enable port, a write address port, and a write enable port; The read-write signal generation circuit built in the edge module includes a read address generator, a read enable generator, a write address generator, and a write enable generator. The read address generator is connected to the read address port of the BRAM module, the read enable generator is connected to the read enable port of the BRAM module, the write address generator is connected to the write address port of the BRAM module, and the write enable generator is connected to the write enable port of the BRAM module; The read-write control signals generated by the read-write signal generation circuit include the read address generated by the read address generator, the read enable generated by the read enable generator, the write address generated by the write address generator, and the write enable generated by the write enable generator.

12. The FPGA according to claim 11, wherein At the same time, multiple BRAM modules connected to the edge module form a full-chip storage array. The read-write controller in the edge module provides corresponding read enable and write enable to each BRAM module through the read-write signal generation circuit according to the obtained full-chip enable signal. The read-write controller in the edge module provides corresponding read address and write address to each BRAM module through the read-write signal generation circuit according to the obtained full-chip enable signal and full-chip address signal.

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