A Design Method of a Current Converter Controller

Abstract

The present invention relates to the technical field of converter controllers, and specifically provides a design method for a converter controller. In order to solve the problem of poor versatility and flexibility of existing converter controllers, a design method for a converter controller is provided. The controller includes a DSP and an FPGA. The DSP reads the information inside the FPGA through a bus and sends information to the FPGA. After receiving the chip select signal, the FPGA determines the read / write signal according to the high or low level of XR / Wn and performs corresponding read / write operations. The pulses generated by the DSP are directly transmitted to the FPGA pins through GPIO. In the present invention, the control parameters inside the FPGA can be configured externally by the DSP. Without changing the FPGA design, different personalized requirements can be met through parameter configuration. On the one hand, it improves the flexibility and versatility of the design, and on the other hand, the stability of the internal design ensures the safety of the design application.

Description

Technical Field

[0001] The present invention relates to the technical field of current conversion controllers, and particularly to a design method for a current conversion controller. Background Art

[0002] In rail transit vehicles, the auxiliary system power supply has the characteristic of variable topological structures compared with the traction drive converters. Therefore, it is difficult to achieve compatibility and universality in the design of controllers. Considering the requirements of development cycle, development cost, safety and reliability, it is particularly important to design a controller that meets various current conversion topologies and is suitable for common power electronic conversions. The traditional controller directly generates waves after sampling and calculation by a DSP and performs analog quantity protection. However, the sampling accuracy and calculation speed of the DSP are relatively low, which cannot meet the control requirements of high frequency and high precision. In addition, the wave generation control of the DSP itself often cannot meet the requirements of complex and diverse PWM pulse production with high flexibility in the auxiliary power supply system. Therefore, there is also a current conversion controller of DSP+FPGA at the present stage. The interface parameters between the DSP and the FPGA are not well designed. No matter how big or small the change is, the FPGA design often needs to be modified, resulting in poor universality and flexibility of the current conversion controller. Summary of the Invention

[0003] In order to solve the problem of poor universality and flexibility of the existing current conversion controllers, the present invention provides a design method for a current conversion controller.

[0004] The present invention is implemented by the following technical solutions: A design method for a current conversion controller, the controller includes a DSP and an FPGA. The DSP reads the information inside the FPGA through a bus and sends information to the FPGA. After receiving the chip select signal of the DSP, the FPGA takes the inverse to obtain the internal chip select signal CS, and determines the internal read / write signals RD / WR according to the high or low level of XR / Wn. When XR / Wn is at a high level, a read operation is performed, and when XR / Wn is at a low level, a write operation is performed. The pulses generated by the DSP are directly transmitted to the FPGA pins through GPIO;

[0005] The inside of the FPGA includes a digital quantity module, an analog quantity module, and a pulse module;

[0006] The digital quantity module processes digital quantity input and output signals. The digital quantity module includes a digital quantity input unit and a digital quantity output unit. The digital quantity input unit reads the digital quantity input signals on the FPGA pins and transmits the digital quantity input signals to the DSP through bus communication. The digital quantity output unit reads the digital quantity output signals sent by the DSP and converts the digital quantity output signals into the levels on the FPGA output pins for output. The read / write of the digital quantity input signals and the digital quantity output signals are both completed at the rising edge of the clock signal.

[0007] The analog module reads analog signals from the analog chips of the ADC board and performs high-speed calculation protection. This module includes an ADC sampling module and an ADC protection module. The ADC sampling module converts the analog signals into digital signals for reading through SPI communication. The sampling of the analog quantity is controlled by the interrupt signal generated by the pulse module inside the FPGA and the chip select signal of the DSP. When the ADC sampling module receives the interrupt signal and the chip select signal of the DSP, it sends the corresponding reading result to the DSP; The ADC protection module performs high-speed operations for analog protection to determine whether the corresponding analog quantity exceeds the designed protection threshold. The specific design method is as follows: Each analog quantity is provided with upper limit protection and lower limit protection, and the protection enable and protection threshold of each analog quantity are independently configured by the DSP;

[0008] The pulse module is used to generate pulses and perform protection operations on the drive feedback signal to achieve drive protection. The pulse module includes a comparison module, a dead zone module, and a drive fault blocking module; The comparison module generates the required pulses through the module enable signal, counter period, and comparison value configured by the DSP; The dead zone module adds the required dead zone based on the pulses generated by the comparison module according to the size of the dead zone configured by the DSP; The drive fault blocking module judges the drive fault according to the protection logic between the drive signal and the pulse signal, and blocks the pulse output when a drive fault is detected.

[0009] The beneficial effects of the present invention are as follows: 1) The control parameters inside the FPGA of the present invention can be externally configured by the DSP. Without changing the FPGA design, different personalized requirements can be met through parameter configuration. On the one hand, it improves the flexibility and universality of the design, and on the other hand, the stability of the internal design ensures the security of the design application; 2) Through the external configuration of the analog protection and the drive feedback duration, the effectiveness of the protection can be flexibly designed and the influence of false protection on the system stability can be avoided; 3) Based on the modular design and the enable configuration through the DSP, the adaptability of the FPGA pulse module to different circuit topologies is improved; 4) The independent enable configuration for analog protection, the selection of protection modules, the duration counting, and the DSP configuration of the protection threshold improve the flexibility and universality of the protection design. Description of the Drawings

[0010] Figure 1 It is a schematic diagram of the overall design of the present invention;

[0011] Figure 2 It is a bus communication design method (in the figure, XTIMCLK = XCLKOUT, lead = 1 represents the setup time, and Active = 1 represents the active time);

[0012] Figure 3For digital quantity module registers;

[0013] Figure 4 Schematic diagram of the design for analog quantity module;

[0014] Figure 5 Schematic diagram of the design for DC / AC ADC sampling module;

[0015] Figure 6 Schematic diagram of the design for DC / DC ADC sampling module;

[0016] Figure 7 Schematic diagram of the design for communication module;

[0017] Figure 8 Schematic diagram of the state control for communication module;

[0018] Figure 9 Schematic diagram of the design for ADC module;

[0019] Figure 10 Schematic diagram of the design for pulse module;

[0020] Figure 11 Schematic diagram of the design for comparison module;

[0021] Figure 12 Schematic diagram of the design for dead zone module;

[0022] Figure 13 Schematic diagram of the design for drive fault blocking module;

[0023] Figure 14 Schematic diagram of the design for PWM direct connection structure. Specific implementation manners

[0024] The following embodiments are for the design method of the converter controller on the locomotive auxiliary power control device, but the same design method can also be applied to power electronic conversion power supplies and motor control devices in other industries.

[0025] Such as Figure 1 And Figure 2As shown in the figure, a design method of a current conversion controller. The controller includes a DSP and an FPGA. The DSP reads the information inside the FPGA through a bus and sends information to the FPGA (essentially configuring the FPGA as a peripheral of the DSP, so that the DSP can directly read and write the internal RAM of the FPGA to achieve data exchange). Specifically, in implementation, to be compatible with the wave generation situation of the DSP, the DSP and the FPGA are connected not only through the bus but also through the connection between pins, so that the pulses generated by the DSP can be directly transmitted to the FPGA pins through the GPIO. The DSP used in this embodiment is the TMS320F28335 processor of Texas Instruments, and the FPGA selects the XC6SLX45-2FGG484C of the SPARTEN6 series.

[0026] The specific design of the bus communication between the FPGA and the DSP is as follows: CS in the FPGA is obtained by inverting XCSn, RD / WR is obtained according to the value of XR / Wn at the rising edge of CLK. After the FPGA receives XCSn, it determines the read / write signal according to the high or low of XR / Wn and performs corresponding read / write operations; CLK in the FPGA is obtained by inverting XCLHOUT / XTIMCLK, and the clock is designed to be 37.5MHz.

[0027] The inside of the FPGA includes a digital quantity module, an analog quantity module, and a pulse module;

[0028] As Figure 3 shown, the digital quantity module processes digital quantity input and output signals. The digital quantity module is a register for digital quantity output and output signals. The digital quantity module includes a digital quantity input unit and a digital quantity output unit. The digital quantity input unit reads the digital quantity input signal on the FPGA pin and transmits the digital quantity input signal to the DSP through bus communication. The digital quantity output unit is divided into IO output and fault output (the fault output is used for the control of the status indicator light). The IO output has 24 output signals, which are divided into 2 registers, and each register has 12 signals. The fault output has 16 signals, occupying one register. The digital quantity output unit reads the digital quantity output signal sent by the DSP and converts the digital quantity output signal into a level output on the FPGA output pin. The digital quantity input unit is divided into IO input (IO input is generally a status feedback signal such as the contactor status) and PWM drive feedback input (the PWM drive feedback input is used to receive and process the PWM drive feedback signal). The IO input has 48 signals, which are divided into 3 registers. The PWM drive feedback input has 20 signals, which are divided into 2 registers, and each register has 10 signals. The read / write of the digital quantity input signal and the digital quantity output signal are both completed at the rising edge of the clock signal. When receiving the reset signal, all registers are reset;

[0029] As Figure 4As shown, the analog module reads the analog signal from the analog chip of the ADC board and performs high-speed calculation protection. This module includes an ADC sampling module and an ADC protection module. The ADC sampling chip converts the analog signal into a digital signal. The ADC sampling module stores the read digital signal into the result Buf for the DSP to read through SPI communication. On the other hand, the ADC protection module reads the data RESULT in the result Buf for high-speed protection calculation. After the SPI communication completes one sampling, it outputs the Adc_Done signal to the ADC protection module. The ADC protection module performs protection calculation on the sampling result according to the control configuration of the DSP, calculates and generates each analog fault flag signal FLG and sends it to the DSP, and at the same time generates different pulse module protection signals and sends them to the pulse module. The pulse module blocks the corresponding pulse output when it detects that the module protection signal reaches 1 to achieve protection. When the ADC protection module detects a fault, it latches the fault value VALUE of the analog quantity, and the DSP can read this fault value as needed for fault data analysis. The sampling of the analog quantity is controlled by the interrupt signal generated by the pulse module inside the FPGA and the chip select signal of the DSP. When the ADC sampling module receives the interrupt signal and the chip select signal of the DSP, it sends its corresponding read result to the DSP. The ADC protection module performs high-speed operation for analog quantity protection to determine whether the corresponding analog quantity exceeds the designed protection threshold. The specific design method is as follows: Each analog quantity is provided with upper limit value protection and lower limit value protection, and the protection enable and protection threshold of each analog quantity are independently configured by the DSP (in order to avoid false protection caused by possible signal interference, the judgment logic of the duration of analog quantity protection is designed in the FPGA, and the duration can be configured by the DSP processor according to the actual situation).

[0030] ADC sampling module: For three-phase inverter, BUCK chopper or BOOST conversion circuit, its sampling is generally carried out at the control moment, such as Figure 5As shown in the figure, PWM_DCAC_SOC in the ADC sampling module of the DC / AC conversion circuit is a signal from the pulse module, and its function is to drive the sampling module to start sampling. At the same time, the registers controlled by the DSP in the ADC sampling module are DSP_CS, DSP_BUSY, and the result Buf. The specific design method of the ADC sampling module is as follows: 1) After CLK is divided by 4, it is used as ADCCLK; 2) There are two start signals for the DC / AC ADC: the chip select signal DSP_CS and the PWM sampling trigger signal PWM_DCAC_SOC; 3) DSP_CS is a continuous signal and needs to be reset. The reset signal is the BUSY signal sent after the communication module enters the conversion state. PWM_DCAC_SOC is a pulse signal and does not need to be reset; 4) Any one of the start signals will set the START register, thus starting the communication module. After the communication module starts, it enters the conversion state and sends the BUSY signal to reset the START register; 5) After the communication module completes the conversion, it will send the SET signal. At this time, the ADC data will be stored in the result Buf; 6) The transition of SET is used as an interrupt signal and sent to the DSP; 7) The DSP can know the BUSY signal sent during the conversion of the communication module through the DSP_BUSY register.

[0031] In specific implementation, for the DC-DC conversion circuit, due to the reason of bias magnetic suppression, it is often necessary to perform two samplings of positive and negative cycles at special moments, such as Figure 6As shown, its embodiments are mainly used in the case where a single-phase half-bridge or full-bridge circuit needs to sample once at a certain determined moment in the positive and negative half-cycles. DSP_CS, DSP_BUSY, DELAY_PRD, and the result Buf2 are controlled by the DSP. The specific design method of the ADC sampling module of the DC / DC conversion circuit is as follows: 1) CLK is divided by 4 and used as ADCCLK; 2) There are three start signals for the DC / DC ADC: DSP_CS, PWM_SOC_P, and PWM_SOC_N; 3) DSP_CS is a continuous signal and needs to be reset. The reset signal is the BUSY signal sent after the communication module enters the conversion state (BUSY is set after START), and PWM_SOC_P and PWM_SOC_N are pulse signals and do not need to be reset; 4) Due to the existence of line delay and switch-on delay of the switch tube, the trigger signals PWM_SOC_P and PWM_SOC_N need to be delayed for a certain period of time. The delay time is set through DELAY_PRD, and the specific setting time needs to be adjusted through actual debugging; 5) Any start signal will set the START register, thereby starting the communication module. After the communication module starts, it enters the conversion state and sends the BUSY signal to reset the START register; 6) The PWM_SOC_P and PWM_SOC_N signals determine the positive and negative of the P / N selection register at this time. The P / N register will determine whether the data obtained by the communication module is stored in the positive result or the negative result; 7) After the communication module completes the conversion, it will send the SET signal. At this time, the ADC data will be stored in the result Buf1, and the positive and negative poles are determined by the P / N register; 8) When the DC / DC INT (DC / DC interrupt signal) is sent, the data in the result Buf1 will be stored in the result Buf2, and the DSP will read the data in Buf2. Setting two layers of caches is to prevent data from being overwritten and lost; 9) The DSP can obtain the BUSY signal sent during the conversion of the communication module through the DSP_BUSY register.

[0032] The communication module in the above ADC sampling module includes a busy register, a status controller, a shift register, a chip select register, and a counter. The inputs of its communication module include START and DATA, and the outputs of its communication module include CS, BUSY, SET, and DATABUF. The specific design method of the status controller is as follows, as Figure 8As shown in the figure: 1) When the system is in the IDLE state, the counter is reset to zero and the shift register does not operate; 2) When the START signal is received, the state jumps to CONV. During the jump, the BUSY signal is set and the CS signal is pulled low to select the ADC chip; 3) When the system is in the CONV state, the CONV counter counts. Each count triggers the shift register to shift and reads the data from DATA; 4) When the CONV counter finishes counting, the state jumps to DONE. During the jump, the CS signal is set and the ADC chip is no longer selected; 5) When the system is in the DONE state, the DONE counter counts. This state is to complete the operation timing of the ADC chip; 6) When the DONE counter finishes counting, the state jumps to IDLE. During the jump, the BUSY signal is pulled low, and the pull-down process generates a conversion complete SET signal; the system returns to the IDLE state and the entire state change process is completed.

[0033] The specific design method of the ADC protection module is as follows: The registers controlled by the DSP in the ADC protection sub-module are DSP_CS, EN (including EnU and EnD), CLR, SEL, LIMIT (including LimitUReg and LimitDReg), QUAL (including QualU and QualD), VALUE, and FLG (read-only by DSP). The signals of the ADC protection module from the ADC sampling sub-module include the result register Result and the sampling conversion complete signal SET, as Figure 9As shown, the specific design method of its ADC protection module is as follows: 1) After receiving the sampling result of the ADC sampling sub-module, the protection logic judgment module of the ADC protection sub-module will perform logical processing in combination with the configuration information in the DSP. When the protection condition is met, the counting enable register QualEnReg will be set high, otherwise it will be pulled low; 2) The protection conditions for analog quantities are: upper limit protection: Result > LimitUReg and EnU = 1 and CLR = 0; limit protection: Result < LimitDReg and EnD = 1 and CLR = 0, where LimitUReg and LimitDReg are the upper and lower protection thresholds of this analog quantity respectively, EnU and EnD are the enable control registers for the corresponding protection, and CLR is the fault clearing instruction register; 3) When the corresponding counting enable register QualEnReg = 1, the counter in the continuous counting logic continuously counts, and the counter increments by 1 at the rising edge of the SET signal after each sampling is completed; when QualEnReg = 0, the continuous counter is cleared; 4) When the value of the continuous counter is equal to the count value QUAL configured by the DSP, the output register QualOut of the continuous counting module is set high, otherwise when the count value does not reach QUAL, the continuous counting module outputs QualOut as 0; 5) When the output register QualOut of the continuous counting module for a certain protection is 1 and the fault clearing instruction CLR is 0, the fault flag ErrFLG of this protection is set to 1, otherwise ErrFLG is set to 0; 6) The fault flag will be sent to the interface register FLG with the DSP for the DSP to read to determine the faults detected inside the FPGA; 7) The module protection logic generates the protection flag PRT_M of each pulse module according to the fault flag register and the selection signal SEL configured by the corresponding DSP. Each fault is individually configured with a pulse module protection selection register SEL by the DSP. After detecting that ErrFlg is 1, the selection register SEL of this fault is configured to the protection flag PRT_M of the corresponding pulse module; 8) After the above faults occur, when the fault value latch logic module detects that ErrFlg is 1, it latches the real-time value of the analog quantity corresponding to the fault into the fault value register, and the DSP can read this fault value through bus communication for fault analysis.

[0034] Pulse module design: According to the main circuit topology, the pulses generated by the pulse module should include 4-pulse output and 6-pulse output (the topologies of 1 pulse of the BUCK circuit and 2 pulses of the half-bridge circuit can use 4 pulses or 6 pulses). The pulse outputs in each module can be independently enabled and the relevant parameters can be independently configured. The compositions of different pulse generation modules are basically the same. The design of the pulse module will be described below taking the 4-pulse as an example, as Figure 10 shown, the pulse module includes a comparison module, a dead zone module, and a drive fault blocking module.

[0035] Registers controlled by the DSP in the comparison module: PWM module enable register (EN). After this register is enabled, the counter can start to operate, and the counting uses sawtooth wave up - counting; counting period register (PRD), comparison value registers (CMPAU, CMPAD, CMPBU, CMPBD). The specific design method is as follows: 1) After the PWM module is enabled, CTR starts to count; 2) There are shadow registers for PRD and CMP. When CTR = 0, the values in the shadow registers are updated to the current registers; 3) When CTR = CMPAU, CMPAD, CMPBU, CMPBD respectively, four pulse signals are generated, named CMP1, CMP2, CMP3, CMP4 here; 4) The middle signal M_A of the A - arm is set high after CMP1 appears and set low after CMP2 appears; the middle signal M_B of the B - arm is set high after CMP3 appears and set low after CMP4 appears; 5) CMP3 is the trigger signal SOC_P given to the ADC, and CMP4 is the trigger signal SOC_N given to the ADC; 6) The DC / DC interrupt signal is given when CTR = 0; 7) When the module protection signal PRT_M input by the ADC module is 0 and the enable signal is 1, the comparison module outputs CMP1, CMP2, CMP3, CMP4 signals. When PRT_M = 1, the pulse output signals are blocked. It should be noted that the counter in the comparison module of the above - mentioned embodiment uses up - counting. Actually, up - down counting can also be used in the comparison module to generate pulses, which will not be elaborated here.

[0036] The register controlled by the DSP in the dead - time module is the dead - time period register DT_PRD. The specific design method is as follows (the working principles of phase A and phase B are the same, so only phase A is taken as an example here): 1) In phase A, after the dead - time module gets any one of the CMP1 and CMP2 signals, DT_CTR starts; 2) During the operation of DT_CTR, the dead - time counter enable signal DT_EN is set; 3) The logical AND of non - DT_EN and the middle signal M_A of the A - arm gives the upper - tube pulse signal S_AU of phase A, and the logical AND of non - DT_EN and non - M_A gives the lower - tube pulse signal S_AD of phase A.

[0037] As Figure 13Among them, in the drive fault blocking module, the DSP controls the drive feedback fault cycle register QUAL_PRD. The specific design method of the drive fault blocking module is as follows: 1) The fault signal is the SO signal from the drive board, which is inverted to generate the TZ signal; 2) The counter performs duration counting when TZ = 1. When the duration of the TZ signal is less than the time corresponding to QUAL_PRD, the pulse signal does not act; when the duration of the TZ signal is greater than the time corresponding to QUAL_PRD, the pulse signal is blocked and remains low; 3) For the case where the SO signal is at the normal level and is continuously high during a fault, if the pulse feedback follows the logic of the PWM pulse, a logical judgment of the PWM and the feedback signal is added in the module to generate the TZ signal.

[0038] During specific implementation, such as Figure 14 , the pulse signal can also be generated in the DSP chip and then output after ADC protection and drive protection by the FPGA. This PWM adopts a direct connection structure, adding an enable register EN and a module protection register PRT_M. When the DSP enable signal EN = 1 and the analog quantity protection register PRT_M = 0, the PWMIN signal is output to the drive fault blocking module; otherwise, the output of the blocking register is 0.

[0039] To make this specification clearer, the English annotations in the specification are now translated into Chinese as follows:

[0040] DSP: Digital Signal Processor

[0041] FPGA: Field Programmable Gate Array

[0042] XR / Wn: Read / Write Signal Line

[0043] GPIO: General Purpose Input / Output Port

[0044] XCLKOUT: DSP Output Clock Signal

[0045] XTIMCLK: DSP Internal Clock Signal

[0046] XCSn: DSP Chip Select Signal

[0047] CLK: FPGA System Clock Signal

[0048] CS: FPGA Chip Select Signal

[0049] Note: (These two signals of the FPGA are obtained by inverting the XCLKOUT and XCSn of the DSP)

[0050] RD / WR: FPGA Read / Write Signal

[0051] Note: (During the rising delay of the FPGA clock, the FPGA performs read / write operations according to the XR / WN signal in the DSP.)

[0052] OUTREG: IO output register;

[0053] ERRREG: Fault register;

[0054] STREG: PWM drive input feedback register;

[0055] SPI: Serial Peripheral Interface;

[0056] Adc_Done: Adc module completes sampling;

[0057] FLG: Fault flag register;

[0058] VALUE: Fault register;

[0059] RESULT: Result register;

[0060] BUCK: Buck converter;

[0061] BOOST: Boost converter;

[0062] DC / AC: DC-AC converter;

[0063] ADC: Digital to Analog Converter;

[0064] DSP_CS: DSP chip select register;

[0065] DSP_BUSY: DSP busy register;

[0066] Result Buf: Result register (read-only for DSP);

[0067] PWM_DCAC_SOC: Sampling trigger signal;

[0068] ADCCLK: ADC chip clock;

[0069] SET: Sampling conversion complete signal;

[0070] DC-DC: DC-DC converter;

[0071] DELAY_PRD: Trigger delay period register;

[0072] PWM_SOC_P: PWM positive sampling trigger signal;

[0073] PWM_SOC_N: PWM negative sampling trigger signal;

[0074] DC / DC INT: DC / DC interrupt signal;

[0075] En: Enable protection register;

[0076] EnU: Upper enable protection register;

[0077] EnD: Lower enable protection register;

[0078] CLR: Fault clear register;

[0079] SEL: Protection selection register;

[0080] LIMIT: Protection threshold register;

[0081] LimitUReg: Upper limit protection register;

[0082] LimitDReg: Lower limit protection register;

[0083] QUAL: Continuous count register;

[0084] QualU: Upper continuous count register;

[0085] QualD: Lower continuous count register;

[0086] QualEnReg: Count enable register;

[0087] QualOut: Module output register;

[0088] PRT_M: Analog protection register;

[0089] PRD: Count period register;

[0090] CMP, CMPAU, CMPAD, CMPBU, CMPBD: Comparison value register;

[0091] CTR: Counter;

[0092] M_A: Intermediate signal of arm A;

[0093] M_B: Intermediate signal of arm B;

[0094] DT_PRD: Dead-time period register;

[0095] DT_CTR: Dead-time counter;

[0096] DT_EN: Dead-time counter enable signal;

[0097] S_AU: Pulse signal of upper switch of phase A;

[0098] S_AD: Pulse signal of lower switch of phase A;

[0099] QUAL_PRD: Drive Feedback Fault Cycle Register;

[0100] SO signal: Status Output Signal;

[0101] TZ signal: Fault Signal.

Claims

1. A design method for a current converter controller, characterized in that The controller includes a DSP and an FPGA. The DSP reads the information inside the FPGA through a bus and sends information to the FPGA. After receiving the chip select signal from the DSP, the FPGA takes it inverted to obtain the internal chip select signal CS, and determines the internal read / write signals RD / WR according to the high or low level of XR / Wn. When XR / Wn is at a high level, a read operation is performed, and when XR / Wn is at a low level, a write operation is performed. The pulse generated by the DSP is directly transmitted to the FPGA pin through GPIO; Inside the FPGA, there are a digital quantity module, an analog quantity module, and a pulse module; The digital quantity module processes digital quantity input and output signals. The digital quantity module includes a digital quantity input unit and a digital quantity output unit. The digital quantity input unit reads the digital quantity input signal on the FPGA pin and transmits the digital quantity input signal to the DSP through bus communication. The digital quantity output unit reads the digital quantity output signal sent by the DSP and converts the digital quantity output signal into the level output on the FPGA output pin. The read / write of the digital quantity input signal and the digital quantity output signal are both completed at the rising edge of the clock signal. When receiving a reset signal, all registers perform a reset; The analog quantity module reads the analog quantity signal from the analog quantity chip of the ADC board and performs high-speed calculation protection. This module includes an ADC sampling module and an ADC protection module. The ADC sampling chip converts the analog quantity signal into a digital quantity signal. The ADC sampling module stores the read digital quantity signal into the result Buf for the DSP to read through SPI communication on the one hand. On the other hand, the ADC protection module reads the data RESULT in the result Buf for high-speed protection calculation. After the SPI communication completes one sampling, it outputs the Adc_Done signal to the ADC protection module; The ADC protection module performs protection calculation on the sampling result according to the control configuration of the DSP, calculates and generates each analog quantity fault flag signal FLG and sends it to the DSP, and at the same time generates different pulse module protection signals and sends them to the pulse module. The pulse module blocks the corresponding pulse output when detecting that the module protection signal reaches 1 to achieve protection. When the ADC protection module detects a fault occurrence, it latches the fault value VALUE of the analog quantity. The DSP can read this fault value according to needs for fault data analysis; The sampling of the analog quantity is controlled by the interrupt signal generated by the pulse module inside the FPGA and the chip select signal of the DSP. When the ADC sampling module receives the interrupt signal and the chip select signal of the DSP, it sends its corresponding read result to the DSP; The ADC protection module performs high-speed operation for analog quantity protection to determine whether the corresponding analog quantity exceeds the designed protection threshold. The specific design method is as follows: Each analog quantity is provided with upper limit value protection and lower limit value protection. The protection enable and protection threshold of each analog quantity are independently configured by the DSP; The pulse module is used to generate pulses and perform protection operation on the drive feedback signal to achieve drive protection. The pulse module includes a comparison module, a dead zone module, and a drive fault blocking module; The comparison module generates the required pulses through the module enable signal, counter period, and comparison value configured by the DSP; the dead-time module adds the required dead time based on the pulses generated by the comparison module according to the size of the dead time configured by the DSP. The drive fault blocking module judges drive faults according to the protection logic between the drive signal and the pulse signal, and blocks the pulse output when a drive fault is detected.

2. The design method of a current conversion controller according to claim 1, wherein Design the judgment logic for the duration of analog protection in the FPGA, and the duration is configured by the DSP processor according to the actual situation.

3. The design method of a current conversion controller according to claim 2, characterized in that, Considering signal interference, the DSP processor cooperates with the fault duration register to prevent mis-output of blocking pulses and avoid mis-protection.

4. The design method of a current conversion controller according to claim 3, characterized in that The sampling trigger signal in the ADC sampling module of the DC / AC conversion circuit is from the pulse module, and its function is to drive the sampling module to start sampling. At the same time, the registers controlled by the DSP in the ADC sampling module are DSP_CS, DSP_BUSY, and the result Buf. The specific design method of the ADC sampling module is as follows: 1) CLK is divided by 4 and used as ADCCLK; 2) There are two start signals for the DC / AC ADC: the chip select signal DSP_CS and the PWM sampling trigger signal PWM_DCAC_SOC; 3) DSP_CS is a continuous signal and needs to be reset. The reset signal is the BUSY signal sent after the communication module enters the conversion state. PWM_DCAC_SOC is a pulse signal and does not need to be reset; 4) Any one of the start signals will set the START register, thereby starting the communication module. After the communication module starts, it enters the conversion state and sends the BUSY signal to reset the START register; 5) After the communication module completes the conversion, it will send the SET signal. At this time, the ADC data will be stored in the result Buf; 6) The transition of SET is used as an interrupt signal and sent to the DSP; 7) The DSP can obtain the BUSY signal sent during the conversion of the communication module through the DSP_BUSY register.

5. A design method of a converter controller according to claim 4, characterized in that DSP_CS, DSP_BUSY, DELAY_PRD, and Result Buf2 are controlled by the DSP. The specific design method of the ADC sampling module of the DC / DC conversion circuit is as follows: 1) CLK is divided by 4 and used as ADCCLK; 2) There are three start signals for the DC / DC ADC: DSP_CS, PWM_SOC_P, and PWM_SOC_N; 3) DSP_CS is a continuous signal and needs to be reset. The reset signal is the BUSY signal sent after the communication module enters the conversion state. PWM_SOC_P and PWM_SOC_N are pulse signals and do not need to be reset; 4) Due to the existence of line delay and switch-on delay of the switch tube, the trigger signals PWM_SOC_P and PWM_SOC_N need to be delayed for a certain period of time. The delay time is set through DELAY_PRD, and the specific setting time needs to be adjusted through actual debugging; 5) Any start signal will set the START register, thereby starting the communication module. After the communication module starts, it enters the conversion state and sends the BUSY signal to reset the START register; 6) The PWM_SOC_P and PWM_SOC_N signals determine the positive and negative of the P / N selection register at this time. The P / N register will determine whether the data obtained by the communication module is stored in the positive result or the negative result; 7) After the communication module completes the conversion, it will send the SET signal. At this time, the ADC data will be stored in Result Buf1, and the positive and negative poles are determined by the P / N register; 8) When the DC / DC conversion circuit sends the INT interrupt signal, the data in Result Buf1 will be stored in Result Buf2, and the DSP will read the data in Buf2; 9) The DSP can obtain the BUSY signal sent during the conversion of the communication module through the DSP_BUSY register.

6. The design method of a variable current controller according to claim 5, characterized in that, The communication module in the ADC sampling module includes a busy register, a status controller, a shift register, a chip select register, and a counter. The specific design method is as follows: 1) When the system is in the IDLE state, the counter is reset to zero and the shift register does not operate; 2) When the START signal is received, the status jumps to CONV. During the jump, the BUSY signal is set and the CS signal is pulled low to select the ADC chip; 3) When the system is in the CONV state, the CONV counter counts. Each count will trigger the shift register to shift and read the data from DATA; 4) When the CONV counter finishes counting, the status jumps to DONE. During the jump, the CS signal is set and the ADC chip is no longer selected; 5) When the system is in the DONE state, the DONE counter counts. This state is for completing the operation timing of the ADC chip; 6) When the DONE counter finishes counting, the status jumps to IDLE. During the jump, the BUSY signal is pulled low, and the pull-down process will send the conversion complete SET signal; The system returns to the IDLE state, and the entire state change process is completed.

7. The design method of a variable current controller according to claim 6, characterized in that, The registers controlled by the DSP in the ADC protection sub-module are DSP_CS, protection enable register EN, CLR, SEL, LIMIT, QUAL, VALUE, and FLG. The signals from the ADC sampling sub-module to the ADC protection module include the result register Result and the sampling conversion completion signal SET. The specific design method of the ADC protection module is as follows: The registers controlled by the DSP in the ADC protection sub-module are the DSP chip select register DSP_CS, protection enable register EN, fault clear register CLR, protection selection register SEL, protection threshold register LIMIT, protection continuous count register QUAL, fault value register VALUE, and fault flag register FLG. The signals from the ADC sampling module to the ADC protection module include the result register Result and the sampling conversion completion signal SET. The specific design method of its ADC protection module is as follows: 1) After receiving the sampling result of the ADC sampling sub-module, the protection logic judgment module in the ADC protection sub-module will perform logical processing in combination with the configuration information in the DSP. When the protection condition is met, the count enable register QualEnReg is set high, otherwise it is pulled low; 2) The protection conditions for analog quantities are: upper limit protection: Result > LimitUReg and EnU = 1 and CLR = 0; lower limit protection: Result < LimitDReg and EnD = 1 and CLR = 0, where LimitUReg and LimitDReg are the upper and lower protection thresholds of the analog quantity respectively, EnU and EnD are the enable control registers for the corresponding protection, and CLR is the fault clear instruction register; 3) When the corresponding count enable register QualEnReg = 1, the counter in the continuous count logic continuously counts, and the counter increments by 1 at the rising edge of the SET signal for each sampling completion; when QualEnReg = 0, the continuous counter is cleared; 4) When the value of the continuous counter is equal to the count value QUAL configured by the DSP, the output register QualOut of the continuous count module is set high, otherwise when the count value does not reach QUAL, the continuous count module outputs QualOut as 0; 5) When the output register QualOut of the continuous count module for a certain protection is 1 and the fault clear instruction CLR is 0, the fault flag ErrFLG of this protection is set to 1, otherwise ErrFLG is set to 0; 6) The fault flag will be sent to the interface register FLG with the DSP for the DSP to read to judge the faults detected inside the FPGA; 7) The module protection logic generates the protection flag PRT_M of each pulse module according to the fault flag register and the corresponding selection signal SEL configured by the DSP. Each fault is individually configured with the pulse module protection selection register SEL by the DSP. After detecting that ErrFlg is 1, the selection register SEL of this fault is configured to the protection flag PRT_M of the corresponding pulse module;8) After the above-mentioned fault occurs, when the fault value latching logic module detects that ErrFlg is 1, it latches the real-time value of the analog quantity corresponding to the fault into the fault value register, and the DSP can read the fault value through bus communication for fault analysis.; 8. A design method of a current converter controller according to claim 7, characterized in that The specific design method of the comparison module is as follows: 1) After the PWM module is enabled, the counter CTR starts counting; 2) There are shadow registers for the period register PRD and the comparison value register CMP. When CTR = 0, the values in the shadow registers are updated to the current registers; 3) When CTR = CMPAU, CMPAD, CMPBU, and CMPBD respectively, four pulse signals are generated, namely CMP1, CMP2, CMP3, and CMP4; 4) The intermediate signal M_A of the A-bridge arm is set high when CMP1 appears and set low when CMP2 appears; the intermediate signal M_B of the B-bridge arm is set high when CMP3 appears and set low when CMP4 appears; 5) CMP3 is the trigger signal SOC_P given to the ADC, and CMP4 is the trigger signal SOC_N given to the ADC; 6) The DC / DC interrupt signal is given when CTR = 0; 7) When the module protection signal PRT_M input by the ADC module is 0 and the enable signal is 1, the comparison module outputs the CMP1, CMP2, CMP3, and CMP4 signals. When PRT_M = 1, the pulse output signal is blocked.

9. The design method of a variable current controller according to claim 8, characterized in that, The register controlled by the DSP in the dead-time module is the dead-time period register DT_PRD. The specific design method for its phase A is as follows: 1) In phase A, after the dead-time module obtains either the CMP1 or CMP2 signal, the DT_CTR starts; 2) The dead-time counter enable signal DT_EN is set during the operation of DT_CTR; 3) The non-DT_EN is ANDed with the intermediate signal M_A of the A-bridge arm to obtain the upper-switch pulse signal S_AU of phase A, and the non-DT_EN is ANDed with the non-M_A to obtain the lower-switch pulse signal S_AD of phase A.

10. A design method of a current conversion controller according to claim 9, characterized in that, In the drive fault blocking module, the drive feedback fault period register QUAL_PRD is controlled by the DSP. The specific design method of the drive fault blocking module is as follows: 1) The fault signal is the SO signal from the drive board, which generates the TZ signal after being inverted; 2) The counter performs a duration count when TZ = 1. When the duration of the TZ signal is less than the time corresponding to QUAL_PRD, the pulse signal does not act; when the duration of the TZ signal is greater than the time corresponding to QUAL_PRD, the pulse signal is blocked and remains low; 3) For the case where the SO signal is at the normal level and is continuously high during a fault, if the pulse feedback follows the logic of the PWM pulse, then the logic judgment of the PWM and the feedback signal is added in the module to generate the TZ signal.

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