Display substrate and driving method thereof, and display device

Abstract

A display substrate and a driving method thereof, and a display device, wherein the display substrate comprises: a first gate driving circuit, a second gate driving circuit and a plurality of pixel driving circuits arranged in an array, wherein the first gate driving circuit comprises a plurality of first shift registers cascaded to each other, and the second gate driving circuit comprises a plurality of second shift registers cascaded to each other, and the plurality of pixel driving circuits comprise: a first pixel driving circuit and a second pixel driving circuit located in different rows, wherein a write control terminal of the first pixel driving circuit and a write control terminal of the second pixel driving circuit are respectively connected to different first shift registers, and a compensation control terminal of the first pixel driving circuit and a compensation control terminal of the second pixel driving circuit are connected to the same second shift register; and when the same signal is written to the data terminal of the first pixel driving circuit and the data terminal of the second pixel driving circuit, the difference in luminance between the first pixel and the second pixel is less than or equal to two grayscales.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate and a driving method thereof, and a display device. Background Art

[0002] Organic Light-Emitting Diode (OLED) screens have the advantages of being light, thin, high brightness, low power consumption, fast response, high clarity, good flexibility and high luminous efficiency, and can meet consumers' new demands for display technology. Summary of the invention

[0003] The present disclosure provides a display substrate, comprising: a substrate, and a first gate driving circuit, a second gate driving circuit, and a plurality of pixel driving circuits arranged in an array, which are arranged on one side of the substrate, wherein the first gate driving circuit comprises a plurality of first shift registers cascaded to each other, the second gate driving circuit comprises a plurality of second shift registers cascaded to each other, and the pixel driving circuit comprises:

[0004] A writing module, connected to the data end, the first node and the writing control end, and used for writing the signal of the data end into the first node according to the signal of the writing control end;

[0005] a driving module connected to the first node, the second node and the third node, and used to write the voltage of the first node into the third node according to the potential of the second node, wherein the third node is also connected to the light emitting device; and

[0006] a compensation module connected to the third node, the second node and the compensation control terminal, and configured to write the signal of the third node into the second node according to the signal of the compensation control terminal;

[0007] The plurality of pixel driving circuits include: a first pixel driving circuit and a second pixel driving circuit located in different rows, a write control terminal of the first pixel driving circuit and a write control terminal of the second pixel driving circuit are respectively connected to different first shift registers, and a compensation control terminal of the first pixel driving circuit and a compensation control terminal of the second pixel driving circuit are connected to the same second shift register; and

[0008] The first pixel driving circuit is used to drive the light-emitting device of the first pixel to emit light, and the second pixel driving circuit is used to drive the light-emitting device of the second pixel to emit light. When the same signal is written to the data end of the first pixel driving circuit and the data end of the second pixel driving circuit, the difference in light-emitting brightness between the first pixel and the second pixel is less than or equal to two gray levels.

[0009] In some embodiments, the first pixel driving circuit and the second pixel driving circuit have different structures.

[0010] In some implementations, the pixel driving circuit further includes:

[0011] A first capacitor, a first plate connected to the first voltage terminal, a second plate connected to the second node, and used to store a signal of the second node;

[0012] The capacitance of the first capacitor in the first pixel driving circuit is different from the capacitance of the first capacitor in the second pixel driving circuit.

[0013] In some embodiments, the write control terminal of the first pixel driving circuit is connected to the output terminal of the nth stage first shift register, and the write control terminal of the second pixel driving circuit is connected to the output terminal of the n+ith stage first shift register, where n and i are both positive integers greater than or equal to 1;

[0014] Wherein, the capacitance of the first capacitor in the first pixel driving circuit is greater than the capacitance of the first capacitor in the second pixel driving circuit.

[0015] In some embodiments, the first plate of the first capacitor has an opening, and the orthographic projection of the opening on the substrate is within the orthographic projection range of the second plate of the first capacitor on the substrate;

[0016] The orthographic projection area of ​​the opening in the first pixel driving circuit on the substrate is smaller than the orthographic projection area of ​​the opening in the second pixel driving circuit on the substrate.

[0017] In some embodiments, the driving module includes:

[0018] a first transistor, a control electrode connected to the second node, a first electrode connected to the first node, and a second electrode connected to the third node;

[0019] The channel width-to-length ratio of the first transistor in the first pixel driving circuit is different from the channel width-to-length ratio of the first transistor in the second pixel driving circuit.

[0020] In some embodiments, the write control terminal of the first pixel driving circuit is connected to the output terminal of the nth stage first shift register, and the write control terminal of the second pixel driving circuit is connected to the output terminal of the n+ith stage first shift register, where n and i are both positive integers greater than or equal to 1;

[0021] The channel width-to-length ratio of the first transistor in the first pixel driving circuit is smaller than the channel width-to-length ratio of the first transistor in the second pixel driving circuit.

[0022] In some embodiments, the first pixel driving circuit and the second pixel driving circuit have the same structure.

[0023] In some implementations, the pixel driving circuit further includes:

[0024] A first reset module, connected to the reset control terminal, the first reset terminal and a fourth node, and used to write the signal of the first reset terminal into the fourth node according to the signal of the reset control terminal, wherein the fourth node is also connected to the first electrode of the light emitting device; and

[0025] A second capacitor, wherein the first plate is connected to the first node, and the second plate is connected to the fourth node;

[0026] Among them, the write control terminal of the first pixel driving circuit is connected to the output terminal of the first shift register of the nth level, the reset control terminal of the first pixel driving circuit is connected to the output terminal of the first shift register of the n+xth level, the write control terminal of the second pixel driving circuit is connected to the output terminal of the first shift register of the n+ith level, and the reset control terminal of the second pixel driving circuit is connected to the output terminal of the first shift register of the n+i+xth level, and the n, the x and the i are all positive integers greater than or equal to 1.

[0027] In some embodiments, x is greater than or equal to 2 and less than or equal to 10.

[0028] In some embodiments, the compensation module includes:

[0029] a second transistor, a control electrode connected to the compensation control terminal, a first electrode connected to the third node, and a second electrode connected to the second node;

[0030] The writing module comprises: a third transistor, a control electrode connected to the writing control terminal, a first electrode connected to the data terminal, and a second electrode connected to the first node;

[0031] The second transistor includes an oxide transistor, and the third transistor includes a polysilicon transistor.

[0032] In some embodiments, the first pixel driving circuit is located in an odd row, and the second pixel driving circuit is located in an even row adjacent to the odd row.

[0033] The present disclosure provides a display device, comprising: a light-emitting device, and a display substrate as described in any embodiment, wherein the display substrate is connected to the light-emitting device and is used to drive the light-emitting device to emit light.

[0034] The present disclosure provides a driving method, applied to a display substrate as described in any embodiment, the driving method comprising:

[0035] Control the first gate drive circuit to output a first write control signal to the write control terminal of the first pixel drive circuit, and output a second write control signal to the write control terminal of the second pixel drive circuit, and control the second gate drive circuit to output a compensation control signal to the compensation control terminal of the first pixel drive circuit and the compensation control terminal of the second pixel drive circuit, so that the first pixel drive circuit writes the signal of its data terminal to its second node, and the second pixel drive circuit writes the signal of its data terminal to its second node, wherein, within one frame period, the pulse period of the compensation control signal covers the pulse period of the first write control signal and the pulse period of the second write control signal, and the pulse period of the first write control signal does not overlap with the pulse period of the second write control signal.

[0036] In some embodiments, within a frame period, the pulse period of the first write control signal is ahead of the pulse period of the second write control signal, the duration between the pulse trailing edge of the compensation control signal and the pulse trailing edge of the first write control signal is a first duration, the duration between the pulse trailing edge of the compensation control signal and the pulse trailing edge of the second write control signal is a second duration, and the ratio of the difference between the first duration and the second duration to the first duration is less than or equal to 1 / 8.

[0037] In some embodiments, the difference between the first time length and the second time length is 1H, the first time length is greater than or equal to 8H, and H is the time length required for the display substrate to scan a row of the pixel driving circuit.

[0038] In some embodiments, a pulse width of the first write control signal is different from a pulse width of the second write control signal.

[0039] In some embodiments, within a frame period, a pulse period of the first write control signal is earlier than a pulse period of the second write control signal, and a pulse width of the first write control signal is smaller than a pulse width of the second write control signal.

[0040] In some implementations, before the step of controlling the first gate driving circuit to output a first write control signal to the write control terminal of the first pixel driving circuit and outputting a second write control signal to the write control terminal of the second pixel driving circuit, the step further includes:

[0041] A first clock signal and a second clock signal are provided to the first gate drive circuit so that the first gate drive circuit generates the first write control signal according to the first clock signal and generates the second write control signal according to the second clock signal, wherein a duty cycle of the first clock signal is smaller than a duty cycle of the second clock signal.

[0042] In some embodiments, when the pixel driving circuit further includes a first reset module and a second capacitor, the first reset module is connected to the reset control terminal, the first reset terminal and the fourth node, the fourth node is also connected to the first electrode of the light-emitting device, the first plate of the second capacitor is connected to the first node, the second plate is connected to the fourth node, and the write control terminal of the first pixel driving circuit is connected to the output terminal of the n-th stage first shift register, the reset control terminal of the first pixel driving circuit is connected to the output terminal of the n+x-th stage first shift register, the write control terminal of the second pixel driving circuit is connected to the output terminal of the n+i-th stage first shift register, the reset control terminal of the second pixel driving circuit is connected to the output terminal of the n+i+x-th stage first shift register, and the n, the i and the x are all positive integers greater than or equal to 1, after the step of controlling the first gate driving circuit to output the first write control signal to the write control terminal of the first pixel driving circuit and output the second write control signal to the write control terminal of the second pixel driving circuit, it also includes:

[0043] Control the first gate driving circuit to output a first reset control signal to the reset control terminal of the first pixel driving circuit, and output a second reset control signal to the reset control terminal of the second pixel driving circuit, wherein, within one frame period, the pulse period of the compensation control signal also covers the pulse period of the first reset control signal and the pulse period of the second reset control signal, and the pulse period of the first reset control signal does not overlap with the pulse period of the second reset control signal.

[0044] The above description is only an overview of the technical solution of the present disclosure. In order to more clearly understand the technical means of the present disclosure, it can be implemented according to the contents of the specification. In order to make the above and other purposes, features and advantages of the present disclosure more obvious and easy to understand, the specific implementation methods of the present disclosure are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or related technologies, the following is a brief introduction to the drawings required for use in the embodiments or related technical descriptions. Obviously, the drawings described below are some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. It should be noted that the proportions in the drawings are only for illustration and do not represent the actual proportions.

[0046] Figure 1 A schematic structural diagram of a display substrate provided by the present disclosure is shown;

[0047] Figure 2 A schematic diagram of the circuit structure of a first pixel driving circuit is shown;

[0048] Figure 3 shows a first driving signal timing diagram of a first pixel driving circuit;

[0049] Figure 4 A schematic diagram of the planar structure of the first capacitor in the first pixel driving circuit and the second pixel driving circuit is shown;

[0050] Figure 5 A schematic diagram of the planar structure of a first transistor channel in a first pixel driving circuit and a second pixel driving circuit is shown;

[0051] Figure 6 Shows a schematic diagram of the circuit structure of two second pixel driving circuits;

[0052] Figure 7 shows a driving signal timing diagram of a second pixel driving circuit;

[0053] Figure 8 shows a second driving signal timing diagram of the first pixel driving circuit;

[0054] Fig. 9 The relative difference between the light emitting current of the first light emitting device and the second light emitting device under different back shift amounts is shown;

[0055] Fig.10 shows a third driving signal timing diagram of the first pixel driving circuit;

[0056] Fig.11 A schematic diagram of the circuit structure of a first shift register is shown. DETAILED DESCRIPTION

[0057] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0058] Reference Figure 1 A schematic diagram of the structure of a display substrate provided by the present disclosure is shown in FIG. Figure 1 As shown, the display substrate includes: a substrate 10, and a first gate driving circuit 11, a second gate driving circuit 12 and a plurality of pixel driving circuits 13 arranged in an array, which are arranged on one side of the substrate 10.

[0059] like Figure 1 As shown, the first gate driving circuit 11 includes a plurality of first shift registers PgateGOA connected in cascade with each other, and the second gate driving circuit 12 includes a plurality of second shift registers Ngate GOA connected in cascade with each other. Figure 1 Only one is shown).

[0060] Reference Figure 2 A structural schematic diagram of a pixel driving circuit is shown, and the pixel driving circuit 13 includes: a writing module 21, connected to the data terminal Data, the first node N1 and the writing control terminal Gate-P1, and used to write the signal of the data terminal Data into the first node N1 according to the signal of the writing control terminal Gate-P1; a driving module 20, connected to the first node N1, the second node N2 and the third node N3, and used to write the voltage of the first node N1 into the third node N3 according to the potential of the second node N2, and the third node N3 is also connected to the light-emitting device LD; and a compensation module 22, connected to the third node N3, the second node N2 and the compensation control terminal Gate-N, and used to write the signal of the third node N3 into the second node N2 according to the signal of the compensation control terminal Gate-N.

[0061] like Figure 1 As shown, the plurality of pixel driving circuits 13 include: a first pixel driving circuit 131 and a second pixel driving circuit 132 located in different rows. The writing control terminal Gate-P1 of the first pixel driving circuit 131 and the writing control terminal Gate-P1 of the second pixel driving circuit 132 are respectively connected to different first shift registers Pgate GOA, and the compensation control terminal Gate-N of the first pixel driving circuit 131 and the compensation control terminal Gate-N of the second pixel driving circuit 132 are connected to the same second shift register Ngate GOA.

[0062] The write control terminal Gate-P1 in the pixel driving circuit 13 is connected to the output terminal of the first shift register Pgate GOA. The compensation control terminal Gate-N in the pixel driving circuit 13 is connected to the output terminal of the second shift register Ngate GOA.

[0063] It should be noted that each second shift register Ngate GOA may have one or more output terminals, and the multiple output terminals output the same signal. The compensation control terminal Gate-N of the first pixel driving circuit 131 and the compensation control terminal Gate-N of the second pixel driving circuit 132 may be connected to the same output terminal or different output terminals in the same second shift register Ngate GOA, and the present disclosure does not limit this.

[0064] The first gate driving circuit 11 is used to output a write control signal. Since the write control signal determines the effective charging time of the pixel driving circuit 13, Figure 1 As shown, a first shift register Pgate GOA drives a row of pixel driving circuits 13 , that is, the first gate driving circuit 11 adopts a 1-drive-1 architecture.

[0065] like Figure 1 As shown, the write control terminal Gate-P1 of the first pixel driving circuit 131 is connected to the output terminal of the n-th stage first shift register Pgate GOA(n), and the write control terminal Gate-P1 of the second pixel driving circuit 132 is connected to the output terminal of the n+i-th stage first shift register Pgate GOA(n+1), where n and i are both positive integers greater than or equal to 1. Figure 1 , i=1.

[0066] The second gate driving circuit 12 is used to output the compensation control signal. Since the pixel driving circuit 13 has low requirements on the rising edge and falling edge of the compensation control signal, in order to achieve a narrow frame, Figure 1 As shown, the compensation control terminal Gate-N of the first pixel driving circuit 131 and the compensation control terminal Gate-N of the second pixel driving circuit 132 are connected to the same second shift register Ngate GOA, that is, the second gate driving circuit 12 adopts a 1-drive-M architecture, where M can be a positive integer greater than or equal to 2. Figure 1 In the embodiment, a second shift register Ngate GOA(2n) drives two rows of pixel driving circuits 13 (ie, the row to which the first pixel driving circuit 131 belongs and the row to which the second pixel driving circuit 132 belongs), that is, the second gate driving circuit 12 adopts a 1-drive-2 (ie, M=2) architecture.

[0067] For example, Figure 1As shown, the first pixel driving circuit 131 is located in an odd row, such as the nth row (n is an odd number), and the second pixel driving circuit 132 is located in an even row adjacent to the odd row, such as the n+1th row, which is not limited in the present disclosure.

[0068] The inventors discovered that when the first gate driving circuit 11 adopts a 1-drive-1 architecture and the second gate driving circuit 12 adopts a 1-drive-2 architecture, when the odd rows where the first pixel driving circuit 131 is located and the even rows where the second pixel driving circuit 132 is located (hereinafter referred to as odd-even rows) display the same grayscale, there is a difference in the display brightness of the pixels in the odd and even rows, which manifests as fine horizontal lines.

[0069] The first pixel driving circuit 131 is used to drive the light emitting device LD1 of the first pixel (ie, the first light emitting device LD1) to emit light, and the second pixel driving circuit 132 is used to drive the light emitting device LD2 of the second pixel (ie, the second light emitting device LD2) to emit light. Figure 2 As shown, when the same signal is written to the data terminal Data of the first pixel driving circuit 131 and the data terminal Data of the second pixel driving circuit 132, the difference between the luminous brightness of the first pixel and the luminous brightness of the second pixel is less than or equal to two gray levels, which can improve the fine horizontal line defect.

[0070] For example, when the same signal is written to the data terminal Data of the first pixel driving circuit 131 and the data terminal Data of the second pixel driving circuit 132, the difference between the light emitting current of the first light emitting device LD1 and the light emitting current of the second light emitting device LD2 is less than or equal to 0.4% of the light emitting current of the first light emitting device LD1. In this way, the brightness difference between the odd and even rows can be reduced, thereby improving the fine horizontal stripe defect.

[0071] For example, Figure 2 As shown, the driving module 20 includes a first transistor T1, a control electrode of the first transistor T1 is connected to the second node N2, a first electrode of the first transistor T1 is connected to the first node N1, and a second electrode of the first transistor T1 is connected to the third node N3.

[0072] For example, Figure 2 As shown, the compensation module 22 includes a second transistor T2, a control electrode of the second transistor T2 is connected to the compensation control terminal Gate-N, a first electrode of the second transistor T2 is connected to the third node N3, and a second electrode of the second transistor T2 is connected to the second node N2.

[0073] For example, Figure 2As shown, the writing module 21 includes a third transistor T3, a control electrode of the third transistor T3 is connected to the writing control terminal Gate-P1, a first electrode of the third transistor T3 is connected to the data terminal Data, and a second electrode of the third transistor T3 is connected to the first node N1.

[0074] Exemplarily, the second transistor T2 may include an oxide transistor, and the oxide transistor may be, for example, an Indium Gallium Zinc Oxide (IGZO) transistor. Due to the low leakage characteristics of the oxide transistor, the low-frequency flicker problem can be improved, so that the display substrate can work in a low-frequency state, which is beneficial to reducing system power consumption and improving the endurance of the display screen.

[0075] Due to the high mobility characteristics of polysilicon transistors, the charging rate can be improved. Exemplarily, the third transistor T3 can be a polysilicon transistor, such as a low-temperature polysilicon transistor.

[0076] For example, Figure 2 As shown, the first transistor T1 and the third transistor T3 are P-type transistors, and the second transistor T2 is an N-type transistor.

[0077] In a specific implementation, the first pixel driving circuit 131 can be controlled to output the write control signal step by step starting from the first stage first shift register PgateGOA. The nth stage first shift register Pgate GOA(n) outputs the first write control signal (e.g., Figure 3 The n+1th stage first shift register Pgate GOA(n+1) outputs a second write control signal (such as Gate-P_O) to the write control terminal Gate-P1 of the second pixel driving circuit 132. Figure 3 Gate-P in ). Figure 3 As shown, within one frame period, the pulse period of the first write control signal Gate-P_odd does not overlap with the pulse period of the second write control signal Gate-P_even, and the pulse period of the first write control signal Gate-P_odd is 1H earlier than the pulse period of the second write control signal Gate-P_even.

[0078] In specific implementation, the second shift register Ngate GOA(2n) of the second gate driving circuit 12 can be controlled to output a compensation control signal to the compensation control terminal Gate-N of the first pixel driving circuit 131 and the compensation control terminal Gate-N of the second pixel driving circuit 132. Since the second gate driving circuit 12 adopts a 1-driving-2 architecture, during the data writing stage and the threshold compensation stage within one frame period, the pulse period (such as Figure 3 the high-level time of Gate-N in Figure 3 ) of the compensation control signal Gate-N output by the second gate driving circuit 12 needs to cover the pulse periods (such as Figure 3 the low-level time of Gate-P_odd in Figure 3 ) of the first writing control signal (such as

[0079] ) and the second writing control signal (such as Figure 2 the Gate-P_even in Figure 3 ). Figure 3 The inventor analyzed the formation mechanism of the fine horizontal stripe defect. Taking the 7T1C pixel driving circuit 13 shown in

[0080] as an example, for the first pixel driving circuit 131, as shown in Figure 3As shown, since the low-level time in the second write control signal Gate-P_even is the effective charging time Tch, when the effective charging time ends, the gate of the first transistor T1 (i.e., the second node N2) is charged to the potential Vn2-even = Vch; when the second write control signal Gate-P_even jumps to a high level, the third transistor T3 is turned off. Since the compensation control signal Gate-N is still at a high potential, the second transistor T2 remains in an open state, and the residual voltage of the first node N1 will continue to charge the second node N2 and perform threshold acquisition of the first transistor T1. This period is the supplementary charging time, and the supplementary charging duration of the second pixel driving circuit 132 (such as Figure 3 T-even shown) is the second duration, that is, the duration between the trailing edge of the pulse of the second write control signal Gate-P_even and the trailing edge of the pulse of the compensation control signal Gate-N.

[0081] Referring to Figure 3 , since the phase difference between the first write control signal Gate-P_odd and the second write control signal Gate-P_even is 1H, that is, the pulse period of the first write control signal Gate-P_odd is 1H earlier than the pulse period of the second write control signal Gate-P_even. Therefore, the supplementary charging duration T-odd of the first pixel driving circuit 131 is 1H longer than the supplementary charging duration T-even of the second pixel driving circuit 132. When the same signal Vdt is written to the data terminal Data of the first pixel driving circuit 131 and the data terminal Data of the second pixel driving circuit 132, the potential Vn2-odd finally charged to the second node N2 in the first pixel driving circuit 131 is Vch + ΔV1, and the potential Vn2-even finally charged to the second node N2 in the second pixel driving circuit 132 is Vch + ΔV2, and ΔV1 > ΔV2. It can be seen that due to the different actual charging times of the first pixel driving circuit 131 and the second pixel driving circuit 132 for the second node N2, the final charging potential of the second node N2 is different, and finally the emission brightness of the first light-emitting device LD1 and the second light-emitting device LD2 is different, resulting in the defect of fine horizontal stripes.

[0082] It should be noted that H is the duration required for the display substrate to scan one row of pixel driving circuits 13.

[0083] In some embodiments, the structures of the first pixel driving circuit 131 and the second pixel driving circuit 132 are different, which may specifically include the following situations: the circuit connection structures of the first pixel driving circuit 131 and the second pixel driving circuit 132 are different, and the circuit connection structures of the first pixel driving circuit 131 and the second pixel driving circuit 132 are the same (such as the circuit connection structure shown in Figure 2 ), but one or more elements in the circuit connection structure are different.

[0084] In order to make the structures of the first pixel driving circuit 131 and the second pixel driving circuit 132 different, in the first embodiment, as Figure 2 shown, the pixel driving circuit 13 further includes a first capacitor C1. The first plate of the first capacitor C1 is connected to the first voltage terminal VDD, and the second plate of the first capacitor C1 is connected to the second node N2. The first capacitor C1 is used to store the signal of the second node N2. Among them, the capacitance value of the first capacitor C1 in the first pixel driving circuit 131 is different from the capacitance value of the first capacitor C1 in the second pixel driving circuit 132.

[0085] Exemplarily, both the first pixel driving circuit 131 and the second pixel driving circuit 132 have the circuit connection structure as Figure 2 shown, and the first capacitor C1 in the first pixel driving circuit 131 and the first capacitor C1 in the second pixel driving circuit 132 have different capacitance values.

[0086] By setting the different capacitance values of the first capacitor C1, the charging speeds of the first pixel driving circuit 131 and the second pixel driving circuit 132 for the second node N2 are different, so that the actual charging time difference between the two for the second node N2 can be offset or balanced, the final charging potential difference of the second node N2 in the first pixel driving circuit 131 and the second pixel driving circuit 132 can be reduced or eliminated, the difference in the light-emitting current and light-emitting brightness between the first light-emitting device LD1 and the second light-emitting device LD2 can be reduced or eliminated, and the fine horizontal stripe defect can be improved or eliminated.

[0087] Furthermore, as Figure 1 shown, the write control terminal Gate-P1 of the first pixel driving circuit 131 is connected to the output terminal of the nth-stage first shift register Pgate GOA(n), and the write control terminal Gate-P1 of the second pixel driving circuit 132 is connected to the output terminal of the (n + i)th-stage first shift register Pgate GOA (such as Figure 1 Pgate GOA(n + 1) in, corresponding to i = 1), where both n and i are positive integers greater than or equal to 1. In this way, within one frame period, the pulse period of the first write control signal (such as Figure 3 Gate-P_odd shown) is i H earlier than the pulse period of the second write control signal (such as Figure 3 Gate-P_even shown), and the supplementary charging duration T-odd of the first pixel driving circuit 131 is i H longer than the supplementary charging duration T-even of the second pixel driving circuit 132. In this case, the capacitance value of the first capacitor C1 in the first pixel driving circuit 131 can be greater than the capacitance value of the first capacitor C1 in the second pixel driving circuit 132.

[0088] In specific implementation, it can be adopted as Figure 3The signal timing shown drives the display substrate provided by this embodiment. In Figure 3 it, the pulse width of the first write control signal (such as Figure 3 Gate-P_odd shown) is the same as the pulse width of the second write control signal (such as Figure 3 Gate-P_even shown). The supplementary charging duration T-even of the second pixel driving circuit 132 is 1H (or 2H, 3H, etc.), and the supplementary charging duration T-odd of the first pixel driving circuit 131 = T-even + 1H (corresponding to i = 1), such as 2H (or 3H, 4H, etc.).

[0089] By setting a first capacitor C1 with a larger capacitance value in the first pixel driving circuit 131, the charging speed of the first pixel driving circuit 131 to the second node N2 can be reduced, and finally the difference in the final charging potential of the second node N2 between the first pixel driving circuit 131 and the second pixel driving circuit 132 can be reduced or eliminated, thereby reducing or eliminating the brightness difference between odd and even rows.

[0090] Exemplarily, the capacitance value of the first capacitor C1 in the first pixel driving circuit 131 can be 65fF, and the capacitance value of the first capacitor C1 in the second pixel driving circuit 132 can be 60fF. The present disclosure does not limit this.

[0091] Exemplarily, as Figure 4 shown, the first electrode plate of the first capacitor C1 has an opening, and the positive projection of the opening on the substrate 10 is located within the positive projection range of the second electrode plate of the first capacitor C1 on the substrate 10. The positive projection area of the opening in the first pixel driving circuit 131 on the substrate 10 is smaller than the positive projection area of the opening in the second pixel driving circuit 132 on the substrate 10. In this way, the overlapping area of the two electrode plates of the first capacitor C1 in the first pixel driving circuit 131 can be made larger, so as to achieve that the capacitance value of the first capacitor C1 in the first pixel driving circuit 131 is greater than the capacitance value of the first capacitor C1 in the second pixel driving circuit 132.

[0092] Exemplarily, as Figure 4 shown, the positive projection shape of the opening on the substrate 10 is a square, and the side length CD1 of the square opening in the first pixel driving circuit 131 is smaller than the side length CD2 of the square opening in the second pixel driving circuit 132.

[0093] It should be noted that the overlapping area of the two electrode plates of the first capacitor C1 in the first pixel driving circuit 131 can also be increased by increasing the positive projection area of the first electrode plate and / or the second electrode plate of the first capacitor C1 on the substrate 10, so as to achieve that the capacitance value of the first capacitor C1 in the first pixel driving circuit 131 is greater than the capacitance value of the first capacitor C1 in the second pixel driving circuit 132.

[0094] In order to make the structures of the first pixel driving circuit 131 and the second pixel driving circuit 132 different, in the second embodiment, as Figure 2 shown, the channel width-to-length ratio of the first transistor T1 in the first pixel driving circuit 131 is different from that of the first transistor T1 in the second pixel driving circuit 132.

[0095] Exemplarily, both the first pixel driving circuit 131 and the second pixel driving circuit 132 have the circuit connection structure as Figure 2 shown, and the first transistor T1 in the first pixel driving circuit 131 and the first transistor T1 in the second pixel driving circuit 132 have different channel width-to-length ratios.

[0096] By setting the different channel width-to-length ratios of the first transistor T1, the charging current magnitudes when the first pixel driving circuit 131 and the second pixel driving circuit 132 charge the second node N2 are different, so that the actual charging time differences between the two for the second node N2 can be offset or balanced, the final charging potential differences of the second node N2 in the first pixel driving circuit 131 and the second pixel driving circuit 132 are reduced or eliminated, and further the light-emitting current and light-emitting brightness differences between the first light-emitting device LD1 and the second light-emitting device LD2 are reduced or eliminated, and the fine stripe defect is improved or eliminated.

[0097] Furthermore, as Figure 1 shown, the write control terminal Gate-P1 of the first pixel driving circuit 131 is connected to the output terminal of the nth-stage first shift register Pgate GOA(n), and the write control terminal Gate-P1 of the second pixel driving circuit 132 is connected to the output terminal of the (n + i)th-stage first shift register Pgate GOA (such as Figure 1 Pgate GOA(n + 1) in Figure 3 , corresponding to i = 1), where both n and i are positive integers greater than or equal to 1. In this way, within one frame period, the pulse period of the first write control signal (such as Figure 3 Gate-P_odd shown) is i H earlier than that of the second write control signal (such as

[0098] Gate-P_even shown), and the supplementary charging duration T-odd of the first pixel driving circuit 131 is i H longer than the supplementary charging duration T-even of the second pixel driving circuit 132. In this case, the channel width-to-length ratio of the first transistor T1 in the first pixel driving circuit 131 is smaller than that of the first transistor T1 in the second pixel driving circuit 132. Figure 3By setting the channel width-to-length ratio of the first transistor T1 in the first pixel driving circuit 131 to be smaller than the channel width-to-length ratio of the first transistor T1 in the second pixel driving circuit 132, the charging current of the first pixel driving circuit 131 can be reduced, and finally the final charging potential difference of the second node N2 in the first pixel driving circuit 131 and the second pixel driving circuit 132 can be reduced or eliminated, thereby reducing or eliminating the brightness difference of odd and even rows.

[0099] In a specific implementation, in order to reduce the channel width-to-length ratio of the first transistor T1 in the first pixel driving circuit 131 , the channel width w1 of the first transistor T1 in the first pixel driving circuit 131 may be reduced, or the channel length of the first transistor T1 in the first pixel driving circuit 131 may be increased.

[0100] For example, Figure 5 As shown, the channel length of the first transistor T1 includes the length of the channel of the first transistor T1 in the first direction. Exemplarily, in the first direction, the channel length CD3 of the first transistor T1 in the first pixel driving circuit 131 is greater than the channel length CD4 of the first transistor T1 in the second pixel driving circuit 132, and finally the channel length of the first transistor T1 in the first pixel driving circuit 131 is greater than the channel length of the first transistor T1 in the second pixel driving circuit 132.

[0101] Exemplarily, the channel width w1 of the first transistor T1 in the first pixel driving circuit 131 is 3 μm, the length is 25 μm, and the aspect ratio is 3 / 25; the channel width w2 of the first transistor T1 in the second pixel driving circuit 132 is 3 μm, the length is 21 μm, and the aspect ratio is 3 / 21.

[0102] In some embodiments, the first pixel driving circuit 131 has the same structure as the second pixel driving circuit 132. For example, the first pixel driving circuit 131 has the same circuit connection structure as the second pixel driving circuit 132 (eg, Figure 6 The two identical circuit connection structures shown in the figure) are identical, and the component structures in the circuit connection structures are also identical.

[0103] In some embodiments, Figure 6 As shown, the pixel driving circuit 13 also includes: a first reset module 61, which is connected to the reset control terminal Gate-P2, the first reset terminal Vinit2 and the fourth node N4, and is used to write the signal of the first reset terminal Vinit2 into the fourth node N4 according to the signal of the reset control terminal Gate-P2, and the fourth node N4 is also connected to the first electrode of the light-emitting device LD; and a second capacitor C2, the first plate of the second capacitor C2 is connected to the first node N1, and the second plate of the second capacitor C2 is connected to the fourth node N4.

[0104] For example, Figure 6 As shown, the first reset module 61 includes a fourth transistor T4, a control electrode of the fourth transistor T4 is connected to the reset control terminal Gate-P2, a first electrode of the fourth transistor T4 is connected to the first reset terminal Vinit2, and a second electrode of the fourth transistor T4 is connected to the fourth node N4.

[0105] For example, Figure 6 As shown, the fourth transistor T4 is a P-type transistor.

[0106] In order to reduce the brightness difference between odd and even rows, in some embodiments, as Figure 6 As shown in FIG. a, the write control terminal Gate-P1 of the first pixel driving circuit 131 is connected to the output terminal of the n-th stage first shift register Pgate GOA(n), and the reset control terminal Gate-P2 of the first pixel driving circuit 131 is connected to the output terminal of the n+x-th stage first shift register Pgate GOA(n+x). Figure 6 As shown in FIG. b, the write control terminal Gate-P1 of the second pixel driving circuit 132 is connected to the output terminal of the first shift register Pgate GOA(n+i) of the n+ith stage, and the reset control terminal Gate-P2 of the second pixel driving circuit 132 is connected to the output terminal of the first shift register Pgate GOA(n+i+x) of the n+i+xth stage. Wherein, n, x and i are all positive integers greater than or equal to 1. Figure 6 , i=1.

[0107] In specific implementation, refer to Figure 6 and Figure 7 , the nth stage first shift register Pgate GOA(n) can be controlled to output a first write control signal (such as Figure 7 The first pixel driving circuit 131 outputs a first reset control signal (such as Gate-P(n)_odd) to the reset control terminal Gate-P2 of the first pixel driving circuit 131. Figure 7 The first shift register Pgate GOA(n+1) of the n+1th stage controls the output of the second write control signal (such as Gate-P(n+x)_odd) to the write control terminal Gate-P1 of the second pixel driving circuit 132. Figure 7 The first shift register Pgate GOA(n+1+x) in the n+1+xth stage is controlled to output a second reset control signal (such as Gate-P(n+1)_even) to the reset control terminal Gate-P2 of the second pixel driving circuit 132. Figure 7 Gate-P(n+1+x)_even in.

[0108] For the first pixel driving circuit 131, the first write control signal (eg Figure 7 The low level time of Gate-P(n)_odd in the effective charging time is the effective charging time Tch. When the effective charging time ends, the gate of the first transistor T1 (i.e., the second node N2) is charged to a potential Vn2(n)-odd of Vch, the potential of the first node N1 is Vdt, and the potential of the fourth node N4 is Vss+Voled. When the first write control signal (e.g. Figure 7 When the Gate-P(n)_odd in the circuit jumps to a high level, the third transistor T3 is turned off. Figure 7 The Gate-N in the first node is still at a high potential, the second transistor T2 is still in the open state, and the residual voltage of the first node N1 continues to charge the second node N2 and obtain the threshold of the first transistor T1, entering the supplementary charging stage until the first reset control signal (such as Figure 7 The Gate-P(n+x)_odd in the fourth node N4 jumps to a low level, and the potential of the fourth node N4 jumps from Vss+Voled to the first reset signal Vinit2. Due to the coupling effect of the second capacitor C2, the potential change of the fourth node N4 can pull down the potential of the first node N1 in a suspended state, and the potential change of the first node N1 is ΔVn1=(C2 / Cn1_all)*[Vinit2-(Vss+Voled)]. Among them, Cn1_all is the sum of all capacitance values ​​of the first node N1. When the potential of the first node N1 is lower than Vdt, the second node N2 cannot continue to be charged, and the second node N2 maintains the potential before the first reset control signal jumps.

[0109] Therefore, the supplementary charging time T-odd of the first pixel driving circuit 131 is the first write control signal (eg Figure 7 The pulse trailing edge of Gate-P(n)_odd) in the first reset control signal (such as Figure 7 The time length between the pulse front edges of Gate-P(n+x)_odd) in the first pixel driving circuit 131 is equal to x Hs, and the final charging potential Vn2(n)-odd of the second node N2 in the first pixel driving circuit 131 is Vch+ΔV.

[0110] Similarly, for the second pixel driving circuit 132, the second writing control signal (eg Figure 7 The low level time of Gate-P(n+1)_even in the effective charging time is the effective charging time Tch. When the effective charging time ends, the gate of the first transistor T1 (i.e., the second node N2) is charged to a potential Vn2(n+1)-even of Vch, the potential of the first node N1 is Vdt, and the potential of the fourth node N4 is Vss+Voled. When the second write control signal (such as Figure 7When the Gate-P(n+1)_even in the circuit jumps to a high level, the third transistor T3 is turned off. Figure 7 The Gate-N in the first node is still at a high potential, the second transistor T2 is still in the open state, and the residual voltage of the first node N1 continues to charge the second node N2 and obtain the threshold of the first transistor T1, entering the supplementary charging stage until the second reset control signal (such as Figure 7 The Gate-P(n+1+x)_even in the fourth node N4 jumps to a low level, and the potential of the fourth node N4 jumps from Vss+Voled to the first reset signal Vinit2. Due to the coupling effect of the second capacitor C2, the potential change of the fourth node N4 can pull down the potential of the first node N1 in a suspended state, and the potential change of the first node N1 is ΔVn1=(C2 / Cn1_all)*[Vinit2-(Vss+Voled)]. Among them, Cn1_all is the sum of all capacitance values ​​of the first node N1. When the potential of the first node N1 is lower than Vdt, the second node N2 cannot continue to be charged, and the second node N2 maintains the potential before the first reset control signal jumps.

[0111] Therefore, the supplementary charging time T-even of the second pixel driving circuit 132 is equal to the second writing control signal (eg Figure 7 The pulse trailing edge of Gate-P(n+1)_even in Figure 7 The time length between the pulse leading edges of Gate-P(n+1+x)-even in the second pixel driving circuit 132 is also equal to x Hs, and the final charging potential Vn2(n+1)-even of the second node N2 in the second pixel driving circuit 132 is also Vch+ΔV.

[0112] In specific implementation, Figure 7 As shown, the pulse width of the first write control signal Gate-P_odd and the pulse width of the second write control signal Gate-P_even can be the same, that is, the effective charging time of the first pixel driving circuit 131 and the second pixel driving circuit 132 are the same. Since the supplementary charging time of the first pixel driving circuit 131 and the second pixel driving circuit 132 are also the same, Figure 6 The pixel driving circuit shown can completely eliminate the final charging potential difference of the second node N2 in the first pixel driving circuit 131 and the second pixel driving circuit 132, thereby significantly reducing or eliminating the brightness difference between odd and even rows.

[0113] like Figure 7As shown, within one frame period, the pulse period of the compensation control signal also covers the pulse period of the first reset control signal and the pulse period of the second reset control signal. In addition, the pulse period of the first write control signal may not overlap with the pulse period of the first write control signal, and the pulse period of the first reset control signal may not overlap with the pulse period of the second reset control signal.

[0114] In some embodiments, x is greater than or equal to 2 and less than or equal to 10. For example, x may be equal to 3, 5, or 7, etc.

[0115] By increasing the value of x, the phase difference between the write control signal and the reset control signal can be enlarged, thereby effectively extending the supplementary charging time and improving the problems of insufficient charging and low grayscale image quality. In specific implementation, the specific value of x can be determined based on factors such as actual display effect and wiring space.

[0116] The present disclosure provides a display device, comprising: a light emitting device, and a display substrate provided in any embodiment, wherein the display substrate is connected to the light emitting device and is used to drive the light emitting device to emit light.

[0117] It is understood that the display device provided by the present disclosure has the advantages of the above-mentioned display substrate, which will not be described in detail here. The display device provided by the present disclosure can be: a display panel, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame or a navigator, or any other product or component with a display function.

[0118] The pixel driving circuit 13 in the display substrate is connected to the light emitting device to provide a light emitting current for the light emitting device.

[0119] The present disclosure provides a driving method, which is applied to a display substrate provided in any embodiment, and the driving method includes:

[0120] Step S01: Control the first gate driving circuit 11 to output a first write control signal to the write control terminal Gate-P1 of the first pixel driving circuit 131, output a second write control signal to the write control terminal Gate-P1 of the second pixel driving circuit 132, and control the second gate driving circuit 12 to output a compensation control signal to the compensation control terminal Gate-N of the first pixel driving circuit 131 and the compensation control terminal Gate-N of the second pixel driving circuit 132, so that the first pixel driving circuit 131 writes the signal of its data terminal Data to its second node N2, and the second pixel driving circuit 132 writes the signal of its data terminal Data to its second node N2. In one frame period, the pulse period of the compensation control signal covers the pulse period of the first write control signal and the pulse period of the second write control signal, and the pulse period of the first write control signal does not overlap with the pulse period of the second write control signal.

[0121] In order to reduce the brightness difference between odd and even rows, in some embodiments, as Figure 8 As shown, within one frame period, the pulse period of the first write control signal Gate-P_odd is earlier than the pulse period of the second write control signal Gate-P_even, the duration between the pulse trailing edge of the compensation control signal Gate-N and the pulse trailing edge of the first write control signal Gate-P_odd is the first duration T-odd, the duration between the pulse trailing edge of the compensation control signal Gate-N and the pulse trailing edge of the second write control signal Gate-P_even is the second duration T-even, and the ratio of the difference between the first duration T-odd and the second duration T-even to the first duration T-odd is less than or equal to 1 / 8.

[0122] For example, the difference between the first time length T-odd and the second time length T-even is 1H, and the first time length T-odd is greater than or equal to 8H. Figure 8 ), 9H, 10H, etc., the second duration T-even is 7H (as shown in Figure 8 As shown), 8H, 9H, etc., the present disclosure is not limited to this.

[0123] The driving method provided in this embodiment can drive a display substrate, in which the first pixel driving circuit 131 and the second pixel driving circuit 132 can have the same structure. For example, the first pixel driving circuit 131 and the second pixel driving circuit 132 both use Figure 2 The circuit connection structure shown, and the component structure in the circuit connection structure is also the same.

[0124] The first time length T-odd is the supplementary charging time length of the first pixel driving circuit 131, and the second time length T-even is the supplementary charging time length of the second pixel driving circuit 132. Figure 3 In the first time period, T-odd is 2 hours, and the second time period, T-even, is 1 hour; Figure 8 In the example, the first duration T-odd is 8 hours, and the second duration T-even is 7 hours.

[0125] This embodiment is equivalent to Figure 3On the basis of the compensation control signal shown, the falling edge of the compensation control signal Gate-N is shifted back, thereby extending the first duration T-odd and the second duration T-even, thereby extending the supplementary charging duration of the first pixel driving circuit 131 and the second pixel driving circuit 132, reducing the proportion of the difference between the supplementary charging durations of the two in the first duration, and reducing the impact of the supplementary charging time difference. As the supplementary charging process proceeds, the charging current decays rapidly, and the charging rate of the second node N2 is close to saturation. Therefore, as the supplementary charging duration is extended, the impact of the supplementary charging time difference can be ignored.

[0126] Reference Fig. 9 The relative difference of the light-emitting current of the first light-emitting device LD1 and the second light-emitting device LD2 under different back shifts is shown. The relative difference on the ordinate is the ratio of the difference between the light-emitting current of the first light-emitting device LD1 and the light-emitting current of the second light-emitting device LD2 to the light-emitting current of the first light-emitting device LD1. The back shift Td on the abscissa represents the difference between the light-emitting current of the first light-emitting device LD1 and the light-emitting current of the second light-emitting device LD2. Figure 3 Based on the compensation control signal shown in FIG, the length of time the falling edge of the compensation control signal is shifted backward. Fig. 9 As shown in FIG. 1 , as the amount of backshift increases, the relative difference between the light-emitting currents of the first light-emitting device LD1 and the second light-emitting device LD2 decreases. In order to achieve that when the data terminal Data of the first pixel driving circuit 131 and the data terminal Data of the second pixel driving circuit 132 are written with the same signal, the relative difference between the light-emitting currents of the first light-emitting device LD1 and the second light-emitting device LD2 is less than or equal to 0.4%, the amount of backshift can be greater than or equal to 6H. Therefore, the first time length T-odd is calculated by Figure 3 The 2H shown is extended to 8H, and the second duration T-even is Figure 3 The 1H shown is extended to 7H.

[0127] In this implementation, illustratively, the pulse width of the first write control signal Gate-P_odd and the pulse width of the second write control signal Gate-P_even may be the same, such as Figure 8 As shown, the pulse width is Tch, which is not limited in the present disclosure.

[0128] It should be noted that the driving method provided in this embodiment can also drive a display substrate in which the first pixel driving circuit 131 and the second pixel driving circuit 132 have different structures.

[0129] In order to reduce the brightness difference between odd and even rows, in some embodiments, as Fig.10 As shown, the pulse width T1 of the first write control signal Gate-P(n)_odd is different from the pulse width T2 of the second write control signal Gate-P(n)_even.

[0130] The driving method provided in this embodiment can drive a display substrate, in which the first pixel driving circuit 131 and the second pixel driving circuit 132 can have the same structure. For example, the first pixel driving circuit 131 and the second pixel driving circuit 132 both use Figure 2 The circuit connection structure shown, and the component structure in the circuit connection structure is also the same.

[0131] By differentially designing the pulse width T1 of the first write control signal and the pulse width T2 of the second write control signal, the actual charging time difference between the first pixel driving circuit 131 and the second pixel driving circuit 132 for the second node N2 can be offset or balanced, the final charging potential difference between the second node N2 in the first pixel driving circuit 131 and the second pixel driving circuit 132 can be reduced or eliminated, the light-emitting current and light-emitting brightness difference between the first light-emitting device LD1 and the second light-emitting device LD2 can be reduced or eliminated, and the fine horizontal line defect can be improved or eliminated.

[0132] Furthermore, if Fig.10 As shown, within one frame period, the pulse period of the first write control signal Gate-P(n)_odd is earlier than the pulse period of the second write control signal Gate-P(n)_even, and the pulse width T1 of the first write control signal Gate-P(n)_odd is smaller than the pulse width T2 of the second write control signal Gate-P(n)_even.

[0133] like Fig.10 As shown, since the pulse period of the first write control signal Gate-P(n)_odd is earlier than the pulse period of the second write control signal Gate-P(n)_even, the supplementary charging time of the second node N2 by the first pixel driving circuit 131 is longer than the supplementary charging time of the second node N2 by the second pixel driving circuit 132. By shortening the pulse width T1 of the first write control signal Gate-P(n)_odd, the effective charging time of the second node N2 by the first pixel driving circuit 131 can be shortened. By adjusting the pulse width T1 of the first write control signal Gate-P(n)_odd and the pulse width T2 of the second write control signal Gate-P(n)_even, the potential finally charged to the second node N2 in the first pixel driving circuit 131 and the second pixel driving circuit 132 can be made consistent, thereby improving the defect of fine horizontal lines.

[0134] Since the charging rate is high in the effective charging stage, in order to make the final charged potential of the second node N2 in the first pixel driving circuit 131 and the second pixel driving circuit 132 consistent, in some embodiments, the difference between the pulse width T2 of the second write control signal and the pulse width T1 of the first write control signal is smaller than the phase difference between the pulse period of the first write control signal and the pulse period of the second write control signal.

[0135] For example, when the phase difference between the pulse period of the first write control signal and the pulse period of the second write control signal is 1H, the difference between the pulse width T2 of the second write control signal and the pulse width T1 of the first write control signal is less than 1H.

[0136] It should be noted that in Fig.10 When the first write control signal is Gate-P(n)_odd, the second write control signal is Gate-P(n)_even; when the first write control signal is Gate-P(n+1)_odd, the second write control signal is Gate-P(n+1)_even.

[0137] It should also be noted that the driving method provided in this embodiment can also drive a display substrate in which the first pixel driving circuit 131 and the second pixel driving circuit 132 have different structures.

[0138] In order to reduce the brightness difference between odd and even rows, in some implementations, before step S01, the method further includes:

[0139] Step S11: providing the first clock signal GCK and the second clock signal GCB to the first gate driving circuit 11, so that the first gate driving circuit 11 generates a first write control signal according to the first clock signal GCK and generates a second write control signal according to the second clock signal GCB. Fig.10 As shown, the duty cycle of the first clock signal GCK is smaller than the duty cycle of the second clock signal GCB. The pulse periods of the first clock signal GCK and the second clock signal GCB are the same.

[0140] For example, refer to Fig.11 A schematic diagram of the circuit structure of a first shift register is shown, such as Fig.11As shown, the first shift register is an 8T1C GOA circuit, which is connected to the input signal terminal Input and outputs a write control signal according to the signal of the input signal terminal Input. The input signal terminal Input of the n-th first shift register Pgate GOA(n) is connected to the first clock signal line, and the input signal terminal Input of the n+1-th first shift register Pgate GOA(n+1) is connected to the second clock signal line, so that the n-th first shift register Pgate GOA(n) can generate a first write control signal according to the first clock signal GCK input by the first clock signal line, and the n+1-th first shift register Pgate GOA(n+1) can generate a second write control signal according to the second clock signal GCB input by the second clock signal line. Among them, the pulse width of the first write control signal is equal to the pulse width of the first clock signal GCK, and the pulse width of the second write control signal is equal to the pulse width of the second clock signal GCB.

[0141] In some embodiments, Figure 6 As shown, the pixel driving circuit 13 also includes a first reset module 61 and a second capacitor C2. The first reset module 61 is connected to the reset control terminal Gate-P2, the first reset terminal Vinit2 and the fourth node N4. The fourth node N4 is also connected to the first electrode of the light-emitting device. The first plate of the second capacitor C2 is connected to the first node N1, and the second plate is connected to the fourth node N4. The write control terminal Gate-P1 of the first pixel driving circuit 131 is connected to the output end of the n-th stage first shift register Pgate GOA, the reset control terminal Gate-P2 of the first pixel driving circuit 131 is connected to the output end of the n+x-th stage first shift register Pgate GOA, the write control terminal Gate-P1 of the second pixel driving circuit 132 is connected to the output end of the n+i-th stage first shift register Pgate GOA, and the reset control terminal Gate-P2 of the second pixel driving circuit 132 is connected to the output end of the n+i+x-th stage first shift register Pgate GOA, and n, i and x are all positive integers greater than or equal to 1. In this embodiment, in step S01, after the step of controlling the first gate driving circuit 11 to output a first write control signal to the write control terminal Gate-P1 of the first pixel driving circuit 131 and output a second write control signal to the write control terminal Gate-P1 of the second pixel driving circuit 132, the method further includes:

[0142] Step S21: Control the first gate driving circuit 11 to output a first reset control signal to the reset control terminal Gate-P2 of the first pixel driving circuit 131, and output a second reset control signal to the reset control terminal Gate-P2 of the second pixel driving circuit 132. Figure 7As shown, within one frame period, the pulse period of the compensation control signal also covers the pulse period of the first reset control signal and the pulse period of the second reset control signal, and the pulse period of the first reset control signal does not overlap with the pulse period of the second reset control signal.

[0143] In specific implementation, Figure 7 As shown, the pulse width of the first write control signal and the pulse width of the second write control signal may be the same, for example, both are Tch.

[0144] It should be noted that the driving method may also include more steps, which may be determined according to actual needs, and the present disclosure does not limit this. The detailed description and technical effects of the driving method can be referred to the above description of the display substrate, which will not be repeated here.

[0145] In the present disclosure, “plurality” means two or more, and “at least one” means one or more, unless otherwise clearly and specifically defined.

[0146] In the present disclosure, the orientation or positional relationship indicated by the terms "upper" and "lower" are based on the orientation or positional relationship shown in the accompanying drawings and are only for the convenience of describing the present disclosure and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present disclosure.

[0147] As used herein, the terms "comprises," "includes," or any other variation thereof are intended to encompass non-exclusive inclusion, such that a process, method, commodity, or device that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, product, or device. In the absence of further limitations, an element defined by the phrase "includes a ..." does not exclude the presence of additional identical elements in the process, method, commodity, or device that includes the element.

[0148] References herein to "one embodiment," "some embodiments," "exemplary embodiments," "one or more embodiments," "example," "an example," "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with the embodiment or example is included in at least one embodiment or example of the present disclosure. Schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0149] In this document, relational terms such as first and second, etc. are used merely to distinguish one entity or operation from another entity or operation, but do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0150] When describing some embodiments, the expressions "coupled" and "connected" may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. As another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0151] A "connection" may be a direct connection or an indirect connection.

[0152] “At least one of A, B, and C” has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0153] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0154] As used herein, the term "if" is optionally interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrases "if it is determined that" or "if [a stated condition or event] is detected" are optionally interpreted to mean "upon determining that" or "in response to determining that" or "upon detecting [a stated condition or event]" or "in response to detecting [a stated condition or event]," depending on the context.

[0155] The use of "for" or "configured to" herein is meant to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0156] The use of "based on" or "according to" herein is meant to be open and inclusive. A process, step, calculation or other action based on one or more of the conditions or values ​​may, in practice, be based on other conditions or exceed the values ​​described. A process, step, calculation or other action based on one or more of the conditions or values ​​may, in practice, be based on other conditions or exceed the values ​​described.

[0157] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of variation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0158] As used herein, "parallel", "perpendicular", "equal", and "flush" include the situations described and situations similar to the situations described, the range of which is within an acceptable deviation range, wherein the acceptable deviation range is as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range for approximate parallelism may be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range for approximate perpendicularity may also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range for approximate equality may be, for example, that the difference between the two being equal is less than or equal to 5% of either one. "Flush" includes absolute flushness and approximate flushness, wherein the acceptable deviation range for approximate flushness may be, for example, that the distance between the two being flush is less than or equal to 5% of the size of either one.

[0159] It will be understood that when a layer or an element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present between the layer or element and the other layer or substrate.

[0160] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0161] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A display substrate, comprising: A substrate, and a first gate driving circuit, a second gate driving circuit and a plurality of pixel driving circuits arranged in an array on one side of the substrate, wherein the first gate driving circuit includes a plurality of first shift registers cascaded to each other, the second gate driving circuit includes a plurality of second shift registers cascaded to each other, and the pixel driving circuit includes: A writing module, connected to the data end, the first node and the writing control end, and used for writing the signal of the data end into the first node according to the signal of the writing control end; a driving module connected to the first node, the second node and the third node, and used to write the voltage of the first node into the third node according to the potential of the second node, wherein the third node is also connected to the light emitting device; and a compensation module connected to the third node, the second node and the compensation control terminal, and configured to write the signal of the third node into the second node according to the signal of the compensation control terminal; The plurality of pixel driving circuits include: a first pixel driving circuit and a second pixel driving circuit located in different rows, a write control terminal of the first pixel driving circuit and a write control terminal of the second pixel driving circuit are respectively connected to different first shift registers, and a compensation control terminal of the first pixel driving circuit and a compensation control terminal of the second pixel driving circuit are connected to the same second shift register; and The first pixel driving circuit is used to drive the light-emitting device of the first pixel to emit light, and the second pixel driving circuit is used to drive the light-emitting device of the second pixel to emit light. When the same signal is written to the data end of the first pixel driving circuit and the data end of the second pixel driving circuit, the difference in light-emitting brightness between the first pixel and the second pixel is less than or equal to two gray levels.

2. The display substrate according to claim 1, wherein: The first pixel driving circuit and the second pixel driving circuit have different structures.

3. The display substrate according to claim 2, wherein the pixel driving circuit further comprises: A first capacitor, a first plate connected to the first voltage terminal, a second plate connected to the second node, and used to store a signal of the second node; The capacitance of the first capacitor in the first pixel driving circuit is different from the capacitance of the first capacitor in the second pixel driving circuit.

4. The display substrate according to claim 3, wherein the write control terminal of the first pixel driving circuit is connected to the output terminal of the n-th stage first shift register, and the write control terminal of the second pixel driving circuit is connected to the output terminal of the n+i-th stage first shift register, wherein both n and i are positive integers greater than or equal to 1; in, The capacitance of the first capacitor in the first pixel driving circuit is greater than the capacitance of the first capacitor in the second pixel driving circuit.

5. The display substrate according to claim 4, wherein the first electrode plate of the first capacitor has an opening, and the orthographic projection of the opening on the substrate is located within the orthographic projection range of the second electrode plate of the first capacitor on the substrate; in, An orthographic projection area of ​​the opening in the first pixel driving circuit on the substrate is smaller than an orthographic projection area of ​​the opening in the second pixel driving circuit on the substrate.

6. The display substrate according to claim 2, wherein the driving module comprises: a first transistor, a control electrode connected to the second node, a first electrode connected to the first node, and a second electrode connected to the third node; The channel width-to-length ratio of the first transistor in the first pixel driving circuit is different from the channel width-to-length ratio of the first transistor in the second pixel driving circuit.

7. The display substrate according to claim 6, wherein the write control terminal of the first pixel driving circuit is connected to the output terminal of the n-th stage first shift register, and the write control terminal of the second pixel driving circuit is connected to the output terminal of the n+i-th stage first shift register, wherein both n and i are positive integers greater than or equal to 1; in, The channel width-to-length ratio of the first transistor in the first pixel driving circuit is smaller than the channel width-to-length ratio of the first transistor in the second pixel driving circuit. 8 . The display substrate according to claim 1 , wherein the first pixel driving circuit and the second pixel driving circuit have the same structure.

9. The display substrate according to claim 8, wherein the pixel driving circuit further comprises: A first reset module, connected to the reset control terminal, the first reset terminal and a fourth node, and used to write the signal of the first reset terminal into the fourth node according to the signal of the reset control terminal, wherein the fourth node is also connected to the first electrode of the light emitting device; and A second capacitor, wherein a first plate is connected to the first node, and a second plate is connected to the fourth node; Among them, the write control terminal of the first pixel driving circuit is connected to the output terminal of the first shift register of the nth level, the reset control terminal of the first pixel driving circuit is connected to the output terminal of the first shift register of the n+xth level, the write control terminal of the second pixel driving circuit is connected to the output terminal of the first shift register of the n+ith level, and the reset control terminal of the second pixel driving circuit is connected to the output terminal of the first shift register of the n+i+xth level, and the n, the x and the i are all positive integers greater than or equal to 1. 10 . The display substrate according to claim 9 , wherein x is greater than or equal to 2 and less than or equal to 10.

11. The display substrate according to any one of claims 1 to 10, wherein the compensation module comprises: a second transistor, a control electrode connected to the compensation control terminal, a first electrode connected to the third node, and a second electrode connected to the second node; The writing module comprises: a third transistor, a control electrode connected to the writing control terminal, a first electrode connected to the data terminal, and a second electrode connected to the first node; The second transistor includes an oxide transistor, and the third transistor includes a polysilicon transistor. 12 . The display substrate according to claim 1 , wherein the first pixel driving circuit is located in odd rows, and the second pixel driving circuit is located in even rows adjacent to the odd rows.

13. A display device, comprising: A light emitting device, and a display substrate as claimed in any one of claims 1 to 12, wherein the display substrate is connected to the light emitting device and is used to drive the light emitting device to emit light.

14. A driving method, applied to the display substrate according to any one of claims 1 to 12, the driving method comprising: Control the first gate drive circuit to output a first write control signal to the write control terminal of the first pixel drive circuit, and output a second write control signal to the write control terminal of the second pixel drive circuit, and control the second gate drive circuit to output a compensation control signal to the compensation control terminal of the first pixel drive circuit and the compensation control terminal of the second pixel drive circuit, so that the first pixel drive circuit writes the signal of its data terminal to its second node, and the second pixel drive circuit writes the signal of its data terminal to its second node, wherein, within one frame period, the pulse period of the compensation control signal covers the pulse period of the first write control signal and the pulse period of the second write control signal, and the pulse period of the first write control signal does not overlap with the pulse period of the second write control signal.

15. According to the driving method of claim 14, within a frame period, the pulse period of the first write control signal is earlier than the pulse period of the second write control signal, the duration between the pulse trailing edge of the compensation control signal and the pulse trailing edge of the first write control signal is a first duration, the duration between the pulse trailing edge of the compensation control signal and the pulse trailing edge of the second write control signal is a second duration, and the ratio of the difference between the first duration and the second duration to the first duration is less than or equal to 1 / 8.

16. The driving method according to claim 15, wherein the difference between the first time length and the second time length is 1H, the first time length is greater than or equal to 8H, and H is the time length required for the display substrate to scan a row of the pixel driving circuit. 17 . The driving method according to claim 14 , wherein a pulse width of the first write control signal is different from a pulse width of the second write control signal.

18. The driving method according to claim 17, wherein within one frame period, a pulse period of the first write control signal is earlier than a pulse period of the second write control signal, and a pulse width of the first write control signal is smaller than a pulse width of the second write control signal.

19. The driving method according to claim 18, before the step of controlling the first gate driving circuit to output a first write control signal to the write control terminal of the first pixel driving circuit and output a second write control signal to the write control terminal of the second pixel driving circuit, further comprising: A first clock signal and a second clock signal are provided to the first gate drive circuit so that the first gate drive circuit generates the first write control signal according to the first clock signal and generates the second write control signal according to the second clock signal, wherein a duty cycle of the first clock signal is smaller than a duty cycle of the second clock signal.

20. The driving method according to claim 14, when the pixel driving circuit further includes a first reset module and a second capacitor, the first reset module is connected to the reset control terminal, the first reset terminal and the fourth node, the fourth node is also connected to the first electrode of the light-emitting device, the first plate of the second capacitor is connected to the first node, the second plate is connected to the fourth node, and the write control terminal of the first pixel driving circuit is connected to the output terminal of the n-th stage first shift register, the reset control terminal of the first pixel driving circuit is connected to the output terminal of the n+x-th stage first shift register, the write control terminal of the second pixel driving circuit is connected to the output terminal of the n+i-th stage first shift register, the reset control terminal of the second pixel driving circuit is connected to the output terminal of the n+i+x-th stage first shift register, and when n, i and x are all positive integers greater than or equal to 1, after the step of controlling the first gate driving circuit to output the first write control signal to the write control terminal of the first pixel driving circuit and output the second write control signal to the write control terminal of the second pixel driving circuit, the method further includes: Control the first gate driving circuit to output a first reset control signal to the reset control terminal of the first pixel driving circuit, and output a second reset control signal to the reset control terminal of the second pixel driving circuit, wherein, within one frame period, the pulse period of the compensation control signal also covers the pulse period of the first reset control signal and the pulse period of the second reset control signal, and the pulse period of the first reset control signal does not overlap with the pulse period of the second reset control signal.

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