A fully digital in-memory computing device

Abstract

This invention discloses an all-digital in-memory computing device, relating to the field of in-memory computing. In this device, an SRAMWL driver and input activation driver module provides word line and input stimuli for SRAM cells, providing different stimuli at different stages; an SRAM read / write control module is connected to the bit lines and provides bit line drive for SRAM cells in memory mode; a memory mode data path provides a path for data interaction with the outside world; a row of SRAM cells is connected to an approximate compressor array; the approximate compressor array is connected to a precise compressor array; the approximate compressor array performs data compression; the precise compressor array performs further data compression to obtain a result that ignores the most significant carry. This invention can improve the energy efficiency and stability of digital in-memory computing architectures.

Description

Technical Field

[0001] This invention relates to the field of in-memory computing, and in particular to an all-digital in-memory computing device. Background Technology

[0002] With the rapid development of artificial intelligence, the existing von Neumann architecture is no longer sufficient for applications with large data volumes. For data transmission on the bus, bandwidth limitations have become a major bottleneck in applications such as convolutional neural networks.

[0003] To address the aforementioned issues, in-memory computing architectures have emerged. The core idea behind this architecture is to combine computing modules with storage modules, eliminating data transmission paths. Currently, analog in-memory computing architectures cannot be applied to high-precision scenarios due to their poor process scalability, while digital in-memory computing is disadvantageous in terms of energy efficiency and area. Therefore, improving the energy efficiency of digital in-memory computing architectures is a pressing issue that needs to be addressed. Summary of the Invention

[0004] The purpose of this invention is to provide an all-digital in-memory computing device that can improve the energy efficiency and stability of digital in-memory computing architecture.

[0005] To achieve the above objectives, the present invention provides the following solution:

[0006] A fully digital in-memory computing device includes: an SRAM WL driver and input activation driver module, an SRAM read / write control module, a memory mode data path module, and multiple computing modules; each computing module includes: an approximate compressor array, a precise compressor array, and a row of SRAM cells;

[0007] The SRAM WL driver & input activation driver module is used to provide word line WL stimuli and input stimuli for SRAM cells, providing different stimuli at different stages;

[0008] The SRAM read / write control module is connected to bit line BL and bit line BLB. The SRAM read / write control module is used to provide bit line BL and bit line BLB drive for SRAM cells when storing data in storage mode.

[0009] Storage-mode data paths are used to provide a path for data interaction with the outside world;

[0010] A column of SRAM cells is connected to an approximate compressor array; the approximate compressor array is connected to a precise compressor array; the approximate compressor array is used for data compression; the precise compressor array is used for further data compression to obtain a result that ignores the most significant carry.

[0011] Optionally, the column of SRAM cells includes 64 SRAM cells.

[0012] Optionally, the SRAM cell includes: a 6T SRAM structure and an XNOR gate;

[0013] A 6T SRAM structure is used to store weights;

[0014] The two inputs of the XNOR gate are the Q terminal and input excitation of the 6T SRAM, respectively; the output of the XNOR gate is connected to the input of the approximate compressor array.

[0015] Optionally, the approximate compressor array comprises: 16 approximate compressors;

[0016] Each approximate compressor is used to compress four 1-bit data segments, producing a 2-bit result.

[0017] Optionally, the approximate compressor includes: tubes P1, P2, P3, P4, N1, N2, N3, N4, inverter I1, inverter I2, NAND gate A1, and 4-input OR AND gate OA22;

[0018] The gate of transistor P1 is connected to input signal X2, the drain of transistor P1 is connected to input signal X1, and the source of transistor P1 is connected to the sources of transistors P2, N1, and N2, as well as one input terminal of NAND gate A1. The gate of transistor P2 is connected to input signal X1, and the drain of transistor P2 is connected to input signal X2. The gate of transistor P3 is connected to input signal X4, the drain of transistor P3 is connected to input signal X3, and the source of transistor P3 is connected to the sources of transistors P4, N3, and N4, as well as the other input terminal of NAND gate A1. The gate of transistor P4 is connected to input signal X3. Connect the following transistors: the drain of transistor P4 is connected to the input signal X4; the gate of transistor N1 is connected to the output of inverter I1, and the drain of transistor N1 is connected to the input signal X1; the gate of transistor N2 is connected to the input signal X1, and the drain of transistor N2 is connected to the output of inverter I1; the gate of transistor N3 is connected to the output of inverter I2, and the drain of transistor N3 is connected to the input signal X3; the gate of transistor N4 is connected to the input signal X3, and the drain of transistor N4 is connected to the output of inverter I2; the input of inverter I1 is connected to the input signal X2; and the input of inverter I2 is connected to the input signal X4.

[0019] The output of NAND gate A1 outputs the sum bit result S;

[0020] The input terminals of the 4-input OR AND gate OA22 are connected to input signals X1, X2, X3 and X4, and the output terminal of the 4-input OR AND gate OA22 outputs the carry result C.

[0021] Optionally, the precision compressor array includes four precision compressors.

[0022] Optionally, the precision compressor includes: XOR gate XOR1, XOR gate XOR2, XOR gate XOR3, XOR gate XOR4, XOR gate XOR5, NAND gate NAND1, NAND gate NAND2, NAND gate NAND3, NAND gate NAND4, and a four-input AND gate AND4.

[0023] The inputs of XOR gate XOR1 are A and B, and the output of XOR gate XOR1 is connected to one input of XOR gate XOR3.

[0024] The inputs of the XOR gate XOR2 are C and D, and the output of the XOR gate XOR2 is connected to the other input of the XOR gate XOR3.

[0025] The output of the XOR gate XOR3 is OUT[0];

[0026] The inputs of the XOR gate XOR4 are B and C, and the output of the XOR gate XOR4 is connected to one end of the input of the NAND gate NAND2.

[0027] The inputs of the XOR gate XOR5 are B and D, and the output of the XOR gate XOR5 is connected to one end of the input of the NAND gate NAND3.

[0028] The inputs of NAND gate NAND1 are the output of XOR gate XOR1 and C, and the output of NAND gate NAND1 is connected to one end of the input of NAND gate NAND4.

[0029] The inputs of NAND gate NAND2 are the output of XOR gate XOR4 and D, and the output of NAND gate NAND2 is connected to one end of the input of NAND gate NAND4.

[0030] The inputs of NAND gate NAND3 are the output of XOR gate XOR5 and A, and the output of NAND gate NAND3 is connected to one end of the input of NAND gate NAND4.

[0031] The input of NAND gate NAND4 is the output of NAND gate NAND1, NAND gate NAND2, and NAND gate NAND3, and the output is OUT[1];

[0032] The inputs of the four-input AND gate AND4 are A, B, C and D, and the output of the four-input AND gate AND4 is OUT[2];

[0033] A, B, C, and D are used to receive the carry result C and the sum result S from the approximate compressor output.

[0034] Optionally, the NAND gate NAND4 is a three-input NAND gate.

[0035] According to specific embodiments provided by the present invention, the present invention discloses the following technical effects:

[0036] This invention provides an all-digital in-memory computing device that uses an approximate compressor array and a precise compressor array to form an adder array, ultimately obtaining a result that ignores the carry-out of the most significant bit. As an all-digital in-memory computing architecture, it avoids the voltage quantization process in the analog domain, thereby improving the overall structural stability and reducing the impact of the PVT effect. This invention employs an approximate data compression structure, which can accelerate the circuit calculation process while reducing the power consumption of the circuit calculation, reducing the number of transistors consumed per bit of compression, and maximizing energy efficiency. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0038] Figure 1 This is a schematic diagram of the structure of an all-digital in-memory computing device provided by the present invention;

[0039] Figure 2 This is a schematic diagram of an approximate compressor structure;

[0040] Figure 3 This is a schematic diagram of the precise compressor structure. Detailed Implementation

[0041] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0042] The purpose of this invention is to provide an all-digital in-memory computing device that can improve the energy efficiency and stability of digital in-memory computing architecture.

[0043] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0044] like Figure 1As shown, the present invention provides an all-digital in-memory computing device, comprising: an SRAM WL driver & input activation driver module, an SRAM read / write control module, a memory mode data path module, and multiple computing modules; each computing module includes: an approximate compressor array, a precise compressor array, and a column of SRAM cells; the column of SRAM cells includes: 64 SRAM cells. Each SRAM cell includes: a 6T SRAM structure and an XNOR gate; the 6T SRAM structure is used to store weights; the two inputs of the XNOR gate are the Q-terminal and input excitation of the 6T SRAM, respectively; the output of the XNOR gate is connected to the input of the approximate compressor array.

[0045] The SRAM WL driver & input activation driver module is used to provide word line WL stimuli and input stimuli for SRAM cells, providing different stimuli at different stages;

[0046] The SRAM read / write control module is connected to bit line BL and bit line BLB. The SRAM read / write control module is used to provide bit line BL and bit line BLB drive for SRAM cells when storing data in storage mode.

[0047] Storage-mode data paths are used to provide a path for data interaction with the outside world;

[0048] A column of SRAM cells is connected to an approximate compressor array; the approximate compressor array is connected to a precise compressor array; the approximate compressor array is used for data compression; the precise compressor array is used for further data compression to obtain a result that ignores the most significant carry.

[0049] The approximate compressor array includes: 16 approximate compressors;

[0050] Each approximate compressor is used to compress four 1-bit data segments, producing a 2-bit result.

[0051] like Figure 2 As shown, the approximate compressor includes: transistors P1, P2, P3, P4, N1, N2, N3, N4, inverter I1, inverter I2, NAND gate A1, and a 4-input OR AND gate OA22; transistors P1, P2, P3, and P4 are P-type transistors; transistors N1, N2, N3, and N4 are N-type transistors.

[0052] The gate of transistor P1 is connected to input signal X2, the drain of transistor P1 is connected to input signal X1, and the source of transistor P1 is connected to the sources of transistors P2, N1, and N2, as well as one input terminal of NAND gate A1. The gate of transistor P2 is connected to input signal X1, and the drain of transistor P2 is connected to input signal X2. The gate of transistor P3 is connected to input signal X4, the drain of transistor P3 is connected to input signal X3, and the source of transistor P3 is connected to the sources of transistors P4, N3, and N4, as well as the other input terminal of NAND gate A1. The gate of transistor P4 is connected to input signal X3. Connect the following transistors: the drain of transistor P4 is connected to the input signal X4; the gate of transistor N1 is connected to the output of inverter I1, and the drain of transistor N1 is connected to the input signal X1; the gate of transistor N2 is connected to the input signal X1, and the drain of transistor N2 is connected to the output of inverter I1; the gate of transistor N3 is connected to the output of inverter I2, and the drain of transistor N3 is connected to the input signal X3; the gate of transistor N4 is connected to the input signal X3, and the drain of transistor N4 is connected to the output of inverter I2; the input of inverter I1 is connected to the input signal X2; and the input of inverter I2 is connected to the input signal X4.

[0053] The output of NAND gate A1 outputs the sum bit result S;

[0054] The input terminals of the 4-input OR AND gate OA22 are connected to input signals X1, X2, X3 and X4, and the output terminal of the 4-input OR AND gate OA22 outputs the carry result C.

[0055] The precision compressor array includes four precision compressors.

[0056] like Figure 3 As shown, the precision compressor includes: XOR gate XOR1, XOR gate XOR2, XOR gate XOR3, XOR gate XOR4, XOR gate XOR5, NAND gate NAND1, NAND gate NAND2, NAND gate NAND3, NAND gate NAND4, and a four-input AND gate AND4.

[0057] The inputs of XOR gate XOR1 are A and B, and the output of XOR gate XOR1 is connected to one input of XOR gate XOR3.

[0058] The inputs of the XOR gate XOR2 are C and D, and the output of the XOR gate XOR2 is connected to the other input of the XOR gate XOR3.

[0059] The output of the XOR gate XOR3 is OUT[0];

[0060] The inputs of the XOR gate XOR4 are B and C, and the output of the XOR gate XOR4 is connected to one end of the input of the NAND gate NAND2.

[0061] The inputs of the XOR gate XOR5 are B and D, and the output of the XOR gate XOR5 is connected to one end of the input of the NAND gate NAND3.

[0062] The inputs of NAND gate NAND1 are the output of XOR gate XOR1 and C, and the output of NAND gate NAND1 is connected to one end of the input of NAND gate NAND4.

[0063] The inputs of NAND gate NAND2 are the output of XOR gate XOR4 and D, and the output of NAND gate NAND2 is connected to one end of the input of NAND gate NAND4.

[0064] The inputs of NAND gate NAND3 are the output of XOR gate XOR5 and A, and the output of NAND gate NAND3 is connected to one end of the input of NAND gate NAND4.

[0065] The input of NAND gate NAND4 is the output of NAND gate NAND1, NAND gate NAND2, and NAND gate NAND3, and the output is OUT[1];

[0066] The inputs of the four-input AND gate AND4 are A, B, C and D, and the output of the four-input AND gate AND4 is OUT[2];

[0067] A, B, C, and D are used to receive the carry result C and the sum result S from the approximate compressor output.

[0068] The NAND4 gate is a three-input NAND gate.

[0069] Each column of SRAM cells is equipped with an approximation compressor array, where each approximation compressor array has 16 approximation compressors. Each approximation compressor performs 4 1-bit data compressions to produce a 2-bit result. Since each approximation compressor array has 64 1-bit inputs, it outputs 32 1-bit results.

[0070] The output of the approximate compressor enters the array of precise compressors, where precise compression is performed, ultimately yielding a 6-bit result that ignores the carry-out bit.

[0071] The all-digital in-memory computing device provided by this invention has two operating modes: storage mode and computing mode.

[0072] Storage Mode: The operation process of storage mode is similar to that of traditional SRAM array. Row and column selection is completed through SRAM read and write control. Data in the storage mode data path is written, and then BL and BLB are precharged. Finally, the SRAM cell for reading data is opened through SRAM WL driver. The final read result is output through SRAM read and write control, thus completing a read and write operation.

[0073] Calculation mode: In calculation mode, the weights are first stored in SRAM cells and the weight storage is completed in 64 clock cycles. Then, the input stimulus is sent to the XOR gate and multiplied bit by bit with the weights in SRAM. Finally, the 64 1-bit results are sent to the adder array of each column.

[0074] The adder array is divided into two parts. The first part is an approximate compressor, which compresses every 4 1-bit data into 1 2-bit data, ignoring the carry in the highest bit. The second part is a precise compressor, which uses the most basic full adder for accumulation. Finally, each adder array obtains a 6-bit result, also ignoring the carry in the highest bit.

[0075] The approximate compressor structure is an optimization and improvement of the precise 4-2 compressor, offering higher data compression efficiency by performing approximate calculations based on the original precise results. For the precise 4-2 compressor, the Boolean logic expression is:

[0076] Sum = x1⊕x2⊕x3⊕x4⊕Cin

[0077] Cout=(x1⊕x2)&x3+~(x1⊕x2)&x1

[0078] Carry=(x1⊕x2⊕x3⊕x4)&Cin+~(x1⊕x2⊕x3⊕x4)&x1

[0079] Based on this, the Boolean logic is simplified by ignoring the carry output Cout and carry Cin, and the Sum and Carry are simplified to obtain the following Boolean logic expression:

[0080] C = (x1|x2) & (x3|x4)

[0081] S=~((x1⊕x2)&(x3⊕x4))

[0082] The circuit design is based on this Boolean logic expression. Since the CMOS XOR structure has a large number of transistors, a transmission gate structure is used to implement the XOR function. The truth table of this approximate compressor is shown in Table 1.

[0083] Table 1

[0084]

[0085]

[0086] As can be seen from Table 1, this approximation calculation only fails in four cases, thus achieving a high accuracy rate and significantly accelerating data compression.

[0087] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0088] This document uses specific examples to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. Furthermore, those skilled in the art will recognize that, based on the ideas of the present invention, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A fully digital in-memory computing device, characterized in that, include: The module includes an SRAMWL driver and input activation driver module, an SRAM read / write control module, a storage mode data path module, and multiple computing modules. Each computing module includes: an approximate compressor array, an exact compressor array, and a row of SRAM cells; The SRAMWL driver & input activation driver module is used to provide word line WL stimulation and input stimulation for SRAM cells, providing different stimuli at different stages; The SRAM read / write control module is connected to bit line BL and bit line BLB. The SRAM read / write control module is used to provide bit line BL and bit line BLB drive for SRAM cells when storing data in storage mode. Storage-mode data paths are used to provide a path for data interaction with the outside world; A column of SRAM cells is connected to an approximate compressor array; the approximate compressor array is connected to a precise compressor array; the approximate compressor array is used for data compression; the precise compressor array is used for further data compression to obtain a result that ignores the most significant carry.

2. The all-digital in-memory computing device according to claim 1, characterized in that, The column of SRAM cells includes 64 SRAM cells.

3. The all-digital in-memory computing device according to claim 2, characterized in that, The SRAM cell includes: a 6TSRAM structure and an XOR gate; A 6TSRAM structure is used to store weights; The two inputs of the XNOR gate are the Q terminal and input excitation of the 6TSRAM, respectively; the output of the XNOR gate is connected to the input of the approximate compressor array.

4. The all-digital in-memory computing device according to claim 1, characterized in that, The approximate compressor array includes: 16 approximate compressors; Each approximate compressor is used to compress four 1-bit data segments, producing a 2-bit result.

5. The all-digital in-memory computing device according to claim 4, characterized in that, The approximate compressor includes: tubes P1, P2, P3, P4, N1, N2, N3, N4, inverter I1, inverter I2, NAND gate A1, and 4-input OR AND gate OA22. The gate of transistor P1 is connected to input signal X2, the drain of transistor P1 is connected to input signal X1, and the source of transistor P1 is connected to the sources of transistors P2, N1, and N2, as well as one input terminal of NAND gate A1. The gate of transistor P2 is connected to input signal X1, and the drain of transistor P2 is connected to input signal X2. The gate of transistor P3 is connected to input signal X4, the drain of transistor P3 is connected to input signal X3, and the source of transistor P3 is connected to the sources of transistors P4, N3, and N4, as well as the other input terminal of NAND gate A1. The gate of transistor P4 is connected to input signal X3. Connect the following transistors: the drain of transistor P4 is connected to the input signal X4; the gate of transistor N1 is connected to the output of inverter I1, and the drain of transistor N1 is connected to the input signal X1; the gate of transistor N2 is connected to the input signal X1, and the drain of transistor N2 is connected to the output of inverter I1; the gate of transistor N3 is connected to the output of inverter I2, and the drain of transistor N3 is connected to the input signal X3; the gate of transistor N4 is connected to the input signal X3, and the drain of transistor N4 is connected to the output of inverter I2; the input of inverter I1 is connected to the input signal X2; and the input of inverter I2 is connected to the input signal X4. The output of NAND gate A1 outputs the sum bit result S; The input terminals of the 4-input OR AND gate OA22 are connected to input signals X1, X2, X3 and X4, and the output terminal of the 4-input OR AND gate OA22 outputs the carry result C.

6. The all-digital in-memory computing device according to claim 5, characterized in that, The precision compressor array includes four precision compressors.

7. The all-digital in-memory computing device according to claim 6, characterized in that, The precision compressor includes: XOR gate XOR1, XOR gate XOR2, XOR gate XOR3, XOR gate XOR4, XOR gate XOR5, NAND gate NAND1, NAND gate NAND2, NAND gate NAND3, NAND gate NAND4, and a four-input AND gate AND4. The inputs of XOR gate XOR1 are A and B, and the output of XOR gate XOR1 is connected to one input of XOR gate XOR3. The inputs of the XOR gate XOR2 are C and D, and the output of the XOR gate XOR2 is connected to the other input of the XOR gate XOR3. The output of the XOR gate XOR3 is OUT[0]; The inputs of the XOR gate XOR4 are B and C, and the output of the XOR gate XOR4 is connected to one end of the input of the NAND gate NAND2. The inputs of the XOR gate XOR5 are B and D, and the output of the XOR gate XOR5 is connected to one end of the input of the NAND gate NAND3. The inputs of NAND gate NAND1 are the output of XOR gate XOR1 and C, and the output of NAND gate NAND1 is connected to one end of the input of NAND gate NAND4. The inputs of NAND gate NAND2 are the output of XOR gate XOR4 and D, and the output of NAND gate NAND2 is connected to one end of the input of NAND gate NAND4. The inputs of NAND gate NAND3 are the output of XOR gate XOR5 and A, and the output of NAND gate NAND3 is connected to one end of the input of NAND gate NAND4. The input of NAND gate NAND4 is the output of NAND gate NAND1, NAND gate NAND2, and NAND gate NAND3, and the output is OUT[1]; The inputs of the four-input AND gate AND4 are A, B, C and D, and the output of the four-input AND gate AND4 is OUT[2]; A, B, C, and D are used to receive the carry result C and the sum result S from the approximate compressor output.

8. The all-digital in-memory computing device according to claim 7, characterized in that, The NAND4 gate is a three-input NAND gate.

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