Switching control circuit, chip and electronic device

Abstract

The present disclosure provides a switch control circuit, a chip and an electronic device, wherein the switch control circuit comprises a first transistor, a second transistor, a third transistor, an enable logic circuit, a first control circuit, a second control circuit, a slope control circuit and a feedback control circuit, the control electrode of the first transistor is controlled by the first control circuit, the first control circuit controls the opening and closing of the first transistor; the control electrode of the second transistor is controlled by the second control circuit, the second control circuit controls the opening and closing of the second transistor; the control electrode of the third transistor is controlled by the slope control circuit, the slope control circuit controls the rising slope of the AVDD voltage by setting the capacitance value of the capacitor array; the enable logic circuit controls the opening and closing of the first control circuit, the second control circuit and the slope control circuit according to the enable signal and the feedback signal.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, specifically to a switch control circuit, chip, and electronic device. Background Technology

[0002] efuse is usually an IP provided by chip manufacturers. It is a non-volatile, one-time programmable memory. To improve the security factor of chip design and the yield of chip mass production testing, chips awaiting production will embed efuse IP.

[0003] During the programming phase, the AVDD pin of efuse draws a significant current. In some applications, the AVDD pin needs to reuse a pin of the chip to be manufactured, requiring an external independent power supply for control. To reduce overall chip power consumption and avoid impacting other chip functions when reusing pins, a switch and its control circuitry need to be added between the AVDD pin and the external power supply. Furthermore, to protect the efuse IP, the rise rate of the AVDD voltage cannot be too large; the added switch control circuitry must ensure that the rise rate of the AVDD voltage is controllable.

[0004] However, the switching control circuits in related technologies have difficulty controlling the rising slope of the AVDD voltage, which may cause the efuse IP to fail. Summary of the Invention

[0005] The main objective of this disclosure is to provide a switch control circuit, chip, and electronic device to solve the problem in the related art where the switch control circuit has difficulty controlling the rise slope of the AVDD voltage, which may cause the efuse IP to fail.

[0006] To achieve the above objectives, a first aspect of this disclosure provides a switch control circuit, comprising: a first transistor, a second transistor, a third transistor, an enable logic circuit, a first control circuit, a second control circuit, a slope control circuit, and a feedback control circuit, wherein:

[0007] The first transistor's first terminal is coupled to the input voltage terminal, the second terminal of the first transistor is coupled to the AVDD terminal of the efuse, and the control terminal of the first transistor is controlled by the first control circuit, which is configured to control the first transistor's on and off states.

[0008] The first terminal of the second transistor is coupled to the input voltage terminal, the second terminal of the second transistor is coupled to the second terminal of the third transistor, and the first terminal of the third transistor is coupled to the AVDD terminal and the input terminal of the feedback control circuit. The feedback control circuit is configured to output a feedback signal to the enable logic circuit via the output terminal.

[0009] The control electrode of the second transistor is controlled by a second control circuit, which is configured to control the turning on and off of the second transistor.

[0010] The control electrode of the third transistor is controlled by a slope control circuit, which is configured to control the turning on and off of the third transistor and control the rising slope of the AVDD voltage by setting the capacitance value of the capacitor array in the slope control circuit, wherein the AVDD voltage is the voltage at the AVDD terminal.

[0011] The enable logic circuit is configured to control the opening and closing of the first control circuit, the second control circuit, and the slope control circuit based on the input enable signal and the feedback signal.

[0012] Optionally, the switch control circuit further includes a first resistor and a first capacitor, wherein the first resistor and the first capacitor are connected in parallel, and the first end of the parallel connection is coupled to the AVDD terminal.

[0013] The input voltage terminal, the first transistor, and the AVDD terminal constitute the main path. The first control circuit is configured to control the conduction and cutoff of the main path by controlling the opening and closing of the first transistor.

[0014] The input voltage terminal, the second transistor, the third transistor, and the AVDD terminal constitute a secondary path. The second control circuit is configured to control the conduction and cutoff of the secondary path by controlling the opening and closing of the second transistor.

[0015] The enabling logic circuit is also configured to control the opening and closing of the main path and the secondary path by controlling the opening and closing of the first control circuit and the second control circuit.

[0016] Optionally, the enable logic circuit includes a first delay, a second delay, a first AND gate, a first inverter, and a second AND gate;

[0017] The input terminal of the first delay is coupled to the enable signal terminal, and the output terminal of the first delay is coupled to the first input terminal of the first AND gate, wherein the enable signal is input via the enable signal terminal;

[0018] The input terminal of the second delay is coupled to the output terminal of the feedback control circuit, and the output terminal of the second delay is coupled to the second input terminal of the first AND gate and the input terminal of the first inverter, respectively.

[0019] The first AND gate is configured to output a first switch enable signal from its output to the first control circuit.

[0020] The first input of the second AND gate is coupled to the output of the first inverter, and the second input of the second AND gate is coupled to the enable signal terminal. The second AND gate is configured to output a second switch enable signal from the output to the second control circuit.

[0021] Optionally, the first control circuit includes a fourth transistor, a second resistor, a second inverter, a fifth transistor, and a third resistor;

[0022] The enable logic circuit is also configured to output a first switch enable signal from the first output terminal to the control terminal of the fourth transistor and the input terminal of the second inverter, respectively.

[0023] The first terminal of the fourth transistor is grounded, and the second terminal of the fourth transistor is coupled to the control terminal of the first transistor and the first terminal of the second resistor, respectively. The second terminal of the second resistor is coupled to the first terminal of the first transistor.

[0024] The output of the second inverter is coupled to the control terminal of the fifth transistor. The first terminal of the fifth transistor is grounded. The second terminal of the fifth transistor is coupled to the first terminal of the third resistor. The second terminal of the third resistor is coupled to the second terminal of the first fourth transistor.

[0025] Optionally, the second control circuit includes a sixth transistor and a fourth resistor;

[0026] The enable logic circuit is also configured to output a second switch enable signal from the second output terminal to the control electrode of the sixth transistor;

[0027] The first terminal of the sixth transistor is grounded, and the second terminal of the sixth transistor is coupled to the control terminal of the second transistor and the first terminal of the fourth resistor, respectively. The second terminal of the fourth resistor is coupled to the first terminal of the second transistor.

[0028] Optionally, the slope control circuit includes a current source, a first control switch, a third inverter, a capacitor array, and a second control switch;

[0029] The enable logic circuit is also configured to output a second switch enable signal from the second output terminal to the input terminals of the first control switch and the third inverter, respectively, to control the opening and closing of the first control switch, and to control the opening and closing of the second control switch via the output terminal of the third inverter.

[0030] The first terminal of the first control switch is coupled to the second terminal of the second transistor and the second terminal of the third transistor, respectively; the second terminal of the first control switch is coupled to the first terminal of the current source.

[0031] The first terminal of the second control switch is coupled to the second terminal of the current source, and the second terminal of the second control switch is coupled to the second terminal of the capacitor array and the ground terminal respectively.

[0032] The first end of the capacitor array is coupled to the control electrode of the third transistor and the second end of the current source, respectively. The capacitor array is configured to be controlled by an external digital control signal. The capacitance value is set according to the binary coded digital provided by the external digital control signal, and the rising slope of the AVDD voltage is controlled based on the capacitance value before the programming and burning stage of efuse.

[0033] The current source is configured to charge the configured capacitor array.

[0034] Furthermore, the number of bits in the binary encoded digit provided by the external digital control signal is N, where N is an integer greater than 1;

[0035] The capacitor array includes N second capacitors and N corresponding third control switches. Each second capacitor and its corresponding third control switch are connected in series to form a capacitor-switch group, and the N capacitor-switch groups are connected in parallel to form a capacitor array.

[0036] The first terminal of each capacitor-switch group is coupled to the control electrode of the third transistor and the second terminal of the current source, respectively, and the second terminal of each capacitor-switch group is grounded.

[0037] Optionally, the feedback control circuit includes a first voltage divider resistor, a second voltage divider resistor, a voltage comparator, a fourth control switch, and a power supply;

[0038] The enable logic circuit is also configured to output a second switch enable signal from the second output terminal to the input terminal of the third inverter, and control the opening and closing of the fourth control switch via the output terminal of the third inverter.

[0039] The first terminal of the fourth control switch is coupled to the inverting terminal of the voltage comparator and the positive terminal of the power supply, respectively. The second terminal of the fourth control switch is coupled to the negative terminal of the power supply and the ground terminal, respectively. The power supply is configured to provide a reference voltage to the inverting terminal of the voltage comparator.

[0040] The first end of the first voltage divider resistor is coupled to the first terminal of the third transistor and the AVDD terminal, respectively. The second end of the first voltage divider resistor is coupled to the non-inverting terminal of the voltage comparator and the first end of the second voltage divider resistor, respectively. The second end of the second voltage divider resistor is grounded.

[0041] The voltage comparator is configured to output a feedback signal from its output to the enable logic circuit, which controls the first and second switch enable signals output by the enable logic circuit.

[0042] Furthermore, the feedback control circuit also includes OR gates and timers;

[0043] The first input of the OR gate is coupled to the output of the third inverter;

[0044] The first terminal of the timer is coupled to the output terminal of the voltage comparator, and the second terminal of the timer is coupled to the second input terminal of the OR gate. The timer is configured to control the fourth control switch to be closed to open the main path when the enable signal is valid and the main path is not opened within a preset time.

[0045] A second aspect of this disclosure provides a chip including a switching control circuit according to any one of the first aspects.

[0046] A third aspect of this disclosure provides an electronic device including the chip of the second aspect.

[0047] The switching control circuit provided in this embodiment includes a first transistor, a second transistor, a third transistor, an enable logic circuit, a first control circuit, a second control circuit, a slope control circuit, and a feedback control circuit. The control electrode of the third transistor is controlled by the slope control circuit, which is configured to control the rising slope of the AVDD voltage by setting the capacitance value of the capacitor array in the slope control circuit. The AVDD voltage is the voltage at the AVDD terminal. By controlling the rising slope of the AVDD voltage by setting the capacitance value of the capacitor array, the slope control circuit solves the problem in related technologies where the switching control circuit has difficulty controlling the rising slope of the AVDD voltage, potentially causing the efuse IP to fail. Attached Figure Description

[0048] To more clearly illustrate the technical solutions in the specific embodiments of this disclosure or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0049] Figure 1 This is a connection diagram of the embedded efuse IP in the chip to be manufactured;

[0050] Figure 2 This is an exemplary circuit diagram of a switch control circuit in the related art;

[0051] Figure 3 An exemplary circuit architecture diagram of the switch control circuit provided in the embodiments of this disclosure;

[0052] Figure 4 An exemplary circuit diagram of a switch control circuit provided in an embodiment of this disclosure;

[0053] Figure 5 Simulation diagram of an instance application of the switch control circuit provided in the embodiments of this disclosure;

[0054] Figure 6 An exemplary circuit diagram of a feedback control circuit provided in an embodiment of this disclosure. Detailed Implementation

[0055] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are also within the scope of protection of this disclosure.

[0056] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this subject matter pertains. It will be further understood that terms such as those defined in commonly used dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the specification and in the relevant art, and shall not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, the statement of “connecting” or “coupling” two or more parts together shall mean that these parts are directly joined together or joined through one or more intermediate components.

[0057] In all embodiments of this disclosure, since the source and drain of a metal-oxide-semiconductor (MOS) transistor are symmetrical, and the conduction current directions between the source and drain of an N-type transistor and a P-type transistor are opposite, the controlled middle terminal of the MOS transistor is referred to as the control terminal, and the remaining two terminals of the MOS transistor are referred to as the first terminal and the second terminal, respectively. The transistors used in the embodiments of this disclosure are primarily switching transistors. Furthermore, for the sake of consistency, in this context, the base of a bipolar junction transistor (BJT) is referred to as the control terminal, the emitter of the BJT as the first terminal, and the collector of the BJT as the second terminal. Additionally, terms such as "first" and "second" are used only to distinguish one component (or part of a component) from another component (or another part of a component).

[0058] efuse is usually an IP provided by chip manufacturers. It is a non-volatile, one-time programmable memory. To improve the security factor of chip design and the yield of chip mass production testing, chips awaiting production will embed efuse IP.

[0059] Figure 1The diagram illustrates the connection of the embedded efuse IP in the chip to be manufactured. The efuse IP communicates with the internal digital control circuitry of the chip to achieve read / write functionality. efuse typically has two power supplies: a DVDD logic power supply and an AVDD programming power supply. DVDD powers the digital portion of the circuit, while AVDD powers the analog portion. During the programming phase, the AVDD pin of the efuse draws a significant current. In some applications, the AVDD pin needs to reuse a pin of the chip to be manufactured, controlled by an external independent power supply, VCC_ext.

[0060] To reduce overall chip power consumption and avoid impacting other chip functions when reusing pins, a switch and control circuitry for this switch need to be added between the AVDD pin and the external independent power supply VCC_ext; for example... Figure 1 The switch control circuit shown is controlled by the avdd_en signal, which in turn controls the SW0 switch. During the efuse read and idle phases, the AVDD power supply is turned off, and before the programming phase begins, the AVDD power supply is turned on. Furthermore, to protect the efuse IP, the AVDD voltage rise rate cannot be too large; therefore, the added switch control circuit needs to make the AVDD voltage rise rate controllable.

[0061] However, the switching control circuits in related technologies have difficulty controlling the rising slope of the AVDD voltage, which may cause the efuse IP to fail. Figure 2 An exemplary circuit diagram of a switch control circuit in the related art is shown. The power transistor Mp0 acts as an SW0 switch, and its on-resistance needs to meet the following requirements:

[0062] Ron_Mp0<(VCC_ext-AVDD) / Imax.

[0063] When avdd_en = 0, Mn0 is off. The current flowing through R0 from the external power supply VCC_ext is very small, causing the switching transistor Mp0 to be off. At the same time, transistor Mn1 is on, providing a path for AVDD to discharge to ground. In this case, the external power supply VCC_ext cannot transfer power to AVDD, and AVDD = 0V. When avdd_en = 1, Mn0 is on. If the on-resistance Ron_Mp0 of Mn0 is much smaller than R0, that is, the gate voltage of Mp0 is approximately 0V, Mp0 is on. At the same time, transistor Mn1 is off, and the external power supply VCC_ext can connect to AVDD, thereby transferring energy.

[0064] R2 serves as the input resistor for the simulated efuse. Before programming, efuse is in an idle state, so R2 is relatively large; during programming, efuse is in the programming stage, so R2 is relatively small. C0 is a filter capacitor. As can be seen, due to the limitation of the AVDD voltage transmission requirement, the on-resistance Ron_Mp0 of Mp0 is small. C0 needs a relatively large value to form a large time constant, thereby making the rise slope of AVDD smaller during startup.

[0065] The switching control circuits in related technologies have the following drawbacks: if AVDD needs to meet a certain rising slope requirement, a relatively large filter capacitor C0 needs to be placed at the output; and the starting rising slope of the voltage AVDD is uncontrollable.

[0066] To address the problem in related technologies where the switch control circuit struggles to control the rise rate of the AVDD voltage, potentially causing the efuse IP to fail, this disclosure provides a switch control circuit. An exemplary circuit architecture diagram of this switch control circuit is shown below. Figure 3 As shown, it includes:

[0067] The circuit comprises a first transistor M1, a second transistor M2, a third transistor M3, an enable logic circuit, a first control circuit, a second control circuit, a slope control circuit, and a feedback control circuit, wherein:

[0068] The first terminal of the first transistor M1 is coupled to the input voltage terminal, the second terminal of the first transistor M1 is coupled to the AVDD terminal of the efuse, and the control terminal of the first transistor M1 is controlled by the first control circuit, which is configured to control the opening and closing of the first transistor M1; the first transistor M1 is a P-type transistor.

[0069] The first terminal of the second transistor M2 is coupled to the input voltage terminal, and the second terminal of the second transistor M2 is coupled to the second terminal of the third transistor M3. The first terminal of the third transistor M3 is coupled to the AVDD terminal and the input terminal of the feedback control circuit, respectively. The feedback control circuit is configured to output a feedback signal to the enable logic circuit via the output terminal. The second transistor M2 is a P-type transistor.

[0070] The control electrode of the second transistor M2 is controlled by the second control circuit, which is configured to control the turning on and off of the second transistor M2.

[0071] The gate of the third transistor M3 is controlled by a slope control circuit, which is configured to control the opening and closing of the third transistor M3 and control the rising slope of the AVDD voltage by setting the capacitance value of the capacitor array CDAC in the slope control circuit. Here, the AVDD voltage is the voltage at the AVDD terminal; the third transistor M3 is an N-type transistor.

[0072] The enable logic circuit is configured to control the opening and closing of the first control circuit, the second control circuit, and the slope control circuit based on the input enable signal and the feedback signal.

[0073] In a preferred embodiment of this disclosure, an exemplary circuit diagram of the switch control circuit is shown below. Figure 4 As shown. The switch control circuit also includes a first resistor R1 and a first capacitor C1, wherein the first resistor R1 and the first capacitor C1 are connected in parallel, and the first end of the parallel connection is coupled to the AVDD terminal; the second end of the parallel connection of the first resistor R1 and the first capacitor C1 is grounded. Furthermore, this disclosure controls the rising slope of the AVDD voltage through a slope control circuit. Compared with the technical solutions in related technologies, it does not require a large filter capacitor, and the first capacitor C1 is relatively small.

[0074] The input voltage terminal, the first transistor M1, and the AVDD terminal constitute the main path. The first control circuit is configured to control the conduction and cutoff of the main path by controlling the opening and closing of the first transistor M1.

[0075] The input voltage terminal, the second transistor M2, the third transistor M3, and the AVDD terminal constitute the secondary path. The second control circuit is configured to control the conduction and cutoff of the secondary path by controlling the opening and closing of the second transistor M2.

[0076] The enabling logic circuit is also configured to control the opening and closing of the main path and the secondary path by controlling the opening and closing of the first control circuit and the second control circuit.

[0077] This disclosure uses two sets of parallel switching transistor paths, including a main path and a secondary path. The main path consists of a large power transistor, M1, connected in series, with its gate controlled by a first control circuit. The secondary path is formed by two smaller power transistors, M2 and M3, connected in series. M2 is controlled by a second control circuit, and M3 is controlled by a slope control circuit. A feedback control circuit is also added to determine which path (main or secondary) is activated. Upon startup, the enable signal avdd_en is 1, activating the secondary path. The AVDD voltage gradually rises, reaching its final value Vm, at which point the enable logic circuit activates the main path and deactivates the secondary path.

[0078] The secondary path is configured to control the rise rate of the AVDD voltage before the efuse program is enabled. The second control circuit controls the second transistor M2, determining the conduction and cutoff of the secondary path; the slope control circuit adjusts the rise rate of the AVDD voltage by controlling the third transistor M3.

[0079] An exemplary circuit diagram of the switch control circuit provided in this disclosure is shown below. Figure 4As shown. The gates of the first transistor M1 in the main path and the second transistor M2 in the secondary path employ an open-drain control structure, which refers to a circuit structure where the output is from the drain of the transistor. A third transistor M3 is connected in series in the secondary path, and the gate of the third transistor M3 is connected to a slope control circuit.

[0080] exist Figure 4 In this circuit, the enable logic circuit includes a first delay1, a second delay2, a first AND gate, a first inverter, and a second AND gate; the enable logic circuit of the preceding stage is configured to select the path to be enabled from the main path and the secondary path.

[0081] The input terminal of the first delay unit delay1 is coupled to the enable signal terminal, and the output terminal of the first delay unit delay1 is coupled to the first input terminal of the first AND gate, wherein the enable signal is input through the enable signal terminal;

[0082] The input of the second delay 2 is coupled to the output of the feedback control circuit, and the output of the second delay 2 is coupled to the second input of the first AND gate and the input of the first inverter, respectively.

[0083] The first AND gate is configured to output a first switch enable signal from its output to the first control circuit.

[0084] The first input of the second AND gate is coupled to the output of the first inverter, and the second input of the second AND gate is coupled to the enable signal terminal. The second AND gate is configured to output a second switch enable signal from the output to the second control circuit.

[0085] exist Figure 4 In the first control circuit, there are a fourth transistor M4, a second resistor R2, a second inverter, a fifth transistor M5, and a third resistor R3; wherein, the fourth transistor M4 is an N-type transistor, and the fifth transistor M5 is an N-type transistor.

[0086] The enable logic circuit is also configured to output a first switch enable signal AVDDH_EN from the first output terminal to the control terminal of the fourth transistor M4 and the input terminal of the second inverter, respectively.

[0087] The first terminal of the fourth transistor M4 is grounded, and the second terminal of the fourth transistor M4 is coupled to the control terminal of the first transistor M1 and the first terminal of the second resistor R2. The second terminal of the second resistor R2 is coupled to the first terminal of the first transistor M1.

[0088] The output of the second inverter is coupled to the control terminal of the fifth transistor M5. The first terminal of the fifth transistor M5 is grounded. The second terminal of the fifth transistor M5 is coupled to the first terminal of the third resistor R3. The second terminal of the third resistor R3 is coupled to the second terminal of the first transistor.

[0089] exist Figure 4 In the second control circuit, there are a sixth transistor M6 and a fourth resistor R4; wherein, the sixth transistor M6 is an N-type transistor;

[0090] The enable logic circuit is also configured to output a second switch enable signal AVDDL_EN from the second output terminal to the control electrode of the sixth transistor M6;

[0091] The first terminal of the sixth transistor M6 is grounded, and the second terminal of the sixth transistor M6 is coupled to the control terminal of the second transistor M2 and the first terminal of the fourth resistor R4. The second terminal of the fourth resistor R4 is coupled to the first terminal of the second transistor M2.

[0092] exist Figure 4 In the circuit, the slope control circuit includes a current source Ibias, a first control switch SW1, a third inverter, a capacitor array CDAC, and a second control switch SW2; the slope control circuit is composed of the current source Ibias and its corresponding first control switch SW1, and the capacitor array CDAC and its corresponding second control switch SW2.

[0093] The enable logic circuit is also configured to output a second switch enable signal AVDDL_EN from the second output terminal to the first control switch SW1 and the input terminal of the third inverter, respectively, to control the opening and closing of the first control switch SW1, and to control the opening and closing of the second control switch SW2 via the output terminal of the third inverter.

[0094] The first terminal of the first control switch SW1 is coupled to the second terminal of the second transistor M2 and the second terminal of the third transistor M3 respectively, and the second terminal of the first control switch SW1 is coupled to the first terminal of the current source Ibias.

[0095] The first terminal of the second control switch SW2 is coupled to the second terminal of the current source Ibias, and the second terminal of the second control switch SW2 is coupled to the second terminal of the capacitor array CDAC and the ground terminal, respectively.

[0096] The first terminal of the capacitor array CDAC is coupled to the control electrode of the third transistor M3 and the second terminal of the current source Ibias, respectively. The capacitor array CDAC is configured to be controlled by an external digital control signal. The capacitor value is set according to the binary coded digital provided by the external digital control signal, and the rising slope of the AVDD voltage is controlled based on the capacitor value before the programming and burning stage of efuse.

[0097] The current source Ibias is configured to charge the configured capacitor array CDAC.

[0098] The slope control circuit controls the rising slope of the AVDD voltage by controlling the switching on and off of the third transistor, thus solving the problem in related technologies where the switching control circuit has difficulty controlling the rising slope of the AVDD voltage, which may cause the efuse IP to fail.

[0099] In a preferred embodiment of this disclosure, the number of bits in the binary encoded number provided by the external digital control signal is N, where N is an integer greater than 1;

[0100] The capacitor array CDAC includes N second capacitors and N corresponding third control switches SW3. Each second capacitor and its corresponding third control switch SW3 are connected in series to form a capacitor-switch group, and the N capacitor-switch groups are connected in parallel to form the capacitor array CDAC.

[0101] The first terminal of each capacitor-switch group is coupled to the control electrode of the third transistor M3 and the second terminal of the current source Ibias, respectively, and the second terminal of each capacitor-switch group is grounded.

[0102] exist Figure 4 In the middle, the feedback control circuit includes a first voltage divider resistor Rf1, a second voltage divider resistor Rf2, a voltage comparator CMP, a fourth control switch SW4, and a power supply; the feedback control circuit is implemented by the series of resistors Rf1 and Rf2, the reference voltage VREF, and the voltage comparator CMP;

[0103] The enable logic circuit is also configured to output a second switch enable signal AVDDL_EN from the second output terminal to the input terminal of the third inverter, and control the opening and closing of the fourth control switch SW4 via the output terminal of the third inverter.

[0104] The first terminal of the fourth control switch SW4 is coupled to the inverting terminal of the voltage comparator CMP and the positive terminal of the power supply, respectively. The second terminal of the fourth control switch SW4 is coupled to the negative terminal of the power supply and the ground terminal, respectively. The power supply is configured to provide a reference voltage to the inverting terminal of the voltage comparator CMP.

[0105] The first terminal of the first voltage divider resistor Rf1 is coupled to the first terminal of the third transistor M3 and the AVDD terminal, respectively. The second terminal of the first voltage divider resistor Rf1 is coupled to the non-inverting terminal of the voltage comparator CMP and the first terminal of the second voltage divider resistor Rf2, respectively. The second terminal of the second voltage divider resistor Rf2 is grounded.

[0106] The voltage comparator CMP is configured to output a feedback signal from its output to the enable logic circuit, controlling the output of the first switch enable signal AVDDH_EN and the second switch enable signal AVDDL_EN from the enable logic circuit.

[0107] The following is an explanation Figure 4 The working principle of the exemplary circuit diagram of the switch control circuit shown.

[0108] When the secondary path is enabled, the slope control circuit starts working, controlled by the external digital control signal code. <n:0>Provide the setting code, external digital control signal code <n:0>The more binary coded numbers there are, the more capacitors are needed, and the longer the charging time. A fixed tail current Ibias charges the pre-set capacitor array CDAC. The gate voltage VGn of the third transistor M3 increases linearly with charging. At this time, the voltage AVDD = VGn - Vthn also increases linearly, where Vthn is the threshold voltage of the third transistor M3. The slope of the gate voltage VGn of the third transistor M3 is:

[0109] Rate = Ibias / Cs,

[0110] Where Ibias is the fixed tail current and Cs is the capacitance value set by the encoding:

[0111] Cs = code <n:0>*Cunit,

[0112] Where Cunit is the unit capacitance value of the capacitor array CDAC, and is also determined by... Figure 4 The final charging value Vm can be obtained as follows:

[0113] Vm=VREF(Rf1+Rf2) / Rf2=K*VREF,

[0114] When AVDD > Vm, the voltage comparator CMP outputs VCOMP = 1. After passing through the enable logic circuit, the VCOMP signal outputs the second switch enable signal AVDDL_EN to close the secondary path and the slope control circuit. Simultaneously, SW1 = 1 discharges the charge on CDAC, SW2 = 1 sets the inverting input of the comparator CMP to 0, and outputs the first switch enable signal AVDDH_EN to open the main path. Energy transfer then begins to be taken over by the high-power transistor M1. The final charging value Vm is the switching threshold. When the voltage AVDD rises to the final charging value Vm, the main path is open and the secondary path is closed.

[0115] As can be seen from the circuit, since the source of the fixed tail current Ibias is close to the input voltage VCC_ext, assuming the current flowing through the third transistor M3 is very small, the maximum value of the final charging value Vm is set to approximately VCC_ext - vthn. Therefore, choosing a third transistor M3 with a low threshold voltage helps to obtain a larger final charging value Vm. For example, choosing a Native Nmos with a threshold voltage close to zero as the third transistor M3 is preferable. Assuming the calculation error caused by vthn is negligible, and the current flowing through the secondary path is relatively small during the preparation stage before burning the efuse, the gate voltage of the third transistor M3 can be estimated as VGn ≈ AVDD. When the final charging value is reached, VGn ≈ Vm. Combining the above formulas, the rise time t_rise of AVDD can be obtained as:

[0116] t_rise=Vm / Rate=K*VREF*code <n:0>*Cunit / Ibias,

[0117] Among them, the configurable encoding code <n:0>The rising slope of voltage AVDD is determined by the adjustable resistor voltage divider coefficient K, which determines the final charging value of voltage AVDD. When voltage AVDD reaches the final charging value Vm, the main path opens, the secondary path closes, and voltage AVDD jumps to the input voltage VCC_ext, i.e., AVDD = VCC_ext.

[0118] Based on the above embodiments, this disclosure provides an instantiated application simulation of a switch control circuit, with the following parameters:

[0119] VCC_ext=5V, Ron_M1=5.3ohm, Ron_M2=1Kohm, Ron_M3=1.3Kohm, Ibias=1uA, Cs=3pF, VREF=2V, Rf1=Rf2=50Kohm;

[0120] Simulation can yield results Figure 5 The simulation diagram of the instantiated application of the switch control circuit shown is based on... Figure 5 The rise time of AVDD for this instance can be calculated as follows:

[0121] t_rise=K*VREF*Cs / Ibias=2*2V*3pF / 1uA=12us;

[0122] As can be seen from the simulation diagram, the rise time of voltage AVDD (13.9846µs) is slightly larger than the theoretically calculated value of 12µs. This is because when voltage AVDD reaches the set final voltage value Vm, the enable logic circuit uses the second delay unit delay2 to delay the output signal VCOMP of voltage comparator CMP by 2µs. This delay is set to prevent erroneous toggling of COMP. Users can set different encoding values. <n:0>This allows for different voltage rise slopes. Furthermore, different final voltage values ​​Vm can be set using the reference voltage VREF, the first voltage divider resistor Rf1, and the second voltage divider resistor Rf2 to meet the different programming power supply voltage requirements of the efuse IP. By combining the final voltage value and the voltage rise slope, the rise time of voltage AVDD can be estimated, thus providing timing constraints for the communication protocol design between the digital control circuitry in the chip and efuse.

[0123] In a preferred embodiment of this disclosure, the feedback control circuit further includes an OR gate and a timer;

[0124] The first input of the OR gate is coupled to the output of the third inverter;

[0125] The first terminal of the timer is coupled to the output of the voltage comparator CMP, and the second terminal of the timer is coupled to the second input of the OR gate. The timer is configured to control the fourth control switch SW4 to be closed to open the main path when the enable signal is valid and the main path is not open within a preset duration. The preset duration is N times the rise time t_rise of AVDD, for example, it can be 3 times or 4 times the rise time t_rise of AVDD.

[0126] Figure 6 An exemplary circuit diagram of a feedback control circuit provided in an embodiment of this disclosure is shown. In this feedback control circuit, to improve the reliability of the circuit application, the output signal VCOMP of the CMP can be connected to the digital control module for timing operation. An OR gate is added after the second switch enable signal AVDDL_EN, and the timing result is output to the second input terminal of the OR gate, as shown below. Figure 6 As shown, when avdd_en=1, if VCOMP fails to flip within the preset time, the fourth control switch SW4=1 can be forcibly set to open the main path, thereby reducing the risk that the main path is not opened when efuse enters the burning stage.

[0127] This disclosure also provides a chip that includes a switch control circuit according to an embodiment of this disclosure. The chip may be a chip with embedded efuse IP.

[0128] This disclosure also provides an electronic device that includes a chip according to embodiments of this disclosure, and the electronic device may be a programming device.

[0129] As can be seen from the above description, this disclosure achieves the following technical effects:

[0130] The slope control circuit disclosed herein controls the rising slope of the AVDD voltage by setting the capacitance value of the capacitor array CDAC, thereby adjusting the rising slope of the AVDD voltage. This solves the problem in related technologies where the switch control circuit has difficulty controlling the rising slope of the AVDD voltage, which may cause the efuse IP to fail.

[0131] Furthermore, the secondary path disclosed herein can control the rise rate of the AVDD voltage before the efuse is enabled for programming. The second control circuit controls the second transistor M2, which determines the conduction and cutoff of the secondary path.

[0132] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatuses and methods according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0133] Unless otherwise expressly indicated by the context, the singular form of words used herein and in the appended claims includes the plural form, and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the terms "comprising" and "including" shall be interpreted as including rather than exclusively. Likewise, the terms "comprising" and "or" shall be interpreted as including unless such interpretation is expressly prohibited herein. Where the term "example" is used herein, particularly when it follows a set of terms, the "example" is merely exemplary and illustrative and should not be considered exclusive or extensive.

[0134] Further aspects and scope will become apparent from the description provided herein. It should be understood that various aspects of this application may be implemented individually or in combination with one or more other aspects. It should also be understood that the description and specific embodiments herein are for illustrative purposes only and are not intended to limit the scope of this application.

[0135] Although embodiments of the present disclosure have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the present disclosure, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A switch control circuit, characterized in that, include: The circuit comprises a first transistor, a second transistor, a third transistor, an enable logic circuit, a first control circuit, a second control circuit, a slope control circuit, and a feedback control circuit, wherein: The first terminal of the first transistor is coupled to the input voltage terminal, the second terminal of the first transistor is coupled to the AVDD terminal of the efuse, and the control terminal of the first transistor is controlled by the first control circuit, which is configured to control the turning on and off of the first transistor. The first terminal of the second transistor is coupled to the input voltage terminal, the second terminal of the second transistor is coupled to the second terminal of the third transistor, the first terminal of the third transistor is coupled to the AVDD terminal and the input terminal of the feedback control circuit, and the feedback control circuit is configured to output a feedback signal to the enable logic circuit via the output terminal. The control electrode of the second transistor is controlled by the second control circuit, which is configured to control the turning on and off of the second transistor. The control electrode of the third transistor is controlled by the slope control circuit, which is configured to control the turning on and off of the third transistor and control the rising slope of the AVDD voltage by setting the capacitance value of the capacitor array in the slope control circuit, wherein the AVDD voltage is the voltage at the AVDD terminal. The enabling logic circuit is configured to control the opening and closing of the first control circuit, the second control circuit, and the slope control circuit based on the input enabling signal and the feedback signal.

2. The switch control circuit according to claim 1, characterized in that, The switch control circuit further includes a first resistor and a first capacitor, wherein the first resistor and the first capacitor are connected in parallel, and the first end of the parallel connection is coupled to the AVDD terminal. The input voltage terminal, the first transistor, and the AVDD terminal constitute the main path. The first control circuit is configured to control the conduction and cutoff of the main path by controlling the opening and closing of the first transistor. The input voltage terminal, the second transistor, the third transistor, and the AVDD terminal constitute a secondary path. The second control circuit is configured to control the conduction and cutoff of the secondary path by controlling the opening and closing of the second transistor. The enabling logic circuit is further configured to control the opening and closing of the main path and the secondary path by controlling the opening and closing of the first control circuit and the second control circuit.

3. The switch control circuit according to claim 1, characterized in that, The enabling logic circuit includes a first delay, a second delay, a first AND gate, a first inverter, and a second AND gate; The input terminal of the first delay is coupled to the enable signal terminal, and the output terminal of the first delay is coupled to the first input terminal of the first AND gate, wherein the enable signal is input via the enable signal terminal; The input terminal of the second delay is coupled to the output terminal of the feedback control circuit, and the output terminal of the second delay is coupled to the second input terminal of the first AND gate and the input terminal of the first inverter, respectively. The first AND gate is configured to output a first switch enable signal from its output to the first control circuit. The first input terminal of the second AND gate is coupled to the output terminal of the first inverter, and the second input terminal of the second AND gate is coupled to the enable signal terminal. The second AND gate is configured to output a second switch enable signal from the output terminal to the second control circuit.

4. The switch control circuit according to claim 1, characterized in that, The first control circuit includes a fourth transistor, a second resistor, a second inverter, a fifth transistor, and a third resistor; The enabling logic circuit is further configured to output a first switch enable signal from the first output terminal to the control terminal of the fourth transistor and the input terminal of the second inverter, respectively. The first terminal of the fourth transistor is grounded, and the second terminal of the fourth transistor is coupled to the control terminal of the first transistor and the first terminal of the second resistor, respectively. The second terminal of the second resistor is coupled to the first terminal of the first transistor. The output terminal of the second inverter is coupled to the control terminal of the fifth transistor, the first terminal of the fifth transistor is grounded, the second terminal of the fifth transistor is coupled to the first terminal of the third resistor, and the second terminal of the third resistor is coupled to the second terminal of the first fourth transistor.

5. The switch control circuit according to claim 1, characterized in that, The second control circuit includes a sixth transistor and a fourth resistor; The enabling logic circuit is also configured to output a second switch enable signal from the second output terminal to the control electrode of the sixth transistor; The first terminal of the sixth transistor is grounded, the second terminal of the sixth transistor is coupled to the control terminal of the second transistor and the first terminal of the fourth resistor, and the second terminal of the fourth resistor is coupled to the first terminal of the second transistor.

6. The switch control circuit according to claim 1, characterized in that, The slope control circuit includes a current source, a first control switch, a third inverter, a capacitor array, and a second control switch. The enabling logic circuit is further configured to output a second switch enable signal from the second output terminal to the input terminals of the first control switch and the third inverter, respectively, to control the opening and closing of the first control switch, and to control the opening and closing of the second control switch via the output terminal of the third inverter. The first terminal of the first control switch is coupled to the second terminal of the second transistor and the second terminal of the third transistor, respectively; the second terminal of the first control switch is coupled to the first terminal of the current source. The first terminal of the second control switch is coupled to the second terminal of the current source, and the second terminal of the second control switch is coupled to the second terminal of the capacitor array and the ground terminal, respectively. The first terminal of the capacitor array is coupled to the control electrode of the third transistor and the second terminal of the current source, respectively. The capacitor array is configured to be controlled by an external digital control signal, and the capacitance value is set according to the binary coded digital provided by the external digital control signal. Based on the capacitance value, the rising slope of the AVDD voltage is controlled before the programming and burning stage of efuse. The current source is configured to charge the configured capacitor array.

7. The switch control circuit according to claim 6, characterized in that, The number of bits in the binary encoded number provided by the external digital control signal is N, where N is an integer greater than 1; The capacitor array includes N second capacitors and N corresponding third control switches. Each second capacitor and the corresponding third control switch are connected in series to form a capacitor-switch group, and the N capacitor-switch groups are connected in parallel to form the capacitor array. The first terminal of each capacitor-switch group is coupled to the control electrode of the third transistor and the second terminal of the current source, respectively, and the second terminal of each capacitor-switch group is grounded.

8. The switch control circuit according to claim 2, characterized in that, The feedback control circuit includes a first voltage divider resistor, a second voltage divider resistor, a voltage comparator, a fourth control switch, and a power supply. The enabling logic circuit is also configured to output a second switch enable signal from the second output terminal to the input terminal of the third inverter, and control the opening and closing of the fourth control switch via the output terminal of the third inverter. The first terminal of the fourth control switch is coupled to the inverting terminal of the voltage comparator and the positive terminal of the power supply, respectively. The second terminal of the fourth control switch is coupled to the negative terminal of the power supply and the ground terminal, respectively. The power supply is configured to provide a reference voltage to the inverting terminal of the voltage comparator. The first terminal of the first voltage divider resistor is coupled to the first terminal of the third transistor and the AVDD terminal, the second terminal of the first voltage divider resistor is coupled to the non-inverting terminal of the voltage comparator and the first terminal of the second voltage divider resistor, and the second terminal of the second voltage divider resistor is grounded. The voltage comparator is configured to output a feedback signal from its output to the enable logic circuit, thereby controlling the first switch enable signal and the second switch enable signal output by the enable logic circuit.

9. The switch control circuit according to claim 8, characterized in that, The feedback control circuit also includes an OR gate and a timer; The first input terminal of the OR gate is coupled to the output terminal of the third inverter; The first terminal of the timer is coupled to the output terminal of the voltage comparator, and the second terminal of the timer is coupled to the second input terminal of the OR gate. The timer is configured to control the fourth control switch to be closed to open the main path when the enable signal is at an active level and the main path is not opened within a preset time.

10. A chip, characterized in that, Includes the switch control circuit according to any one of claims 1-9.

11. An electronic device, characterized in that, Includes the chip described in claim 10.

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