Adapter plate, method of forming same, package structure, and mask layout

Abstract

The application discloses a transfer plate and a forming method thereof, and a mask plate layout. The method comprises the following steps: forming a first electrode plug penetrating through a first dielectric layer on the top of an upper electrode in a capacitor unit area, the first electrode plug is in a strip shape, and the first electrode plug extends along a second direction; and forming a second electrode plug penetrating through the first dielectric layer on the top of a lower electrode exposed by the upper electrode in a sub-capacitor area, the second electrode plug is in a comb shape, the second electrode plug comprises a first comb handle part and a first comb tooth part connected with the first comb handle part, the first comb handle part is located at one side of the first electrode plug close to a capacitor area boundary and crosses the capacitor area along a first direction, and the first comb tooth part is located at two sides of the capacitor unit area. The impedance of the capacitor in the transfer plate is reduced from two aspects of increasing a contact area and shortening a current transmission path, so that the performance of the transfer plate is improved.

Description

Technical Field

[0001] This invention relates to the field of adapter board manufacturing, and more particularly to an adapter board, its forming method, packaging structure, and mask layout. Background Technology

[0002] With technological advancements, 3D integrated circuits (or 2.5D integrated circuits, etc.) based on interposers have emerged as the most promising solution. They can expand on-chip stacking technologies for a variety of complex chips, enabling the industry to move beyond Moore's Law, rapidly provide large-scale complex chip integration, and offer new ways to reduce power consumption and costs.

[0003] An adapter board is a circuit board-like connection structure made of silicon wafers, similar to a PCB. Adapter boards typically feature through-silicon vias (TSVs) interconnects, allowing different chips to transmit data to the connected circuit board via these TSVs. Therefore, an adapter board acts as a bridge connecting multiple chips to the same circuit board. Adapter boards with TSVs are called TSV adapter boards, and the packaging structure using TSV adapter boards is called a 2.5D interposer.

[0004] With the rise of FinFET devices, they offer higher drive strength compared to previous planar devices.

[0005] The use of FinFET devices increases the drive strength per unit area, which translates to higher current density and larger current transients. This trend makes chips increasingly sensitive to fluctuations in supply voltage, exacerbating the power integrity challenges of system design. Therefore, relying on decoupling capacitors as a fundamental tool for reducing PDN (power delivery network) impedance, and suppressing noise through decoupling or bypass circuitry or interconnects, requires controlling impedance and inductance. Summary of the Invention

[0006] The problem solved by the embodiments of the present invention is to provide an adapter board and its forming method, packaging structure and mask layout, which is beneficial to improving the performance of the adapter board.

[0007] To address the aforementioned problems, this invention provides an adapter board comprising: a substrate including one or more capacitor regions, each capacitor region including capacitor cell regions arranged in a grid pattern along a first direction and a second direction, wherein adjacent capacitor cell regions in the first direction constitute a sub-cell region, and the first and second directions are perpendicular to each other; a groove located in the substrate of the capacitor cell regions, the groove extending along the first direction; a capacitor located in the groove, the capacitor including a lower electrode covering the bottom and sidewalls of the groove and extending to cover the top of the substrate outside the groove, a capacitor dielectric layer located on top of the lower electrode, and an upper electrode located on top of the capacitor dielectric layer, the upper electrode exposing the edge region of the lower electrode and filling the remaining space of the groove; and a strip-shaped first electrode plug located in the capacitor cell region and on top of the upper electrode, the first electrode plug extending along the second direction and electrically connected to the capacitor cell regions. The capacitor comprises: upper electrodes; comb-shaped second electrode plugs, each located in a sub-capacitor region and on top of the exposed lower electrode of the upper electrode; the second electrode plugs include a first comb handle portion and a first comb tooth portion connected to the first comb handle portion; the first comb handle portion is located on one side of the first electrode plug near the boundary of the capacitor region and traverses the capacitor region in a first direction; the first comb tooth portion is located on both sides of the capacitor cell region; a comb-shaped first wire, including a second comb handle portion and a second comb tooth portion connected to the second comb handle portion; the second comb tooth portion is located in the capacitor cell region and on top of the first electrode plug; the second comb tooth portion is electrically connected to the first electrode plug; the second comb handle portion is located at the boundary of adjacent sub-capacitor regions and traverses the capacitor region in a first direction; a comb-shaped second wire, located on top of the second electrode plug and electrically connected to the second electrode plug; and a dielectric layer, located on top of the capacitor and the substrate, covering the sidewalls of the first electrode plug, the second electrode plug, the first wire, and the second wire.

[0008] Accordingly, embodiments of the present invention also provide a method for forming an adapter plate, comprising: providing a substrate, the substrate including one or more capacitor regions, each capacitor region including capacitor cell regions arranged in a grid pattern along a first direction and a second direction, and in each capacitor region, two adjacent capacitor cell regions in the first direction constitute a sub-capacitor region, the first direction and the second direction being perpendicular to each other; forming a groove in the substrate of the capacitor cell region, the groove extending along the first direction; forming a capacitor in the groove, the capacitor including a lower electrode located at the bottom and sidewalls of the groove and extending to cover the top of the substrate outside the groove, a capacitor dielectric layer located at the top of the lower electrode, and an upper electrode located at the top of the capacitor dielectric layer, the upper electrode exposing the edge region of the lower electrode, and the upper electrode filling the remaining space of the groove; after forming the capacitor, forming a first dielectric layer on the top of the substrate and the capacitor; in the capacitor cell region, forming a first electrode plug penetrating the first dielectric layer on the top of the upper electrode, the first electrode plug being strip-shaped, and the first electrode plug extending along the second direction; In the sub-capacitor region, a second electrode plug is formed on top of the exposed lower electrode of the upper electrode, penetrating the first dielectric layer. The second electrode plug is comb-shaped, including a first comb handle and a first comb tooth connected to the first comb handle. The first comb handle is located on one side of the first electrode plug near the boundary of the capacitor region and traverses the capacitor region in a first direction. The first comb tooth is located on both sides of the capacitor cell region. After forming the first electrode plug and the first electrode plug, a second dielectric layer is formed on top of the first dielectric layer, the first electrode plug, and the second electrode plug. A comb-shaped first wire is formed in the second dielectric layer. The first wire includes a second comb handle and a second comb tooth connected to the second comb handle. The second comb tooth is located in the capacitor cell region and on top of the first electrode plug. The second comb tooth is electrically connected to the first electrode plug. The second comb handle is located at the boundary of adjacent sub-capacitor regions and traverses the capacitor region in a first direction. A comb-shaped second wire is formed on top of the second electrode plug, penetrating the second dielectric layer. The second wire is electrically connected to the second electrode plug.

[0009] Accordingly, embodiments of the present invention also provide a packaging structure, including: a circuit board; an adapter board, bonded to the circuit board and electrically connected to the circuit board; and a chip, bonded to the side of the adapter board facing away from the circuit board and electrically connected to the adapter board.

[0010] Accordingly, this embodiment of the invention also provides a mask pattern, comprising: a mask pattern for fabricating an adapter plate, the adapter plate including one or more capacitor regions, each capacitor region including capacitor cell regions arranged in a grid pattern along a first direction and a second direction, and in each capacitor region, two adjacent capacitor cell regions in the first direction constitute a sub-capacitor region, the first direction and the second direction being perpendicular to each other; the mask pattern including: a first layer including a groove pattern located in the capacitor cell region and extending along the first direction; a second layer above the first layer including a lower electrode pattern for forming the lower electrode in the capacitor, the lower electrode pattern covering the capacitor region; a third layer above the second layer including an upper electrode pattern for forming the upper electrode in the capacitor, the upper electrode pattern covering the capacitor cell region; and a fourth layer above the third layer including a strip-shaped first electrode plug pattern and a comb-shaped second electrode. The first electrode plug pattern is located above the upper electrode pattern in the capacitor cell region and extends along the second direction. The second electrode plug patterns are located in the sub-capacitor regions and above the lower electrode pattern exposed by the upper electrode pattern. The second electrode plug pattern includes a first comb handle pattern and a first comb tooth pattern connected to the first comb handle pattern. The first comb handle pattern is located on one side of the first electrode plug pattern near the boundary of the capacitor region and traverses the capacitor region along the first direction. The first comb tooth pattern is located on both sides of the capacitor cell region. The fifth layer is located above the fourth layer. The fifth layer includes a comb-shaped first conductor pattern and a second conductor pattern. The first conductive pattern includes a second comb handle pattern and a second comb tooth pattern connected to the second comb handle pattern. The second comb tooth pattern is located in the capacitor cell region and above the first electrode plug pattern. The second comb handle pattern is located at the boundary of adjacent sub-capacitor regions and traverses the capacitor region along the first direction. The second conductive pattern is located above the second electrode plug pattern.

[0011] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0012] This invention provides a method for forming an adapter plate. In a capacitor cell region, a first electrode plug penetrating a first dielectric layer is formed on the top of the upper electrode. The first electrode plug is strip-shaped and extends along a second direction. In a sub-capacitor region, a second electrode plug penetrating the first dielectric layer is formed on the top of the lower electrode exposed by the upper electrode. The second electrode plug is comb-shaped and includes a first comb handle portion and a first comb tooth portion connected to the first comb handle portion. The first comb handle portion is located on one side of the first electrode plug near the boundary of the capacitor region and traverses the capacitor region along a first direction. The first comb tooth portion is located on both sides of the capacitor cell region. Compared to the perforated plug, the strip-shaped first electrode plug has a larger contact area with the upper electrode layer, and the comb-shaped second electrode plug has a larger contact area with the lower electrode layer. This increases the number of charges passing through per unit time, thereby reducing the capacitor's impedance. Simultaneously, the comb-shaped second electrode plug surrounds the capacitor cell area on three sides, and the comb-shaped first wire is electrically connected to the first electrode plug. This allows the current passing through the second electrode plug to simultaneously reach the lower electrodes in multiple capacitor cell areas, shortening the current transmission path. Since the length of the current transmission path is inversely proportional to the generated resistance, this further reduces the capacitor's impedance. In summary, by increasing the contact area and shortening the current transmission path, the impedance of the capacitor in the adapter plate is reduced, thereby improving the adapter plate's performance. Attached Figure Description

[0013] Figure 1 This is a top view of an adapter plate;

[0014] Figure 2 yes Figure 1 A sectional view along the ef direction;

[0015] Figure 3 This is a top view of an embodiment of the adapter plate of the present invention;

[0016] Figure 4 yes Figure 3 A cross-sectional view along the cd direction;

[0017] Figures 5 to 14 This is a schematic diagram of the structure corresponding to each step in one embodiment of the method for forming the adapter plate of the present invention;

[0018] Figure 15 This is the mask plate of the present invention. Figure 1 A schematic diagram of an embodiment. Detailed Implementation

[0019] The performance of current adapter boards needs improvement. This paper analyzes the reasons why the performance of adapter boards needs improvement, using a structural diagram of one such board as an example.

[0020] Figures 1 to 2This is a structural diagram of an adapter plate. Figure 1 This is a top view of an adapter plate. Figure 2 yes Figure 1 A sectional view along the ef direction.

[0021] refer to Figures 1 to 2 The adapter board structure includes: a substrate 10, the substrate 10 including one or more capacitor regions 10A, each capacitor region 10A including capacitors along a first direction (e.g., ...). Figure 1 The capacitor cell region 10B is arranged in the Y direction (as shown in the figure); multiple grooves (not shown) are located in the substrate 10 of the capacitor cell region 10B, and the grooves are arranged parallel to each other along the first direction and along the second direction (as shown in the figure). Figure 1 Extending in the X direction (as shown in the middle), the first and second directions are perpendicular to each other; capacitor 17, located in the groove, capacitor 17 includes a lower electrode 16 covering the bottom and sidewalls of the groove and extending to cover the top of the substrate 10 outside the groove, a capacitor dielectric layer 12 located on top of the lower electrode 16, and an upper electrode 13 located on top of the capacitor dielectric layer 12, the upper electrode 13 exposing the edge region of the lower electrode 16, and the upper electrode 13 filling the remaining space of the groove; columnar first electrode plugs 19, located in the capacitor cell region 10B and spaced apart on top of the upper electrode 13; columnar second electrode plugs 21, located in the capacitor cell region 10B and spaced apart on top of the lower electrode 16 exposed by the upper electrode 13; comb-shaped first lead wire 32, including a first comb handle portion 30 and a first comb tooth portion 31 connected to the first comb handle portion 30, the first The comb tooth portion 31 is located in the capacitor region 10A. The first comb tooth portion 31 extends along the first direction and is located at the top of the first electrode plug 19. The first comb tooth portion 31 is electrically connected to each of the first electrode plugs 19 in the first direction. The first comb handle portion 32 is located on one side of the boundary of the capacitor region 10A and traverses the capacitor region 10A along the second direction. The comb-shaped second conductor 52 includes the second comb handle portion 51 and the second comb tooth portion 50 connected to the second comb handle portion 51. The second comb tooth portion 50 is located in the capacitor region 10A. The second comb tooth portion 50 extends along the first direction and is located at the top of the second electrode plug 21. The second comb tooth portion 50 is electrically connected to each of the second electrode plugs 21 in the first direction. The second comb handle portion 50 is located on the other side of the boundary region of the capacitor region 10A and traverses the capacitor region 10A along the second direction. The first comb handle portion 30 and the second comb handle portion 51 are disposed opposite to each other.

[0022] Research revealed that the contact area between the columnar first electrode plug 19 and the upper electrode layer 13 is too small. Consequently, the contact area between the first electrode plug 19 and the first wire 32 is also too small, resulting in a low charge throughput per unit time and thus increasing the impedance of the capacitor 17. Simultaneously, the first wire 32 is electrically connected to the spaced-apart first electrode plugs 19, and the second wire 52 is electrically connected to the spaced-apart second electrode plugs 21. Because the current transmission paths of the first wires 32 and 52 are relatively long, the current passing through the first electrode plugs 19 and 21 cannot simultaneously reach the upper electrode 13 and lower electrode 16 in multiple capacitor cell regions 10B. This further lengthens the current transmission path, and since the length of the current transmission path is inversely proportional to the resulting resistance, the impedance of the capacitor 17 becomes excessively high. In summary, both the excessively small contact area and the excessively long current transmission path contribute to the excessive impedance of the capacitor 17 in the adapter plate, thereby reducing the performance of the adapter plate.

[0023] To address the technical problem, this invention provides a method for forming an adapter plate, comprising: providing a substrate, the substrate including one or more capacitor regions, each capacitor region including capacitor cell regions arranged in a grid pattern along a first direction and a second direction, wherein in each capacitor region, two adjacent capacitor cell regions in the first direction constitute a sub-capacitor region, and the first direction and the second direction are perpendicular to each other; forming a groove in the substrate of the capacitor cell regions, the groove extending along the first direction; forming a capacitor in the groove, the capacitor including a lower electrode located at the bottom and sidewalls of the groove and extending to cover the top of the substrate outside the groove, a capacitor dielectric layer located at the top of the lower electrode, and an upper electrode located at the top of the capacitor dielectric layer, the upper electrode exposing the edge region of the lower electrode, and the upper electrode filling the remaining space of the groove; after forming the capacitor, forming a first dielectric layer on the top of the substrate and the capacitor; in the capacitor cell regions, forming a first electrode plug penetrating the first dielectric layer at the top of the upper electrode, the first electrode plug being strip-shaped and extending along the second direction. In the sub-capacitor region, a second electrode plug is formed on top of the exposed lower electrode of the upper electrode, penetrating the first dielectric layer. The second electrode plug is comb-shaped, including a first comb handle and a first comb tooth connected to the first comb handle. The first comb handle is located on one side of the first electrode plug near the boundary of the capacitor region and traverses the capacitor region in a first direction. The first comb tooth is located on both sides of the capacitor cell region. After forming the first electrode plug and the first electrode plug, a second dielectric layer is formed on top of the first dielectric layer, the first electrode plug, and the second electrode plug. A comb-shaped first wire is formed in the second dielectric layer. The first wire includes a second comb handle and a second comb tooth connected to the second comb handle. The second comb tooth is located in the capacitor cell region and on top of the first electrode plug. The second comb tooth is electrically connected to the first electrode plug. The second comb handle is located at the boundary of adjacent sub-capacitor regions and traverses the capacitor region in a first direction. A comb-shaped second wire is formed on top of the second electrode plug, penetrating the second dielectric layer. The second wire is electrically connected to the second electrode plug.

[0024] In the forming method provided by this invention, compared with the perforated plug, the contact area between the strip-shaped first electrode plug and the upper electrode layer is increased, and the contact area between the comb-shaped second electrode plug and the lower electrode layer is increased, resulting in an increase in the number of charges passing through per unit time, thereby reducing the impedance of the capacitor. At the same time, the comb-shaped second electrode plug surrounds the capacitor unit area on three sides, and the comb-shaped first wire is electrically connected to the first electrode plug. This is beneficial to enable the current passing through the second electrode plug to reach the lower electrode in multiple capacitor unit areas simultaneously in a short time, thus shortening the current transmission path. Since the length of the current transmission path is inversely proportional to the generated resistance value, the impedance of the capacitor is reduced. In summary, by increasing the contact area and shortening the current transmission path, the impedance of the capacitor in the adapter plate is reduced, thereby improving the performance of the adapter plate.

[0025] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0026] Figures 3 to 4 This is a schematic diagram of the structure of an embodiment of the adapter board of the present invention, wherein, Figure 3 It is a top view. Figure 4 yes Figure 3 A cross-sectional view along the cd direction.

[0027] The adapter board includes: a substrate 200, the substrate 200 including one or more capacitor regions 200A, each capacitor region 200A including along a first direction (e.g., Figure 3 (as shown in the X direction) and the second direction (as shown in the X direction) Figure 3The capacitor cell regions 200B are arranged in a grid pattern (as shown along the Y direction). In each capacitor region 200A, two adjacent capacitor cell regions 200B in the first direction constitute a sub-cell region 200C. The first and second directions are perpendicular to each other. A groove 295 is located in the substrate 200 of the capacitor cell region 200B and extends along the first direction. A capacitor 207 is located in the groove 295. The capacitor 207 includes a lower electrode 206 covering the bottom and sidewalls of the groove 295 and extending to cover the top of the substrate 200 outside the groove 295, and a top electrode 206. The capacitor has a dielectric layer 202 and an upper electrode 203 on top of the dielectric layer 202. The upper electrode 203 exposes the edge region of the lower electrode 206 and fills the remaining space of the groove 295. A strip-shaped first electrode plug 211 is located in the capacitor cell region 200B and on top of the upper electrode 203. The first electrode plug 211 extends along the second direction and is electrically connected to each upper electrode 203 in the capacitor cell region 200B. A comb-shaped second electrode plug 210 is located in the sub-capacitor regions 200C and on the exposed area of ​​the upper electrode 203. The top of the lower electrode 206, the second electrode plug 210 includes a first comb handle portion 2102 and a first comb tooth portion 2101 connected to the first comb handle portion 2102. The first comb handle portion 2102 is located on one side of the first electrode plug 211 near the boundary of the capacitor region 200A and traverses the capacitor region 200A in a first direction. The first comb tooth portion 2101 is located on both sides of the capacitor cell region 200B. The comb-shaped first lead wire 213 includes a second comb handle portion 2131 and a second comb tooth portion 2132 connected to the second comb handle portion 2131. The second comb tooth portion 2132 is located in the capacitor cell region. In region 200B and located on top of the first electrode plug 211, the second comb tooth portion 2132 is electrically connected to the first electrode plug 211, and the second comb handle portion 2131 is located at the boundary of adjacent sub-capacitor regions 200C and traverses capacitor region 200A in the first direction; the comb-shaped second wire 212 is located on top of the second electrode plug 210 and is electrically connected to the second electrode plug 210; the dielectric layer 290 is located on top of capacitor 207 and substrate 200 and covers the sidewalls of the first electrode plug 211, the second electrode plug 210, the first wire 213, and the second wire 212.

[0028] This invention provides an adapter plate where the contact area between the strip-shaped first electrode plug 211 and the upper electrode layer 203 is increased, and the contact area between the comb-shaped second electrode plug 210 and the lower electrode layer 206 is also increased. This increases the number of charges passing through per unit time, thereby reducing the impedance of the capacitor 207. Simultaneously, the comb-shaped second electrode plug 210 surrounds the capacitor cell region 200B on three sides, and the comb-shaped first wire 213 is electrically connected to the first electrode plug 211. This facilitates the current passing through the second electrode plug 210 to simultaneously reach the lower electrode 206 in multiple capacitor cell regions 200B, shortening the current transmission path. Since the length of the current transmission path is inversely proportional to the generated resistance, this further reduces the impedance of the capacitor 207. In summary, by increasing the contact area and shortening the current transmission path, the impedance of the capacitor in the adapter plate is reduced, thereby improving the performance of the adapter plate.

[0029] The substrate 200 is used to provide a process platform for the manufacturing process.

[0030] In this embodiment, the substrate 200 is used to isolate various components formed in the substrate 200, such as capacitors or TSV structures.

[0031] In this embodiment, the substrate 200 may include doped or undoped silicon, or an active layer of a semiconductor-on-insulator (SOI) substrate. In other embodiments, the substrate material may also be germanium, silicon carbide, gallium arsenide, or indium gallium phosphate, and the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.

[0032] In this embodiment, the adapter plate has multiple capacitors 207. Therefore, in this embodiment, the substrate 200 includes one or more capacitor regions 200A, and each capacitor region 200A includes capacitor cell regions 200B arranged in a grid pattern along the first direction and the second direction.

[0033] Each capacitor unit area 200B contains a capacitor 207.

[0034] In this embodiment, in order to set up strip-shaped electrode plugs, the capacitor unit area 200B is arranged in a grid pattern.

[0035] In this embodiment, the groove 295 provides space for the formation of the capacitor 207.

[0036] In this embodiment, there are multiple grooves 295, and the multiple grooves 295 extend along the first direction and are arranged in parallel along the second direction. In other embodiments, the number of grooves may be one.

[0037] It should be noted that the dimension d1 of the groove 295 along the second direction should not be too large or too small. Since multiple grooves 295 arranged parallel to each other along the second direction are formed in the substrate 200, if the dimension of the groove 295 along the second direction is too large, the overall area of ​​the substrate 200 will easily become too large, resulting in an overly large overall size of the adapter plate, affecting the bonding of the adapter plate with other device structures (e.g., circuit boards). If the dimension d1 of the groove 295 along the second direction is too small, during the formation of the capacitor 207 in the groove 295, the small process window increases the difficulty of depositing various film layers in the groove 295, thus affecting the working performance of the capacitor. Therefore, in this embodiment, the dimension d1 of the groove 295 along the second direction is 0.5 micrometers to 1 micrometer.

[0038] It should be noted that the length dimension d2 of the groove 295 along the first direction should not be too large or too small. Since multiple grooves 295 arranged in a flat pattern along the second direction are formed in the substrate 200, if the length dimension d2 of the groove 295 along the first direction is too large, the overall size of the adapter plate will easily become too large, which will easily generate greater stress on the substrate 200 during the fabrication process of the adapter plate, increasing the probability of deformation of the substrate 200. If the length dimension d2 of the groove 295 along the first direction is too small, the power density and energy density of the capacitor 207 located in the groove 295 will easily fail to meet the process requirements, thus affecting the performance of the adapter plate. Therefore, in this embodiment, the dimension d2 of the groove 295 along the first direction is 10 micrometers to 20 micrometers.

[0039] It should also be noted that the depth h1 of the groove 295 should not be too large or too small. If the depth h1 of the groove 295 is too large, it will easily lead to an excessively large aspect ratio of the groove 295. During the formation of the capacitor 207 in the groove 295, this increases the difficulty of depositing the upper electrode layer 203 and the lower electrode layer 206 in the groove 295, resulting in a decrease in the adhesion between the film layers of the capacitor 207, thus affecting the performance of the adapter board. If the depth h1 of the groove 295 is too small, the size of the capacitor 207 formed in the groove 295 may not meet the process requirements. Consequently, the impedance value of the capacitor 207 in the adapter board will not decrease significantly, thus affecting the performance of the adapter board. Therefore, in this embodiment, the depth h1 of the groove 295 is 5 micrometers to 35 micrometers. For example, the depth h1 of the groove 295 is 10 micrometers, 20 micrometers, or 25 micrometers.

[0040] In this embodiment, along the second direction, the distance w1 between adjacent grooves 295 in the capacitor unit region 200B should not be too large or too small. If the distance w1 between the grooves 295 is too large, the power density and energy density of the capacitors 207 located in the grooves 295 may not meet the process requirements, thus affecting the performance of the adapter board. If the distance w1 between the grooves 295 is too small, the process difficulty of forming the grooves 295 is increased due to the influence of overlay accuracy deviation, making it impossible for the effective structure of the adapter board to meet the process requirements. Therefore, in this embodiment, the distance w1 between adjacent grooves 295 in the capacitor unit region 200B is 0.5 micrometers to 1 micrometer.

[0041] Specifically, during the operation of the adapter board, the capacitor 207 in the adapter board is used to control the generated impedance.

[0042] In this embodiment, capacitor 207 is a deep trench capacitor (DTC).

[0043] It should be noted that the lower electrode 206 is in Figure 3 Only the outermost outline is shown in the diagram.

[0044] In this embodiment, the lower electrode 206 is made of a conductive material, such as one or more of tungsten, copper, aluminum, titanium, and tantalum. As an example, the lower electrode 206 is made of tungsten.

[0045] In this embodiment, the capacitor dielectric layer 202 is used to electrically isolate the lower electrode 206 and the upper electrode 203.

[0046] Specifically, the capacitor dielectric layer 202 is made of a dielectric material. Therefore, in this embodiment, the material of the capacitor dielectric layer 202 includes one or more of titanium oxide, titanium nitride, silicon oxide, silicon nitride, zirconium oxide, hafnium oxide, and aluminum oxide.

[0047] It should be noted that the upper electrode 203 is in Figure 3 Only the outermost outline is shown in the diagram.

[0048] In this embodiment, the upper electrode 203 is used to achieve electrical connection with the formed first electrode plug 211. Therefore, the upper electrode 203 is made of a conductive material, such as one or more of tungsten, copper, aluminum, titanium, and tantalum. As an example, the upper electrode 203 is made of tungsten.

[0049] It should be noted that the upper electrode 203 exposes the edge area of ​​the lower electrode 206, which facilitates the direct formation of a second electrode plug 210 penetrating the dielectric layer 290 on the top of the exposed lower electrode 206. This reduces the step of removing part of the edge area of ​​the upper electrode 203 that exposes the lower electrode 206, thereby simplifying the process steps and reducing the process cost.

[0050] The phrase "the upper electrode 203 exposes the edge region of the lower electrode 206" refers to the top part of the upper electrode 203 that is exposed near the boundary of the capacitor cell region. In other words, the projection of the upper electrode 203 on the substrate is located within the projection of the lower electrode 206 on the substrate, and the projection area of ​​the upper electrode 203 on the substrate is smaller than the projection area of ​​the lower electrode 206 on the substrate.

[0051] In this embodiment, in the capacitor region 200A, the upper electrode 203 is shaped like a grid, and the lower electrode 206 is shaped like a square.

[0052] Specifically, the design of the upper electrode 203 in a grid shape and the lower electrode in a square shape simplifies the structural design of the adapter plate, which is beneficial to improving the process integration and reduces the probability of defects in the adapter plate during the manufacturing process.

[0053] In this embodiment, the adapter plate further includes a pad layer 208, located between the substrate 200 and the lower electrode 206.

[0054] Specifically, the pad layer 208 is used to improve the adhesion between the lower electrode 206 and the substrate 200, reduce the probability of air gaps being generated between the lower electrode 206 and the substrate 200, thereby improving the performance of the adapter plate. In addition, the pad layer 208 is also used to achieve electrical insulation between the capacitor and the substrate 200.

[0055] In this embodiment, the material of the liner layer 208 includes one or both of silicon nitride and silicon dioxide.

[0056] In this embodiment, the dielectric layer 290 is used to electrically isolate the first electrode plug 211 and the second electrode plug 210, as well as the first wire 213 and the second wire 212.

[0057] In this embodiment, the dielectric layer 290 includes: a first dielectric layer 209, located on top of the capacitor 207 and the substrate 200, and covering the sidewalls of the first electrode plug 211 and the second electrode plug 210, the top of the first dielectric layer 209 being flush with the top of the first electrode plug 211 and the second electrode plug 210; and a second dielectric layer 214, located on top of the first dielectric layer 209, and covering the sidewalls of the first conductor 213 and the second conductor 212, the top of the second dielectric layer 214 being flush with the top of the first conductor 213 and the second conductor 212.

[0058] It should be noted that by first forming the first dielectric layer 209, and then forming the first electrode plug 211 and the second electrode plug 210 in the first dielectric layer 209, it is beneficial to control the effective height of the first electrode plug 211 and the second electrode plug 210, reduce the formation difficulty of the first electrode plug 211 and the second electrode plug 210, improve the compatibility of the formation process of the first electrode plug 211 and the second electrode plug 210, and at the same time make the top surface flatness of the first electrode plug 211 and the second electrode plug 210 higher, which provides a good process basis for forming the first wire 213 on the top of the first electrode plug 211 and the second wire 212 on the top of the second electrode plug 210.

[0059] The first dielectric layer 209 is made of an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbonitride. As an example, the first dielectric layer 209 is made of silicon oxide.

[0060] By forming a second dielectric layer 214, and forming a first conductor 213 and a second conductor 212 in the second dielectric layer 214, it is beneficial to control the effective height of the first conductor 213 and the second conductor 212, reduce the formation difficulty of the first conductor 213 and the second conductor 212, improve the compatibility of the formation process of the first conductor 213 and the second conductor 212, and at the same time make the top surface flatness of the first conductor 213 and the second conductor 212 higher.

[0061] The material of the second dielectric layer 214 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbonitride. As an example, the material of the second dielectric layer 214 is silicon oxide.

[0062] The first electrode plug 211 is used to connect the upper electrode 203 to the external circuit structure.

[0063] In this embodiment, the first electrode plug 211 is strip-shaped. Compared with a cylindrical plug, the strip-shaped first electrode plug 211 has a larger contact area with the upper electrode layer 203, and the number of charges passing through per unit time increases, thereby reducing the impedance of the capacitor.

[0064] In this embodiment, the first electrode plug 211 is made of tungsten. Tungsten has a low resistivity, which helps to further reduce the impedance of capacitor 207, improve the performance of the adapter board, and also helps to reduce power consumption and cost. In other embodiments, the source and drain plugs can also be made of conductive materials such as ruthenium or molybdenum.

[0065] In this embodiment, in the capacitor cell region 200B, there are multiple first electrode plugs 211, and these multiple first electrode plugs 211 are arranged along a first direction (e.g., Figure 8 (As shown in the X direction) Extended parallel arrangement.

[0066] Specifically, the top of the upper electrode 203 in each groove 201 is covered with multiple first electrode plugs 211, which increases the contact area between the upper electrode 203 and the first electrode plugs 211, thereby increasing the number of charges passing through per unit time and thus reducing the impedance of the capacitor.

[0067] Meanwhile, multiple first electrode plugs 211 extend in parallel along the first direction, meaning that the current through the first electrode plugs 211 is in parallel. Consequently, the current through the first wire 213 electrically connected to the first electrode plugs 211 can reach the lower electrode 206 in multiple capacitor cell regions 200B simultaneously, thus shortening the current transmission path and reducing the impedance of the capacitor.

[0068] It should be noted that the number of first electrode plugs 211 in the capacitor unit area 200B should not be too many or too few. Given a fixed dimension of the capacitor unit area 200B along the first direction, if the number of first electrode plugs 211 is too large, the probability of short-circuiting due to overlay accuracy deviations increases, thus affecting the performance of the adapter board. If the number of first electrode plugs 211 is too small, the contact area between the first electrode plugs 211 and the upper electrode 203 becomes smaller, correspondingly reducing the amount of charge passing through a unit area, thereby increasing the impedance of the capacitor 207 and further affecting the performance of the adapter board. Therefore, in this embodiment, the number of first electrode plugs 211 in the capacitor unit area 200B is 3 to 9.

[0069] It should also be noted that the width w2 of the first electrode plug 211 along the first direction should not be too large or too small. If the width w2 of the first electrode plug 211 along the first direction is too large, the probability of multiple first electrode plugs 211 short-circuiting each other in the first direction increases, thus affecting the performance of the adapter plate. If the width w2 of the first electrode plug 211 along the first direction is too small, the contact area between the first electrode plug 211 and the upper electrode 203 becomes smaller, correspondingly reducing the number of charges passing through a unit area, thereby increasing the impedance of the capacitor 207 and further affecting the performance of the adapter plate. Therefore, in this embodiment, the width W2 of the first electrode plug 211 along the first direction is 0.2 micrometers to 1 micrometer.

[0070] In addition, in other embodiments, in the capacitor cell region, multiple first electrode plugs can be combined into a single electrode plug.

[0071] The second electrode plug 210 is used to connect the lower electrode 206 to the external circuit structure.

[0072] In this embodiment, the second electrode plug 210 and the first electrode plug 211 are formed in the same step, and the material of the second electrode plug 210 is the same as that of the first electrode plug 211. Therefore, the material of the second electrode plug 210 is also tungsten. In other embodiments, the first electrode plug and the second electrode plug may be formed in different steps, and the materials of the first electrode plug and the second electrode plug may also be different.

[0073] It should be noted that the width w3 of the second electrode plug 210 should not be too large or too small. Due to the limited area of ​​the edge region of the lower electrode 206 exposed by the upper electrode 203, if the width w3 of the second electrode plug 210 is too large, the bottom of the second electrode plug 210 may not fully contact the top of the lower electrode 206, increasing the risk of leakage. If the width w3 of the second electrode plug 210 is too small, the contact area between the second electrode plug 210 and the lower electrode 206 becomes smaller, correspondingly reducing the amount of charge passing through a unit area, thus increasing the impedance of the capacitor 207 and affecting the performance of the adapter plate. Therefore, in this embodiment, the width w3 of the second electrode plug 210 is between 0.36 micrometers and 0.68 micrometers.

[0074] In this embodiment, in the sub-capacitor region 200C, adjacent capacitor unit regions 200B share the first comb tooth portion 2101.

[0075] Specifically, the fact that adjacent capacitor unit areas 200B share the first comb tooth section 2101 is beneficial to improving the structural integration of the adapter board and reducing the overall structural area of ​​the adapter board.

[0076] The first wire 213 is used to electrically connect the upper electrode 203 of the capacitor 207 to the external circuit structure through the first electrode plug 211.

[0077] In this embodiment, the first wire 213 is configured as a comb, and the second comb teeth 2132 are arranged in parallel along the first direction. That is, the current through the second comb teeth 2132 is in parallel. Accordingly, the current through the first wire 213 can reach the upper electrode 203 in multiple capacitor cell regions 200B at the same time, which shortens the current transmission path and reduces the impedance of the capacitor.

[0078] In this embodiment, the second comb handle portion 2131 is located at the boundary of adjacent sub-capacitor regions 200C and traverses capacitor region 200A along the first direction.

[0079] In this embodiment, the first conductor 213 is made of tungsten. Tungsten has a low resistivity, which helps to reduce the resistance generated by the current flowing through the first conductor 213, further reducing the impedance generated by the capacitor 207 and improving the working performance of the adapter plate. At the same time, tungsten has a fast electron mobility, which can improve the electrical performance of the first conductor 213. In other embodiments, the first conductor can also be made of conductive materials such as molybdenum or ruthenium.

[0080] The second wire 212 is used to electrically connect the lower electrode 206 of the capacitor 207 to the external circuit structure through the second electrode plug 210.

[0081] In this embodiment, the second conductor 212 is configured in a comb shape, that is, the current through the second conductor 212 is in parallel. Accordingly, the current through the second conductor 212 can reach the lower electrode 206 in multiple capacitor cell regions 200B at the same time, which shortens the current transmission path and thus reduces the impedance of the capacitor.

[0082] In this embodiment, in the capacitor unit area 200B, there are multiple second comb teeth 2132, and each second comb tooth 2132 corresponds to a first electrode plug 211.

[0083] Specifically, the second comb tooth portion 2132 corresponds one-to-one with the first electrode plug 211, so that the current flowing through the first wire 213 can reach the lower electrode 206 in multiple capacitor cell regions 200B at the same time, which shortens the current transmission path and thus reduces the impedance of the capacitor 207.

[0084] In this embodiment, in capacitor region 200A, adjacent sub-capacitor regions 200C share the second comb handle portion 2131.

[0085] Specifically, adjacent sub-capacitor regions 200C share the second comb handle portion 2131, which helps to improve the structural integration of the adapter board and reduce the overall structural area of ​​the adapter board.

[0086] It should be noted that the second wire 212 and the first wire 213 are formed in the same step, therefore, the material of the second wire 212 is also tungsten. In other embodiments, the second wire and the first wire may be formed in different steps, and the materials of the second wire and the first wire may also be different.

[0087] Figures 5 to 14 This is a schematic diagram of the structure corresponding to each step in one embodiment of the method for forming the adapter plate of the present invention.

[0088] refer to Figure 5 , Figure 5 This is a top view showing a substrate 100, which includes one or more capacitor regions 100A, each capacitor region 100A including regions along a first direction (e.g., ...). Figure 5 (as shown in the X direction) and the second direction (as shown in the X direction) Figure 5 The capacitor cell regions 100B are arranged in a grid pattern (as shown in the Y direction). In each capacitor region 100A, two adjacent capacitor cell regions 100B in the first direction constitute a sub-capacitor region 100C. The first direction and the second direction are perpendicular to each other.

[0089] Substrate 100 is used to provide a process platform for subsequent process manufacturing.

[0090] In this embodiment, the substrate 100 is used to isolate various components formed in the substrate 100, such as capacitors or TSV structures.

[0091] In this embodiment, the substrate 100 includes one or more capacitor regions 100A, and each capacitor region 100A includes capacitor cell regions 100B arranged in a grid pattern along a first direction and a second direction.

[0092] Each capacitor unit region 100B subsequently contains a capacitor 107.

[0093] In this embodiment, in order to enable the subsequent setting of strip-shaped electrode plugs, the capacitor unit area 100B is arranged in a grid pattern.

[0094] In this embodiment, the description of the substrate 100 can be found in the descriptions of other embodiments above, and will not be repeated here.

[0095] refer to Figures 6 to 7 , Figure 6 It is a top view. Figure 7 yes Figure 6 A cross-sectional view along the AB direction shows a groove 101 formed in the substrate 100 of the capacitor cell region 100B, the groove 101 being along a first direction (e.g., ...). Figure 6 Extending in the X direction and along the second direction (as shown in the middle X direction) and as shown in the second direction (e.g Figure 6 (As shown in the Y direction) Flat arrangement.

[0096] The groove 101 provides space for the subsequent formation of the capacitor.

[0097] In this embodiment, the process of forming the groove 101 in the substrate 100 of the capacitor cell region 100B includes a dry etching process.

[0098] Specifically, the dry etching process includes anisotropic dry etching. Anisotropic dry etching has anisotropic characteristics, therefore its longitudinal etching rate is much greater than its lateral etching rate. This allows for the precise removal of a portion of the substrate 100 to form the groove 101 while ensuring the integrity of the sidewall morphology of the groove 101, providing a favorable process environment for the subsequent formation of capacitors in the groove 101.

[0099] It should be noted that the depth H1 of the groove 101 should not be too large or too small. If the depth H1 of the groove 101 is too large, it will easily lead to an excessively large aspect ratio of the groove 101. This will increase the difficulty of depositing the upper and lower electrode layers in the groove 101 during the subsequent formation of the capacitor, reducing the adhesion between the capacitor layers and thus affecting the performance of the adapter plate. If the depth H1 of the groove 101 is too small, the size of the capacitor formed in the groove may not meet the process requirements. Consequently, the impedance value of the capacitor in the adapter plate will not decrease significantly, thus affecting the performance of the adapter plate. Therefore, in this embodiment, the depth H1 of the groove 101 is 5 micrometers to 35 micrometers. For example, the depth H1 of the groove 101 is 10 micrometers, 20 micrometers, or 25 micrometers.

[0100] It should be noted that the dimension D1 of the groove 101 along the second direction should not be too large or too small. Since multiple grooves 101 arranged parallel to each other along the second direction are formed in the substrate 100, if the dimension D1 of the groove 101 along the second direction is too large, the overall area of ​​the substrate 100 will easily become too large, resulting in an overly large overall size of the adapter plate, affecting the bonding of the adapter plate with other device structures (e.g., circuit boards). If the dimension D1 of the groove 101 along the second direction is too small, during the subsequent formation of the capacitor in the groove 101, the small process window increases the difficulty of depositing various film layers in the groove 101, thus affecting the working performance of the capacitor. Therefore, in this embodiment, the dimension D1 of the groove 101 along the second direction is 0.5 micrometers to 1 micrometer.

[0101] It should also be noted that the length dimension D2 of the groove 101 along the first direction should not be too large or too small. If the length dimension D2 of the groove 101 along the first direction is too large, it will easily lead to an excessively large overall size of the adapter plate, which will easily generate greater stress on the substrate 100 during the fabrication process of the adapter plate, increasing the probability of deformation of the substrate 100. If the length dimension D2 of the groove 101 along the first direction is too small, it will easily lead to the power density and energy density of the capacitor subsequently formed in the groove 101 not meeting the process requirements, thereby affecting the performance of the adapter plate. Therefore, in this embodiment, the length dimension D2 of the groove 101 along the first direction is 10 micrometers to 20 micrometers.

[0102] In this embodiment, the distance W1 between adjacent grooves 101 in the capacitor unit region 100B should not be too large or too small. If the distance W1 between the grooves 101 is too large, the power density and energy density of the capacitors subsequently formed in the grooves 101 may not meet the process requirements, thus affecting the performance of the adapter board. If the distance W1 between the grooves 101 is too small, the process difficulty of forming the grooves 101 will be increased due to the overlay accuracy deviation, making it impossible for the effective structure of the adapter board to meet the process requirements. Therefore, in this embodiment, the distance W1 between adjacent grooves 101 in the capacitor unit region 100B is 0.5 micrometers to 1 micrometer.

[0103] refer to Figure 8 A capacitor 107 is formed in the groove 101. The capacitor 107 includes a lower electrode 106 covering the bottom and sidewalls of the groove 101 and extending to cover the top of the substrate 100 outside the groove 101, a capacitor dielectric layer 102 located on top of the lower electrode 106, and an upper electrode 103 located on top of the capacitor dielectric layer 102. The upper electrode 103 exposes the edge region of the lower electrode 106 and fills the remaining space in the groove 101.

[0104] Specifically, during the operation of the adapter board, the capacitor 107 in the adapter board is used to control the generated impedance.

[0105] In this embodiment, capacitor 107 is a deep trench capacitor (DTC).

[0106] In this embodiment, the process of forming the lower electrode 106 at the bottom and sidewalls of the groove 101 and at the top of the substrate 100 outside the groove 101 includes an atomic layer deposition process.

[0107] Atomic layer deposition (ALD) involves multiple ALD cycles. ALD offers excellent step coverage, which helps improve the thickness uniformity of the lower electrode 106, allowing it to cover the bottom and sidewalls of the groove 101, as well as the top of the substrate 100 outside the groove 101. In other embodiments, chemical vapor deposition (CVD) or physical vapor deposition (PVD) can also be used to form the lower electrode.

[0108] In this embodiment, the lower electrode 106 is used to achieve electrical connection with the subsequently formed second electrode plug. Therefore, the lower electrode 106 is made of a conductive material, such as one or more of tungsten, copper, aluminum, titanium, and tantalum. As an example, the lower electrode 106 is made of tungsten.

[0109] In this embodiment, after forming the lower electrode 106, the method for forming the adapter plate further includes forming a capacitor dielectric layer 102 covering the top and sidewalls of the lower electrode 106.

[0110] The capacitor dielectric layer 102 is used to electrically isolate the lower electrode 106 and the subsequently formed upper electrode.

[0111] Specifically, the capacitor dielectric layer 102 is made of a dielectric material. Therefore, in this embodiment, the material of the capacitor dielectric layer 102 includes one or more of titanium oxide, titanium nitride, silicon oxide, silicon nitride, and aluminum oxide.

[0112] In this embodiment, the process of forming the capacitor dielectric layer 102 covering the top and sidewalls of the lower electrode 106 includes an atomic layer deposition process.

[0113] In this embodiment, after the capacitor dielectric layer 102 is formed, an upper electrode 103 is formed on the top and sidewalls of the capacitor dielectric layer 102, and the upper electrode 103 also fills the remaining space in the groove 101.

[0114] In this embodiment, the upper electrode 103 is used to achieve electrical connection with the subsequently formed first electrode plug. Therefore, the upper electrode 103 is made of a conductive material, such as one or more of tungsten, copper, aluminum, titanium, and tantalum. As an example, the upper electrode 103 is made of tungsten.

[0115] It should be noted that the upper electrode 103 exposes the edge area of ​​the lower electrode 106, which facilitates the subsequent formation of a second electrode plug penetrating the first dielectric layer directly on the top of the exposed lower electrode 106. This reduces the step of removing part of the edge area of ​​the upper electrode 103 that exposes the lower electrode 106, thereby simplifying the process steps and reducing the process cost.

[0116] The phrase "the upper electrode 103 exposes the edge region of the lower electrode 106" refers to the top part of the upper electrode 103 that is exposed near the boundary of the capacitor cell region. In other words, the projection of the upper electrode 103 on the substrate is located within the projection of the lower electrode 106 on the substrate, and the projection area of ​​the upper electrode 103 on the substrate is smaller than the projection area of ​​the lower electrode 106 on the substrate.

[0117] In this embodiment, the upper electrode 103 is shaped like a grid, and the lower electrode 106 is shaped like a square.

[0118] Specifically, the design of the upper electrode 103 in a grid shape and the lower electrode 106 in a square shape simplifies the structural design of the adapter plate, which is beneficial to improving the process integration and reduces the probability of defects in the adapter plate during the manufacturing process.

[0119] In this embodiment, the process of forming the upper electrode 103 on the top and sidewalls of the capacitor dielectric layer 102 includes a chemical vapor deposition process.

[0120] Chemical vapor deposition has the characteristics of fast deposition rate and good filling effect. The upper electrode 103 formed in the remaining space of the groove 101 can be closely attached to the side wall of the capacitor dielectric layer 102, which reduces the probability of forming an air gap between the capacitor dielectric layer 102 and the upper electrode 103, thereby improving the performance of the adapter plate.

[0121] In other embodiments, the process of forming the top electrode 103 on the top and sidewalls of the capacitor dielectric layer 102 may also include atomic layer deposition or physical vapor deposition.

[0122] In this embodiment, the method of forming the adapter plate further includes: before forming the lower electrode 106, forming a pad layer 108 on the bottom and sidewalls of the groove 101 and on the top of the substrate 100 outside the groove 101.

[0123] The padding layer 108 is used to improve the adhesion between the lower electrode 106 and the substrate 100, reduce the probability of air gaps being generated between the lower electrode 106 and the substrate 100, thereby improving the performance of the adapter plate.

[0124] In this embodiment, the material of the liner layer 108 includes one or both of silicon nitride and silicon dioxide.

[0125] refer to Figure 9 After forming capacitor 107, a first dielectric layer 109 is formed on top of substrate 100 and capacitor 107.

[0126] The first dielectric layer 109 provides space for the subsequent formation of the first electrode plug and the second electrode plug, and also serves to electrically isolate the first electrode plug and the second electrode plug.

[0127] Meanwhile, by first forming the first dielectric layer 109, and then forming the first electrode plug and the second electrode plug in the first dielectric layer 109, it is beneficial to control the effective height of the first electrode plug and the second electrode plug, reduce the formation difficulty of the first electrode plug and the second electrode plug, improve the compatibility of the formation process of the first electrode plug and the second electrode plug, and also make the top surface of the first electrode plug and the second electrode plug have a high degree of flatness, which provides a good process foundation for the subsequent formation of the first wire on the top of the first electrode plug and the second wire on the top of the second electrode plug.

[0128] In this embodiment, the process of forming the first dielectric layer 109 on top of the substrate 100 and the capacitor 107 includes a chemical vapor deposition process.

[0129] In this embodiment, the material of the first dielectric layer 109 is an insulating material, which includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbonitride. As an example, the material of the first dielectric layer 109 is silicon oxide.

[0130] refer to Figures 10 to 11 , Figure 10 It is a top view. Figure 11 yes Figure 10 In a top view along the AB direction, in capacitor cell region 100B, a first electrode plug 111 is formed on the top of the upper electrode 106, penetrating the first dielectric layer 109. The first electrode plug 111 is strip-shaped and extends along a second direction. In sub-capacitor region 100C, a second electrode plug 110 is formed on the top of the lower electrode 106 exposed by the upper electrode 106, penetrating the first dielectric layer 109. The second electrode plug 110 is comb-shaped and includes a first comb handle portion 1102 and a first comb tooth portion 1101 connected to the first comb handle portion 1102. The first comb handle portion 1102 is located on the side of the first electrode plug 111 near the boundary of capacitor region 100A and extends along a first direction (e.g., ...). Figure 10 (As shown in the X direction) It traverses the capacitor region 100A, and the first comb tooth 1101 is located on both sides of the capacitor unit region 100B.

[0131] In this embodiment, the contact area between the strip-shaped first electrode plug 111 and the upper electrode layer 103 is increased, and the contact area between the comb-shaped second electrode plug 110 and the lower electrode layer 106 is increased, resulting in an increase in the number of charges passing through per unit time, thereby reducing the impedance of the capacitor. At the same time, the comb-shaped second electrode plug 110 surrounds the capacitor unit area 100B on three sides, and the subsequently formed comb-shaped first wire is electrically connected to the first electrode plug 111. This is beneficial for the current passing through the second electrode plug 110 to reach the lower electrode 106 in multiple capacitor unit areas 100B simultaneously in a short time, thus shortening the current transmission path. Since the length of the current transmission path is inversely proportional to the generated resistance value, the impedance of the capacitor decreases. In summary, by increasing the contact area and shortening the current transmission path, the impedance of the capacitor in the adapter plate is reduced, thereby improving the performance of the adapter plate.

[0132] In this embodiment, the steps of forming the first electrode plug 111 and the second electrode plug 110 include: forming a first trench (not shown) penetrating the first dielectric layer 109 at the top of the upper electrode 103 in the capacitor cell region 100B, the first trench being strip-shaped and extending along a second direction; forming a second trench (not shown) penetrating the first dielectric layer 109 at the top of the lower electrode 106 exposed by the upper electrode 103 in the sub-capacitor region 100C, the second trench being comb-shaped, the second trench including a first comb handle groove and a first comb tooth groove connected to the first comb handle groove, the first comb handle groove being located on one side of the capacitor near the boundary of the capacitor region 100A and traversing the capacitor region 100A along a first direction, and the first comb tooth groove being located on both sides of the capacitor cell region 100B; forming the first electrode plug 111 in the first trench and forming the second electrode plug 110 in the second trench.

[0133] The first electrode plug 111 is used to connect the upper electrode 103 to the external power distribution structure, and the second electrode plug 110 is used to connect the lower electrode 106 to the external power distribution structure.

[0134] In this embodiment, the first electrode plug 111 is made of tungsten. Tungsten has a low resistivity, which helps to further reduce the impedance of the capacitor 107, improve the working performance of the adapter board, and also helps to reduce power consumption and cost. In other embodiments, the source and drain plugs can also be made of conductive materials such as molybdenum or ruthenium.

[0135] In this embodiment, in the capacitor cell region 100B, there are multiple first electrode plugs 111, and these multiple first electrode plugs 111 are arranged along a first direction (e.g., Figure 10 (As shown in the X direction) Extended parallel arrangement.

[0136] Specifically, the top of the upper electrode 103 in each groove 101 is covered with a plurality of first electrode plugs 111, which increases the contact area between the upper electrode 103 and the first electrode plugs 111, thereby increasing the number of charges passing through per unit time and thus reducing the impedance of the capacitor.

[0137] Meanwhile, multiple first electrode plugs 111 extend in parallel along the first direction, meaning that the current through the first electrode plugs 111 is in parallel. Consequently, the current through the first wire electrically connected to the first electrode plugs 111 can simultaneously reach the lower electrode 106 in multiple capacitor cell regions 100B, thus shortening the current transmission path and reducing the impedance of the capacitor.

[0138] It should be noted that the number of first electrode plugs 111 in the capacitor unit area 100B should not be too many or too few. Given a fixed dimension of the capacitor unit area 100B along the first direction, if the number of first electrode plugs 111 is too large, the probability of short-circuiting due to overlay accuracy deviations increases, thus affecting the performance of the adapter board. If the number of first electrode plugs 111 is too small, the contact area between the first electrode plugs 111 and the upper electrode 103 becomes smaller, correspondingly reducing the amount of charge passing through a unit area, thereby increasing the impedance of the capacitor 107 and further affecting the performance of the adapter board. Therefore, in this embodiment, the number of first electrode plugs 111 in the capacitor unit area 100B is 3 to 9.

[0139] It should also be noted that the width W2 of the first electrode plug 111 along the first direction should not be too large or too small. If the width W2 of the first electrode plug 111 along the first direction is too large, the probability of multiple first electrode plugs 111 short-circuiting each other in the first direction increases, thus affecting the performance of the adapter plate. If the width W2 of the first electrode plug 111 along the first direction is too small, the contact area between the first electrode plug 111 and the upper electrode 103 becomes smaller, correspondingly reducing the number of charges passing through a unit area, thereby increasing the impedance of the capacitor 107 and further affecting the performance of the adapter plate. Therefore, in this embodiment, the width W2 of the first electrode plug 111 along the first direction is 0.2 micrometers to 1 micrometer.

[0140] Specifically, the second electrode plug 110 and the first electrode plug 111 are formed in the same step, and therefore, the material of the second electrode plug 110 is also tungsten. In other embodiments, the first electrode plug and the second electrode plug may be formed in different steps, and the materials of the first electrode plug and the second electrode plug may also be different.

[0141] In this embodiment, in the sub-capacitor region 100C, adjacent capacitor unit regions 100B share the first comb tooth portion 1101.

[0142] Specifically, the fact that adjacent capacitor unit areas 100B share the first comb tooth section 1101 is beneficial to improving the structural integration of the adapter board and reducing the overall structural area of ​​the adapter board.

[0143] It should be noted that the width W3 of the second electrode plug 110 should not be too large or too small. Due to the limited area of ​​the edge region of the lower electrode 106 exposed by the upper electrode 103, if the width W3 of the second electrode plug 110 is too large, the bottom of the second electrode plug 110 may not fully contact the top of the lower electrode 106, increasing the risk of leakage. If the width W3 of the second electrode plug 110 is too small, the contact area between the second electrode plug 110 and the lower electrode 106 becomes smaller, correspondingly reducing the amount of charge passing through a unit area, thereby increasing the impedance of the capacitor 107 and affecting the performance of the adapter plate. Therefore, in this embodiment, the width W3 of the second electrode plug 110 is between 0.36 micrometers and 0.68 micrometers.

[0144] refer to Figure 12 After the first electrode plug 111 and the second electrode plug 110 are formed, a second dielectric layer 114 is formed on top of the first dielectric layer 109, the first electrode plug 111 and the second electrode plug 110.

[0145] The second dielectric layer 114 provides space for the subsequent formation of the first and second conductors, and also serves to electrically isolate the first and second conductors.

[0146] Meanwhile, by forming the second dielectric layer 114, the first conductor and the second conductor are subsequently formed in the second dielectric layer 114, which helps to control the effective height of the first conductor and the second conductor, and also makes the top surface of the first conductor and the second conductor have a high degree of flatness.

[0147] In this embodiment, the process of forming the second dielectric layer 114 on top of the first dielectric layer 109, the first electrode plug 111, and the second electrode plug 110 includes a chemical vapor deposition process.

[0148] The material of the second dielectric layer 114 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbonitride. As an example, the material of the second dielectric layer 114 is silicon oxide.

[0149] refer to Figures 13 to 14 , Figure 13 It is a top view. Figure 14 yes Figure 13In a cross-sectional view along the CD direction, a comb-shaped first conductor 113 is formed in the second dielectric layer 114. The first conductor 113 includes a second comb handle portion 1131 and a second comb tooth portion 1132 connected to the second comb handle portion 1131. The second comb tooth portion 1132 is located in the capacitor cell region 100B and is located on top of the first electrode plug 111. The second comb tooth portion 1132 is electrically connected to the first electrode plug 111. The second comb handle portion 1131 is located at the boundary of adjacent sub-capacitor regions 100C and along the first direction (e.g., ...). Figure 13 (As shown in the X direction) traverses the capacitor region 100A; a comb-shaped second conductor 112 is formed on the top of the second electrode plug 110, penetrating the second dielectric layer 114, and the second conductor 112 is electrically connected to the second electrode plug 110.

[0150] The first wire 113 is used to electrically connect the upper electrode 103 of the capacitor 107 to the external power distribution structure through the first electrode plug 111, and the second wire 112 is used to electrically connect the lower electrode 106 of the capacitor 107 to the external circuit structure through the second electrode plug 110.

[0151] In this embodiment, the steps of forming the first conductor 113 and the second conductor 112 include: forming a comb-shaped third trench in the second dielectric layer 114, the third trench including a second comb handle groove and a second comb tooth groove connected to the second comb handle groove, the second comb tooth groove being located in the capacitor cell region 100B and penetrating the second dielectric layer 114 at the top of the first electrode plug 111, the second comb handle groove being located at the boundary of adjacent sub-capacitor regions 100C and traversing the capacitor region 100A along a first direction; forming a comb-shaped fourth trench penetrating the second dielectric layer 114 at the top of the second electrode plug 110, the third trench exposing the top of the second electrode plug 110; forming the first conductor 113 in the third trench and forming the second conductor 112 in the fourth trench.

[0152] In this embodiment, the first conductor 113 is made of tungsten. Tungsten has a low resistivity, which helps to reduce the resistance generated when flowing through the first conductor 113, further reducing the impedance generated by the capacitor 107 and improving the working performance of the adapter plate. At the same time, tungsten has a fast electron mobility, which can improve the electrical performance of the first conductor 113. In other embodiments, the first conductor can also be made of conductive materials such as molybdenum or ruthenium.

[0153] In this embodiment, the first wire 113 is configured as a comb, and the second comb teeth 1132 are arranged in parallel along the first direction. That is, the current through the second comb teeth 1132 is in parallel. Accordingly, the current through the first wire 113 can reach the upper electrode 103 in multiple capacitor cell regions 100B at the same time, which shortens the current transmission path and reduces the impedance of the capacitor.

[0154] It should be noted that the second wire 112 and the first wire 113 are formed in the same step, therefore, the material of the second wire 112 is also tungsten. In other embodiments, the second wire and the first wire may be formed in different steps, and the materials of the second wire and the first wire may also be different.

[0155] In this embodiment, the second conductor 112 is configured in a comb shape, that is, the current through the second conductor 112 is in parallel. Accordingly, the current through the second conductor 112 can reach the lower electrode 106 in multiple capacitor cell regions 100B at the same time, which shortens the current transmission path and reduces the impedance of the capacitor.

[0156] In this embodiment, in the capacitor unit area 100B, there are multiple second comb teeth 1132, and each second comb tooth 1132 corresponds to a first electrode plug 111.

[0157] Specifically, the second comb tooth portion 1132 corresponds one-to-one with the first electrode plug 111, so that the current flowing through the first wire 113 can reach the lower electrode 106 in multiple capacitor unit regions 100B at the same time, which shortens the current transmission path and thus reduces the impedance of the capacitor 107.

[0158] In this embodiment, in capacitor region 100A, adjacent sub-capacitor regions 100C share the second comb handle portion 1131.

[0159] Specifically, the fact that adjacent sub-capacitor regions 100C share the second comb handle portion 1131 is beneficial to improving the structural integration of the adapter board and reducing the overall structural area of ​​the adapter board.

[0160] Accordingly, embodiments of the present invention also provide a packaging structure.

[0161] Packaging structure: Circuit board; as mentioned above, the adapter board is bonded to the circuit board and is electrically connected to the circuit board; chip, bonded to the side of the adapter board facing away from the circuit board and is electrically connected to the adapter board.

[0162] In this embodiment, the circuit board is electrically connected to an external circuit to provide drive current to the adapter board and the chip.

[0163] In this embodiment, as can be seen from the previous embodiments, the contact area between the first electrode plug and the upper electrode layer in the adapter plate is increased, and the contact area between the comb-shaped second electrode plug and the lower electrode layer is increased, resulting in an increase in the number of charges passing through per unit time, thereby reducing the impedance of the capacitor. At the same time, the comb-shaped second electrode plug surrounds the capacitor unit area on three sides, and the comb-shaped first wire is electrically connected to the first electrode plug. This is beneficial for the current passing through the second electrode plug to reach the lower electrode in multiple capacitor unit areas simultaneously in a short time, thus shortening the current transmission path. Since the length of the current transmission path is inversely proportional to the generated resistance value, the impedance of the capacitor decreases. In summary, by increasing the contact area and shortening the current transmission path, the impedance of the capacitor in the adapter plate is reduced, thereby improving the performance of the adapter plate.

[0164] In this embodiment, the chip is used to process data and signal conversion.

[0165] Accordingly, embodiments of the present invention also provide a mask layout. Figure 15 This is the mask plate of the present invention. Figure 1 A schematic diagram of an embodiment.

[0166] refer to Figure 15 The mask pattern is used to fabricate an adapter plate, which includes one or more capacitor regions 400A, each capacitor region 400A including a region along a first direction (e.g., ...). Figure 15 (as shown in the X direction) and the second direction (as shown in the X direction) Figure 15 The capacitor cell regions 400B are arranged in a grid pattern (as shown in the Y direction). In each capacitor region 400A, two adjacent capacitor cell regions 400B in the first direction constitute a sub-capacitor region 400C. The first direction and the second direction are perpendicular to each other.

[0167] Specifically, the mask layout includes: a first layer, including a groove pattern 495, which is located in the capacitor cell area 400B and extends along a first direction.

[0168] Groove pattern 495 is used to form grooves.

[0169] It should be noted that the dimension d1 of the groove pattern 495 along the second direction should not be too large or too small. If the dimension of the groove pattern 495 along the second direction is too large, the groove size formed by the groove pattern 495 may not meet the process requirements; if the dimension d1 of the groove pattern 495 along the second direction is too small, the groove size formed by the groove pattern 495 along the second direction may be too small, increasing the difficulty of depositing various film layers in the groove, thereby affecting the working performance of the capacitor. Therefore, in this embodiment, the dimension d1 of the groove pattern 495 along the second direction is 0.5 micrometers to 1 micrometer.

[0170] It should also be noted that, along the second direction, the distance w1 between adjacent groove patterns 495 in the capacitor unit region 400B should not be too large or too small. If the distance w1 between the groove patterns 495 is too large, the power density and energy density of the capacitors formed in the grooves may not meet the process requirements, thus affecting the performance of the adapter board. If the distance w1 between the groove patterns 495 is too small, the process difficulty of forming the grooves will increase due to the influence of overlay accuracy deviation, making it impossible for the effective structure of the adapter board to meet the process requirements. Therefore, in this embodiment, along the second direction, the distance w1 between adjacent groove patterns 495 in the capacitor unit region 400B is 0.5 micrometers to 1 micrometer.

[0171] In this embodiment, the mask layout further includes a second layer, located above the first layer. The second layer includes a lower electrode pattern 406 for forming the lower electrode in the capacitor. The lower electrode pattern 406 covers the capacitor region 400A.

[0172] In this embodiment, the lower electrode pattern 406 is used to form the lower electrode in a deep trench capacitor (DTC).

[0173] In this embodiment, the second layer is located above the first layer, so in the semiconductor forming process, the lower electrode is formed after the groove is formed.

[0174] In this embodiment, the mask layout further includes a third layer, located above the second layer. The third layer includes an upper electrode pattern 403 for forming the upper electrode in the capacitor. The upper electrode pattern 403 covers the capacitor cell area 400B.

[0175] In this embodiment, the upper electrode pattern 403 is used to form the upper electrode in a deep trench capacitor (DTC).

[0176] In this embodiment, the third layer is located above the second layer, so in the semiconductor forming process, the upper electrode is formed after the lower electrode is formed.

[0177] In semiconductor fabrication processes, the upper electrode exposes the edge region of the lower electrode. Therefore, the upper electrode pattern exposes the edge region of the lower electrode pattern.

[0178] In this embodiment, the mask layout further includes a fourth layer, located above the third layer. The fourth layer includes a strip-shaped first electrode plug pattern 411 and a comb-shaped second electrode plug pattern 410. The first electrode plug pattern 411 is located above the upper electrode pattern 403 of the capacitor cell region 400B and extends along the second direction. The second electrode plug pattern 410 is located in the sub-capacitor region 400C and above the lower electrode pattern 406 exposed by the upper electrode pattern 403. The second electrode plug pattern 410 includes a first comb handle pattern 4102 and a first comb tooth pattern 4101 connected to the first comb handle pattern 4102. The first comb handle pattern 4102 is located on one side of the first electrode plug pattern 411 near the boundary of the capacitor region 400A and traverses the capacitor region 400A along the first direction. The first comb tooth pattern 4101 is located on both sides of the capacitor cell region 400B.

[0179] In this embodiment, the first electrode plug pattern 411 is used to form the first electrode plug, and the second electrode plug pattern 410 is used to form the second electrode plug.

[0180] In this embodiment, in the capacitor unit area 400B, there are multiple first electrode plug patterns 411, and the multiple first electrode plug patterns 411 extend in parallel along the first direction.

[0181] It should be noted that the number of first electrode plug patterns 411 in the capacitor unit area 400B should not be too many or too few. With a fixed dimension of the capacitor unit area 400B along the first direction, if the number of first electrode plug patterns 411 is too large, the probability of short circuits between the formed first electrode plugs increases due to overlay accuracy deviations, thus affecting the performance of the adapter plate. If the number of first electrode plug patterns 411 is too small, the contact area between the first electrode plug and the upper electrode becomes smaller, correspondingly reducing the amount of charge passing through a unit area, thus increasing the impedance of the capacitor and further affecting the performance of the adapter plate. Therefore, in this embodiment, the number of first electrode plug patterns 411 in the capacitor unit area 200B is 3 to 9.

[0182] It should also be noted that the width w2 of the first electrode plug pattern 411 along the first direction should not be too large or too small. If the width w2 of the first electrode plug pattern 411 along the first direction is too large, the probability of multiple first electrode plugs short-circuiting each other in the first direction increases, thus affecting the performance of the adapter plate. If the width w2 of the first electrode plug pattern 411 along the first direction is too small, the contact area between the first electrode plug and the upper electrode becomes smaller, and correspondingly, the number of charges passing through a unit area decreases, thereby increasing the impedance of the capacitor and affecting the performance of the adapter plate. Therefore, in this embodiment, the width w2 of the first electrode plug pattern 411 along the first direction is 0.2 micrometers to 1 micrometer.

[0183] It should be noted that the width w3 of the second electrode plug pattern 410 should not be too large or too small. If the width w3 of the second electrode plug pattern 410 is too large, the bottom of the second electrode plug may not make complete contact with the top of the lower electrode, increasing the risk of leakage. If the width w3 of the second electrode plug pattern 410 is too small, the contact area between the second electrode plug and the lower electrode will be smaller, resulting in a decrease in the amount of charge passing through a unit area, thereby increasing the impedance of the capacitor and affecting the performance of the adapter plate. Therefore, in this embodiment, the width w3 of the second electrode plug pattern 410 is between 0.36 micrometers and 0.68 micrometers.

[0184] In this embodiment, in the sub-capacitor region 400C, adjacent capacitor unit regions 400B share the first comb tooth pattern 4101.

[0185] Specifically, the fact that adjacent capacitor unit areas 400B share the first comb tooth pattern 4101 is beneficial to improving the structural integration of the adapter board and reducing the overall structural area of ​​the adapter board.

[0186] In this embodiment, the mask layout further includes a fifth layer, located above the fourth layer. The fifth layer includes a comb-shaped first conductive pattern 413 and a second conductive pattern 412. The first conductive pattern 413 includes a second comb handle pattern 4131 and a second comb tooth pattern 4132 connected to the second comb handle pattern 4131. The second comb tooth pattern 4132 is located in the capacitor cell region 400B and above the first electrode plug pattern 411. The second comb handle pattern 4131 is located at the boundary of adjacent sub-capacitor regions 400C and traverses the capacitor region 400A along the first direction. The second conductive pattern 412 is located above the second electrode plug pattern 410.

[0187] The first conductive pattern 413 is used to form the first conductive wire, and the second conductive pattern 412 is used to form the second conductive wire.

[0188] In this embodiment, the first conductor pattern 413 is configured as a comb, and the second comb tooth pattern 4132 is arranged in parallel along the first direction. That is, the current direction through the second comb tooth is in parallel. Accordingly, the current through the first conductor can reach the upper electrode of multiple capacitor unit areas 400B at the same time, which shortens the current transmission path and reduces the impedance of the capacitor.

[0189] In this embodiment, the second comb handle pattern 4131 is located at the boundary of adjacent sub-capacitor regions 400C and traverses capacitor region 400A along the first direction.

[0190] In this embodiment, the second conductor pattern 412 is configured as a comb, that is, the current through the second conductor is in parallel. Accordingly, the current through the second conductor can reach the lower electrode of multiple capacitor cell regions 400B at the same time, which shortens the current transmission path and thus reduces the impedance of the capacitor.

[0191] In this embodiment, in the capacitor unit area 400B, there are multiple second comb tooth patterns 4132, and each second comb tooth pattern 4132 corresponds to a first electrode plug pattern 411.

[0192] In this embodiment, in capacitor region 400A, adjacent sub-capacitor regions 400C share the second comb handle pattern 4131.

[0193] Specifically, adjacent sub-capacitor regions 400C share the second comb handle pattern 4131, which helps to improve the structural integration of the adapter board and reduce the overall structural area of ​​the adapter board.

[0194] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. An adapter board, characterized in that, include: The substrate includes one or more capacitor regions, each capacitor region including capacitor cell regions arranged in a grid pattern along a first direction and a second direction, and in each capacitor region, two adjacent capacitor cell regions in the first direction constitute a sub-capacitor region, and the first direction and the second direction are perpendicular to each other. A groove is located in the substrate of the capacitor cell region, and the groove extends along the first direction; A capacitor is located in the groove, the capacitor including a lower electrode covering the bottom and sidewalls of the groove and extending to cover the top of a substrate outside the groove, a capacitor dielectric layer located on top of the lower electrode, and an upper electrode located on top of the capacitor dielectric layer, the upper electrode exposing the edge region of the lower electrode and filling the remaining space of the groove; A strip-shaped first electrode plug is located in the capacitor cell region and on top of the upper electrode. The first electrode plug extends along the second direction and is electrically connected to each of the upper electrodes in the capacitor cell region. The comb-shaped second electrode plugs are located in the sub-capacitor regions and on top of the lower electrode exposed by the upper electrode. The second electrode plugs include a first comb handle portion and a first comb tooth portion connected to the first comb handle portion. The first comb handle portion is located on the side of the first electrode plug near the boundary of the capacitor region and traverses the capacitor region along the first direction. The first comb tooth portion is located on both sides of the capacitor unit region. The comb-shaped first lead includes a second comb handle portion and a second comb tooth portion connected to the second comb handle portion. The second comb tooth portion is located in the capacitor cell area and is located on top of the first electrode plug. The second comb tooth portion is electrically connected to the first electrode plug. The second comb handle portion is located at the boundary of adjacent sub-capacitor areas and traverses the capacitor area along the first direction. A comb-shaped second lead is located at the top of the second electrode plug and is electrically connected to the second electrode plug; A dielectric layer is located on top of the capacitor and the substrate, and covers the sidewalls of the first electrode plug, the second electrode plug, the first wire, and the second wire.

2. The adapter board as described in claim 1, characterized in that, In the capacitor cell region, there are multiple grooves, and the multiple grooves extend along the first direction and are arranged in parallel along the second direction.

3. The adapter board as described in claim 2, characterized in that, Along the second direction, the distance between adjacent grooves in the capacitor cell region is 0.5 micrometers to 1 micrometer.

4. The adapter board as described in claim 1, characterized in that, In the capacitor unit area, there are multiple first electrode plugs, which extend along the second direction and are arranged in parallel along the first direction.

5. The adapter board as described in claim 4, characterized in that, In the capacitor unit area, there are multiple second comb teeth, and each second comb tooth corresponds to one of the first electrode plugs.

6. The adapter board as described in claim 4, characterized in that, In the capacitor cell area, the number of the first electrode plugs is 3 to 9.

7. The adapter board as described in claim 1, characterized in that, In the capacitor region, adjacent sub-capacitor regions share the second comb handle portion.

8. The adapter board as described in claim 1, characterized in that, In the sub-capacitor region, adjacent capacitor cell regions share the first comb tooth portion.

9. The adapter board as described in claim 1, characterized in that, The dielectric layer includes: a first dielectric layer located on top of the capacitor and the substrate, and covering the sidewalls of the first electrode plug and the second electrode plug, wherein the top of the first dielectric layer is flush with the top of the first electrode plug and the second electrode plug; A second dielectric layer is located on top of the first dielectric layer and covers the sidewalls of the first and second conductors. The top of the second dielectric layer is flush with the top of the first and second conductors.

10. The adapter board as described in claim 1, characterized in that, The groove has a dimension of 0.5 micrometers to 1 micrometer along the second direction; The length of the groove along the first direction is 10 micrometers to 20 micrometers; The depth of the groove is 5 micrometers to 35 micrometers.

11. The adapter board as described in claim 1, characterized in that, The width of the first electrode plug along the first direction is 0.2 micrometers to 1 micrometer.

12. The adapter board as described in claim 1, characterized in that, The width of the second electrode plug is between 0.36 micrometers and 0.68 micrometers.

13. A method for forming an adapter plate, characterized in that, include: A substrate is provided, the substrate including one or more capacitor regions, each capacitor region including capacitor cell regions arranged in a grid pattern along a first direction and a second direction, and in each capacitor region, two adjacent capacitor cell regions in the first direction constitute a sub-capacitor region, the first direction and the second direction being perpendicular to each other. A groove is formed in the substrate of the capacitor cell region, and the groove extends along the first direction; A capacitor is formed in the groove, the capacitor including a lower electrode located at the bottom and sidewalls of the groove and extending to cover the top of a substrate outside the groove, a capacitor dielectric layer located on top of the lower electrode, and an upper electrode located on top of the capacitor dielectric layer, the upper electrode exposing the edge region of the lower electrode and filling the remaining space of the groove; After the capacitor is formed, a first dielectric layer is formed on top of the substrate and the capacitor; In the capacitor cell region, a first electrode plug is formed on the top of the upper electrode, penetrating the first dielectric layer. The first electrode plug is strip-shaped and extends along a second direction. In the sub-capacitor region, a second electrode plug is formed on the top of the lower electrode exposed by the upper electrode, penetrating the first dielectric layer. The second electrode plug is comb-shaped and includes a first comb handle portion and a first comb tooth portion connected to the first comb handle portion. The first comb handle portion is located on the side of the first electrode plug near the boundary of the capacitor region and traverses the capacitor region along the first direction. The first comb tooth portion is located on both sides of the capacitor cell region. After the first electrode plug and the second electrode plug are formed, a second dielectric layer is formed on top of the first dielectric layer, the first electrode plug and the second electrode plug; A comb-shaped first conductor is formed in the second dielectric layer. The first conductor includes a second comb handle portion and a second comb tooth portion connected to the second comb handle portion. The second comb tooth portion is located in the capacitor cell region and is located on top of the first electrode plug. The second comb tooth portion is electrically connected to the first electrode plug. The second comb handle portion is located at the boundary of adjacent sub-capacitor regions and traverses the capacitor region along the first direction. A comb-shaped second conductor is formed at the top of the second electrode plug, penetrating the second dielectric layer, and the second conductor is electrically connected to the second electrode plug.

14. A packaging structure, comprising: Circuit board; The adapter board as described in any one of claims 1 to 12 is bonded to the circuit board, and the adapter board is electrically connected to the circuit board; The chip is bonded to the side of the adapter board facing away from the circuit board, and the chip is electrically connected to the adapter board.

15. A photomask layout, characterized in that, The mask pattern is used to fabricate an adapter plate, which includes one or more capacitor regions. Each capacitor region includes capacitor cell regions arranged in a grid pattern along a first direction and a second direction. In each capacitor region, two adjacent capacitor cell regions along the first direction constitute a sub-capacitor region. The first direction and the second direction are perpendicular to each other. The mask pattern includes: The first layer includes a groove pattern located in the capacitor cell area and extending along the first direction; The second layer, located above the first layer, includes a lower electrode pattern for forming the lower electrode in the capacitor, the lower electrode pattern covering the capacitor area; The third layer, located above the second layer, includes an upper electrode pattern for forming the upper electrode in the capacitor, and the upper electrode pattern covers the capacitor cell area respectively. The fourth layer, located above the third layer, includes a strip-shaped first electrode plug pattern and a comb-shaped second electrode plug pattern. The first electrode plug pattern is located above the upper electrode pattern of the capacitor unit area and extends along the second direction. The second electrode plug patterns are located in the sub-capacitor areas and above the lower electrode pattern exposed by the upper electrode pattern. The second electrode plug pattern includes a first comb handle pattern and a first comb tooth pattern connected to the first comb handle pattern. The first comb handle pattern is located on the side of the first electrode plug pattern near the boundary of the capacitor area and traverses the capacitor area along the first direction. The first comb tooth pattern is located on both sides of the capacitor unit area. The fifth layer, located above the fourth layer, includes a comb-shaped first and second conductor pattern. The first conductor pattern includes a second comb handle pattern and a second comb tooth pattern connected to the second comb handle pattern. The second comb tooth pattern is located in the capacitor cell area and above the first electrode plug pattern. The second comb handle pattern is located at the boundary of adjacent sub-capacitor areas and traverses the capacitor area along the first direction. The second conductor pattern is located above the second electrode plug pattern.

16. The mask layout as described in claim 15, characterized in that, In the capacitor cell region, there are multiple groove patterns, and the multiple groove patterns extend along the first direction and are arranged in parallel along the second direction.

17. The mask layout as described in claim 15, characterized in that, In the capacitor unit area, there are multiple first electrode plug patterns, and these multiple first electrode plug patterns are arranged in parallel at intervals along the first direction.

18. The mask layout as described in claim 17, characterized in that, In the capacitor unit area, there are multiple second comb teeth patterns, and each second comb tooth pattern corresponds to a first electrode plug pattern.

19. The mask layout as described in claim 15, characterized in that, In the capacitor region, adjacent sub-capacitor regions share the second comb handle pattern.

20. The mask layout as described in claim 15, characterized in that, In the sub-capacitor region, adjacent capacitor cell regions share the first comb tooth pattern.

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