A high-performance TFT array substrate with an etching stopper layer and a manufacturing method thereof

Abstract

The application relates to the technical field of liquid crystal display screens, and provides a high-performance TFT array substrate with etching blocking layers and a manufacturing method thereof, which comprises a glass substrate, a first metal layer for forming a gate electrode, a gate insulation layer fixedly arranged on the upper surface of the first metal layer and the glass substrate, a left active layer and a right active layer fixedly arranged on the upper surface of the gate insulation layer, a bridging layer with the left and right ends connected with the left active layer and the right active layer respectively, a left etching blocking layer fixedly arranged on the upper surface of the gate insulation layer and the left active layer, a right etching blocking layer fixedly arranged on the upper surface of the gate insulation layer and the right active layer, a second metal layer connected with the left active layer for forming a source electrode, and a third metal layer connected with the right active layer for forming a drain electrode.The TFT array substrate has the advantages of quick reaction, large on-state current, small threshold voltage and the like.

Description

Technical Field

[0001] The present invention relates to the technical field of liquid crystal display screens, and in particular to a high-performance TFT array substrate with an etching stopper layer and a manufacturing method thereof. Background Art

[0002] With the rapid development of artificial intelligence, TFT-LCD screen technology has also been continuously improved. High definition, fast speed, and low power consumption will become the development trend of TFT-LCD screens.

[0003] To achieve high-performance displays, one of the current manufacturing methods used by manufacturers is to miniaturize TFT devices by shortening the active layer channel length. This shortened active layer channel length can achieve higher on-state current, improve device response speed, and reduce threshold voltage, among other advantages. However, in practice, the design of the active layer channel length is limited to the distance between the source and drain of the TFT device, mainly considering the risk of short circuits if the source and drain are too close. After years of technological development, the source and drain spacing of current thin-film transistors (TFTs) is selected to a safe minimum distance, generally controlled by the industry at 5-6μm.

[0004] See Figure 1 , which is a schematic diagram of the structure of a traditional TFT device. The active layer is a semiconductor, and the active layer channel length refers to the length of the semiconductor from the source to the drain.

[0005] Therefore, how to shorten the active layer channel length without shortening the source-drain distance of the TFT device is a technical problem that needs to be solved urgently in this field. Summary of the Invention

[0006] The technical problem to be solved by the present invention is to provide a high-performance TFT array substrate with an etch stop layer and a manufacturing method thereof, which can shorten the active layer channel length without shortening the source-drain distance of the TFT device.

[0007] The present invention is implemented as follows: a high-performance TFT array substrate with an etching stop layer, comprising:

[0008] glass substrate;

[0009] A first metal layer is fixedly disposed on the upper surface of the glass substrate to form a gate;

[0010] a gate insulating layer fixedly disposed on the upper surfaces of the first metal layer and the glass substrate;

[0011] a left active layer, fixedly disposed on the upper surface of the gate insulating layer and also located above the left end of the first metal layer;

[0012] a right active layer, fixedly disposed on the upper surface of the gate insulating layer and also located above the right end of the first metal layer;

[0013] a bridging layer, fixedly disposed on the upper surface of the gate insulating layer, with left and right ends respectively connected to the left active layer and the right active layer;

[0014] a left etching stop layer, fixedly disposed on the upper surfaces of the gate insulating layer and the left active layer, and further having a left hole;

[0015] a right etching stop layer, fixedly disposed on the upper surfaces of the gate insulating layer and the right active layer, and further having a right hole;

[0016] a second metal layer, fixedly disposed on the upper surface of the left etching stop layer, and also passing through the left hole to connect with the left active layer to form a source electrode;

[0017] The third metal layer is fixedly arranged on the upper surface of the right etching stop layer and passes through the right hole to be connected with the right active layer to form a drain.

[0018] Furthermore, it also includes:

[0019] a pixel electrode, fixedly disposed on the upper surface of the right etching stop layer and connected to the third metal layer;

[0020] a conductive layer fixedly disposed on the upper surface of the right etching stop layer;

[0021] A passivation layer is fixedly disposed on the upper surfaces of the second metal layer, the third metal layer, the left etching stop layer, the right etching stop layer, the bridge layer, the pixel electrode, and the conductive layer, wherein the passivation layer is provided with a through hole;

[0022] The common electrode is fixedly arranged on the upper surface of the passivation layer and is connected to the conductive layer through the through hole.

[0023] Furthermore, it also includes:

[0024] A common electrode is fixedly disposed on the upper surface of the right etching stop layer;

[0025] a conductive layer, fixedly disposed on the upper surface of the right etching stop layer and connected to the common electrode;

[0026] A passivation layer is fixedly arranged on the upper surfaces of the second metal layer, the third metal layer, the left etching barrier layer, the right etching barrier layer, the bridge layer, the common electrode, and the conductive layer, and the passivation layer is provided with a through hole;

[0027] The pixel electrode is fixedly arranged on the upper surface of the passivation layer and is connected to the third metal layer through the through hole.

[0028] Furthermore, the first metal layer, the second metal layer, the third metal layer, and the conductive layer are any one of a MO single-layer structure, a Ti single-layer structure, a MO / AL / MO three-layer structure, a Ti / AL / Ti three-layer structure, an AL / MO double-layer structure, and an AL / Ti double-layer structure.

[0029] Furthermore, the left active layer and the right active layer are both made of IGZO material, the left etching stop layer and the right etching stop layer are both made of SiOx material, and the bridge layer, the pixel electrode, and the common electrode are all made of ITO material.

[0030] Furthermore, the gate insulating layer is a SiOx single-layer structure or a SiNx / SiOx double-layer structure, and the passivation layer is made of SiOx, SiNO or SiNx.

[0031] Furthermore, the left hole, the right hole and the through hole are all in an inverted cone shape.

[0032] A method for manufacturing a high-performance TFT array substrate having an etching stop layer comprises the following steps:

[0033] S1, plating a first metal layer on the upper surface of the glass substrate to form a gate;

[0034] S2, coating a gate insulating layer on the upper surface of the first metal layer and the glass substrate;

[0035] S3, plating a left active layer and a right active layer on the upper surface of the gate insulating layer, wherein the left active layer and the right active layer are located above the first metal layer;

[0036] S4, coating a left etching stop layer on the upper surface of the gate insulating layer and the left active layer, and coating a right etching stop layer on the upper surface of the gate insulating layer and the right active layer;

[0037] S5, plating a bridge layer on the upper surface of the gate insulating layer, wherein the left and right ends of the bridge layer are connected to the left active layer and the right active layer respectively;

[0038] S6, opening a left hole in the left etching stop layer, exposing the left active layer from the left hole, and opening a right hole in the right etching stop layer, exposing the right active layer from the right hole;

[0039] S7, plating a second metal layer on the upper surface of the left etching stop layer, wherein the second metal layer is further connected to the left active layer through the left hole to form a source electrode;

[0040] A third metal layer is plated on the upper surface of the right etching stop layer. The third metal layer also passes through the right hole and is connected to the right active layer to form a drain.

[0041] Further, the S5 further comprises: plating a pixel electrode on the upper surface of the right etching barrier layer, the pixel electrode being located at the side of the bridge layer;

[0042] The S7 further comprises: the third metal layer is further connected with the pixel electrode; and plating a conductive layer on the upper surface of the right etching barrier layer, the conductive layer being located at the side of the pixel electrode.

[0043] Further, the S5 further comprises: plating a pixel electrode on the upper surface of the right etching barrier layer, the pixel electrode being located at the side of the bridge layer;

[0044] S8, plating a passivation layer on the upper surfaces of the second metal layer, the third metal layer, the left etching barrier layer, the right etching barrier layer, the bridge layer, the pixel electrode and the conductive layer, the passivation layer being provided with a through hole, and the conductive layer being exposed to the through hole;

[0045] S9, plating a common electrode on the upper surface of the passivation layer, the common electrode being further connected with the conductive layer through the through hole.

[0046] The advantages of the present application are as follows: 1. Different from the conventional TFT device, the present application replaces a section of the active layer with a bridge layer, the bridge layer being a conductor and the active layer being a semiconductor, so that the overall active layer channel length is shortened, but the distance between the source and the drain remains unchanged, ensuring the safety of the device; that is, the active layer channel length is shortened without shortening the distance between the source and the drain of the TFT device, the TFT array substrate of the present application has the advantages of fast response, large on-state current, small threshold voltage and the like, and improves the performance of the display screen after practical application. 2. The left etching barrier layer and the right etching barrier layer prevent the etching acid used in the subsequent ITO film layer process from damaging the left active layer and the right active layer. 3. Since the ITO material has excellent conductivity and light transmission characteristics, the materials of the bridge layer and the pixel electrode of the TFT device of the present application are both ITO, the bridge layer and the pixel electrode under this structure are formed in the same process, so that the structure of the array substrate is simplified, the production is improved, and the cost is reduced. BRIEF DESCRIPTION OF DRAWINGS

[0047] The present application will be further described below with reference to the accompanying drawings and embodiments.

[0048] Figure 1 is a structural schematic diagram of a conventional TFT device in the background art.

[0049] Figure 2 is a manufacturing process of the high-performance TFT array substrate with an etching barrier layer of the present application Figure 1 .

[0050] Figure 3 is a manufacturing process of the high-performance TFT array substrate with an etching barrier layer of the present application Figure 2 .

[0051] Figure 4 The present invention is a process for manufacturing a high-performance TFT array substrate with an etching stop layer. Figure 3 .

[0052] Figure 5 The present invention is a process for manufacturing a high-performance TFT array substrate with an etching stop layer. Figure 4 .

[0053] Figure 6 The present invention is a process for manufacturing a high-performance TFT array substrate with an etching stop layer. Figure 5 .

[0054] Figure 7 The present invention is a process for manufacturing a high-performance TFT array substrate with an etching stop layer. Figure 6 .

[0055] Figure 8 The present invention is a process for manufacturing a high-performance TFT array substrate with an etching stop layer. Figure 7 .

[0056] Figure 9 The present invention is a process for manufacturing a high-performance TFT array substrate with an etching stop layer. Figure 8 .

[0057] Figure 10 The present invention is a process for manufacturing a high-performance TFT array substrate with an etching stop layer. Figure 9 .

[0058] Figure 11 It will Figure 10 Schematic diagram after the positions of the pixel electrode and the common electrode are swapped.

[0059] Figure 1: Glass substrate 1; gate 2; gate insulating layer 3; active layer 4; left active layer 41; right active layer 42; bridging layer 5; source 6; drain 7; pixel electrode 8; conductive layer 9; passivation layer 10; through hole 101; common electrode 20; left etching stop layer 30; left hole 301; right etching stop layer 40; right hole 401. DETAILED DESCRIPTION

[0060] The embodiments of the present invention provide a high-performance TFT array substrate with an etch stop layer and a method for manufacturing the same, thereby resolving the problem in the background art that the design of the active layer channel length is limited to the distance between the source and drain electrodes of the TFT device. When the source-drain distance is at a safe minimum distance, if the source-drain distance is further shortened, a source-drain short circuit will occur. The embodiments of the present invention achieve a reduction in the active layer channel length without shortening the source-drain distance of the TFT device. The TFT device carried on the array substrate of the present invention has the advantages of fast response, large on-state current, and low threshold voltage, thereby improving the performance of the display screen after practical application.

[0061] The technical solution in the embodiment of the present invention is to solve the above shortcomings, and the overall idea is as follows:

[0062] The difference from traditional TFT devices is that the TFT device of the present invention replaces the middle section of the active layer with a bridge layer. The bridge layer is a conductor and the active layer is a semiconductor, so that the overall active layer channel length is shortened, that is, the length of the semiconductor is shortened, but the distance between the source and the drain remains unchanged, ensuring the safety of the device; the active layer channel length is shortened without shortening the source-drain distance of the TFT device.

[0063] Before plating the bridge layer, the left etch stop layer and the right etch stop layer are first plated on the left active layer and the right active layer. The function of the left etch stop layer and the right etch stop layer is to prevent the etching acid used in the subsequent ITO film process from damaging the left active layer and the right active layer.

[0064] The influence of the active layer channel length on the gate characteristics of thin film transistors (TFTs) is very significant. The general trend is: the shorter the channel, the greater the on-state current, and the longer the channel, the smaller the on-state current. This can be attributed to the fact that as the channel length increases, the probability of carriers being captured during the drift process increases, and the decrease in carrier density causes the threshold voltage to increase, which also causes the source-drain current I DS The growth slows down, resulting in an increase in the subthreshold swing, which means that the response speed of the device will decrease.

[0065] In order to better understand the above technical solution, the above technical solution will be described in detail below with reference to the accompanying drawings and specific implementation methods.

[0066] See Figures 1 to 11 , a preferred embodiment of the present invention.

[0067] Combine Figure 10 , a high-performance TFT array substrate with an etch stop layer, comprising:

[0068] Glass substrate 1;

[0069] A first metal layer is fixedly disposed on the upper surface of the glass substrate 1 to form a gate 2;

[0070] a gate insulating layer 3 fixedly disposed on the upper surface of the first metal layer and the glass substrate 1;

[0071] a left active layer 41 fixedly disposed on the upper surface of the gate insulating layer 3 and also located above the left end of the first metal layer;

[0072] a right active layer 42 fixedly disposed on the upper surface of the gate insulating layer 3 and also located above the right end of the first metal layer;

[0073] a bridge layer 5 fixedly disposed on the upper surface of the gate insulating layer 3 , with its left and right ends respectively connected to the left active layer 41 and the right active layer 42 ;

[0074] A left etching stop layer 30 is fixedly disposed on the upper surface of the gate insulating layer 3 and the left active layer 41 and further has a left hole 301 formed therein;

[0075] A right etching stop layer 40 is fixedly disposed on the upper surface of the gate insulating layer 3 and the right active layer 42 and is further provided with a right hole 401;

[0076] A second metal layer is fixedly disposed on the upper surface of the left etching stop layer 30 and is connected to the left active layer 41 through the left hole 301 to form a source electrode 6;

[0077] The third metal layer is fixedly disposed on the upper surface of the right etching stopper layer 40 and is connected to the right active layer 42 through the right hole 401 to form a drain 7 .

[0078] The difference from the traditional TFT device is that the TFT device of the present invention replaces the middle section of the active layer with a bridge layer 5. The bridge layer 5 is a conductor, and the left active layer 41 and the right active layer 42 are both semiconductors, so that the overall active layer channel length is shortened, that is, the length of the semiconductor is shortened, but at this time the distance between the source 6 and the drain 7 remains unchanged, ensuring the safety of the device; that is, without shortening the distance between the source 6 and the drain 7 of the TFT device, the active layer channel length is shortened. The TFT array substrate of the present invention has the advantages of fast response, large on-state current, and low threshold voltage, and improves the performance of the display screen after actual application.

[0079] A left etching stopper layer 30 and a right etching stopper layer 40 are provided on the upper surfaces of the left active layer 41 and the right active layer 42 ; the left etching stopper layer 30 and the right etching stopper layer 40 are used to prevent the etching acid used in the subsequent ITO film process from damaging the left active layer 41 and the right active layer 42 .

[0080] Pixel electrode 8, fixedly arranged on the upper surface of the right etching stop layer 40, and connected with the third metal layer;

[0081] Conductive layer 9, fixedly arranged on the upper surface of the right etching stop layer 40;

[0082] Passivation layer 10, fixedly arranged on the upper surfaces of the second metal layer, the third metal layer, the left etching stop layer 30, the right etching stop layer 40, the bridging layer 5, the pixel electrode 8 and the conductive layer 9, and the passivation layer 10 is provided with a through hole 101;

[0083] Common electrode 20, fixedly arranged on the upper surface of the passivation layer 10, and connected with the conductive layer 9 through the through hole 101.

[0084] The first metal layer (gate 2), the second metal layer (source 6), the third metal layer (drain 7) and the conductive layer 9 are any one of MO single-layer structure, Ti single-layer structure, MO / AL / MO three-layer structure, Ti / AL / Ti three-layer structure, AL / MO double-layer structure and AL / Ti double-layer structure.

[0085] The left active layer 41 and the right active layer 42 are IGZO material, the left etching stop layer 30 and the right etching stop layer 40 are SiOx material, and the bridging layer 5, the pixel electrode 8 and the common electrode 20 are ITO material.

[0086] The gate insulating layer 3 is SiOx single-layer structure or SiNx / SiOx double-layer structure, and the passivation layer 10 is SiOx or SiNO or SiNx material.

[0087] The left hole 301, the right hole 401 and the through hole 101 are all inverted conical shape, which is convenient for depositing and fixing materials in the hole position.

[0088] In combination Figures 2 to 10 , the manufacturing method of the high-performance TFT array substrate with etching stop layer of the embodiment comprises the following steps:

[0089] S1, plating the first metal layer on the upper surface of the glass substrate 1 to form the gate 2;

[0090] The gate 2 is used to transmit the gate 2 signal to turn on and off the TFT device, and the material can be any one of MO single-layer structure, Ti single-layer structure, MO / AL / MO three-layer structure, Ti / AL / Ti three-layer structure, AL / MO double-layer structure and AL / Ti double-layer structure, and PVD film forming and acid liquid wet etching are adopted.

[0091] S2, plating the gate insulating layer 3 on the upper surface of the first metal layer and the glass substrate 1;

[0092] The gate insulating layer 3 serves as an insulating medium and also as a capacitor medium between the gate 2 and the active layer. The material is a SiOx single-layer structure or a SiNx / SiOx double-layer structure, and is formed by CVD and dry etching.

[0093] Considering that the current requirements for TFT devices are fast response and low power consumption, which are achieved by shrinking TFT devices, in order to achieve miniaturization of the device, a suitable high-K material (such as HfO2) needs to be selected for the gate insulating layer. However, considering that there are many defects in the interface of HfO2, if it is directly in contact with the active layer or gate metal, it may affect the stability of the device. Therefore, it is possible to consider using SiOx or SiNx with a better interface (SiNx can only be used as a contact film layer with the gate metal layer. If it is used as a contact surface with IGZO, the H remaining in the SiNx film during the film formation process will destroy the IGZO characteristics) as the contact surface, such as a SiOx / HfO2 / SiOx three-layer structure as the GI insulating layer. In order to ensure that the advantages of high-K materials are reflected, the thickness of HfO2 in the three-layer structure needs to be larger than that of SiOx.

[0094] S3, plating a left active layer 41 and a right active layer 42 on the upper surface of the gate insulating layer 3, wherein the left active layer 41 and the right active layer 42 are located above the first metal layer;

[0095] The left active layer 41 and the right active layer 42 serve as semiconductor layers, providing or closing carrier channels under the action of the gate 2 voltage. The material used is metal oxide semiconductors such as IGZO, PVD film formation, and acid wet etching.

[0096] S4, coating the left etching stopper layer 30 on the upper surface of the gate insulating layer 3 and the left active layer 41, and coating the right etching stopper layer 40 on the upper surface of the gate insulating layer 3 and the right active layer 42;

[0097] The left etch stop layer 30 and the right etch stop layer 40 are used to prevent the metal oxide semiconductor (ie, the left active layer and the right active layer) from being damaged by the etching acid used in the subsequent ITO film process. The material is SiOx, the film is formed by CVD, and the dry etching is performed.

[0098] S5, coating a bridge layer 5 on the upper surface of the gate insulating layer 3, with the left and right ends of the bridge layer 5 connected to the left active layer 41 and the right active layer 42 respectively;

[0099] Plating a pixel electrode 8 on the upper surface of the right etching stop layer 40 , wherein the pixel electrode 8 is located on the side of the bridge layer 5 ;

[0100] The bridge layer 5 connects the left and right active layers together, and the pixel electrode 8 acts as an electrode that provides an electric field for the liquid crystal molecules. Both are made of ITO, so they are formed together through PVD and wet etching with acid.

[0101] S6, opening a left hole 301 in the left etching stop layer 30, exposing the left active layer 41 through the left hole 301, and opening a right hole 401 in the right etching stop layer 40, exposing the right active layer 42 through the right hole 401;

[0102] The etching stop layer is bored by dry etching to provide small holes for connecting the source electrode 6 and the drain electrode 7 with the active layer.

[0103] S7, plating a second metal layer on the upper surface of the left etching stop layer 30, the second metal layer also passing through the left hole 301 and connected to the left active layer 41 to form a source electrode 6;

[0104] A third metal layer is plated on the upper surface of the right etching stop layer 40 . The third metal layer is also connected to the right active layer 42 through the right hole 401 . The third metal layer is also connected to the pixel electrode 8 to form a drain electrode 7 .

[0105] A conductive layer 9 is plated on the upper surface of the right etching stop layer 40 , and the conductive layer 9 is located on the side of the pixel electrode 8 ;

[0106] The source electrode 6, the drain electrode 7 and the conductive layer 9 are used to provide signals to the pixel electrode 8 and the common electrode 20. The film is formed by PVD magnetron sputtering. The material can be any one of MO single-layer structure, Ti single-layer structure, MO / AL / MO three-layer structure, Ti / AL / Ti three-layer structure, AL / MO double-layer structure, and AL / Ti double-layer structure. The etching method is acid wet etching.

[0107] S8, coating a passivation layer 10 on the upper surfaces of the second metal layer, the third metal layer, the left etching stop layer 30, the right etching stop layer 40, the bridge layer 5, the pixel electrode 8, and the conductive layer 9, wherein the passivation layer 10 is provided with a through hole 101, and the conductive layer 9 is exposed through the through hole 101;

[0108] The passivation layer 10 protects the TFT device and acts as a capacitor between the pixel electrode 8 and the common electrode 20. It can be made of insulating materials such as SiOx, SiNO, or SiNx, and is deposited using CVD and dry etching. The purpose of drilling holes above the conductive layer 9 is to transmit signals from the conductive layer 9 to the common electrode 20.

[0109] S9 , plating a common electrode 20 on the upper surface of the passivation layer 10 , wherein the common electrode 20 is connected to the conductive layer 9 through the through hole 101 .

[0110] The common electrode 20 serves as an electrode for providing an electric field to the liquid crystal molecules. The common electrode 20 is made of ITO, formed by PVD and wet-etched with acid.

[0111] Combine Figure 11 In the present invention, the positions of the common electrode 20 and the pixel electrode 8 are interchangeable, namely:

[0112] The common electrode 20 is fixedly disposed on the upper surface of the right etching stop layer 40;

[0113] A conductive layer 9 is fixedly disposed on the upper surface of the right etching stop layer 40 and is also connected to the common electrode 20;

[0114] A passivation layer 10 is fixedly disposed on the upper surfaces of the second metal layer, the third metal layer, the left etching stopper layer 30, the right etching stopper layer 40, the bridge layer 5, the common electrode 20, and the conductive layer 9, and the passivation layer 10 is provided with a through hole 101;

[0115] The pixel electrode 8 is fixedly disposed on the upper surface of the passivation layer 10 and is connected to the third metal layer through the through hole 101 .

[0116] Because ITO material has excellent electrical conductivity and light transmittance, the materials used for the bridge layer 5 and pixel electrode 8 of the TFT array substrate of the present invention are both ITO. In this structure, the bridge layer 5 and pixel electrode 8 are formed in the same process, which can simplify the structure of the array substrate, improve production capacity, and reduce costs.

[0117] Although the specific embodiments of the present invention are described above, those skilled in the art should understand that the specific embodiments described are merely illustrative and are not intended to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be included within the scope of protection of the claims of the present invention.

Claims

1. A high-performance TFT array substrate with an etch stop layer, characterized in that: include: glass substrate; A first metal layer is fixedly disposed on the upper surface of the glass substrate to form a gate; a gate insulating layer fixedly disposed on the upper surfaces of the first metal layer and the glass substrate; a left active layer, fixedly disposed on the upper surface of the gate insulating layer and also located above the left end of the first metal layer; a right active layer, fixedly disposed on the upper surface of the gate insulating layer and also located above the right end of the first metal layer; a bridging layer, fixedly disposed on the upper surface of the gate insulating layer, with left and right ends respectively connected to the left active layer and the right active layer; a left etching stop layer, fixedly disposed on the upper surfaces of the gate insulating layer and the left active layer, and further having a left hole; a right etching stop layer, fixedly disposed on the upper surfaces of the gate insulating layer and the right active layer, and further having a right hole; a second metal layer, fixedly disposed on the upper surface of the left etching stop layer, and also passing through the left hole to connect with the left active layer to form a source electrode; a third metal layer, fixedly disposed on the upper surface of the right etching stop layer, and also passing through the right hole to connect with the right active layer to form a drain; The left active layer and the right active layer are both made of IGZO material, the left etching stop layer and the right etching stop layer are both made of SiOx material, and the bridge layer is made of ITO material; The gate insulating layer is a SiOx single-layer structure or a SiNx / SiOx double-layer structure.

2. The high-performance TFT array substrate with an etching stop layer according to claim 1, characterized in that: Also includes: a pixel electrode, fixedly disposed on the upper surface of the right etching stop layer and connected to the third metal layer; a conductive layer fixedly disposed on the upper surface of the right etching stop layer; A passivation layer is fixedly disposed on the upper surfaces of the second metal layer, the third metal layer, the left etching stop layer, the right etching stop layer, the bridge layer, the pixel electrode, and the conductive layer, wherein the passivation layer is provided with a through hole; The common electrode is fixedly arranged on the upper surface of the passivation layer and is connected to the conductive layer through the through hole.

3. The high-performance TFT array substrate with an etching stop layer according to claim 1, characterized in that: Also includes: A common electrode is fixedly disposed on the upper surface of the right etching stop layer; a conductive layer, fixedly disposed on the upper surface of the right etching stop layer and connected to the common electrode; A passivation layer is fixedly arranged on the upper surfaces of the second metal layer, the third metal layer, the left etching stop layer, the right etching stop layer, the bridge layer, the common electrode, and the conductive layer, and the passivation layer is provided with a through hole; The pixel electrode is fixedly arranged on the upper surface of the passivation layer and is connected to the third metal layer through the through hole.

4. The high-performance TFT array substrate with an etching stop layer according to claim 2, wherein: The first metal layer, the second metal layer, the third metal layer, and the conductive layer are any one of a MO single-layer structure, a Ti single-layer structure, a MO / AL / MO three-layer structure, a Ti / AL / Ti three-layer structure, an AL / MO double-layer structure, and an AL / Ti double-layer structure.

5. The high-performance TFT array substrate with an etching stop layer according to claim 2, characterized in that: The left dug hole, the right dug hole and the through hole are all in an inverted cone shape.

6. A method for manufacturing a high-performance TFT array substrate with an etching stop layer, characterized in that: The following steps are involved: S1, plating a first metal layer on the upper surface of the glass substrate to form a gate; S2, coating a gate insulating layer on the upper surface of the first metal layer and the glass substrate; S3, plating a left active layer and a right active layer on the upper surface of the gate insulating layer, wherein the left active layer and the right active layer are located above the first metal layer; S4, coating a left etching stop layer on the upper surface of the gate insulating layer and the left active layer, and coating a right etching stop layer on the upper surface of the gate insulating layer and the right active layer; S5, plating a bridge layer on the upper surface of the gate insulating layer, wherein the left and right ends of the bridge layer are connected to the left active layer and the right active layer respectively; S6, opening a left hole in the left etching stop layer, exposing the left active layer from the left hole, and opening a right hole in the right etching stop layer, exposing the right active layer from the right hole; S7, plating a second metal layer on the upper surface of the left etching stop layer, wherein the second metal layer is further connected to the left active layer through the left hole to form a source electrode; Plating a third metal layer on the upper surface of the right etching stop layer, wherein the third metal layer also passes through the right hole and is connected to the right active layer to form a drain; The left active layer and the right active layer are both made of IGZO material, the left etching stop layer and the right etching stop layer are both made of SiOx material, and the bridge layer is made of ITO material.

7. The method for manufacturing a high-performance TFT array substrate with an etching stop layer according to claim 6, wherein: The S5 further includes: plating a pixel electrode on the upper surface of the right etching stop layer, wherein the pixel electrode is located on the side of the bridge layer; The step S7 further includes: the third metal layer is further connected to the pixel electrode; and a conductive layer is plated on the upper surface of the right etching stop layer, wherein the conductive layer is located on the side of the pixel electrode.

8. The method for manufacturing a high-performance TFT array substrate with an etching stop layer according to claim 7, wherein: Also includes: S8, coating a passivation layer on the upper surfaces of the second metal layer, the third metal layer, the left etching stop layer, the right etching stop layer, the bridge layer, the pixel electrode, and the conductive layer, wherein the passivation layer is provided with a through hole, and the conductive layer is exposed through the through hole; S9. Plating a common electrode on the upper surface of the passivation layer, wherein the common electrode is connected to the conductive layer through the through hole.

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