Surface acoustic wave (SAW) filter and method for manufacturing the same

Abstract

The present application provides a surface acoustic wave (SAW) filter, comprising: a bottom substrate; a piezoelectric layer disposed above the bottom substrate, wherein the piezoelectric layer has a bottom surface facing the bottom substrate and a top surface opposite to the bottom surface; a cavity disposed below the piezoelectric layer; a first interdigital transducer (IDT) disposed on the bottom surface of the piezoelectric layer, and a second IDT disposed on the top surface of the piezoelectric layer; wherein the interdigital portion of the first IDT is exposed in the cavity, and the interdigital portion of the second IDT is vertically aligned with the interdigital portion of the first IDT. The present application also provides a method for manufacturing a SAW filter.

Description

Technical Field

[0001] The present application relates to the field of semiconductor devices, and in particular to a surface acoustic wave (SAW) filter and a manufacturing method thereof. Background Art

[0002] Surface acoustic wave (SAW) devices, such as SAW resonators and SAW filters, are used in many applications such as radio frequency (RF) filters. A typical SAW filter includes a plurality of interdigital transducers (IDTs) formed on a piezoelectric substrate. The plurality of IDTs are connected in series or in parallel.

[0003] As the use of SAW filters in modern RF communication systems increases, there is a growing need for SAW filters with improved quality factor (Q). Summary of the invention

[0004] According to one aspect of the present disclosure, a surface acoustic wave (SAW) filter is provided. The SAW filter comprises: a bottom substrate; a piezoelectric layer disposed above the bottom substrate, and the piezoelectric layer has a bottom surface facing the bottom substrate and a top surface opposite to the bottom surface; a cavity disposed below the piezoelectric layer; a first interdigital transducer (IDT) disposed on the bottom surface of the piezoelectric layer, and a second IDT disposed on the top surface of the piezoelectric layer; wherein the interdigital portion of the first IDT is exposed in the cavity, and the interdigital portion of the second IDT is vertically aligned with the interdigital portion of the first IDT.

[0005] According to one aspect of the present disclosure, a method for manufacturing a surface acoustic wave (SAW) filter is provided. The method includes: obtaining a piezoelectric substrate; forming a first interdigital transducer (IDT) on a first portion of the piezoelectric substrate; forming a first pad metal layer on the first IDT, wherein a first portion of the first pad metal layer is formed on a first input and output end of the first IDT, and a second portion of the first pad metal layer is formed on a second input and output end of the first IDT; forming a first dielectric layer covering the first IDT and the first pad alloy layer on the first portion of the piezoelectric substrate; forming a groove in the first dielectric layer that exposes a portion of the first portion of the piezoelectric substrate, wherein the groove surrounds the first dielectric layer; The invention relates to a method for forming a piezoelectric substrate having a first dielectric layer covering a portion of the interdigital portion of the first IDT; forming a second dielectric layer covering the sidewalls and the bottom of the groove on the first dielectric layer; forming a third dielectric layer filling the groove on the second dielectric layer; bonding the bottom substrate to the third dielectric layer; removing the second portion of the piezoelectric substrate and leaving the first portion of the piezoelectric substrate so that the first portion of the piezoelectric substrate constitutes a piezoelectric layer; forming a second IDT on the piezoelectric layer; and etching and releasing the portion of the first dielectric layer surrounded by the groove through a release hole formed in the piezoelectric layer to form a cavity below the interdigital portion of the first IDT. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate the disclosed embodiments and, together with the description, serve to explain the disclosed embodiments.

[0007] Figure 1A is a cross-sectional view of a SAW filter provided according to an embodiment of the present disclosure;

[0008] Figure 1B According to one embodiment of the present disclosure, Figure 1A A top view of a selected portion of a SAW filter;

[0009] Figure 1C According to one embodiment of the present disclosure, Figure 1A A top view of other selected portions of the SAW filter;

[0010] Figure 1D is a top view of an interdigital transducer IDT provided according to an embodiment of the present disclosure;

[0011] Figure 1E is a cross-sectional view of a SAW filter provided according to an embodiment of the present disclosure;

[0012] Figure 2 According to one embodiment of the present disclosure, a manufacturing method is provided. Figure 1A Flow chart of the SAW filter process;

[0013] Figures 3A-3N According to one embodiment of the present disclosure, Figure 2 A cross-sectional view of a structure formed in a process of

[0014] Figure 4 A manufacturing method according to an embodiment of the present disclosure is provided Figure 1E Flowchart of a SAW filter. DETAILED DESCRIPTION

[0015] The following text describes the present disclosure in detail in conjunction with the specific embodiments shown in the accompanying drawings. However, these embodiments do not limit the present disclosure. The protection scope of the present invention includes changes made to the structure, method or function by ordinary technicians in this field based on these embodiments.

[0016] In order to facilitate the presentation of the drawings in the present disclosure, the size of some structures or parts may be enlarged relative to other structures or parts. Therefore, the drawings in the present disclosure are only used for the purpose of illustrating the basic structure of the subject matter of the present disclosure. Unless otherwise specified, the same numbers in different drawings represent the same or similar elements.

[0017] In addition, terms indicating relative spatial positions, such as "top", "bottom", "upper", "lower", "above", "below", etc., are used herein to describe the relationship between an element or feature depicted in a figure and another element or feature therein for purposes of explanation. Terms indicating relative spatial positions may refer to positions other than those depicted in the drawings when the device is in use or operation. For example, if the device shown in the figure is turned over, a unit described as being "below" or "below" another element or feature would be "above" the other element or feature. Thus, the illustrative term "below" may include both above and below positions. The device may be oriented in other ways (e.g., rotated 90 degrees or facing another direction), and descriptive terms appearing in the text and relating to space should be interpreted accordingly. When a component or layer is referred to as being "on" or "connected to" another component or layer, it can be directly on or directly connected to the other component or layer, or there may be intervening components or layers.

[0018] Figure 1A is a cross-sectional view of a SAW filter 1000 provided according to an embodiment of the present disclosure. Figure 1B is a top view of selected portions of a SAW filter 1000 provided according to one embodiment of the present disclosure. Figure 1B The cross section of the selected part along the A-A' line is as follows Figure 1A shown. Figure 1C is a top view of other selected portions of the SAW filter 1000 provided according to one embodiment of the present disclosure. Figure 1C The cross section of the selected part along the line A-A' is as follows Figure 1A As shown. Figure 1A , 1B As shown in 1C, the SAW filter 1000 includes: a bottom substrate 210 and a piezoelectric layer 140 arranged above the bottom substrate 210, the piezoelectric layer 140 having a bottom surface 140a facing the bottom substrate 210 and a top surface 140b parallel to and opposite to the bottom surface 140a; a cavity 500 arranged below the piezoelectric layer 140; a first interdigital transducer IDT130 arranged on the bottom surface 140a of the piezoelectric layer 140; and a second interdigital transducer IDT160 arranged on the top surface 140b of the piezoelectric layer 140.

[0019] Figure 1D FIG. 1 is a top view of an IDT 130 provided according to an embodiment of the present disclosure. Figure 1DAs shown, the first IDT 130 includes a first input and output terminal 131, a second input and output terminal 132, and an interdigital portion 133. The interdigital portion 133 includes a first group of electrode fingers 1331 coupled to the first input and output terminal 131 and a second group of electrode fingers 1332 coupled to the second input and output terminal 132. The second group of electrode fingers 1332 are staggered and parallel to the first group of electrode fingers 1331. The interdigital portion 133 of the first IDT 130 is exposed in the cavity 500.

[0020] Similar to IDT130, the second IDT160 includes a first input and output terminal 161, a second input and output terminal 162 and a forked finger portion 163. The forked finger portion 163 includes a first group of electrode fingers coupled to the first input and output terminal 161 and a second group of electrode fingers 1332 coupled to the second input and output terminal 162. The second group of electrode fingers are staggered and parallel to the first group of electrode fingers. The forked finger portion 163 of the second IDT160 is vertically aligned with the forked finger portion 133 of the first IDT130.

[0021] Reference again Figure 1A , 1B 1C, a first pad metal layer 310 is disposed under the first IDT 130. A first portion 311 of the first pad metal layer 310 is disposed under the first input and output terminal 131 of the first IDCT 130 and is electrically connected to the first input and output terminal 131 of the first IDCT 130. A second portion 312 of the first pad metal layer 310 is disposed under the second input and output terminal 132 of the first IDT 130 and is electrically connected to the second input and output terminal 132 of the first IDT 130.

[0022] The first dielectric layer 180 is disposed between the piezoelectric layer 140 and the bottom substrate 210, and covers the bottom surface 140a of the piezoelectric layer 140, the first input and output terminals 131 and the second input and output terminals 132 of the first IDT 130, and the first portion 311 and the second portion 312 of the first pad metal layer 310. The second dielectric layer 240 is disposed below the first dielectric layer 180 and contacts a portion of the bottom surface 140a of the piezoelectric layer 140. The third dielectric layer 250 is disposed below the second dielectric layer 240 and includes a protruding structure 251 protruding toward the piezoelectric layer 140. The protruding structure 251 and a portion of the second dielectric layer 240 disposed on the sidewall of the protruding structure 251 constitute a double-wall boundary structure 350 surrounding the cavity 500. In other words, the piezoelectric layer 140, the second dielectric layer 240, and the third dielectric layer 250 together surround the cavity 500.

[0023] A release hole 145 is formed in the piezoelectric layer 140, and the release hole 145 is connected to the cavity 500. The release hole 145 is used to release an etchant and an etching product in an etching and releasing process for forming the cavity 500.

[0024] The first dielectric layer 180 may be formed of silicon oxide, silicon nitride, or a stacked combination of these materials. The second dielectric layer 240 may be formed of a non-conductive material that cannot be etched by hydrofluoric acid, including but not limited to polysilicon, amorphous silicon, AlN, SiN, TaN, GaN, or a stacked combination of two or more of these materials. The third dielectric layer 250 may be formed of silicon oxide, silicon nitride, or a stacked combination of these materials. The bottom substrate 210 may be made of Si, SiO 2 , polysilicon, silicon carbide, sapphire (Al 2 O 3 ) or a stacked combination of two or more of these materials. The base substrate 210 may be bonded to the third dielectric layer 250.

[0025] A first opening 441 is formed in the piezoelectric layer 140 , exposing a portion of the first input and output terminal 131 of the IDT 130 . A second opening 442 is formed in the piezoelectric layer 140 , exposing a portion of the second input and output terminal 132 of the IDT 130 .

[0026] The second pad metal layer 300 is disposed on the piezoelectric layer 140. The first portion 301 of the second pad metal layer 300 is disposed in the first opening 441 of the piezoelectric layer 140 and is electrically connected to the first input and output terminal 131 of the first IDT 130 through the first opening 441. The second portion 302 of the second pad metal layer is disposed in the second opening 442 of the piezoelectric layer 140 and is electrically connected to the second input and output terminal 132 of the first IDT 130 through the second opening 442. The third portion 303 of the second pad metal layer 300 is disposed above the first input and output terminal 161 of the second IDT 160 and is electrically connected to the first input and output terminal 161 of the second IDT 160. The fourth portion 304 of the second pad metal layer is electrically connected to the second input and output terminal 162 of the second IDT 260.

[0027] Figure 1E 1 is a cross-sectional view of a SAW filter 1001 according to an embodiment of the present disclosure. The SAW filter 1001 is different from the SAW filter 1000 in that the SAW filter 1001 includes a non-conductive layer 320 and a buffer layer 330 disposed between the third dielectric layer 250 and the base substrate 210 .

[0028] Specifically, the non-conductive layer 320 is disposed above the bottom substrate 210, and the buffer layer 330 is disposed above the non-conductive layer 310. The functions of the non-conductive layer 330 and the buffer layer 330 are to make the bonding of the bottom substrate 210 easier and ensure the bonding quality, or to improve the performance of the SAW filter 1001 by improving the quality factor Q of the SAW resonator. The non-conductive layer 320 can be formed of polycrystalline silicon, amorphous silicon, silicon nitride, aluminum nitride, gallium nitride, or a stacked combination of two or more of these materials. The non-conductive layer 320 is used to improve the quality factor Q of the SAW resonator. The buffer layer 330 can be formed of silicon nitride, silicon oxide, or a stacked combination of these materials. The buffer layer 330 is used to create a suitable bonding surface for the bottom substrate 210, or to balance the warping of the bottom substrate 210, so that the bottom substrate 210 is more smoothly bonded to the third dielectric layer 250.

[0029] In some alternative embodiments, the SAW filter may include only one of the non-conductive layer 320 and the buffer layer 330. For example, the SAW filter may include the non-conductive layer 320 disposed between the third dielectric layer 250 and the bottom substrate 210. Alternatively, the SAW filter may include the buffer layer 330 disposed between the third dielectric layer 250 and the bottom substrate 210.

[0030] The structure and components of the SAW filter 1001 are the same as those of the SAW filter 1000 except for the non-conductive layer 320 and the buffer layer 330 , and thus, a detailed description of the other components of the SAW filter 1001 will not be repeated.

[0031] Figure 2 FIG. 1 is a flowchart of a process of manufacturing a SAW filter 1000 according to an embodiment of the present disclosure. Figures 3A-3N According to one embodiment of the present disclosure, Figure 2 A cross-sectional view of a structure formed in the process.

[0032] like Figure 3A As shown, in step S1, a piezoelectric substrate 100 is obtained. The piezoelectric substrate may be a lithium niobate or lithium tantalate single crystal substrate.

[0033] like Figure 3B As shown, in step S2, ions are implanted into the piezoelectric substrate 100 at a predetermined implantation depth d, thereby forming an ion layer 101 at the depth d of the piezoelectric substrate 200. The ions may be helium ions or hydrogen ions. The implantation depth d may be determined based on the desired thickness of the piezoelectric layer 140. For example, the implantation depth d may range from about 0.3 μm to about 10 μm. The first portion 100 a of the piezoelectric substrate 100 is disposed above the ion layer 101, and the second portion 100 b of the piezoelectric substrate is disposed below the ion layer 101.

[0034] like Figure 3C As shown, in step S3, a first IDT 130 is formed on the first portion 100a of the piezoelectric substrate 100. The first IDT 130 includes a first input and output terminal 131, a second input and output terminal 132, and an interdigital portion 133 disposed between the first input and output terminal 131 and the second input and output terminal 132.

[0035] like Figure 3D As shown, in step S4, Figure 3C The first pad metal layer 310 is formed on the structure. Then, the first pad metal layer 310 is patterned to form: a first portion 311 disposed over the first input and output terminal 131 of the first IDT 130 and electrically connected to the first input and output terminal 131 of the first IDT 130; and a second portion 312 disposed over the second input and output terminal 132 of the first IDCT 130 and electrically connected to the second input and output terminal 132 of the first IDCT 130.

[0036] like Figure 3E As shown, in step S5, a first dielectric layer 180 is deposited on the first portion 100a of the piezoelectric substrate 100, and the first dielectric layer 180 covers the first IDT 130 and the first pad metal layer 310. The first dielectric layer 180 may include silicon oxide, silicon nitride, or a stacked combination of these materials. The first dielectric layer 180 may be deposited using a physical vapor deposition (PVD) process or a low-temperature chemical vapor deposition (CVD) process.

[0037] like Figure 3F As shown, in step S6, the first dielectric layer 180 is patterned by etching to form a groove 190 exposing the first portion 100a of the piezoelectric substrate 100. The patterned first dielectric layer 180 includes a peripheral portion 181 and an island portion 182 separated from each other by the groove 190. The peripheral portion 181 surrounds the groove 190, and the island portion 182 is vertically aligned with the interdigital portion 133 of the first IDT 130. The island portion 182 will be removed in the subsequent etching and release process, thereby forming a cavity 500.

[0038] like Figure 3G As shown, in step S7, Figure 3FThe second dielectric layer 240 is deposited on the structure of the first dielectric layer 180. That is, the second dielectric layer 240 is deposited on the top surface of the first dielectric layer 180, the side of the groove 190, and a portion of the first portion 100a of the piezoelectric substrate 100 exposed by the groove 190. Therefore, the island portion 182 of the first dielectric layer 180 is surrounded by the second dielectric layer 240 and the first portion 100a of the piezoelectric substrate 100. Therefore, the cavity 500 formed subsequently is surrounded by the second dielectric layer 240 and the piezoelectric layer 140. The second dielectric layer 240 may be formed of a non-conductive material that cannot be etched by hydrofluoric acid, including but not limited to polysilicon, amorphous silicon, AlN, SiN, TaN, GaN, or a stacked combination of two or more of these materials.

[0039] like Figure 3H As shown, in step S8, Figure 3G The third dielectric layer 250 is deposited on the structure of the piezoelectric substrate 100. That is, the third dielectric layer 250 is deposited on the second dielectric layer 240 and fills in the groove 190. The portion of the third dielectric layer 250 that fills the groove 190 constitutes a protruding structure 251 in the SAW filter 1000. Then, the top surface of the third dielectric layer 250 is polished by a polishing process such as chemical mechanical polishing (CMP) so that the top surface of the third dielectric layer 250 is parallel to the main plane of the piezoelectric substrate 100. The third dielectric layer 250 can be a non-conductive material, such as silicon oxide, silicon nitride, or a stacked combination thereof.

[0040] like Fig. 3I As shown, in step S9, the base substrate 210 is bonded to the third dielectric layer 250. The base substrate 210 may include Si, SiO 2 , polysilicon, silicon carbide, sapphire (Al 2 O 3 ) or a stacked combination of two or more of these materials.

[0041] like Figure 3J As shown, in step S10, flip Fig. 3IThe structure shown in FIG. 1 is formed by removing the second portion 100b of the piezoelectric substrate 100 below the ion layer 101 and performing thermal annealing on the structure. The thermal annealing temperature may be in the range of about 400° C. to about 650° C. After the thermal annealing, the ion layer 101 in the piezoelectric substrate 100 is destroyed. The second portion 100b of the piezoelectric substrate 100 below the ion layer 101 is removed, and the first portion 100a of the piezoelectric substrate 100 above the ion layer 101 is retained. The first portion 100a of the piezoelectric substrate 100 constitutes the piezoelectric layer 140 in the SAW filter 1000. The piezoelectric layer 130 has a bottom surface 140a on which the first IDT 130 is formed, and an exposed top surface 140b. CMP is performed on the exposed top surface 140b of the piezoelectric layer 140 to obtain a smooth surface and achieve the desired thickness of the piezoelectric layer in the SAW filter 1000. In some embodiments, an ion beam etching (IBE) or ion beam milling process may be performed on the piezoelectric layer 140 to achieve a more uniform thickness.

[0042] like Figure 3K As shown, in step S11, a second IDT 160 is formed on the top surface 140b of the piezoelectric layer 140. The second IDT 160 includes a first input and output terminal 161, a second input and output terminal 162, and an interdigital portion 163 disposed between the first input and output terminal 161 and the second input and output terminal 162. The interdigital portion 163 of the second IDT 160 is vertically aligned with the interdigital portion 133 of the first IDT 130.

[0043] like Figure 3L As shown, in step S12, the piezoelectric layer 140 is etched to form: a first opening 441 exposing a portion of the first input and output terminal 131 of the first IDT 130; a second opening 442 exposing a portion of the second input and output terminal 132 of the first IDT 130; and a release hole 145 exposing a portion of the island portion 182 of the first dielectric layer 180. The release hole 145 is used to form the cavity 500 in the subsequent etching and release processes.

[0044] like Figure 3M As shown, in step S13, Figure 3LThe second pad metal layer 300 is formed on the structure. Then, the second pad metal layer 300 is patterned to form: a first portion 301 disposed in the first opening 441 and electrically connected to the first input and output terminal 131 of the first IDT 130 via the first opening 441; a second portion 302 disposed in the second opening 442 and electrically connected to the second input and output terminal 132 of the first IDT 130 via the second opening 445; a third portion 303 disposed above the first input and output terminal 161 of the second IDT 160 and electrically connected to the first input and output terminal 161 of the second IDT 160; and a fourth portion 304 disposed above the second input and output terminal 162 of the second IDT 160 and electrically connected to the second input and output terminal 162 of the second IDT 160.

[0045] like Figure 3N As shown, in step S14, the island portion 182 of the first dielectric layer 180 is etched and released through the release hole 145 to form a cavity 500 below the interdigital portion 133 of the first IDT 130. The island portion 182 can be formed by using XeF 2 The etching is performed by a plasma dry etching process. The etchant and etching products of the etching process can be released through the release holes formed in the piezoelectric layer in step S11. Figure 1A The SAW filter 1000 shown is manufactured.

[0046] Figure 4 A manufacturing method according to an embodiment of the present disclosure is provided Figure 1E 1 is a process flow chart of the SAW filter 1001. The process of manufacturing the SAW filter 1001 is the same as the process of manufacturing the SAW filter 1000, except that: in step S8, a base substrate 210 is obtained, at least one of the non-conductive layer 320 or the buffer layer 330 is deposited on the base substrate 210, and then the base substrate 210 on which at least one of the non-conductive layer 330 or the buffer layer 300 is deposited is bonded to the third dielectric layer 250. When both the non-conductive layer 320 and the buffer layer 330 are deposited on the base substrate 210, the non-conductive layer 320 is first deposited on the base substrate 210, and then the buffer layer 330 is deposited on the non-conductive layer 320.

[0047] The manufacturing process of the SAW filter 1001 is the same as the manufacturing process of the SAW filter 1000 except step S9, and thus detailed description of the other steps of manufacturing the SAW filter 1001 will not be repeated.

[0048] In the SAW filters 1000 and 1001 provided according to the embodiments of the present invention, the first IDT 130 and the second IDT 160 are arranged on both sides of the piezoelectric layer 140. Therefore, the size of the filter chip can be reduced, thereby realizing the miniaturization of the filter chip. For example, some IDTs of a single-frequency filter are arranged on one side of the piezoelectric layer, while the IDTs of another single-frequency filter are arranged on the other side of the piezoelectric layer, thereby reducing the area of ​​the filter chip. For example, the first filter of the first frequency band is arranged on one side of the piezoelectric layer, and the second filter of the second frequency band is arranged on the opposite side of the piezoelectric layer. That is, a filter device with two frequency bands can be realized by using the same piezoelectric area.

[0049] In addition, since the first IDT 130 and the second IDT 160 are disposed on both sides of the piezoelectric layer 140 , a higher effective electromechanical coupling coefficient of the resonant device, also referred to as Keff2, can be obtained.

[0050] Other embodiments of the invention will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and examples be considered exemplary only, with the true scope and spirit of the invention being indicated by the following claims.

Claims

1. A surface acoustic wave (SAW) filter, It is characterized in that include: bottom substrate; a piezoelectric layer disposed above the bottom substrate and having a bottom surface facing the bottom substrate and a top surface opposite to the bottom surface; a cavity disposed below the piezoelectric layer; A first interdigital transducer IDT is disposed on the bottom surface of the piezoelectric layer, and a finger portion of the first IDT is exposed in the cavity; A second IDT is disposed on the top surface of the piezoelectric layer, the interdigital portion of the second IDT is vertically aligned with the interdigital portion of the first IDT, the first IDT and the second IDT each include a first input and output terminal, a second input and output terminal and an interdigital portion, the interdigital portion includes a first group of electrode fingers coupled to the first input and output terminal and a second group of electrode fingers coupled to the second input and output terminal, the second group of electrode fingers are staggered and parallel to the first group of electrode fingers; A first pad metal layer is formed below the first IDT; wherein a first portion of the first pad metal layer is electrically connected to a first input and output terminal of the first IDT, and a second portion of the first pad metal layer is electrically connected to a second input and output terminal of the first IDT; a first opening formed in the piezoelectric layer and exposing first input and output terminals of the first IDT; a second opening formed in the piezoelectric layer and exposing second input and output terminals of the first IDT; A second pad metal layer is formed on the piezoelectric layer; wherein a first portion of the second pad metal layer is electrically connected to a first input and output terminal of the first IDT via a first opening, a second portion of the second pad metal layer is electrically connected to a second input and output terminal of the first IDT via a second opening, a third portion of the second pad metal layer is electrically connected to the first input and output terminal of the second IDT, and a fourth portion of the second pad metal layer is electrically connected to the second input and output terminal of the second IDT; A first dielectric layer, disposed between the piezoelectric layer and the bottom substrate, covers the bottom surface of the piezoelectric layer, the first input and output terminals and the second input and output terminals of the first IDT, and the first portion and the second portion of the first pad metal layer; a second dielectric layer disposed below the first dielectric layer; The third dielectric layer is disposed below the second dielectric layer and includes a protruding structure protruding toward the first dielectric layer; wherein the cavity is surrounded by a double-wall boundary structure formed by the second dielectric layer and the protruding structure of the third dielectric layer.

2. The SAW filter according to claim 1, It is characterized in that The bottom substrate is made of Si, SiO 2 , polysilicon, silicon carbide, sapphire Al 2 O 3 or a stacked combination of two or more of these materials; and The bottom substrate is bonded to the third dielectric layer.

3. The SAW filter according to claim 1, It is characterized in that The first dielectric layer is formed of silicon oxide, silicon nitride, or a stacked combination of these materials.

4. The SAW filter according to claim 1, It is characterized in that The second dielectric layer is formed of polysilicon, amorphous silicon, AlN, SiN, TaN, GaN, or a stacked combination of two or more of these materials.

5. The SAW filter according to claim 1, It is characterized in that The third dielectric layer is formed of silicon oxide, silicon nitride, or a stacked combination of these materials.

6. The SAW filter according to claim 1, It is characterized in that Also includes: a non-conductive layer disposed between the third dielectric layer and the bottom substrate, wherein the non-conductive layer is formed of polysilicon, amorphous silicon, silicon nitride, aluminum nitride, gallium nitride, or a stacked combination of two or more of these materials; and The buffer layer is disposed between the third dielectric layer and the non-conductive layer; wherein the buffer layer is formed of silicon nitride, silicon oxide or a stacked combination of these materials.

7. A method for manufacturing a surface acoustic wave (SAW) filter according to any one of claims 1 to 6, It is characterized in that include: obtaining a piezoelectric substrate; forming a first interdigital transducer (IDT) on a first portion of the piezoelectric substrate; forming a first pad metal layer on the first IDT; wherein a first portion of the first pad metal layer is formed on the first input and output terminals of the first IDT, and a second portion of the first pad metal layer is formed on the second input and output terminals of the first IDCT; forming a first dielectric layer on a first portion of the piezoelectric substrate; wherein the first dielectric layer covers the first IDT and the first pad metal layer; forming a groove in the first dielectric layer; wherein the groove exposes a portion of the first portion of the piezoelectric substrate, and the groove surrounds a portion of the first dielectric layer covering the first IDT interdigital portion; forming a second dielectric layer on the first dielectric layer to cover the sidewalls and bottom of the trench; forming a third dielectric layer on the second dielectric layer; wherein the third dielectric layer is filled in the trench; bonding the bottom substrate to the third dielectric layer; wherein, before bonding the bottom substrate to the third dielectric layer: forming a non-conductive layer on the bottom substrate; and, forming a buffer layer on the non-conductive layer; removing the second portion of the piezoelectric substrate and retaining the first portion of the piezoelectric substrate; wherein the first portion of the piezoelectric substrate constitutes a piezoelectric layer; forming a second IDT on the piezoelectric layer; etching and releasing a portion of the first dielectric layer surrounded by the trench through a release hole formed in the piezoelectric layer to form a cavity below an interdigitated portion of the IDT; forming a first opening in the piezoelectric layer exposing a first input and output terminal of the IDT, forming a second opening in the piezoelectric layer exposing a second input and output terminal of the IDT, and forming a release hole exposing a portion of the first dielectric layer surrounded by the trench; and A second pad metal layer is formed on the piezoelectric layer; wherein a first portion of the second pad metal layer is electrically connected to the first input and output ends of the first IDT via the first opening, a second portion of the second pad metal layer is electrically connected to the second input and output ends of the first IDT via the second opening, a third portion of the second pad metal layer is electrically connected to the first input and output ends of the second IDT, and a fourth portion of the second pad metal layer is electrically connected to the second input and output ends of the second IDT.

8. The method according to claim 7, It is characterized in that Also includes: Before forming the first IDT on the first portion of the piezoelectric substrate, ions are implanted into the piezoelectric substrate to form an ion layer at a predetermined depth of the piezoelectric substrate; wherein the first portion of the piezoelectric substrate is disposed above the ion layer and the second portion of the piezoelectric substrate is disposed below the ion layer; After bonding the bottom substrate to the third dielectric layer, thermal annealing is performed to destroy the ion layer in the piezoelectric substrate, thereby removing the second portion of the piezoelectric substrate.

9. The method according to claim 7, It is characterized in that The first dielectric layer is formed of silicon oxide, silicon nitride, or a stacked combination of these materials; The second dielectric layer is formed of polysilicon, amorphous silicon, AlN, SiN, TaN, GaN, or a stacked combination of two or more of these materials; and The third dielectric layer is formed of silicon oxide, silicon nitride, or a stacked combination of these materials.

10. The method according to claim 7, It is characterized in that The piezoelectric substrate is a lithium niobate or lithium tantalate single crystal substrate.

11. The method according to claim 7, It is characterized in that The bottom substrate is made of Si, SiO 2 , polysilicon, silicon carbide, sapphire Al 2 O 3 Or a stacked combination of two or more materials.

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