A sampling phase detector and phase-locked loop system

Abstract

The present invention relates to a sampling phase detector and a phase-locked loop system, wherein the sampling phase detector comprises: a ramp generator, comprising: an input end of a first inverter P1 for generating a ramp wave clock signal f ref The output terminal is electrically connected to the gate of M1, the drain of M1 is connected to the power supply, the source of M1 is electrically connected to the drain of M2, and the gate of M2 is the control clock signal f div The source of M2 is electrically connected to the drain of M3 and one end of the first capacitor C1, the other end of C1 is grounded, the gate of M3 is electrically connected to the output end of the second inverter P2, and the input end of P2 is f div , the source of M3 is electrically connected to the drain of M4, the source of M4 is grounded, f div The sample-hold filter module is electrically connected to the gate of M4 via buffers 1, 2, and 3. The sample-hold filter module includes a switch circuit composed of M5 and M6, and a filter composed of R, C2, and C3. This application solves the problem of poor linearity in sampling phase detectors in related technologies and improves the linearity of the sampling phase detector.

Description

Technical Field

[0001] The present invention relates to the technical field of phase-locked loops, and in particular to a sampling phase detector and a phase-locked loop system. Background Art

[0002] There are two methods for suppressing and offsetting the phase noise of the phase-locked loop (PLL) system: module-level optimization and system-level optimization. For the PLL system-level optimization solution, some commonly used architectures include sub-sampling phase-locked loops and sampling phase-locked loops. The sampling phase-locked loop increases the gain of the sampling phase detector (SPD), which has a good suppressive effect on the phase noise equivalent to the output of other modules including the charge pump and SPD in the system loop. For the integer sampling phase-locked loop, the greater the gain of the sampling phase detector (SPD), the better. However, at the same time, while meeting the gain requirement, it is also necessary to ensure excellent linearity. The integer sampling phase-locked loop structure is as follows: Figure 1 shown.

[0003] The principle of sampling phase-locked loop is: Figure 1 As shown in Figure 1, a sampling phase-locked loop consists of a voltage-controlled oscillator (VCO), a divider, a sampling phase detector (SPD), a transconductance (Gm), a loop filter, and a delta-sigma modulator that controls the fractional frequency division. The SPD is usually composed of a slope generator and a sample-and-hold circuit. The working mechanism of a sampling phase-locked loop is as follows: First, the reference clock frequency f ref The ramp generator in the SPD generates a ramp signal with a certain slope, and then the frequency divider outputs the signal f div The sampled voltage V sam The current signal is converted into a current signal by the transconductance amplifier Gm, and the phase error contained in it is also converted into a current signal. Then, the high-frequency signal is filtered out by the low-pass filter LPF to generate the VCO control signal V ctrl The VCO output signal is divided by the frequency divider and fed back to the input to form a closed-loop feedback.

[0004] The sampling phase detector (SPD) in a sampling phase-locked loop (PLL) functions as follows: The sampling phase detector (SPD) consists of a ramp generator and a sample-and-hold circuit. It converts the phase difference between the feedback signal from the frequency divider and the reference signal into a voltage signal. Specifically, the ramp generator generates a signal with a certain slope on the rising or falling edge of the reference signal. This ramp is output by the frequency divider and sampled by the sample-and-hold circuit. The deviation of the sampled signal from the midpoint of the ramp signal represents the phase difference between the two signals. In this way, the phase difference is converted into a voltage.

[0005] The sampling phase detector structure currently used is as follows: Figure 2 As shown in Figure 1, it consists of two parts: a slope generator and a sample-and-hold circuit. The slope generator is composed of an inverter with an RC delay. First, the reference signal f ref After passing through an inverter, it is fed to an inverter with RC delay. Due to the RC delay at the output of the second inverter, the output signal will have a certain slope. Then, it passes through a two-stage sampling and holding circuit to generate a sampling voltage V sam In the sampling and holding phase, the two sampling switches are respectively div and f div The reverse signal is controlled by two non-overlapping clocks clk1 and clk2 to control the sampling and holding stages. When the switch controlled by clk1 is turned on, the switch controlled by clk2 is turned off, and the first stage enters the sampling stage V sam1 The voltage value is obtained by sampling, and the output remains unchanged; when the switch controlled by clk2 is turned on and the switch controlled by clk1 is turned off, the second-level sampling updates the output voltage value V sam .

[0006] The timing waveform of the sampling phase detector is as follows: Figure 3 As shown. First, analyze the ramp generator. When f ref When it is low, that is, clk ref = 0, the NMOS tube of the second inverter is turned on, the PMOS tube is turned off, and the output of the ramp generator is low level; when f ref When it is high, that is, clk ref =1, at this time, the second inverter NMOS of the ramp generator is turned off, the PMOS is turned on, and the level of the output point will be connected to the power supply through the variable resistor, and then slowly pulled up from the low level, thus generating a certain slope. Then the sample and hold circuit is analyzed. The sample and hold circuit is output through the frequency divider f div To generate sampling clocks clk1 and clk2, where clk1 is the inverse of clk2, and the two signals are non-overlapping clocks. The principle is as follows: when sampling f div When it is high, that is, clk div =1, at this time, clk1 = 0, clk2 = 1, the first switch is open, the second switch is closed, the first switch enters the holding phase, the second switch samples the output node of the first switch to obtain V sam When f div When it is low, clk div =0, the first switch is closed, the second switch is open, the first switch samples the output of the ramp generator and charges the first capacitor, the second switch is closed, the output enters the holding stage, the output voltage waveforms of the two switches are as follows Figure 3 shown.

[0007] Existing sampling phase detectors have the following disadvantages: 1. High linearity is difficult to achieve. As can be seen from the above analysis, the ramp generator's ramp is generated by slowly charging resistors and capacitors, which takes time to build up. Furthermore, achieving a stable slope is difficult because the change is slow and the slope gradually decreases. Therefore, achieving high linearity is difficult. This significantly affects the common-mode voltage sampled, thereby impacting phase-locked loop performance. For example, a narrow linear range can cause the loop to fail to lock. 2. The achievable linear range is small, and the gain is relatively low. This structure can only be used in scenarios where the sampling phase detector has low linearity requirements. When the loop has high requirements for linearity, linear range, and gain, this structure is unsuitable because its RC delay makes it difficult to achieve a constant slope. 3. The sampled voltage contains high ripple. Although this signal can be filtered out by the loop filter, when this ripple is fed to the subsequent voltage-to-current module, it will have a certain impact on the module's common-mode input.

[0008] Currently, no effective solution has been proposed for the problem of poor linearity of sampling phase detectors in related technologies. Summary of the Invention

[0009] The purpose of this application is to address the deficiencies in the prior art and provide a sampling phase detector and a phase-locked loop system to at least solve the problem of poor linearity of the sampling phase detector in the related art.

[0010] To achieve the above objectives, the technical solutions adopted in this application are:

[0011] In a first aspect, an embodiment of the present application provides a sampling phase detector, comprising:

[0012] The ramp generator includes: a first inverter P1 whose input terminal is a ramp generating clock signal f ref The output terminal is electrically connected to the gate of the first PMOS tube M1, the drain of M1 is connected to the power supply, the source of M1 is electrically connected to the drain of the second PMOS tube M2, and the gate of M2 is the control clock signal f div The source of M2 is electrically connected to the drain of the first NMOS tube M3 and one end of the first capacitor C1, the other end of C1 is grounded, the gate of M3 is electrically connected to the output end of the second inverter P2, and the input end of P2 is the control clock signal f div The source of M3 is electrically connected to the drain of the second NMOS tube M4, the source of M4 is grounded, and the control clock signal f div is electrically connected to the gate of M4 through a first buffer buffer1, a second buffer buffer2, and a third buffer buffer3;

[0013] The sampling and holding filter module includes: a switch circuit composed of a third NMOS tube M5 and a third PMOS tube M6 and a filter composed of a resistor R, a second capacitor C2 and a third capacitor C3, wherein the input end of buffer1 is the control clock signal f div The output end of buffer 1 is electrically connected to the input end of buffer 2, the input end of the third inverter P3, and the gate of M5. The drain of M5 is electrically connected to one end of C1 and the drain of M6. The gate of M6 is electrically connected to the output end of P3. The source of M6 is electrically connected to the source of M5, one end of C2, and one end of R. The other end of C2 is grounded. The other end of R is electrically connected to one end of C3. The other end of C3 is grounded. The output end of buffer 2 is electrically connected to the input end of buffer 3. The output end of buffer 3 is electrically connected to the gate of M4.

[0014] In some embodiments, the structures of buffer1, buffer2, and buffer3 are:

[0015] The input end is electrically connected to the gates of the fourth PMOS transistor M7 and the fourth NMOS transistor M8, respectively. The drain of M7 is connected to the power supply, the source of M7 is connected to the drain of M8, the source of M8 is grounded, the node between the source of M7 and the drain of M8 is electrically connected to the gates of the fifth PMOS transistor M9 and the fifth NMOS transistor M10, the drain of M9 is connected to the power supply, the source of M9 is connected to the drain of M10, the source of M10 is grounded, and the node between the source of M9 and the drain of M10 is the output end.

[0016] In some embodiments, when f ref and f div When both are at low level, M1 and M4 are turned off, M2 and M3 are turned on, and the output voltage V at one end of C1 is sample remain unchanged;

[0017] When f ref is high level, f div When it is low, M1, M2, and M3 are turned on, and M4 is turned off. C1 is charged through M1 and M2, and a ramp signal is generated. The output voltage V sample Start rising from a low level;

[0018] When f ref and f div When both are high, M1 is turned on, but M2, M3, and M4 are turned off, the ramp signal generation stops, and the sampling phase begins;

[0019] When f ref is low level, f div When the voltage is high, M1 and M2 are turned off, M3 and M4 are turned on, and the output voltage V sample is pulled low.

[0020] In some embodiments, the output voltage V sample The calculation formula is:

[0021] V sample =K slope ×Δt

[0022] Among them, K slope is the slope, and Δt is the time interval from the generation of the ramp signal to the entry into the sampling phase.

[0023] In some embodiments, when f div The clock signal clk generated after the delay of buffer1 sw When the voltage is high, the switch circuit is closed, the ramp signal generation stops, and the sampling point is performed. The sampled voltage is filtered by the filter and the output voltage V tune .

[0024] In a second aspect, an embodiment of the present application provides a phase-locked loop system, comprising the sampling phase detector described in the first aspect above.

[0025] The present application adopts the above technical solution. Compared with the prior art, the sampling phase detector provided in the embodiment of the present application uses the output clock of the divider in the phase-locked loop to control the ramp generator to generate a ramp wave, so that the ramp wave signal is generated between two phases, thereby improving the linearity and gain of the ramp wave generator. At the same time, the divider clock also generates pulse signals through different delays to control the sampling capacitor for sampling and control the switch to pull the high level down. The sampling capacitor is connected to a resistor and capacitor to form a low-pass filter to filter the ripple of the sampled DC level. In this way, the linearity of the SPD is improved while obtaining a high-gain, clean DC level. At the same time, the ramp wave is no longer generated in the form of a resistor, avoiding the defect that the resistance value of the resistor has a large change in PVT. This solves the problem of poor linearity of the sampling phase detector in the related art and achieves the effect of improving the linearity of the sampling phase detector.

[0026] The details of one or more embodiments of the present application are set forth in the following drawings and description to make other features, objects, and advantages of the present application more readily apparent. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0028] Figure 1 is a schematic diagram of an integer sampling phase-locked loop structure according to related art;

[0029] Figure 2 1. It is a structural diagram of a sampling phase detector according to related art;

[0030] Figure 3 It is a working timing waveform diagram of the sampling phase detector according to the relevant technology;

[0031] Figure 4 is a structural diagram of a sampling phase detector according to an embodiment of the present application;

[0032] Figure 5 is a schematic structural diagram of a buffer in a sampling phase detector according to an embodiment of the present application;

[0033] Figure 6 1 is a working timing waveform diagram of the sampling phase detector according to an embodiment of the present application. DETAILED DESCRIPTION

[0034] In order to make the purpose, technical solutions and advantages of this application more clearly understood, the present application is described and illustrated below in conjunction with the accompanying drawings and examples. It should be understood that the specific embodiments described herein are merely used to explain this application and are not intended to limit this application. Based on the embodiments provided in this application, all other embodiments obtained by those of ordinary skill in the art without making any creative efforts are within the scope of protection of this application.

[0035] Obviously, the drawings described below are merely examples or embodiments of the present application. Those skilled in the art can, without inventive effort, apply the present application to other similar scenarios based on these drawings. Furthermore, it is also understood that, although the effort involved in such a development process may be complex and lengthy, for those skilled in the art related to the content disclosed in this application, changes in design, manufacturing, or production based on the technical content disclosed in this application are merely conventional technical means and should not be construed as an insufficiency of the content disclosed in this application.

[0036] References to "embodiments" in this application mean that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it refer to independent or alternative embodiments that are mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described in this application may be combined with other embodiments unless there is a conflict.

[0037] Unless otherwise defined, the technical or scientific terms used in this application should have the ordinary meaning understood by a person of ordinary skill in the technical field to which this application belongs. The words "one", "a", "the" and the like used in this application do not indicate a limit on quantity and may indicate the singular or plural. The terms "include", "comprise", "have" and any variations thereof used in this application are intended to cover non-exclusive inclusions; for example, a process, method, system, product or device that includes a series of steps or modules (units) is not limited to the listed steps or units, but may also include steps or units that are not listed, or may also include other steps or units that are inherent to these processes, methods, products or devices. The words "connect", "connected", "coupled" and the like used in this application are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The word "multiple" used in this application refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships can exist. For example, "A and / or B" can mean: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects before and after are in an "or" relationship. The terms "first", "second", "third", etc. involved in this application are only used to distinguish similar objects and do not represent a specific order for the objects.

[0038] This embodiment provides a sampling phase detector. Figure 4 : is a structural diagram of a sampling phase detector according to an embodiment of the present application. Figure 4 As shown, the sampling phase detector includes: a ramp generator and a sampling and holding filter module, wherein the sampling and holding filter module includes: a switch circuit composed of a third NMOS transistor M5 and a third PMOS transistor M6, and a filter composed of a resistor R, a second capacitor C2 and a third capacitor C3.

[0039] like Figure 4 As shown, the input terminal of the first inverter P1 is the ramp wave generating clock signal f ref The output terminal is electrically connected to the gate of the first PMOS tube M1, the drain of M1 is connected to the power supply, the source of M1 is electrically connected to the drain of the second PMOS tube M2, and the gate of M2 is the control clock signal f div The source of M2 is electrically connected to the drain of the first NMOS tube M3 and one end of the first capacitor C1, the other end of C1 is grounded, the gate of M3 is electrically connected to the output end of the second inverter P2, and the input end of P2 is the control clock signal f div The source of M3 is electrically connected to the drain of the second NMOS tube M4, the source of M4 is grounded, and the control clock signal f divThe first buffer buffer1, the second buffer buffer2 and the third buffer buffer3 are electrically connected to the gate of M4; the input end of buffer1 is the control clock signal f div The output end of buffer 1 is electrically connected to the input end of buffer 2, the input end of the third inverter P3, and the gate of M5. The drain of M5 is electrically connected to one end of C1 and the drain of M6. The gate of M6 is electrically connected to the output end of P3. The source of M6 is electrically connected to the source of M5, one end of C2, and one end of R. The other end of C2 is grounded. The other end of R is electrically connected to one end of C3. The other end of C3 is grounded. The output end of buffer 2 is electrically connected to the input end of buffer 3. The output end of buffer 3 is electrically connected to the gate of M4.

[0040] In some embodiments, the structures of buffer1, buffer2, and buffer3 are as follows: Figure 5 As shown, the input end is electrically connected to the gates of the fourth PMOS transistor M7 and the fourth NMOS transistor M8, respectively. The drain of M7 is connected to the power supply, the source of M7 is connected to the drain of M8, the source of M8 is grounded, the node between the source of M7 and the drain of M8 is electrically connected to the gates of the fifth PMOS transistor M9 and the fifth NMOS transistor M10, the drain of M9 is connected to the power supply, the source of M9 is connected to the drain of M10, the source of M10 is grounded, and the node between the source of M9 and the drain of M10 is the output end.

[0041] In some embodiments, the ramp generator generates a slope by charging a capacitor through a clock control signal, and the ramp generation clock is f ref signal, the control clock is f div Signal (f divn f div The reverse signal) and at the same time through f div To control the switch to sample the ramp wave. Figure 6 , the specific working mode of the ramp generator is as follows:

[0042] When f ref and f div When both are at low level, M1 and M4 are turned off, M2 and M3 are turned on, and the output voltage V at one end of C1 is sample remain unchanged;

[0043] When f ref is high level, f div When it is low, M1, M2, and M3 are turned on, and M4 is turned off. C1 is charged through M1 and M2, and a ramp signal is generated. The output voltage V sample Start rising from a low level;

[0044] When f refand f div When both are high, M1 is turned on, but M2, M3, and M4 are turned off, the ramp signal generation stops, and the sampling phase begins;

[0045] When f ref is low level, f div When the voltage is high, M1 and M2 are turned off, M3 and M4 are turned on, and the output voltage V sample is pulled low.

[0046] According to the above working mechanism, the process of ramp wave generation can be summarized as follows: when the reference signal f ref When the divider outputs the signal f div When it is low, the ramp wave starts to be generated, and after a period of time, the divider clock f div The rising edge begins to arrive, at which point the ramp generation stops and the sampling phase begins.

[0047] In some embodiments, the output voltage V sample The calculation formula is:

[0048]

[0049] Among them, K slope is the slope, Δt is the time interval from the generation of the ramp signal to the sampling phase, that is, the phase difference between the two, T ref is the reference clock period.

[0050] In some embodiments, the sampling and holding filter module generates a clock clk after a certain delay from the divided clock. sw The switch is controlled and the filter is composed of resistors and capacitors. The sampled DC voltage signal is generated and filtered by controlling the switch to open. Figure 6 , its working mode is as follows: when f div The clock signal clk generated after the delay of buffer1 sw When the voltage is high, the switch circuit is closed, the ramp signal generation stops, and the sampling point is performed. The sampled voltage is filtered by the filter and the output voltage V tune .

[0051] The sampling phase detector SPD proposed in the embodiment of the present application controls the generation of the ramp wave by the output signal of the frequency divider, and further controls the sampling thereof. div Only when it is low can the ramp signal be obtained.

[0052] In this embodiment, the divider output clock in a phase-locked loop (PLL) is used to control a ramp generator to generate a ramp wave, ensuring that the ramp signal is generated between two phases. This improves the linearity and gain of the ramp generator. The divider clock also generates pulse signals through different delays to control sampling on a sampling capacitor and to control a switch to pull a high level down. Furthermore, a low-pass filter is formed by connecting a resistor and capacitor to the sampling capacitor to remove ripple from the sampled DC level. This improves the linearity of the SPD while producing a high-gain, clean DC level. Furthermore, the ramp wave is no longer generated using resistors, avoiding the drawback of resistors' large resistance variations due to PVT.

[0053] The sampling phase detector provided in the embodiment of the present application differs from the existing sampling phase detector SPD in that:

[0054] Improve the linearity of SPD by controlling ramp generation and sampling through the divider output;

[0055] The sampling capacitor is connected to the resistor and capacitor to form a low-pass filter to reduce the signal ripple.

[0056] a. Traditional SPDs use a reference signal to directly generate a ramp signal, and delay is achieved by connecting resistors and capacitors to the inverter output. However, this structure suffers from poor linearity and cannot achieve high gain. This embodiment of the present application proposes using a divider clock to control ramp generation, which in turn controls capacitor charging, to improve linearity.

[0057] b. The clock output by the divider is passed through a delay buffer to control the switch for sampling and holding to obtain the sampled DC level. This can better control the sampling time and then control the sampling level, increase the common mode range, and help improve the linear range.

[0058] c. The sampling switch adopts the form of CMOS switch, which can reduce the impact of switch charge sharing and clock feedthrough.

[0059] d. The frequency divider outputs the inverse signal of the clock signal, which is the same operation as controlling the sampling. After a certain delay buffer, the switch is controlled to end the sampling process, that is, to enter the holding stage.

[0060] e. Connecting a resistor-capacitor filter after the capacitor can reduce ripple caused by sampling switches and other non-ideal factors, thereby obtaining a cleaner DC signal. From a system architecture perspective, the sampling capacitor and loop filter capacitor can be shared, which saves area.

[0061] Based on the sampling phase detector provided in the above embodiment of the present application, the embodiment of the present application further provides a phase-locked loop system, which may include the sampling phase detector described in the above embodiment. It should be noted that other parts of the phase-locked loop system provided in the embodiment of the present application can refer to Figure 1 The structure described in will not be repeated here.

[0062] The embodiments of the present application can achieve the following technical effects:

[0063] Sampling phase detectors (SPDs) can be used in sampling phase-locked loops to improve their performance. As a new type of PLL architecture proposed in recent years, sampling phase-locked loops (PLLs) can significantly improve the shortcomings of traditional PLLs. For example, the PFD and CP in traditional charge pump PLLs often experience numerous non-idealities during design. Issues such as precise matching of the CP's pull-up and pull-down currents and charge leakage are particularly severe, significantly increasing the complexity of layout design. Furthermore, the PFD's function is limited to frequency and phase detection, and its gain is ultimately related to the phase difference between the two signals, which does not provide sufficient gain within the loop. In this respect, sampling phase-locked loops (PLLs) are superior to charge pump PLLs. They not only provide a high-gain sampling phase detector (SPD) instead of the PFD, but also replace the CP with a transconductance amplifier (Gm), significantly reducing design complexity. Furthermore, the SPD's increased gain reduces the noise performance pressure on the Gm module while suppressing the noise performance of other modules, resulting in an optimized circuit structure. Secondly, compared to sub-sampling phase-locked loops, sampling phase-locked loops perform sampling operations after frequency division via a frequency divider, rather than directly sampling the VCO output. This avoids crosstalk between the high-frequency VCO output signal and the low-frequency reference signal through the sampling switch, reducing the design difficulty of the sampling circuit. For sampling phase-locked loops, if the module-level circuit is properly designed and its performance is optimized as much as possible, the noise and spurious performance of the phase-locked loop can be greatly improved. Therefore, the performance of the SPD becomes particularly important. A high-linearity, high-gain sampling phase detector is crucial to the loop's locking and noise performance. A high-gain SPD can suppress the phase noise of modules such as Gm, reducing the phase noise of the phase-locked loop. High linearity can improve the locking range, prevent loop loss, and increase the common-mode range of the VCO control voltage.

[0064] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0065] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art could make various modifications and improvements without departing from the spirit of the present application, all of which fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A sampling phase detector, characterized in that: include: The ramp generator includes: a first inverter P1 whose input terminal is a ramp generating clock signal f ref The output terminal is electrically connected to the gate of the first PMOS tube M1, the drain of M1 is connected to the power supply, the source of M1 is electrically connected to the drain of the second PMOS tube M2, and the gate of M2 is the control clock signal f div The source of M2 is electrically connected to the drain of the first NMOS tube M3 and one end of the first capacitor C1, the other end of C1 is grounded, the gate of M3 is electrically connected to the output end of the second inverter P2, and the input end of P2 is the control clock signal f div The source of M3 is electrically connected to the drain of the second NMOS tube M4, the source of M4 is grounded, and the control clock signal f div is electrically connected to the gate of M4 through a first buffer buffer1, a second buffer buffer2, and a third buffer buffer3; The sampling and holding filter module includes: a switch circuit composed of a third NMOS tube M5 and a third PMOS tube M6 and a filter composed of a resistor R, a second capacitor C2 and a third capacitor C3, wherein the input end of buffer1 is the control clock signal f div , the output end of buffer 1 is electrically connected to the input end of buffer 2, the input end of the third inverter P3, and the gate of M5, the drain of M5 is electrically connected to one end of C1 and the drain of M6, the gate of M6 is electrically connected to the output end of P3, the source of M6 is electrically connected to the source of M5, one end of C2, and one end of R, the other end of C2 is grounded, the other end of R is electrically connected to one end of C3, the other end of C3 is grounded, the output end of buffer 2 is electrically connected to the input end of buffer 3, and the output end of buffer 3 is electrically connected to the gate of M4; When f ref and f div When both are at low level, M1 and M4 are turned off, M2 and M3 are turned on, and the output voltage V at one end of C1 is sample remain unchanged; When f ref is high level, f div When it is low, M1, M2, and M3 are turned on, and M4 is turned off. C1 is charged through M1 and M2, and a ramp signal is generated. The output voltage V sample Start rising from a low level; When f ref and f div When both are high, M1 is turned on, but M2, M3, and M4 are turned off, the ramp signal generation stops, and the sampling phase begins; When f ref is low level, f div When the voltage is high, M1 and M2 are turned off, M3 and M4 are turned on, and the output voltage V sample is pulled low.

2. The sampling phase detector according to claim 1, characterized in that The structures of buffer1, buffer2, and buffer3 are: The input end is electrically connected to the gates of the fourth PMOS transistor M7 and the fourth NMOS transistor M8, respectively. The drain of M7 is connected to the power supply, the source of M7 is connected to the drain of M8, the source of M8 is grounded, the node between the source of M7 and the drain of M8 is electrically connected to the gates of the fifth PMOS transistor M9 and the fifth NMOS transistor M10, the drain of M9 is connected to the power supply, the source of M9 is connected to the drain of M10, the source of M10 is grounded, and the node between the source of M9 and the drain of M10 is the output end.

3. The sampling phase detector according to claim 1 or 2, characterized in that: The output voltage V sample The calculation formula is: V sample =K slope ×Δt Among them, K slope is the slope, and Δt is the time interval from the generation of the ramp signal to the entry into the sampling phase.

4. The sampling phase detector according to claim 1 or 2, characterized in that: When f div The clock signal clk generated after the delay of buffer1 sw When the voltage is high, the switch circuit is closed, the ramp signal generation stops, and the sampling point is performed. The sampled voltage is filtered by the filter and the output voltage V tune .

5. A phase-locked loop system, characterized in that: The sampling phase detector comprises the sampling phase detector according to any one of claims 1 to 4.

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