A message processing method and device

Abstract

The present application proposes a message processing method and device, including: when the information transceiver module receives a message packet, if the packet receiving queue is in a non-congested state, the information transceiver module writes the message header of the message packet into the first target address segment, and writes the message body of the message packet into the second target address segment; the information transceiver module writes the first address information and the second address information into the first target packet receiving descriptor; the information transceiver module marks the first target packet receiving descriptor as occupied; after the processor processes the message header corresponding to the packet receiving descriptor in the occupied state in a preset order, it updates the packet sending queue based on the first address information and the second address information corresponding to the packet receiving descriptor to complete the message forwarding. The latency of the processor accessing the first memory is less than the latency of the processor accessing the second memory. The memory access latency of the processor can be reduced, thereby improving the overall forwarding efficiency.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a message processing method and device. Background Art

[0002] With the advancement of science and technology, especially the advancement of communication technology, the reception, processing and forwarding of data messages have received more and more attention. For example, with the rapid development of communication technology, people have higher and higher requirements for communication speed, which requires it to have high speed characteristics. Extremely fast network speed can provide users with high-speed upload and download experience. In addition, the communication network will also carry more and more rich services. On this basis, a large amount of data traffic will inevitably be generated, which will put forward higher requirements and challenges for network forwarding processing performance.

[0003] Therefore, how to improve network forwarding processing performance has become a difficult problem that technical personnel in this field are concerned about. Summary of the invention

[0004] The purpose of the present application is to provide a message processing method and device to at least partially improve the above-mentioned problem.

[0005] In order to achieve the above purpose, the technical solution adopted in the embodiment of the present application is as follows:

[0006] In a first aspect, an embodiment of the present application provides a message processing method, which is applied to a message processing device, wherein the message processing device includes an information transceiver module, a processor, a first memory, and a second memory, wherein a packet receiving queue is provided in the second memory, and the packet receiving queue includes a pre-configured packet receiving descriptor, and the method includes:

[0007] When the information transceiver module receives a message packet, if the packet receiving queue is in a non-congested state, the information transceiver module writes a message header of the message packet into a first target address segment, and writes a message body of the message packet into a second target address segment, wherein the first target address segment belongs to a first memory, and the second target address segment belongs to a second memory;

[0008] The information transceiver module writes the first address information and the second address information into a first target packet receiving descriptor, wherein the first target packet receiving descriptor is any packet receiving descriptor that is currently in an idle state in the packet receiving queue, the first address information is identification information of the write address of the message header, and the second address information is identification information of the write address of the message body;

[0009] The information transceiver module marks the first target packet receiving descriptor as being in an occupied state;

[0010] After processing the message header corresponding to the packet receiving descriptor in the occupied state in a preset order, the processor updates the packet sending queue based on the first address information and the second address information corresponding to the packet receiving descriptor to complete message forwarding.

[0011] In a second aspect, an embodiment of the present application provides a message processing method, which is applied to a message processing device, wherein the message processing device includes an information transceiver module, a processor, a first memory, and a second memory, wherein a packet sending queue is provided in the second memory, and the packet sending queue includes a pre-configured packet sending descriptor, and the method includes:

[0012] After processing the message header of the packet receiving descriptor in the occupied state, the processor writes the first address information and the second address information corresponding to the packet receiving descriptor into the first target packet sending descriptor;

[0013] The first address information initially written into the first target packet sending descriptor belongs to the first memory, the first address information is identification information of the write address of the message header corresponding to the packet receiving descriptor, the second address information is identification information of the write address of the message body corresponding to the packet receiving descriptor, and the first target packet sending descriptor is any packet sending descriptor that is currently in an idle state in the packet sending queue;

[0014] The processor adjusts the first target packet sending descriptor to an occupied state;

[0015] When the packet sending queue is in a congested state, the information transceiver module moves the message headers corresponding to the second target packet sending descriptors of the difference quantity to the second memory, wherein the second target packet sending descriptors are the packet sending descriptors in an occupied state and ranked later;

[0016] The information transceiver module updates the first address information in the second target packet sending descriptor, and the updated first address information in the second target packet sending descriptor belongs to the second memory;

[0017] The information transceiver module forwards messages for the packet sending descriptors in the packet sending queue that are in an occupied state based on a preset order.

[0018] In a third aspect, an embodiment of the present application provides a device, which includes: an information transceiver module, a processor, a first memory and a second memory, and the device can execute the above-mentioned message processing method.

[0019] Compared with the prior art, a message processing method and device provided by an embodiment of the present application includes: when an information transceiver module receives a message packet, if the packet receiving queue is in a non-congested state, the information transceiver module writes the message header of the message packet into the first target address segment, and writes the message body of the message packet into the second target address segment, wherein the first target address segment belongs to the first memory, and the second target address segment belongs to the second memory; the information transceiver module writes the first address information and the second address information into the first target packet receiving descriptor, wherein the first target packet receiving descriptor is any packet receiving descriptor currently in an idle state in the packet receiving queue, the first address information is the identification information of the write address of the message header, and the second address information is the identification information of the write address of the message body; the information transceiver module marks the first target packet receiving descriptor as an occupied state; after the processor processes the message header corresponding to the packet receiving descriptor in the occupied state in a preset order, the processor updates the packet sending queue based on the first address information and the second address information corresponding to the packet receiving descriptor to complete the message forwarding. The latency of the processor accessing the first memory is less than the latency of the processor accessing the second memory. It can reduce the processor's memory access latency, thereby improving the overall forwarding efficiency.

[0020] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, preferred embodiments are specifically cited below and described in detail with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0022] Figure 1 A schematic diagram of the structure of a message processing device provided in an embodiment of the present application;

[0023] Figure 2 One of the flow charts of the message processing method provided in the embodiment of the present application;

[0024] Figure 3 A second flowchart of the message processing method provided in an embodiment of the present application;

[0025] Figure 4 The third flowchart of the message processing method provided in the embodiment of the present application;

[0026] Figure 5 A fourth flowchart of the message processing method provided in an embodiment of the present application;

[0027] Figure 6 A fifth flowchart of the message processing method provided in an embodiment of the present application;

[0028] Figure 7 The sixth flowchart of the message processing method provided in the embodiment of the present application.

[0029] In the figure: 10 - information transceiver module; 20 - processor; 30 - first memory; 40 - second memory. DETAILED DESCRIPTION

[0030] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0031] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0032] It should be noted that similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. At the same time, in the description of this application, the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0033] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0034] In the description of the present application, it should be noted that the terms "upper", "lower", "inside", "outside", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, or are the orientations or positional relationships in which the product of the application is usually placed when in use. They are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0035] In the description of this application, it is also necessary to explain that, unless otherwise clearly specified and limited, the terms "disposed" and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be an indirect connection through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0036] In conjunction with the accompanying drawings, some embodiments of the present application are described in detail below. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0037] The present application embodiment provides a message processing device, such as a router device or an intelligent network card device. Figure 1 , a schematic diagram of the structure of a message processing device. The message processing device includes an information transceiver module 10, a processor 20, a first memory 30 and a second memory 40, the processor 20 is respectively connected to the information transceiver module 10, the first memory 30 and the second memory 40 for communication, and the information transceiver module 10 is respectively connected to the first memory 30 and the second memory 40 for communication. Optionally, the information transceiver module 10, the processor 20, the first memory 30 and the second memory 40 are connected via a bus. The first memory 30 is, for example, a static random access memory (SRAM for short), and the second memory 40 is, for example, a dynamic random access memory (also known as memory or DRAM), and the second memory 40 can specifically select DDR. The delay of the processor 20 accessing the first memory 30 is less than the delay of the processor 20 accessing the second memory 40.

[0038] The processor 20 can be a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, and discrete hardware components.

[0039] The information transceiver module 10 may be a hardware device, such as a Field-Programmable Gate Array (FPGA) or a network card. It should be understood that the information transceiver module 10 may directly access the first memory 30 and the second memory 40 .

[0040] In an optional scenario, the working process of the message processing device provided in the embodiment of the present application is as follows.

[0041] In the first step, the information transceiver module 10 completes the line-side message reception and uploading;

[0042] In the second step, the information transceiver module 10 stores the message into the DDR;

[0043] In the third step, the processor 20 senses the message reception through software;

[0044] Step 4: The processor 20 parses the message through software;

[0045] Step 5: The processor 20 performs a business table lookup through software;

[0046] Step 6: The processor 20 performs business processing (such as flow learning, statistics, deep analysis, security policies, encryption and decryption, etc.) through software;

[0047] Step 7: The processor 20 makes a forwarding decision (e.g., determines the network port for forwarding) through software;

[0048] Step 8: The processor 20 edits the message (for example, edits the message header) through software;

[0049] In the ninth step, the processor 20 sends the processed message through software, and completes the message sending through the information transceiver module 10.

[0050] In the above process, after receiving the message, it is necessary to identify it based on the message header information, and then forward it by software table lookup. The message header is usually in a storage device, such as DDR, which is a type of DRAM. There is a delay in the processor 20 (CPU) accessing DRAM. If the message rate to be processed is high, such as reaching the Mpps level, the CPU memory access delay is a key point affecting the forwarding performance.

[0051] In an optional scenario, in order to improve forwarding efficiency, some key services can be offloaded to hardware (information transceiver module 10) for execution, and the information transceiver module 10 completes parsing, table lookup, message editing and other tasks.

[0052] However, the router service specifications are large, and the hardware table entries are usually stored in SRAM, resulting in high hardware costs. In addition, this method can only offload part of the services. For example, the hardware table entries of access routers are usually below the MB (million byte) level, and a large number of service table entries are still on DDR. The table entries on DDR can easily reach the M / even G level. Most of the services can only be sent to the CPU for processing, resulting in low overall forwarding efficiency.

[0053] In order to overcome the above problems, an embodiment of the present application provides a message processing method, which is based on the message forwarding architecture of the front-end and rear-end first memory 30 and the second memory 40, and cooperates with the CPU Core dedicated to packet receiving to distribute packet receiving or packet sending tasks, which can effectively improve the overall performance of soft forwarding.

[0054] In the embodiment of the present application, a packet receiving queue and a packet sending queue are provided in the second memory 40. The packet receiving queue includes a pre-configured packet receiving descriptor, and the packet sending queue includes a pre-configured packet sending descriptor.

[0055] Optionally, a queue space is provided in the first memory 30, which may be a circular queue (Ring Buffer) for storing a message header (header) of a portion of message packets.

[0056] It should be understood that Figure 1 The structure shown is only a schematic diagram of a portion of the message processing device. The message processing device may also include Figure 1 More or fewer components as shown, or with Figure 1 Different configurations are shown. Figure 1 Each component shown in the figure can be implemented by hardware, software or a combination thereof.

[0057] The message processing method provided in the embodiment of the present application can be applied to but not limited to Figure 1 For the detailed process of the message processing device shown in the figure, please refer to Figure 2The message processing method includes: S115, S117, S118 and S211, which are specifically described as follows.

[0058] S115, when the information transceiver module receives a message packet, if the packet receiving queue is in a non-congested state, the information transceiver module writes the message header of the message packet into the first target address segment, and writes the message body of the message packet into the second target address segment.

[0059] The first target address segment belongs to the first memory, and the second target address segment belongs to the second memory.

[0060] It should be noted that when the processor 20 performs business processing, only the message header in the message packet needs to be edited. The information transceiver module 10 writes the message header of the message packet into the first target address segment in the first memory 30, and writes the message body of the message packet into the second target address segment in the second memory 40. When the processor 20 performs processing, it can directly access the first memory 30 without accessing the second memory 40, because the delay of the processor 20 accessing the first memory 30 is less than the delay of the processor 20 accessing the second memory 40. Therefore, the memory access delay of the processor 20 can be reduced through S115, thereby improving the overall forwarding efficiency.

[0061] In a possible scenario, when the message packet is short, it may be necessary to store the corresponding message header but not the message body, and the second target address segment may be configured as empty.

[0062] S117, the information transceiver module writes the first address information and the second address information into the first target packet receiving descriptor.

[0063] The first target packet receiving descriptor is any packet receiving descriptor currently in an idle state in the packet receiving queue, the first address information is identification information of the write address of the message header, and the second address information is identification information of the write address of the message body.

[0064] Optionally, a certain number of packet receiving descriptors are preconfigured in the packet receiving queue, and each packet receiving descriptor is provided with a first field and a second field, the first field is used to fill in the first address information, and the second field is used to fill in the second address information. In this way, when the processor 20 performs business processing, it can obtain the message header corresponding to the packet receiving descriptor through the first address information. The second address information is used to obtain the message body when forwarding.

[0065] Optionally, the first address information may be the starting address of a storage address segment for storing a message header, and the second address information may be the starting address of a storage address segment for storing a message body. When the packet receiving queue is in a non-congested state, the written first address information belongs to the first memory 30, and when the packet receiving queue is in a congested state, the written first address information may belong to the second memory 40, as described below. Because the processor 20 does not need to use the message body during business processing, the written second address information belongs to the second memory 40 regardless of the state of the packet receiving queue.

[0066] Optionally, the information transceiver module 10 can access the packet receiving queue to know the current state of each packet receiving descriptor in the packet receiving queue. Optionally, after determining the last packet receiving descriptor in the packet receiving queue that has switched to the occupied state, the information transceiver module 10 determines the first packet receiving descriptor in the idle state arranged behind it as the first target packet receiving descriptor.

[0067] Optionally, each packet receiving descriptor is provided with a third field, and the third field is used to store an offset, which is an offset between the actual write address of the message header and the starting address of the storage address segment storing the message header. It should be understood that when the processor 20 edits the message header, the length of the message header may change, for example, become longer or shorter, so it is necessary to reserve a certain space in the storage address segment storing the message header, that is, the offset.

[0068] By writing the offset into the first target packet receiving descriptor, it is convenient for the CPU to quickly determine the start part of the message header during processing.

[0069] Optionally, the first offset represents the offset between the actual write address of the message header and the first start address; the second offset represents the offset between the actual write address of the processed message header and the first start address.

[0070] S118, the information transceiver module marks the first target packet receiving descriptor as occupied.

[0071] Optionally, the purpose of marking the first target packet receiving descriptor as occupied is to facilitate notifying the processor 20 that the information stored in the address segment in the first target packet receiving descriptor needs to be processed for packet receiving.

[0072] S211, after processing the message header corresponding to the packet receiving descriptor in the occupied state in a preset order, the processor updates the packet sending queue based on the first address information and the second address information corresponding to the packet receiving descriptor to complete message forwarding.

[0073] Optionally, after updating the status of a batch of packet receiving descriptors, the information transceiver module 10 may send a first type of trigger instruction to the processor 20. The processor 20 (CPU) may determine whether there are any occupied packet receiving descriptors in the packet receiving queue upon receiving the first type of trigger instruction or according to a cycle, and if so, process them.

[0074] It should be understood that when the processor 20 is processing, it can directly access the first memory 30 without accessing the second memory 40, because the latency of the processor 20 accessing the first memory 30 is less than the latency of the processor 20 accessing the second memory 40. The memory access latency of the processor 20 can be reduced, thereby improving the overall forwarding efficiency.

[0075] Optionally, the packet sending queue is updated based on the first address information, the second address information and the second offset corresponding to the packet receiving descriptor to complete message forwarding.

[0076] In summary, the embodiment of the present application provides a message processing method, including: when the information transceiver module receives a message packet, if the packet receiving queue is in a non-congested state, the information transceiver module writes the message header of the message packet into the first target address segment, and writes the message body of the message packet into the second target address segment, wherein the first target address segment belongs to the first memory, and the second target address segment belongs to the second memory; the information transceiver module writes the first address information and the second address information into the first target packet receiving descriptor, wherein the first target packet receiving descriptor is any packet receiving descriptor currently in an idle state in the packet receiving queue, the first address information is the identification information of the write address of the message header, and the second address information is the identification information of the write address of the message body; the information transceiver module marks the first target packet receiving descriptor as an occupied state; after the processor processes the message header corresponding to the packet receiving descriptor in the occupied state in a preset order, the processor updates the packet sending queue based on the first address information and the second address information corresponding to the packet receiving descriptor to complete the message forwarding. The delay of the processor accessing the first memory is less than the delay of the processor accessing the second memory. It can reduce the processor's memory access latency, thereby improving the overall forwarding efficiency.

[0077] Optionally, regarding how to complete the writing of message information when receiving a message, the embodiment of the present application also provides an optional implementation method, please refer to Figure 3 The message processing method also includes: S111, S112, S113, S114 and S116, which are specifically described as follows.

[0078] S111, when the information transceiver module receives a message packet, the information transceiver module determines whether the packet receiving queue is in a congested state. If so, execute S113; if not, execute S112.

[0079] Optionally, a status flag may be set on the packet receiving queue to indicate whether the packet receiving queue is in a congested state. The information transceiver module 10 may determine whether it is in a congested state by reading the status flag without repeatedly calculating the threshold comparison.

[0080] If it is in a congested state, it means that the first memory 30 (SRAM) stores a lot of message header information. In order to avoid excessive occupation of the resources of the first memory 30, the message header needs to be stored in the second memory 40 (DRAM), so S113 is executed. If it is in a non-congested state, in order to save the memory access latency of the processor 20 when performing business processing, the message header can be directly stored in the first memory 30, that is, S112 is executed.

[0081] S112, the information transceiver module determines the first target address segment in the first memory as the write address of the message header.

[0082] Optionally, an address manager is also provided in the message processing device. The address manager can query the packet receiving queue and the packet sending queue, and determine whether the occupied address has been returned based on the status of the packet receiving descriptor and the packet sending descriptor therein, and then determine the free address segment in the first memory 30 and use it as the first target address.

[0083] S113, the information transceiver module determines the third target address segment in the second memory as the write address of the message header.

[0084] Optionally, the address manager can query the packet receiving queue and the packet sending queue, and determine whether the occupied address has been returned based on the status of the packet receiving descriptor and the packet sending descriptor therein, and then determine the free address segment in the second memory 40 and use it as the third target address.

[0085] S114, the information transceiver module determines the second target address segment in the second memory as the write address of the message body.

[0086] Optionally, when receiving the address distribution request corresponding to the information transceiver module 10, the address manager may send the corresponding first target address segment, second target address segment and third target address segment to it.

[0087] It should be noted that S114 can be executed directly when the message is received, or before S112 or S113, or synchronously therewith, and the execution order is not limited here. After executing S112 and S114, S115 is executed; after executing S113 and S114, S116 is executed.

[0088] S116, the information transceiver module writes the message header of the message packet into the third target address segment, and writes the message body of the message packet into the second target address segment.

[0089] It should be understood that when in a congested state, the information transceiver module 10 writes the message header of the message packet into the third target address segment and writes the message body of the message packet into the second target address segment to avoid occupying too much space in the first memory 30.

[0090] When the packet receiving queue is in a congested state, the present application embodiment also provides an optional implementation method for further reducing the delay. Please refer to Figure 4 When the packet receiving queue is in a congested state, the message processing method further includes: S121 and S122, which are specifically described as follows.

[0091] S121, if the processor updates the packet receiving descriptor in the occupied state to the idle state, the information transceiver module moves the message header corresponding to the second target packet receiving descriptor from the second memory to the first memory.

[0092] The second target packet receiving descriptor is a descriptor of the corresponding message header stored in the second memory.

[0093] Optionally, the processor 20 updates the occupied packet receiving descriptor to an idle state, that is, the processor 20 returns any packet receiving descriptor when the packet receiving queue is in a congested state, and at this time, the message header corresponding to the second target packet receiving descriptor can be moved from the second memory 40 to the first memory 30. Specifically, the moving target address can be obtained by the information transceiver module 10 requesting the address manager.

[0094] It should be understood that after the move, the original occupied address of the message header corresponding to the second target packet receiving descriptor in the second memory 40 is released and returned, and is in an idle state.

[0095] S122, the information transceiver module updates the first address information in the second target packet receiving descriptor.

[0096] Optionally, the first address information in the second target packet receiving descriptor is changed from identification information of the original occupied address to identification information of the moved target address.

[0097] It should be understood that as the processor 20 updates the occupied packet receiving descriptor to the idle state, the information transceiver module 10 will move the message headers corresponding to all the second target packet receiving descriptors from the second memory 40 to the first memory 30. Therefore, when the processor 20 performs service processing, the first memory 30 is always accessed, thereby reducing the delay and improving the overall forwarding efficiency.

[0098] 5 It should be understood that at the initial moment, the packet receiving queue is in a non-congested state. Regarding how to switch the packet receiving queue, the embodiment of the present application also provides a possible implementation method, please refer to Figure 5 The message processing method also includes: S131 and S132, which are specifically described as follows.

[0099] S131, when the packet receiving queue is in a non-congested state, the information transceiver module marks the packet receiving queue as being in a congested state when the monitoring amount is greater than a preset first threshold.

[0100] 0 Wherein, the monitoring amount is the number of packet receiving descriptors in the packet receiving queue that are in an occupied state, or the number of message headers stored in the first memory, or the number of storage units occupied by the message packets. The first threshold can be a global configuration or a per-queue configuration.

[0101] It should be understood that when the packet receiving queue is in a non-congested state, the message headers are all written into the first memory 30 .

[0102] S132: When the packet receiving queue is in a congested state and the information transceiver module does not store the message header corresponding to the packet receiving descriptor in the second memory, the packet receiving queue is marked as a non-congested state.

[0103] Optionally, when the packet receiving queue is in a congested state, newly received message headers are all written into the second memory 40. After the successive moves in S121, when the message header corresponding to the packet receiving descriptor is not stored in the second memory 40, the packet receiving queue is marked as a non-congested state.

[0104] It should be noted that, in the embodiment of the present application, the message body can be stored in a continuous space or multiple spaces (link-list of addresses) on the second memory 40. When stored in multiple spaces, the second address information corresponding to the packet receiving descriptor can include multiple sub-information, each of which represents the identification information of a space.

[0105] Optionally, a corresponding RingBuffer is provided in the first memory 30 and the second memory 40 according to the packet receiving queue for storing the message header. The Ring Buffer can be divided into a preset number of sub-segments, the idle sub-segments in the first memory 30 can be used as the first target address segment, and the idle sub-segments in the second memory 40 can be used as the third target address segment. The message header and the message body in the embodiment of the present application are stored separately. Each sub-segment is provided with a reserved space (Headroom), that is, an offset. When the message header is written in the packet receiving, the message header is written starting from the headroom.

[0106] Optionally, the present application also provides a message processing method, please refer to Figure 6 The message processing method also includes: S221, S222, S143, S144 and S146, which are specifically described as follows.

[0107] S221, after processing the message header of the packet receiving descriptor in the occupied state, the processor writes the first address information and the second address information corresponding to the packet receiving descriptor into the first target packet sending descriptor.

[0108] Among them, the first address information initially written into the first target packet descriptor belongs to the first memory, the second address information belongs to the second memory, the first address information is the identification information of the write address of the message header corresponding to the packet receiving descriptor, the second address information is the identification information of the write address of the message body corresponding to the packet receiving descriptor, and the first target packet descriptor is any packet descriptor that is currently in an idle state in the packet queue.

[0109] Optionally, the processor 20 can access the packet sending queue to know the current state of each packet sending descriptor in the packet sending queue. Optionally, after determining the last packet sending descriptor in the packet sending queue that switches to the occupied state, the processor 20 determines the first packet sending descriptor in the idle state arranged behind it as the first target packet sending descriptor.

[0110] Optionally, the packet sending descriptor is also provided with a first field, a second field and a third field, and the functions thereof are the same as those of the first field, the second field and the third field in the above-mentioned packet receiving descriptor.

[0111] It should be understood that the first address information initially written by the processor 20 into the first field of the first target packet descriptor belongs to the first memory, that is, the initial message headers are all stored in the first memory 30 .

[0112] In a possible implementation, the processor 20 further writes the second offset into the third field of the first target packet sending descriptor.

[0113] Optionally, the processor 20 also writes the forwarding decision (forwarding network port) into the fourth field of the first target packet sending descriptor.

[0114] S222: The processor adjusts the first target packet sending descriptor to an occupied state.

[0115] Optionally, the purpose of adjusting the first target packet sending descriptor to the occupied state is to facilitate notifying the information transceiver module 10 that the information stored in the address segment in the first target packet sending descriptor needs to be processed for packet sending.

[0116] It should be understood that the information transceiver module 10 will perform packet processing on the packet descriptors in the occupied state according to the arrangement order in the packet queue. However, the packet sending speed of the information transceiver module 10 may be lower than the packet receiving speed of the processor 20, which may cause the packet sending queue to be in a crowded state. If this state is ignored, the space in the first memory 30 may be over-occupied, resulting in the inability to write the newly received message into the first memory 30, so that the processor 20 cannot process subsequent messages. In order to overcome this problem, it is necessary to execute S143.

[0117] S143, when the packet sending queue is in a congested state, the information transceiver module moves the message headers corresponding to the second target packet sending descriptors of the difference quantity to the second memory.

[0118] It should be understood that by moving the message headers corresponding to the second target packet descriptors of the difference quantity from the first memory 30 to the second memory 40, the space of the first memory 30 can be released for receiving new message information, so that the processor 20 can continue to process subsequent messages.

[0119] Optionally, under what circumstances will the information transceiver module 10 determine that the packet sending queue is in a congested state? The embodiment of the present application also provides a possible implementation method. The information transceiver module 10 can query the packet sending queue according to a predetermined period and determine its state by polling.

[0120] It should be understood that continuous polling will occupy the hardware resources of the information transceiver module 10. In order to avoid occupying hardware resources, the embodiment of the present application also provides a possible implementation method, which can be that the processor 20 executes S222 and updates the packet descriptor, and then sends a second type of trigger instruction to the information transceiver module 10 to enable the information transceiver module 10 to determine whether the packet queue is in a congested state.

[0121] In one possible scenario, the second type of trigger instruction also includes the number of currently updated packet descriptors; then the information transceiver module 10 can determine the difference number based on the current update number and the number of remaining unsent packet descriptors, and move the difference number sorted later to the second memory 40.

[0122] It should be understood that the destination address of the migration can be the destination address of the difference quantity allocated by the address manager when the information transceiver module 10 sends a request to the address manager.

[0123] S144, the information transceiver module updates the first address information in the second target packet sending descriptor, and the updated first address information in the second target packet sending descriptor belongs to the second memory.

[0124] The second target packet sending descriptor is a packet sending descriptor that is in an occupied state and is ranked later.

[0125] It should be understood that in order to ensure the correctness of the packet content, the first address information in the second target packet descriptor needs to be updated. Specifically, the original first address information in the first field will be replaced by the newly allocated destination address. The first address information in the updated second target packet descriptor belongs to the second memory.

[0126] Optionally, after the update is completed, the space of the first memory 30 can be released, and the originally occupied address space becomes available and can be allocated again by the address manager, for example, to receive new message information so that the processor 20 can continue to process subsequent messages.

[0127] S146, the information transceiver module forwards messages for the packet sending descriptors in the occupied state in the packet sending queue based on a preset order.

[0128] Optionally, after the message forwarding is completed, the occupied space in the corresponding first memory 30 or second memory 40 can be returned, and the originally occupied address space becomes idle and available, and the address manager can allocate it again.

[0129] exist Figure 6 Based on this, the present application embodiment also provides an optional implementation method, please refer to Figure 7 The message processing method also includes: S141, S142 and S145, which are specifically described as follows.

[0130] S141, the information transceiver module determines whether the number of the third target packet descriptors in the packet queue is greater than a preset second threshold. If yes, execute S142; if no, execute S145.

[0131] The third target packet descriptor is a packet descriptor in an occupied state and the corresponding message header is stored in the first memory. The second threshold may be a global configuration or a per-queue configuration, and of course, may also be a fixed value.

[0132] Optionally, S141 is not necessarily executed after S222, and S141 may be executed when the information transceiver module 10 receives the second type of trigger instruction.

[0133] S142, determining that the packet sending queue is in a congested state.

[0134] S145, determining that the packet sending queue is in a non-congested state.

[0135] After S142, S143 is executed, and after S145, S146 can be directly executed.

[0136] Optionally, S146 is independent of the above steps. Regardless of whether the packets are moved or not, the information transceiver module 10 will forward the packets of the occupied packet descriptors in the packet sending queue based on a preset order.

[0137] It should be understood that the message processing method provided by the present application is assisted by application-specific integrated circuit hardware (ASIC). When the processor 20 (CPU) senses the message reception, the message header is already in the first memory 30 (SRAM). After the CPU completes the filling of the packet DMA TX descriptor, the hardware automatically releases the SRAM space where the message header is located. It can effectively reduce the memory access delay when the CPU processes the message, reduce the CPU waiting time, thereby greatly improving the soft forwarding efficiency and improving the overall forwarding bandwidth.

[0138] The following provides a message processing device, such as a router device or an intelligent network card device. Figure 1 As shown, the above-mentioned message processing method can be implemented; specifically, the message processing device includes: an information transceiver module 10, a processor 20, a first memory 30 and a second memory 40. The processor 20 can be a CPU. The message processing device can execute the message processing method of the above-mentioned embodiment.

[0139] In the embodiments provided in the present application, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely schematic. For example, the flowcharts and block diagrams in the accompanying drawings show the possible architecture, functions and operations of the devices, methods and computer program products according to the multiple embodiments of the present application. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of a code, and the module, a program segment or a part of a code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or the flowchart, and the combination of boxes in the block diagram and / or the flowchart can be implemented with a dedicated hardware-based system that performs a specified function or action, or can be implemented with a combination of dedicated hardware and computer instructions.

[0140] In addition, the functional modules in the various embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

[0141] If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product is stored in a storage medium, including several instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0142] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

[0143] It will be apparent to those skilled in the art that the present application is not limited to the details of the exemplary embodiments described above, and that the present application can be implemented in other specific forms without departing from the spirit or essential features of the present application. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the present application is defined by the appended claims rather than the above description, and it is intended that all changes falling within the meaning and scope of the equivalent elements of the claims be included in the present application. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

Claims

1. A message processing method, characterized in that: Applied to a message processing device, the message processing device includes an information transceiver module, a processor, a first memory and a second memory, the second memory is provided with a packet receiving queue, the packet receiving queue includes a pre-configured packet receiving descriptor, and the method includes: When the information transceiver module receives a message packet, the information transceiver module determines whether the packet receiving queue is in a congested state; If the packet receiving queue is in a non-congested state, the information transceiver module determines the first target address segment in the first memory as the write address of the message header of the message packet; The information transceiver module determines the second target address segment in the second memory as the write address of the message body of the message packet; If the packet receiving queue is in a non-congested state, the information transceiver module writes the message header of the message packet into a first target address segment, and writes the message body of the message packet into a second target address segment, wherein the first target address segment belongs to a first memory, and the second target address segment belongs to a second memory; The information transceiver module writes the first address information and the second address information into a first target packet receiving descriptor, wherein the first target packet receiving descriptor is any packet receiving descriptor that is currently in an idle state in the packet receiving queue, the first address information is identification information of the write address of the message header, and the second address information is identification information of the write address of the message body; The information transceiver module marks the first target packet receiving descriptor as being in an occupied state; After processing the message header corresponding to the packet receiving descriptor in the occupied state in a preset order, the processor updates the packet sending queue based on the first address information and the second address information corresponding to the packet receiving descriptor to complete message forwarding.

2. The message processing method according to claim 1, characterized in that: The method further comprises: If the packet receiving queue is in a congested state, the information transceiver module determines the third target address segment in the second memory as the write address of the message header; The information transceiver module determines the second target address segment in the second memory as the write address of the message body; The information transceiver module writes the message header of the message packet into the third target address segment, and writes the message body of the message packet into the second target address segment.

3. The message processing method according to claim 2, characterized in that: When the packet receiving queue is in a congested state, the method further includes: If the processor updates the packet receiving descriptor in the occupied state to the idle state, the information transceiver module moves the message header corresponding to the second target packet receiving descriptor from the second memory to the first memory; The information transceiver module updates the first address information in the second target packet receiving descriptor.

4. The message processing method according to claim 1, characterized in that: When the packet receiving queue is in a non-congested state, the method further includes: When the monitoring amount is greater than a preset first threshold, the information transceiver module marks the packet receiving queue as a congested state, wherein the monitoring amount is the number of packet receiving descriptors in the packet receiving queue that are in an occupied state, or the number of message headers stored in the first memory, or the number of storage units occupied by message packets.

5. The message processing method according to claim 4, characterized in that: When the packet receiving queue is in a congested state, the method further includes: When the information transceiver module does not store the message header corresponding to the packet receiving descriptor in the second memory, the packet receiving queue is marked as a non-congested state.

6. A message processing method, characterized in that: Applied to a message processing device, the message processing device includes an information transceiver module, a processor, a first memory and a second memory, the second memory is provided with a packet sending queue, the packet sending queue includes a pre-configured packet sending descriptor, and the method includes: After processing the message header of the packet receiving descriptor in the occupied state, the processor writes the first address information and the second address information corresponding to the packet receiving descriptor into the first target packet sending descriptor; The first address information initially written into the first target packet sending descriptor belongs to the first memory, the first address information is identification information of the write address of the message header corresponding to the packet receiving descriptor, the second address information is identification information of the write address of the message body corresponding to the packet receiving descriptor, and the first target packet sending descriptor is any packet sending descriptor that is currently in an idle state in the packet sending queue; The processor adjusts the first target packet sending descriptor to an occupied state; When the packet sending queue is in a congested state, the information transceiver module moves the message headers corresponding to the second target packet sending descriptors of the difference quantity to the second memory, wherein the second target packet sending descriptors are the packet sending descriptors in an occupied state and ranked later; The information transceiver module updates the first address information in the second target packet sending descriptor, and the updated first address information in the second target packet sending descriptor belongs to the second memory; The information transceiver module forwards messages for the packet sending descriptors in the packet sending queue that are in an occupied state based on a preset order.

7. The message processing method according to claim 6, characterized in that: Before moving the message header corresponding to the second target packet sending descriptor of the difference quantity to the second memory, the method further includes: When the number of the third target packet sending descriptors in the packet sending queue is greater than a preset second threshold, the information transceiver module determines that the packet sending queue is in a congested state; The third target packet descriptor is a packet descriptor in an occupied state and a corresponding message header is stored in the first memory.

8. The message processing method according to claim 7, characterized in that: The method further comprises: When the packet sending queue is in a non-congested state, the information sending and receiving module directly forwards messages for the packet sending descriptors in an occupied state in the packet sending queue based on a preset order.

9. A message processing device, characterized in that: include: An information transceiver module, a processor, a first memory and a second memory, and the message processing device is used to execute the message processing method described in any one of claims 1-8.

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