Semiconductor structure and method of manufacturing the same

Abstract

Embodiments of the present application relate to the field of semiconductor, and provide a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises: a substrate comprising spaced-apart bit lines and semiconductor channels, the bit lines extending along a first direction, the semiconductor channels being located on part of top surfaces of the bit lines, and in a direction perpendicular to the top surfaces of the bit lines, the semiconductor channels comprising a first region, a second region and a third region arranged in sequence; a dielectric layer located between adjacent bit lines and on sidewalls of the semiconductor channels; a gate electrode surrounding the dielectric layer of the second region and extending along a second direction, the first direction being different from the second direction; a metal-semiconductor compound layer located on top surfaces of the semiconductor channels; a diffusion barrier layer at least surrounding sidewalls of the metal-semiconductor compound layer; and an insulating layer located between adjacent semiconductor channels on the same bit line and separating the gate electrode and the diffusion barrier layer located on adjacent dielectric layers. The embodiments of the present application can at least improve the electrical performance of the semiconductor structure.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the field of semiconductor, and in particular, to a semiconductor structure and a manufacturing method thereof. BACKGROUND

[0002] With the development of the integration density of dynamic memory towards higher direction, while researching on the arrangement mode of transistors in the dynamic memory array structure and how to reduce the size of a single functional device in the dynamic memory array structure, it is also necessary to improve the electrical performance of the small-size functional device.

[0003] When a vertical Gate-All-Around (GAA) transistor structure is used as an access transistor of dynamic memory, the area occupied by the access transistor can reach 4F2(F: the minimum pattern size that can be obtained under given process conditions), and in principle, higher density efficiency can be achieved. However, due to the small spacing between adjacent transistors, when the semiconductor channel is processed, the insulating layer between adjacent transistors is easily affected, which reduces the insulating effect of the insulating layer, thereby affecting the electrical performance of the semiconductor structure. SUMMARY

[0004] Embodiments of the present application provide a semiconductor structure and a manufacturing method thereof, which at least facilitate to improve the electrical performance of the semiconductor structure.

[0005] According to some embodiments of the present application, the present application provides a semiconductor structure, comprising: a substrate, the substrate comprising spaced-apart bit lines and semiconductor channels, the bit lines extending along a first direction, the semiconductor channels being located on part of the top surface of the bit lines, and in a direction perpendicular to the top surface of the bit lines, the semiconductor channels comprising a first region, a second region and a third region arranged in sequence; a dielectric layer located between adjacent bit lines and on the sidewall of the semiconductor channel; a gate electrode surrounding the dielectric layer of the second region and extending along a second direction, the first direction being different from the second direction; a metal-semiconductor compound layer located on the top surface of the semiconductor channel; a diffusion barrier layer at least surrounding the sidewall of the metal-semiconductor compound layer; and an insulating layer located between adjacent semiconductor channels on the same bit line and isolating the gate electrode and the diffusion barrier layer located on adjacent dielectric layers.

[0006] In some embodiments, the metal-semiconductor compound layer has a doping element, and the doping element is a P-type doping element or an N-type doping element.

[0007] In some embodiments, the semiconductor channel has the doping element, and the concentration of the doping element in the metal-semiconductor compound layer is greater than the concentration in the semiconductor channel.

[0008] In some embodiments, the top surface of the metal-semiconductor compound layer is flush with the top surface of the diffusion barrier layer, and the length of the metal-semiconductor compound layer is less than or equal to the length of the diffusion barrier layer in a direction perpendicular to the top surface of the bit line.

[0009] In some embodiments, the semiconductor structure further comprises an electrical connection layer on the top surface of the metal-semiconductor compound layer and on the top surface of the diffusion barrier layer, and the insulating layer separates adjacent electrical connection layers on adjacent semiconductor channels.

[0010] In some embodiments, a single gate extends in the second direction and surrounds adjacent semiconductor channels on adjacent bit lines, and a single diffusion barrier layer surrounds only a single semiconductor channel.

[0011] In some embodiments, the semiconductor structure further comprises a metal silicide structure in at least the bit line directly opposite the bottom surface of the insulating layer.

[0012] In some embodiments, the depth of the metal silicide structure gradually increases in a direction pointing to the insulating layer along the semiconductor channel on both sides of the insulating layer.

[0013] In some embodiments, the cross-sectional area of the semiconductor channel in the first region is greater than the cross-sectional area of the semiconductor channel in the second region in a plane perpendicular to the sidewall of the semiconductor channel.

[0014] In some embodiments, the dielectric layer comprises a first dielectric layer between adjacent bit lines and between the semiconductor channels in the first region on adjacent bit lines, a second dielectric layer on the sidewall of the semiconductor channel in the first region and on the sidewall of the first dielectric layer in the first region, and a third dielectric layer surrounding the sidewall of the semiconductor channel in the second region and in the third region.

[0015] In some embodiments, the gate is on at least part of the top surface of the first dielectric layer and part of the top surface of the second dielectric layer, and the diffusion barrier layer is on the top surface of the third dielectric layer.

[0016] In some embodiments, the insulating layer comprises a first insulating layer between the dielectric layer adjacent to the semiconductor channel and between the gates, and extending in the second direction, and the top surface of the first insulating layer is not lower than the top surface of the metal-semiconductor compound layer, and a second insulating layer on the top surface of the gate and between the first insulating layer and the diffusion barrier layer.

[0017] According to some embodiments of the present application, another aspect of the present application provides a method for manufacturing a semiconductor structure, comprising: providing a substrate, the substrate comprising a plurality of spaced-apart bit lines and a plurality of initial semiconductor channels, the bit lines extending along a first direction, the initial semiconductor channels being located on top surfaces of portions of the bit lines, and in a direction perpendicular to the top surfaces of the bit lines, the initial semiconductor channels comprising, in sequence, a first region, a second region, and an initial third region; forming a dielectric layer between adjacent ones of the bit lines and on sidewalls of portions of the initial semiconductor channels; forming a gate electrode around the dielectric layer of the second region and extending along a second direction, the first direction being different from the second direction; forming a diffusion barrier layer around remaining sidewalls of the initial semiconductor channels, the diffusion barrier layer being spaced apart from the gate electrode; performing a metal silicidation process on top surfaces of the initial semiconductor channels to convert portions of the initial semiconductor channels of the initial third region into a metal semiconductor compound layer, the remaining initial third region, the second region, and the third region forming a semiconductor channel; and forming an insulating layer between adjacent ones of the semiconductor channels on the same bit line.

[0018] In some embodiments, after the diffusion barrier layer is formed and before the metal semiconductor compound layer is formed, the method further comprises: performing a doping process on the top surfaces of the initial semiconductor channels to dope portions of the initial semiconductor channels of the initial third region with a dopant element, the dopant element being a P-type dopant element or an N-type dopant element.

[0019] In some embodiments, the step of providing the substrate comprises: providing an initial substrate having an initial first dielectric layer extending along the first direction; patterning the initial substrate and the initial first dielectric layer to form the plurality of spaced-apart bit lines and the plurality of initial semiconductor channels, and the initial first dielectric layer between adjacent ones of the bit lines, the top surfaces of the initial first dielectric layer being no lower than the top surfaces of the initial semiconductor channels, the sidewalls of the initial semiconductor channels, the sidewalls of the initial first dielectric layer, and portions of the top surfaces of the bit lines forming trenches, the trenches extending along the second direction.

[0020] In some embodiments, the steps of forming the dielectric layer, the gate, the diffusion barrier layer and the insulating layer include: forming a first dielectric layer between and on the semiconductor channel of the first region between adjacent bit lines, and forming a second dielectric layer on the trench sidewall of the first region; forming a first insulating layer in the trench and separating adjacent second dielectric layers, the top surface of the first insulating layer being not lower than the top surface of the initial semiconductor channel; forming a third dielectric layer on the trench sidewall of the second region and the initial third region, and forming a second insulating layer between the first insulating layer and the third dielectric layer; forming a diffusion barrier layer on the remaining trench sidewall of the initial third region, the first dielectric layer, the second dielectric layer and the third dielectric layer constituting the dielectric layer, and the first insulating layer and the second insulating layer constituting the insulating layer.

[0021] In some embodiments, the steps of forming the first dielectric layer, the second dielectric layer and the first insulating layer include: forming an initial second dielectric layer on the trench sidewall, and having a first interval between adjacent initial second dielectric layers; forming the first insulating layer in the first interval; etching the initial first dielectric layer and the initial second dielectric layer with the first insulating layer as a mask to form the first dielectric layer and the second dielectric layer.

[0022] In some embodiments, before forming the first insulating layer, after forming the initial second dielectric layer, a part of the top surface of the bit line exposed by the initial second dielectric layer is subjected to a metal silicidation process to form a metal semiconductor compound structure.

[0023] In some embodiments, the steps of forming the third dielectric layer, the gate and the second insulating layer include: forming an initial third dielectric layer on the initial semiconductor channel sidewall of the second region and the initial third region, and having a second interval between the initial third dielectric layer and the first insulating layer; forming the gate in the second interval of the second region; forming the second insulating layer in the remaining second interval; etching the initial third dielectric layer with the second insulating layer as a mask to form the third dielectric layer; the third dielectric layer, the second insulating layer and the semiconductor channel surrounding a groove, and forming the diffusion barrier layer filling the groove.

[0024] In some embodiments, the top surface of the insulating layer is higher than the top surface of the metal semiconductor compound layer, the insulating layer, the metal semiconductor compound layer and the diffusion barrier layer surrounding a via, and the manufacturing method further includes forming an electrical connection layer filling the via.

[0025] The technical scheme provided by the embodiments of the present application has at least the following advantages:

[0026] In the technical solution, the vertical GAA transistor is formed in the substrate, and the bit line is embedded in the substrate and located below the semiconductor channel, so that a 3D stacked semiconductor structure can be formed, and the integration density of the semiconductor structure is improved. Moreover, the metal-semiconductor compound layer is arranged on the top surface of the semiconductor channel away from the bit line. Since the metal-semiconductor compound layer has a relatively smaller resistivity than the non-metalized semiconductor channel, the metal-semiconductor compound layer can be used as a transition layer to realize ohmic contact between the top surface of the semiconductor channel and other conductive structures, reduce the contact resistance between the top surface of the semiconductor channel and other conductive structures, and improve the electrical performance of the semiconductor channel. In addition, the diffusion barrier layer at least surrounds the sidewall of the metal-semiconductor compound layer, so that the metal-semiconductor compound layer and the insulating layer are separated by the diffusion barrier layer, which prevents the metal elements in the metal-semiconductor compound layer from diffusing into the insulating layer and reducing the insulation performance of the insulating layer. Therefore, the embodiments of the present application can reduce the contact resistance between the top surface of the semiconductor channel and other conductive structures through the metal-semiconductor compound layer while ensuring the good insulation performance of the insulating layer, thereby improving the electrical performance of the semiconductor structure. BRIEF DESCRIPTION OF DRAWINGS

[0027] One or more embodiments are illustrated by way of example in the figures that are part of this disclosure and which are illustrative, but not restrictive, of the embodiments, unless otherwise specified, the figures in the drawings do not constitute a proportional limitation.

[0028] Figures 1 to 17 The manufacturing method of the semiconductor structure provided by another embodiment of the present application is provided. DETAILED DESCRIPTION

[0029] As known from the background, the electrical performance of the semiconductor structure needs to be improved.

[0030] It is found through analysis that, in order to realize ohmic contact between the semiconductor channel and other conductive structures, a metal element is doped into only the end of the semiconductor channel by using a related technical means to reduce the resistivity of the end of the semiconductor channel and realize ohmic contact between the end of the semiconductor channel and other conductive structures. However, when the adjacent semiconductor channels are electrically insulated by the insulating layer, the metal element in the semiconductor channel diffuses into the insulating layer, which reduces the insulation effect of the insulating layer, thereby increasing the parasitic capacitance between the adjacent semiconductor channels, and thus reducing the electrical performance of the semiconductor structure.

[0031] The application provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises a metal semiconductor compound layer as a transition layer on a top surface of a semiconductor channel to realize ohmic contact between the semiconductor channel and other conductive structures, to reduce the contact resistance between the semiconductor channel and the other conductive structures. In addition, a diffusion barrier layer is arranged between the metal semiconductor compound layer and an insulating layer, which is beneficial to prevent the metal elements in the metal semiconductor compound layer from diffusing into the insulating layer. Therefore, the application is beneficial to reducing the contact resistance between the semiconductor channel and the other conductive structures through the metal semiconductor compound layer, and ensuring the good insulation performance of the insulating layer, so as to improve the electrical performance of the semiconductor structure.

[0032] The embodiments of the application will be described in detail below with reference to the drawings. However, those skilled in the art can understand that, in the embodiments of the application, many technical details are provided to make the readers better understand the application. However, the technical solutions claimed by the application can be implemented even without these technical details and various changes and modifications based on the following embodiments.

[0033] The application provides a semiconductor structure, and the semiconductor structure provided by the application will be described in detail below with reference to the drawings. Figures 1 to 3 The semiconductor structure provided by the application corresponds to the structure schematic diagram. Wherein, Figure 1 The top view schematic diagram of the semiconductor structure provided by the application, Figure 2 The sectional view schematic diagram of the semiconductor structure provided by the application along the first cross-sectional direction AA1, Figure 1 The sectional view schematic diagram of the semiconductor structure provided by the application along the second cross-sectional direction BB1, Figure 3 The sectional view schematic diagram of the semiconductor structure provided by the application along the second cross-sectional direction BB1, Figure 1 The sectional view schematic diagram of the semiconductor structure provided by the application along the second cross-sectional direction BB1, Figure 4 The sectional view schematic diagram of the semiconductor structure provided by the application along the second cross-sectional direction BB1.

[0034] Reference is made to Figures 1 to 4, the semiconductor structure comprises: a substrate 100, the substrate 100 comprises a plurality of spaced-apart bit lines 101 and semiconductor channels 102, the bit lines 101 extend along a first direction X, the semiconductor channels 102 are located on part of the top surface of the bit lines 101, and in a direction Z perpendicular to the top surface of the bit lines 101, the semiconductor channels 102 comprise a first region I, a second region II and a third region III arranged in sequence; a dielectric layer 103 located between adjacent bit lines 101 and on the side wall of the semiconductor channel 102; a gate 104 surrounding the dielectric layer 103 of the second region II and extending along a second direction Y, the first direction X being different from the second direction Y; a metal-semiconductor compound layer 105 located on the top surface of the semiconductor channel 102; a diffusion barrier layer 106 at least surrounding the side wall of the metal-semiconductor compound layer 105; and an insulating layer 107 located between adjacent semiconductor channels 102 on the same bit line 101 and isolating the gate 104 and the diffusion barrier layer 106 located on adjacent dielectric layers 103.

[0035] In the semiconductor structure, the semiconductor channel 102, the dielectric layer 103 surrounding the side wall of the semiconductor channel 102 of the second region II, and the gate 104 constitute a vertical GAA transistor, the substrate 100 comprises a substrate 110, the bit line 101 is located between the substrate 110 and the GAA transistor, thereby forming a 3D stacked semiconductor structure, which is conducive to improving the integration density of the semiconductor structure.

[0036] It should be noted that the first region I and the third region III can both serve as a source or a drain of the GAA transistor, and the second region II corresponds to the dielectric layer 103 and the gate 104 of the GAA transistor.

[0037] In some embodiments, continuing to refer to Figure 1 , the first direction X is perpendicular to the second direction Y, so that the semiconductor channel 102 has a 4F 2 (F: the minimum pattern size that can be obtained under given process conditions) arrangement, which is conducive to improving the integration density of the semiconductor structure. In other embodiments, the first direction intersects the second direction, and the included angle therebetween can not be 90°.

[0038] It should be noted that the substrate 100 has a plurality of spaced-apart bit lines 101, and each bit line 101 can be in contact with at least one first region I, Figure 1 In the above embodiment, four mutually spaced-apart bit lines 101 and each bit line 101 in contact with four first regions I are taken as examples, and in actual applications, the number of bit lines 101 and the number of first regions I in contact with each bit line 101 can be reasonably set according to actual electrical requirements.

[0039] The semiconductor structure will be described in more detail below. Figures 1 to 3

[0040] ​In some embodiments, the material type of the substrate 100 can be an elemental semiconductor material or a crystalline inorganic compound semiconductor material. The elemental semiconductor material can be silicon or germanium; the crystalline inorganic compound semiconductor material can be silicon carbide, silicon germanium, gallium arsenide, or indium gallium, etc.

[0041] In some embodiments, the substrate 100 includes the bit line 101 and the semiconductor channel 102, and the substrate 100, the bit line 101, and the semiconductor channel 102 can have the same semiconductor element. The semiconductor channel 102 and the bit line 101 can be formed by using the same film layer structure composed of the semiconductor element, so that the semiconductor channel 102 and the bit line 101 are integrated into one structure, thereby improving the interface state defects between the semiconductor channel 102 and the bit line 101 and improving the electrical performance of the semiconductor structure.

[0042] In some embodiments, the semiconductor element can include at least one of silicon, carbon, germanium, arsenic, gallium, and indium. In the following, the bit line 101 and the semiconductor channel 102 are exemplarily described as including silicon elements.

[0043] In some embodiments, the semiconductor structure can further include a metal silicide structure 111 located at least in the bit line 101 opposite to the bottom surface of the insulating layer 107, i.e., the metal silicide structure 111 is located at least in the bit line 101 opposite to the bottom surface of the first insulating layer 117.

[0044] Compared with the semiconductor material without metal, the metal silicide structure 111 has a relatively small resistivity. Therefore, compared with the semiconductor channel 102, the bit line 101 containing the metal silicide structure 111 has a smaller resistivity, thereby being beneficial to reduce the resistance of the bit line 101 itself and the contact resistance between the bit line 101 and the semiconductor channel 102 of the first region I, and further improving the electrical performance of the semiconductor structure. In addition, the resistivity of the bit line 101 is also smaller than the resistivity of the substrate 110.

[0045] It should be noted that in some embodiments, the material of the region of the bit line 101 directly below the first region I can be a semiconductor material, and the material of the part of the region of the bit line 101 not covered by the first region I can be a metal silicide. It can be understood that, with the continuous reduction of device size or adjustment of manufacturing process parameters, the material of the part of the region of the bit line 101 directly below the first region I can be a semiconductor material, and the material of the remaining region of the bit line 101 directly below the first region I can also be a metal silicide. Here, the position of the “remaining region” is located at the periphery of the “part of the region”.

[0046] For example, referring to Figure 2The plurality of metal silicide structures 111 in the bit line 101 are connected to each other to form a part of the bit line 101, and the metal silicide structure 111 can be partially located in the bit line 101 and partially located in the semiconductor channel 102 of the first region I. In other embodiments, the plurality of metal silicide structures in the same bit line can be spaced from each other.

[0047] Figure 2 The metal silicide structure 111 is located in the region of the substrate 100 defined by the dashed line similar to the ellipse, and the size of the region where the adjacent metal silicide structures 111 are in contact with each other is not limited in practical applications. In other embodiments, the entire thickness of the bit line can be the metal silicide structure 111.

[0048] In some embodiments, continuing to refer to Figure 2 For a single metal silicide structure 111, the depth of the metal silicide structure 111 gradually increases in the direction of the semiconductor channel 102 located on both sides of the insulating layer 107 and pointing to the insulating layer 107, that is, in the direction of C1 and C2.

[0049] Taking silicon as an example of a semiconductor element, the material of the metal silicide structure 111 includes at least one of cobalt silicide, nickel silicide, molybdenum silicide, titanium silicide, tungsten silicide, tantalum silicide, or platinum silicide.

[0050] In some embodiments, the semiconductor channel 102 can have a doping element, which is beneficial to improve the conductivity of the semiconductor channel 102, thereby being beneficial to reduce the on-voltage between the first region I and the third region III, that is, the on-voltage between the source and the drain in the GAA transistor. The doping element is a P-type doping element or an N-type doping element. Specifically, the N-type doping element can be at least one of arsenic, phosphorus, or antimony; and the P-type doping element can be at least one of boron, indium, or gallium.

[0051] In some embodiments, the GAA transistor can be a junctionless transistor, i.e., the types of the doping elements in the first region I, the second region II and the third region III are the same. Wherein, "junctionless" refers to no PN junction, i.e., the doping concentrations of the doping elements in the first region I, the second region II and the third region III are the same, and the advantages include: on the one hand, no additional doping is needed for the first region I and the third region III, thereby avoiding the problem that the doping process of the first region I and the third region III is difficult to control, especially as the transistor size is further reduced, if the first region I and the third region III are additionally doped, the doping concentration is more difficult to control; on the other hand, since the device is a junctionless transistor, it is beneficial to avoid using a super-steep source-drain concentration gradient doping process to make a super-steep PN junction in the nanometer scale range, thereby avoiding the problems of threshold voltage drift and increased leakage current caused by doping mutation, and it is also beneficial to suppress the short channel effect, thereby helping to further improve the integration density and electrical performance of the semiconductor structure. It can be understood that the additional doping here refers to the doping performed in order to make the type of the doping elements of the first region I and the third region III different from the type of the doping elements of the second region II.

[0052] With continued reference to Figure 2 and Figure 3 , in a plane perpendicular to the sidewall of the semiconductor channel 102, the cross-sectional area of the semiconductor channel 102 of the first region I is greater than the cross-sectional area of the semiconductor channel 102 of the second region II.

[0053] Wherein, the cross-sectional area of the semiconductor channel 102 of the second region II is smaller than the cross-sectional area of the semiconductor channel 102 of the first region I, and the semiconductor channel 102 of the second region II can serve as a channel region of the GAA transistor, thereby being beneficial to form a channel region with a smaller cross-sectional area and being beneficial to improve the control ability of the gate 104 surrounding the sidewall of the channel region on the channel region, thereby more easily controlling the turn-on or turn-off of the GAA transistor.

[0054] With reference to Figure 2 and Figure 3 , the dielectric layer 103 can include: a first dielectric layer 113 located between adjacent bit lines 101 and between the semiconductor channels 102 of the first region I on the adjacent bit lines 101; a second dielectric layer 123 located on the sidewall of the semiconductor channel 102 of the first region I and the sidewall of the first dielectric layer 113 of the first region I; and a third dielectric layer 133 surrounding the sidewall of the semiconductor channel 102 of the second region II and the third region III.

[0055] The first dielectric layer 113 between the adjacent bit lines 101 is used to realize electrical insulation between the adjacent bit lines 101; the first dielectric layer 113, the second dielectric layer 123 and the insulating layer 107 between the semiconductor channels 102 of the first region I on the adjacent bit lines 101 are used to realize electrical insulation between the semiconductor channels 102 of the first region I which are spaced apart along the first direction X and / or the second direction Y; the third dielectric layer 133 surrounding the sidewalls of the semiconductor channels 102 of the second region II can be used as a gate dielectric layer between the subsequently formed gate 104 and the semiconductor channels 102 of the second region II; the third dielectric layer 133 and the insulating layer 107 surrounding the sidewalls of the semiconductor channels 102 of the third region III are used to realize electrical insulation between the semiconductor channels 102 of the third region III which are spaced apart along the first direction X and / or the second direction Y.

[0056] In some embodiments, the third dielectric layer 133 can also be located on part of the sidewalls of the second dielectric layer 123, which is advantageous for further ensuring the insulation between the gate 104 and the semiconductor channels 102.

[0057] In some embodiments, the material of the first dielectric layer 113 and the material of the second dielectric layer 123 are the same, and further, the material of the first dielectric layer 113 and the material of the second dielectric layer 123 can both be silicon oxide; in other embodiments, the material of the third dielectric layer 133, the material of the second dielectric layer 123 and the material of the first dielectric layer 113 can all be the same; in yet other embodiments, the material of the third dielectric layer 133 can be different from the material of the second dielectric layer 123 and the material of the first dielectric layer 113, as long as the material of the third dielectric layer 133, the material of the second dielectric layer 123 and the material of the first dielectric layer 113 are all materials with good insulating effect.

[0058] In some embodiments, referring to Figure 4 , the single gate 104 extends along the second direction Y and surrounds the adjacent semiconductor channels 102 on the adjacent bit lines 101, and the single diffusion barrier layer 106 only surrounds the single metal-semiconductor compound layer 105. In some embodiments, the orthogonal projection of the third dielectric layer 133 on the substrate 110 and the orthogonal projection of the diffusion barrier layer 106 on the substrate 110 can coincide.

[0059] In some embodiments, the single gate 104 can surround a plurality of semiconductor channels 102 along the second direction Y, and the third dielectric layer 133 is between the gate 104 and the plurality of semiconductor channels 102, and the adjacent diffusion barrier layers 106 can be spaced apart by the second insulating layer 127.

[0060] In some embodiments, the material of the gate 104 includes at least one of polysilicon, titanium nitride, tantalum nitride, copper or tungsten, and the material of the diffusion barrier layer 106 can be titanium nitride.

[0061] In some embodiments, if the cross-sectional area of the semiconductor channel 102 in the first region I is larger than the cross-sectional area of the semiconductor channel 102 in the second region II in a plane perpendicular to the sidewall of the semiconductor channel 102, and the dielectric layer 103 includes the first dielectric layer 113, the second dielectric layer 123 and the third dielectric layer 133, the gate 104 is located at least on part of the top surface of the first dielectric layer 113 and part of the top surface of the second dielectric layer 123, and the diffusion barrier layer 106 is located on the top surface of the third dielectric layer 133.

[0062] The diffusion barrier layer 106 surrounds the sidewall of the metal-semiconductor compound layer 105, which is beneficial to prevent the metal elements in the metal-semiconductor compound layer 105 from diffusing into the insulating layer 107, so as to ensure the good insulating performance of the insulating layer 107. In addition, the diffusion barrier layer 106 is located on the top surface of the third dielectric layer 133, which can also avoid the diffusion of the related conductive elements in other conductive structures located on the top surface of the diffusion barrier layer 106 into the third dielectric layer 133, so as to ensure the good insulating performance of the third dielectric layer 133.

[0063] In some embodiments, the orthogonal projection of the diffusion barrier layer 106 on the substrate 110 can cover the orthogonal projection of the third dielectric layer 133 on the substrate 110, which is beneficial to more comprehensively prevent the diffusion of the related conductive elements in other conductive structures located on the top surface of the diffusion barrier layer 106 into the third dielectric layer 133.

[0064] In other embodiments, if the dielectric layer includes the first dielectric layer, the second dielectric layer and the third dielectric layer, the cross-sectional area of the semiconductor channel in the first region is equal to the cross-sectional area of the semiconductor channel in the second region in a plane perpendicular to the sidewall of the semiconductor channel, and the third dielectric layer and the gate jointly cover the top surface of the second dielectric layer.

[0065] In addition, the metal-semiconductor compound layer 105 has a relatively small resistivity compared with the non-metallic semiconductor material, and thus the resistivity of the metal-semiconductor compound layer 105 is smaller than that of the semiconductor channel 102. If the metal-semiconductor compound layer 105 has the electrically connecting layer 108 on the top surface, it is beneficial to form an ohmic contact between the top surface of the semiconductor channel 102 and the electrically connecting layer 108 by taking the metal-semiconductor compound layer 105 as a transition layer, so as to avoid the direct contact between the electrically connecting layer 108 and the semiconductor material to form a Schottky barrier contact. The ohmic contact is beneficial to reduce the contact resistance between the top surface of the semiconductor channel 102 and the electrically connecting layer 108, thereby reducing the energy consumption of the semiconductor structure during operation and improving the RC delay effect, so as to improve the electrical performance of the semiconductor structure. The material of the metal-semiconductor compound layer 105 includes at least one of cobalt silicide, nickel silicide, molybdenum silicide, titanium silicide, tungsten silicide, tantalum silicide or platinum silicide.

[0066] In some embodiments, the metal-semiconductor compound layer 105 can have a doping element, which is a P-type doping element or an N-type doping element. In this way, the conductivity of the metal-semiconductor compound layer 105 itself can be further improved.

[0067] In addition, based on the metal-semiconductor compound layer 105 having the doping element, the semiconductor channel 102 can also have the same type of doping element as that in the metal-semiconductor compound layer 105, and the concentration of the doping element in the metal-semiconductor compound layer 105 is greater than that in the semiconductor channel 102. In this way, while the conductivity of the semiconductor channel 102 itself is improved, the contact resistance between the metal-semiconductor compound layer 105 and the semiconductor channel 102 can be further reduced.

[0068] In some embodiments, the top surface of the metal-semiconductor compound layer 105 can be flush with the top surface of the diffusion barrier layer 106, and the length of the metal-semiconductor compound layer 105 in the direction Z perpendicular to the top surface of the bit line 101 can be less than or equal to the length of the diffusion barrier layer 106. In this way, the diffusion barrier layer 106 can at least cover the sidewall of the entire metal-semiconductor compound layer 105, thereby increasing the total area of the diffusion barrier layer 106 for preventing diffusion, so as to improve the effect of preventing the metal element in the metal-semiconductor compound layer 105 from diffusing into the insulating layer 107. In addition, the length of the diffusion barrier layer 106 is greater than the length of the metal-semiconductor compound layer 105, i.e., the diffusion barrier layer 106 also surrounds part of the sidewall of the semiconductor channel 102, which is conducive to preventing the doping element in the semiconductor channel 102 from diffusing into the insulating layer 107.

[0069] In some embodiments, the ratio of the length of the metal-semiconductor compound layer 105 to the length of the diffusion barrier layer 106 in the direction Z perpendicular to the top surface of the bit line 101 can be 0.8-1.2. In this way, it is conducive to ensuring that the diffusion barrier layer 106 and the gate 104 have a suitable spacing therebetween, so as to avoid parasitic capacitance between the diffusion barrier layer 106 and the gate 104.

[0070] In some embodiments, the insulating layer 107 includes: a first insulating layer 117 located between the dielectric layers 103 of adjacent semiconductor channels 102 and between the gates 104, and extending along the second direction Y, the top surface of the first insulating layer 117 being not lower than the top surface of the metal-semiconductor compound layer 105; and a second insulating layer 127 located on the top surface of the gate 104 and between the first insulating layer 117 and the diffusion barrier layer 106.

[0071] In some embodiments, the first insulating layer 117 and the second insulating layer 127 jointly function to achieve electrical insulation between adjacent semiconductor channels 102 and electrical insulation between adjacent gates 104. In addition, the second insulating layer 127 located on the top surface of the gate 104 can achieve electrical insulation between the gate 104 and other conductive structures.

[0072] In some embodiments, the semiconductor structure can further include: an electrical connection layer 108 located on the top surface of the metal-semiconductor compound layer 105 and the top surface of the diffusion barrier layer 106, and the insulating layer 107 separates the adjacent electrical connection layers 108 located on the top surface of the adjacent semiconductor channel 102.

[0073] The electrical connection layer 108 can be used to realize the electrical connection between the semiconductor channel 102 and a capacitor structure (not shown).

[0074] As the metal-semiconductor compound layer 105 has a relatively smaller resistivity than the non-metallized semiconductor channel 102, the metal-semiconductor compound layer 105 is beneficial to realize the ohmic contact between the top surface of the semiconductor channel 102 and other conductive structures, such as the electrical connection layer 108, reduce the contact resistance between the top surface of the semiconductor channel 102 and the electrical connection layer 108, and improve the electrical performance of the semiconductor channel 102. In addition, the diffusion barrier layer 106 separates the metal-semiconductor compound layer 105 and the insulating layer 107, which is beneficial to prevent the metal elements in the metal-semiconductor compound layer 105 from diffusing into the insulating layer 107, causing the insulating performance of the insulating layer 107 to decrease. Therefore, the embodiments of the present application are beneficial to reduce the contact resistance between the top surface of the semiconductor channel 102 and the electrical connection layer 108 through the metal-semiconductor compound layer 105 while ensuring the good insulating performance of the insulating layer 107, thereby improving the electrical performance of the semiconductor structure.

[0075] Another embodiment of the present application further provides a manufacturing method of a semiconductor structure, which can be used to form the semiconductor structure described above.

[0076] Figures 1 to 17 The manufacturing method of the semiconductor structure provided by another embodiment of the present application is described in detail below in combination with the drawings. The same or corresponding parts of the manufacturing method of the semiconductor structure provided by another embodiment of the present application will not be described in detail below.

[0077] It should be noted that, in order to facilitate the description and clearly show the steps of the manufacturing method of the semiconductor structure, the cross-sectional structure schematic diagrams of the semiconductor structure in the embodiments of the present application are all local structure schematic diagrams. Figures 1 to 17

[0078] In the above-mentioned embodiments, the semiconductor structure can be a semiconductor structure shown in FIG. 1, and the manufacturing method of the semiconductor structure can include the following steps. Figure 7 Figure 6 The cross-sectional structure schematic diagram of the structure shown in FIG. 1 along the first cross-sectional direction AA1 and the cross-sectional structure schematic diagram along the second cross-sectional direction BB1, it should be noted that one or both of the cross-sectional structure schematic diagram along the first cross-sectional direction AA1 and the cross-sectional structure schematic diagram along the second cross-sectional direction BB1 will be set according to the description needs. ​​

[0079] Referring to Figures 5 to 7 , a substrate 100 is provided, the substrate 100 comprises spaced-apart bit lines 101 and an initial semiconductor channel 112, the bit lines 101 extend along a first direction X, the initial semiconductor channel 102 is located on part of the top surface of the bit lines 101, and in a direction Z perpendicular to the top surface of the bit lines 101, the initial semiconductor channel 112 comprises a first region I, a second region II and an initial third region IV arranged in sequence; a dielectric layer 103 is formed, the dielectric layer 103 is located between adjacent bit lines 101 and part of the side wall of the initial semiconductor channel 112.

[0080] It should be noted that the first region I and the second region II of the initial semiconductor channel 112 are the first region and the second region of the subsequent semiconductor channel, and the initial third region IV of the initial semiconductor channel 112 is prepared for the third region of the subsequently formed semiconductor channel and the metal semiconductor compound layer. It can be understood that the first region I and the subsequently formed third region can both serve as the source or drain of the subsequently formed GAA transistor with a semiconductor channel, and the second region II corresponds to the dielectric layer and the gate of the subsequently formed GAA transistor.

[0081] In some embodiments, providing the substrate 100 can comprise the following steps:

[0082] Referring to Figure 5 , an initial substrate 120 is provided, the initial substrate 120 has an initial first dielectric layer 143 extending along a first direction X; referring to Figures 6 to 7 , the initial substrate 120 and the initial first dielectric layer 143 are patterned to form spaced-apart bit lines 101 and an initial semiconductor channel 112, and the initial first dielectric layer 143 between adjacent bit lines 101, and the top surface of the initial first dielectric layer 143 is not lower than the top surface of the initial semiconductor channel 112, the side wall of the initial semiconductor channel 112, the side wall of the initial first dielectric layer 143 and part of the top surface of the bit lines 101 form a trench 109, the trench 109 extends along a second direction X.

[0083] Wherein, the material type of the initial substrate 120 can be an elemental semiconductor material or a crystalline inorganic compound semiconductor material. The elemental semiconductor material can be silicon or germanium; the crystalline inorganic compound semiconductor material can be silicon carbide, silicon germanium, gallium arsenide or indium gallium, etc. The initial substrate 120 is the basis for forming the bit lines 101 and the initial semiconductor channel 112, and at the same time of patterning the initial substrate 120 and the initial first dielectric layer 143 to form the bit lines 101 and the initial semiconductor channel 112, the substrate 110 is also formed.

[0084] The method of patterning the initial substrate 120 and the initial first dielectric layer 143 includes a self-aligned quadruple patterning (SAQP) or a self-aligned double patterning (SADP).

[0085] In some embodiments, the initial substrate 120 can also be subjected to a doping process and an annealing process, so that the initial substrate 120 is doped with N-type doping elements or P-type doping elements, which is beneficial to improve the conductivity of the initial semiconductor channel 102 formed based on the initial substrate 120, thereby reducing the on-state voltage between the first region I and the initial third region III, i.e., reducing the on-state voltage between the source and the drain in the subsequently formed GAA transistor. In addition, doping the initial substrate 120 with N-type doping elements or P-type doping elements is beneficial to improve the conductivity of the bit line 101 formed based on the initial substrate 120, thereby reducing the contact resistance between the first region I and the bit line 101, and improving the electrical performance of the semiconductor structure.

[0086] The doping elements are P-type doping elements or N-type doping elements. Specifically, the N-type doping elements can be at least one of arsenic, phosphorus, or antimony, and the P-type doping elements can be at least one of boron, indium, or gallium.

[0087] Reference Figures 8 to 17 The gate 104 is formed to surround the dielectric layer 103 of the second region II and extend along a second direction Y, and the first direction X is different from the second direction Y. The diffusion barrier layer 106 is formed to surround the remaining sidewall of the initial semiconductor channel 112, and the diffusion barrier layer 106 has a spacing with the gate 104. The top surface of the initial semiconductor channel 112 is subjected to a metal silicidation process, so that part of the initial semiconductor channel 112 of the initial third region IV is converted into a metal semiconductor compound layer 105, and the remaining initial third region IV, the second region II, and the third region III constitute the semiconductor channel 102. The insulating layer 107 is formed between adjacent semiconductor channels 102 on the same bit line 101.

[0088] In some embodiments, the step of forming the metal semiconductor compound layer 105 by the metal silicidation process can include forming a first metal layer (not shown) on the top surface of the initial semiconductor channel 112, and the first metal layer provides metal elements for the metal semiconductor compound layer 105. The material of the first metal layer includes at least one of cobalt, nickel, molybdenum, titanium, tungsten, tantalum, or platinum.

[0089] In some embodiments, when the initial semiconductor channel 112 sidewall, the initial first dielectric layer 143 sidewall and the partial top surface of the bit line 101 enclose the trench 109, the formation of the dielectric layer 103, the gate 104, the diffusion barrier layer 106 and the insulating layer 107 can include the following steps:

[0090] Referring to Figures 8 to 10 , the first dielectric layer 113 is formed between adjacent bit lines 101 and the semiconductor channels 102 in the first region I on the adjacent bit lines 101; the second dielectric layer 123 is formed on the sidewall of the trench 109 in the first region I; the first insulating layer 117 is formed, which is located in the trench 109 and separates the adjacent second dielectric layers 123, and the top surface of the first insulating layer 117 is not lower than the top surface of the initial semiconductor channel 112.

[0091] The top surface of the first insulating layer 117 is not lower than the top surface of the initial semiconductor channel 112, which is beneficial for the subsequent formation of the second interval between the first insulating layer 117 and the semiconductor channels 102 in the second region II and the third region III. Then, the gate with accurate size can be formed in the second interval by self-alignment, without the need for etching process to form the gate with high size accuracy. This is beneficial for simplifying the formation steps of the gate, and by adjusting the size of the second interval, a small size gate can be obtained.

[0092] In some embodiments, the formation of the first dielectric layer 113, the second dielectric layer 123 and the first insulating layer 117 can include the following steps:

[0093] Referring to Figure 8 , the initial second dielectric layer 153 is formed on the sidewall of the trench 109 (refer to Figure 7 ), and the first interval 119 is formed between adjacent initial second dielectric layers 153. In some embodiments, the following process steps can be used to form the initial second dielectric layer 153: a deposition process is performed to form a surface covering the top surface of the semiconductor channel 102 and all exposed sidewalls, and also covering the top surface and sidewalls exposed at the initial first dielectric layer 143. The material of the initial second dielectric layer 153 includes silicon oxide.

[0094] Referring to Figure 8 and Figure 9 , the first insulating layer 117 is formed in the first interval 119. In some embodiments, the following process steps can be used to form the first insulating layer 117: a first insulating film is formed covering the top surface of the initial second dielectric layer 153 and filling the first interval 119; the first insulating film is subjected to chemical mechanical planarization treatment until the initial second dielectric layer 153 is exposed, and the remaining first insulating film serves as the first insulating layer 117. The material of the first insulating layer 117 includes silicon nitride.

[0095] The material of the initial first dielectric layer 143 is the same as that of the initial second dielectric layer 153, which is beneficial for removing part of the initial first dielectric layer 143 and part of the initial second dielectric layer 153 by the same removal step to form the second space.

[0096] In some embodiments, continuing to refer to Figure 8 Before forming the first insulating layer 117, after forming the initial second dielectric layer 153, the part of the top surface of the bit line 101 exposed by the initial second dielectric layer 153 is subjected to a metal silicide process to form the metal silicide structure 111.

[0097] The metal silicide structure 111 has a relatively small resistivity compared to the non-metallized semiconductor material, so the bit line 101 containing the metal silicide structure 111 has a smaller resistivity than the semiconductor channel 102, thereby reducing the resistance of the bit line 101 itself and reducing the contact resistance between the bit line 101 and the semiconductor channel 102 of the first region I, further improving the electrical performance of the semiconductor structure.

[0098] In some embodiments, the step of subjecting the part of the top surface of the bit line 101 exposed by the initial second dielectric layer 153 to a metal silicide process can include forming a second metal layer (not shown) on the top surface of the bit line 101 exposed, the second metal layer providing a metal element for the metal silicide structure 111. The material of the second metal layer includes at least one of cobalt, nickel, molybdenum, titanium, tungsten, tantalum, or platinum.

[0099] In other embodiments, the top surface of the bit line exposed can not be subjected to a metal silicide process, and the first insulating layer can be directly formed on the top surface of the bit line exposed.

[0100] Then, referring to Figure 10 The initial first dielectric layer 143 and the initial second dielectric layer 153 are etched with the first insulating layer 117 as a mask to form the first dielectric layer 113 and the second dielectric layer 123.

[0101] In the step of etching the initial first dielectric layer 143 and the initial second dielectric layer 153, the top surface of the semiconductor channel 102 is also exposed, which is beneficial for subsequent metal silicide processing of the top surface of the semiconductor channel 102 to form a metal semiconductor compound layer.

[0102] Referring to Figures 11 to 17, the third dielectric layer 133 is located on the sidewall of the trench 109 in the second region II and the partial sidewall of the trench 109 in the initial third region IV, and the second insulating layer 127 is located between the first insulating layer 117 and the third dielectric layer 133; the diffusion barrier layer 106 is formed on the remaining sidewall of the trench 109 in the initial third region IV, and the first dielectric layer 113, the second dielectric layer 123 and the third dielectric layer 133 constitute the dielectric layer 103; and the first insulating layer 117 and the second insulating layer 127 constitute the insulating layer 107.

[0103] In some embodiments, the forming of the third dielectric layer 133, the gate 104 and the second insulating layer 127 can include the following steps:

[0104] Referring to Figure 13 , the initial third dielectric layer 163 is formed on the sidewall of the initial semiconductor channel 112 in the second region II and the initial third region IV, and the initial third dielectric layer 163 and the first insulating layer 117 have the second interval 129 therebetween. In some embodiments, the initial third dielectric layer 163 can be formed by the following process steps: performing a thermal oxidation treatment on the exposed surface of the initial semiconductor channel 112 in the second region II and the initial third region IV to form the initial third dielectric layer 163. In this case, the material of the initial third dielectric layer 163 is silicon oxide. In other embodiments, the initial third dielectric layer covering the surface of the initial semiconductor channel in the second region and the initial third region can also be formed by a deposition process.

[0105] Referring to Figures 12 to 13 , the gate 104 is formed in the second interval 129 (referring to Figure 11 ) in the second region II. In this case, the step of forming the gate 104 can include the following steps: Figure 12 , forming the initial gate 114, which fills the second interval 129 and is located on the top surface of the initial third dielectric layer 163; and Figure 13 , etching to remove the initial gate 114 surrounding the sidewall of the semiconductor channel 102 in the initial third region IV and located on the top surface of the initial third dielectric layer 163, and the remaining initial gate 114 serves as the gate 104, so that the gate 104 only surrounds the sidewall of the semiconductor channel 102 in the second region II.

[0106] Referring to Figure 14 , the second insulating layer 127 is formed in the remaining second interval 129. In some embodiments, the second insulating layer 127 can be formed by the following process steps: performing a deposition process to form the second insulating layer 127 which fills the remaining second interval 129 (referring to Figure 11and a second insulating film covering the top surface of the initial third dielectric layer 163; performing chemical mechanical grinding on the second insulating film and the first insulating layer 117 until the initial third dielectric layer 163 is exposed, and the remaining second insulating film serves as a second insulating layer 127. The material of the second insulating film includes silicon nitride.

[0107] Referring to Figure 15 etching the initial third dielectric layer 163 with the second insulating layer 127 as a mask to form a third dielectric layer 133.

[0108] In the step of forming the third dielectric layer 133, not only the top surface of the initial semiconductor channel 112 is exposed, but also the side wall of the portion of the initial semiconductor channel 112 close to the top surface of the initial third region IV is exposed, which prepares for the subsequent formation of the diffusion barrier layer.

[0109] Referring to Figure 15 and Figure 16 The third dielectric layer 133, the second insulating layer 127 and the initial semiconductor channel 112 enclose a recess 139, and the diffusion barrier layer 106 is formed to fill the recess 139. In some embodiments, the diffusion barrier layer 106 can be formed by the following process steps: forming a barrier film covering the top surface of the initial semiconductor channel 112 and filling the recess 139; etching the barrier film until the side wall of the portion of the initial semiconductor channel 112 close to the top surface of the initial third region IV is exposed, and the remaining barrier film serves as the diffusion barrier layer 106. The material of the diffusion barrier layer 106 includes titanium nitride.

[0110] The diffusion barrier layer 106 is beneficial to prevent the metal elements in the metal semiconductor compound layer 105 from diffusing into the insulating layer 107, so as to ensure the good insulating performance of the insulating layer 107. In addition, the diffusion barrier layer 106 is located on the top surface of the third dielectric layer 133, which can also avoid the diffusion of the related conductive elements in other conductive structures located on the top surface of the diffusion barrier layer 106 into the third dielectric layer 133, so as to ensure the good insulating performance of the third dielectric layer 133.

[0111] Then, referring to Figure 16 and Figure 17 performing metal silicidation treatment on the top surface of the initial semiconductor channel 112 to convert part of the initial semiconductor channel 112 of the initial third region IV into the metal semiconductor compound layer 105, and the remaining initial third region IV, the second region II and the third region III constitute the semiconductor channel 102.

[0112] Compared with the semiconductor channel 102, the metal-semiconductor compound layer 105 has a smaller resistivity, which is conducive to forming an ohmic contact between the top surface of the semiconductor channel 102 and the electrically connected layer by taking the metal-semiconductor compound layer 105 as a transition layer, thereby avoiding the formation of a Schottky barrier contact between the electrically connected layer and the semiconductor channel 102. The ohmic contact is conducive to reducing the contact resistance between the top surface of the semiconductor channel 102 and the electrically connected layer, thereby reducing the energy consumption of the semiconductor structure during operation and improving the RC delay effect, so as to improve the electrical performance of the semiconductor structure.

[0113] In some embodiments, after the diffusion barrier layer 106 is formed, before the metal-semiconductor compound layer 105 is formed, the manufacturing method can further include: performing a doping treatment on the top surface of the initial semiconductor channel 112 to make the part of the initial semiconductor channel 112 in the initial third region IV have a doping element, which is a P-type doping element or an N-type doping element.

[0114] In addition, the semiconductor channel 102 can have the same type of doping element as the metal-semiconductor compound layer 105, and the concentration of the doping element in the metal-semiconductor compound layer 105 is greater than that in the semiconductor channel 102. In this way, while improving the conductivity of the semiconductor channel 102 itself, the contact resistance between the metal-semiconductor compound layer 105 and the semiconductor channel 102 is further reduced.

[0115] In some embodiments, in combination with reference to Figure 17 and Figures 2 to 3 The top surface of the insulating layer 107 is higher than the top surface of the metal-semiconductor compound layer 105, and the insulating layer 107, the metal-semiconductor compound layer 105, and the diffusion barrier layer 106 enclose a through hole 149. The manufacturing method can further include: forming an electrically connected layer 108 that fills the through hole 149. The electrically connected layer 108 can be used to realize the electrical connection between the semiconductor channel 102 and a capacitor structure (not shown).

[0116] In summary, the formation of second spacers 129 between first insulating layer 117 and semiconductor channel 102 in second region II and third region III facilitates the self-alignment formation of a precisely dimensioned gate 104 within second spacers 129. This allows for the formation of highly dimensionally precise gate 104 without the need for an etching process, simplifying the steps for forming gate 104. Furthermore, by adjusting the size of second spacers 129, a small gate 104 can be obtained. Furthermore, a metal-semiconductor compound layer 105 is formed as a transition layer on the top surface of semiconductor channel 102 to achieve ohmic contact between the top surface of semiconductor channel 102 and electrical connection layer 108, thereby reducing the contact resistance between the top surface of semiconductor channel 102 and electrical connection layer 108. Moreover, the diffusion barrier layer 106 is formed between the metal semiconductor compound layer 105 and the insulating layer 107, which is beneficial to prevent the metal elements in the metal semiconductor compound layer 105 from diffusing into the insulating layer 107. This is beneficial to reducing the contact resistance between the top surface of the semiconductor channel 102 and the electrical connection layer 108 through the metal semiconductor compound layer 105 while ensuring the good insulation performance of the insulating layer 107, thereby improving the electrical performance of the semiconductor structure.

[0117] Those skilled in the art will appreciate that the above-described embodiments are specific examples for implementing the present application, and that in actual applications, various changes in form and detail may be made thereto without departing from the spirit and scope of the present application. Any person skilled in the art may make changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be subject to the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that include: a substrate comprising bit lines and semiconductor channels arranged at intervals, the bit lines extending along a first direction, the semiconductor channels being located on a portion of a top surface of the bit lines, and comprising a first region, a second region, and a third region arranged in sequence in a direction perpendicular to the top surface of the bit lines; a dielectric layer located between adjacent bit lines and on the sidewalls of the semiconductor channel; the dielectric layer includes: a third dielectric layer surrounding the sidewalls of the semiconductor channel in the second region and the third region; a gate, surrounding the dielectric layer in the second region and extending along a second direction, wherein the first direction is different from the second direction; a metal semiconductor compound layer, located on the top surface of the semiconductor channel; a diffusion barrier layer, at least surrounding the sidewall of the metal semiconductor compound layer; the diffusion barrier layer is located on the top surface of the third dielectric layer; An insulating layer is located between adjacent semiconductor channels on the same bit line and isolates the gate and the diffusion barrier layer located on adjacent dielectric layers.

2. The semiconductor structure according to claim 1, wherein The metal semiconductor compound layer contains a doping element, and the doping element is a P-type doping element or an N-type doping element.

3. The semiconductor structure according to claim 2, wherein: The semiconductor channel has the doping element, and the concentration of the doping element in the metal-semiconductor compound layer is greater than the concentration in the semiconductor channel.

4. The semiconductor structure according to claim 1, wherein The top surface of the metal semiconductor compound layer is flush with the top surface of the diffusion barrier layer. In a direction perpendicular to the top surface of the bit line, the length of the metal semiconductor compound layer is less than or equal to the length of the diffusion barrier layer.

5. The semiconductor structure according to claim 1, wherein Also includes: The electrical connection layer is located on the top surface of the metal semiconductor compound layer and the top surface of the diffusion barrier layer, and the insulating layer isolates the adjacent electrical connection layers located on the top surfaces of adjacent semiconductor channels.

6. The semiconductor structure according to claim 1, wherein The single gate extends along the second direction and surrounds the adjacent semiconductor channels on the adjacent bit lines, and the single diffusion barrier layer only surrounds the single metal-semiconductor compound layer.

7. The semiconductor structure according to claim 1, wherein: Also includes: The metal silicide structure is located at least in the bit line facing the bottom surface of the insulating layer.

8. The semiconductor structure according to claim 7, wherein: Along the direction from the semiconductor channels located on both sides of the insulating layer to the insulating layer, the depth of the metal silicide structure gradually increases.

9. The semiconductor structure according to claim 1, wherein: In a plane perpendicular to a sidewall of the semiconductor channel, a cross-sectional area of ​​the semiconductor channel in the first region is greater than a cross-sectional area of ​​the semiconductor channel in the second region.

10. The semiconductor structure according to claim 1, wherein: The dielectric layer further comprises: A first dielectric layer is located between adjacent bit lines and between the semiconductor channels of the first region on adjacent bit lines; The second dielectric layer is located on the sidewalls of the semiconductor channel in the first region and the sidewalls of the first dielectric layer in the first region.

11. The semiconductor structure according to claim 10, wherein: The gate is located at least on a portion of the top surface of the first dielectric layer and a portion of the top surface of the second dielectric layer.

12. The semiconductor structure according to claim 1, wherein The insulating layer comprises: a first insulating layer, located between the dielectric layers and the gates of adjacent semiconductor channels and extending along the second direction, wherein a top surface of the first insulating layer is not lower than a top surface of the metal-semiconductor compound layer; The second insulating layer is located on the top surface of the gate and between the first insulating layer and the diffusion barrier layer.

13. A method for manufacturing a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising bit lines and initial semiconductor channels arranged at intervals, the bit lines extending along a first direction, the initial semiconductor channels being located on a portion of a top surface of the bit lines, and comprising a first region, a second region, and an initial third region arranged in sequence in a direction perpendicular to the top surface of the bit lines; forming a dielectric layer, the dielectric layer being located between adjacent bit lines and on a sidewall of the initial semiconductor channel portion; the dielectric layer comprising: a third dielectric layer surrounding the semiconductor channel sidewall of the second region and the third region; forming a gate, the gate surrounding the dielectric layer in the second region and extending along a second direction, wherein the first direction is different from the second direction; forming a diffusion barrier layer, the diffusion barrier layer surrounding the remaining sidewalls of the initial semiconductor channel, with a gap between the diffusion barrier layer and the gate; the diffusion barrier layer is located on the top surface of the third dielectric layer; Performing metal silicide treatment on the top surface of the initial semiconductor channel to convert a portion of the initial semiconductor channel in the initial third region into a metal semiconductor compound layer, with the remaining initial third region, the second region, and the third region constituting a semiconductor channel; An insulating layer is formed, where the insulating layer is located between adjacent semiconductor channels on the same bit line.

14. The manufacturing method according to claim 13, wherein: After forming the diffusion barrier layer and before forming the metal semiconductor compound layer, the method further includes: performing doping treatment on the top surface of the initial semiconductor channel so that the initial semiconductor channel in part of the initial third region has a doping element, and the doping element is a P-type doping element or an N-type doping element.

15. The manufacturing method according to claim 13, wherein: The step of providing a substrate comprises: Providing an initial substrate, wherein the initial substrate has an initial first dielectric layer extending along the first direction; The initial substrate and the initial first dielectric layer are patterned to form the spaced-apart bit lines and the initial semiconductor channels, and the initial first dielectric layer is located between adjacent bit lines, wherein a top surface of the initial first dielectric layer is not lower than a top surface of the initial semiconductor channels, and sidewalls of the initial semiconductor channels, sidewalls of the initial first dielectric layer, and portions of the top surfaces of the bit lines form trenches, and the trenches extend along the second direction.

16. The manufacturing method according to claim 15, wherein: The steps of forming the dielectric layer, the gate, the diffusion barrier layer and the insulating layer include: forming a first dielectric layer between adjacent bit lines and between the semiconductor channels of the first regions on adjacent bit lines; forming a second dielectric layer on the sidewalls of the trench in the first region; forming a first insulating layer, wherein the first insulating layer is located in the trench and isolates the adjacent second dielectric layer, and a top surface of the first insulating layer is not lower than a top surface of the initial semiconductor channel; forming the third dielectric layer and the second insulating layer, wherein the third dielectric layer is located on the sidewalls of the trench in the second region and on a portion of the sidewalls of the trench in the initial third region, and the second insulating layer is located between the first insulating layer and the third dielectric layer; A diffusion barrier layer is formed on the remaining sidewalls of the trench in the initial third region. The first dielectric layer, the second dielectric layer and the third dielectric layer constitute the dielectric layer; and the first insulating layer and the second insulating layer constitute the insulating layer.

17. The manufacturing method according to claim 16, wherein the step of forming the first dielectric layer, the second dielectric layer and the first insulating layer comprises: forming an initial second dielectric layer on the sidewall of the trench, with a first gap between adjacent initial second dielectric layers; forming the first insulating layer in the first space; The initial first dielectric layer and the initial second dielectric layer are etched using the first insulating layer as a mask to form the first dielectric layer and the second dielectric layer.

18. The manufacturing method according to claim 17, wherein: Before forming the first insulating layer and after forming the initial second dielectric layer, a metal silicide treatment is performed on a portion of the top surface of the bit line exposed by the initial second dielectric layer to form a metal silicide structure.

19. The manufacturing method according to claim 16, wherein: The steps of forming the third dielectric layer, the gate and the second insulating layer include: forming an initial third dielectric layer on the sidewalls of the initial semiconductor channel in the second region and the initial third region, with a second gap between the initial third dielectric layer and the first insulating layer; forming the gate in the second space of the second region; forming the second insulating layer in the remaining second spaces; etching the initial third dielectric layer using the second insulating layer as a mask to form the third dielectric layer; The third dielectric layer, the second insulating layer and the initial semiconductor channel form a groove to form the diffusion barrier layer that fills the groove.

20. The manufacturing method according to claim 13, wherein: The top surface of the insulating layer is higher than the top surface of the metal semiconductor compound layer. The insulating layer, the metal semiconductor compound layer and the diffusion barrier layer form a through hole. The manufacturing method further includes: forming an electrical connection layer that fills the through hole.

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