A write-and-read heterogeneous dual-gate neuromorphic device and its fabrication method

Abstract

This invention belongs to the field of semiconductor technology and discloses a write-and-read heterogeneous dual-gate neuromorphic device and its fabrication method. The device includes a bottom gate electrode, a gate insulating layer, an electrolyte layer, a charge trapping layer, an organic semiconductor layer, a horizontal gate electrode, and source / drain electrodes. The key feature is that the horizontal gate and the organic semiconductor layer of the neuromorphic device are located above the charge trapping layer and are separated from each other; the source / drain electrodes are located above the organic semiconductor layer. The device provided by this invention simultaneously possesses a bottom gate and a horizontal gate. The dual-gate structure enables the device to perform bottom-gate writing and horizontal-gate reading, or vice versa, effectively avoiding crosstalk problems during write and read operations. The device also exhibits both electrical double-layer effect and charge trapping effect. Most of the device is fabricated using a solution method, which is simple, easy to operate, low-cost, and easy to promote, and possesses good stability.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, specifically relating to a dual-gate neuromorphic device with heterogeneous writing and reading capabilities and its fabrication method. Background Technology

[0002] With the rapid development of information technology, traditional artificial intelligence chips have encountered two major challenges: the "memory wall" problem caused by the von Neumann architecture and the "failure" of Moore's Law, making them unable to meet the urgent needs of today's rapidly developing information technology for efficient and high-speed computing. Neuromorphic computing systems inspired by the brain, with their advantages of high parallelism, in-memory computing, and ultra-low power consumption, are expected to fundamentally break through the bottlenecks of the traditional von Neumann computer system architecture, leading to the rapid development of computer miniaturization and artificial intelligence.

[0003] Neuromorphic devices are crucial hardware carriers for neuromorphic computing and a key technology for constructing neuromorphic chips. Based on the number of input ports, neuromorphic devices can be categorized into two-terminal, three-terminal, and multi-terminal devices. Two-terminal devices include phase-change memories and memristors; three-terminal devices include ferroelectric transistors and organic field-effect transistors; and multi-terminal devices include memristor synaptic transistors, among others. Among these, organic field-effect transistors (OFETs) have broad application prospects in memory, sensors, and integrated circuits due to their advantages such as light weight, low cost, large-area flexible fabrication, and solution-processability, making them one of the important frontier directions in the research of organic semiconductor materials and devices.

[0004] Organic field-effect transistors (OFETs), as three-port devices, can not only simultaneously transmit signals and perform training and learning, but also perform nonlinear spatiotemporal integration and coordinated control of multiple signals. Currently, in the testing and application of OFET neuromorphic devices, the isomorphic nature of writing and reading (using the same gate for both operations) leads to crosstalk within the device, affecting its performance.

[0005] In view of this, the present invention provides a writing and reading heterogeneous dual-gate neuromorphic device and its fabrication method.

[0006] Based on the above analysis, the problems and shortcomings of the existing technology are as follows:

[0007] Currently, during the testing and application of OFET neuromorphic devices, the isomorphic nature of writing and reading (i.e., using the same gate for both operations) leads to crosstalk within the device, affecting its performance. Summary of the Invention

[0008] To address the aforementioned technical problems of existing OFET neuromorphic devices, this invention provides a dual-gate neuromorphic device with heterogeneous write and read operations and its fabrication method, aiming to solve the crosstalk problem generated during the write and read processes.

[0009] The invention discloses a write-and-read heterogeneous dual-gate neuromorphic device comprising a bottom gate electrode, a gate insulating layer, an electrolyte layer, a charge trapping layer, an organic semiconductor layer, a horizontal gate electrode, and source / drain electrodes. The electrode material is either Cu or Au; the electrolyte layer material is chitosan + lactic acid; the charge trapping layer material is either PS (polystyrene), OTS (octadecyltrichlorosilane), or PVDF (polyvinylidene fluoride); the semiconductor layer material is pentacene; the gate insulating layer is SiO2; and the bottom gate is Si.

[0010] The objective of this invention is achieved through the following technical solution:

[0011] The neuromorphic device of this invention is an organic field-effect transistor, using organic semiconductors as the conductive channel, a charge trapping layer for capturing charges, and an electrolyte layer as the ion transport layer. The device structure has been optimized, employing a dual-gate structure with a horizontal gate and a bottom gate, enabling heterogeneous writing and reading.

[0012] To achieve the above objectives, the present invention also provides a method for fabricating a writing and reading heterogeneous dual-gate neuromorphic device, with the charge trapping layer taking OTS as an example, and the specific steps are as follows:

[0013] Step 1: Prepare an OTS solution with OTS as the solute and toluene as the solvent, in a ratio of 15 μl: 15 ml.

[0014] Step 2: Prepare the Si / SiO2 substrate, ultrasonically clean it; clean it with anhydrous ethanol, blow away the surface moisture with a nitrogen gun, and dry it in a forced-air drying oven.

[0015] Step 3: Treat the substrate prepared in Step 2 with ultraviolet ozone for 10 minutes, preheat the chitosan / lactic acid solution with ultrasonic uniform heating for 3 hours, then spin-coat it onto the side of the substrate away from the gate electrode, and perform thermal annealing.

[0016] Step 4: Spin-coat the OTS solution and place it on a hot plate for heat annealing.

[0017] Step 5: Place the silicon wafer that has completed the above steps into a vacuum evaporation system and sequentially deposit 30nm pentacene and 50nm horizontal gate and source / drain electrodes.

[0018] Step 6: Remove the fabricated device and perform relevant electrical tests.

[0019] In step 3, the spin coating speed of the chitosan / lactic acid solution is 3000 rpm, the spin coating time is 1 min, and the heat annealing is 20 min at a temperature of 110℃.

[0020] In step 4, the spin coating speed of the OTS solution is 3000 rpm, the spin coating time is 30 s, and the heat annealing is 20 min at a temperature of 110℃.

[0021] In step 5, the evaporation rate of pentacene is The electrode deposition rate is The film thickness is monitored and controlled by a crystal oscillator film thickness gauge.

[0022] Based on the above technical solutions and the technical problems solved, the advantages and positive effects of the technical solution to be protected by this invention are as follows:

[0023] First, addressing the technical problems existing in the prior art and the difficulty in solving them, this paper closely analyzes, in conjunction with the technical solution to be protected by this invention and the results and data obtained during the research and development process, how the technical solution of this invention solves the technical problems, and the inventive technical effects brought about by solving these problems. The specific description is as follows:

[0024] The device provided by this invention has both a bottom gate and a horizontal gate. The dual-gate structure enables the device to perform operations such as bottom gate writing and horizontal gate reading or horizontal gate writing and bottom gate reading, effectively avoiding crosstalk problems generated during writing and reading operations.

[0025] The device of the present invention also exhibits two types of charge effects: electric double-layer effect and charge trapping effect.

[0026] Most of the devices provided by this invention are prepared by solution method, which is simple and easy to operate, low in cost and easy to promote, and has good stability.

[0027] Second, considering the technical solution as a whole or from a product perspective, the technical effects and advantages of the technical solution to be protected by this invention are specifically described as follows:

[0028] This invention provides a heterogeneous dual-gate neuromorphic device for writing and reading, and its fabrication method. The neuromorphic device includes a bottom gate electrode, a gate insulating layer, an electrolyte layer, a charge trapping layer, an organic semiconductor layer, a horizontal gate electrode, and source / drain electrodes. The purpose is to solve the crosstalk problem generated during writing and reading. Furthermore, the device of this invention exhibits both charge trapping effect and electrical double-layer effect.

[0029] Third, as supplementary evidence of the inventive step of the claims of this invention, it is also reflected in the following important aspects:

[0030] (1) The expected benefits and commercial value of the technical solution of this invention after transformation are as follows:

[0031] The device of this invention has good electrical and gate control characteristics, which can effectively avoid crosstalk problems generated during writing and reading. It is simple to manufacture, easy to operate, and low in cost, which is conducive to its widespread application.

[0032] (2) The technical solution of this invention fills a technical gap in the industry both domestically and internationally:

[0033] (3) Whether the technical solution of the present invention solves the technical problem that people have long wanted to solve but have never been able to solve successfully:

[0034] Solving the crosstalk effect during the writing and reading process of neuromorphic devices is an urgent problem for researchers. The neuromorphic device designed in this invention has the characteristics of heterogeneous reading and writing, which can effectively avoid crosstalk, thus improving the existing technology. Attached Figure Description

[0035] Figure 1 This is a structural diagram of a dual-gate neuromorphic device with heterogeneous writing and reading capabilities provided in an embodiment of the present invention;

[0036] Figure 2 This is a diagram of device transfer characteristic curves (horizontal gate write, horizontal gate read) provided in an embodiment of the present invention;

[0037] Figure 3 This is a diagram of device transfer characteristic curves (horizontal gate write, bottom gate read) provided in an embodiment of the present invention;

[0038] Figure 4 This is a diagram of device transfer characteristic curves (bottom gate write, bottom gate read) provided in an embodiment of the present invention;

[0039] Figure 5 This is a device transfer characteristic curve (bottom gate write, horizontal gate read) provided in an embodiment of the present invention. Detailed Implementation

[0040] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0041] To enable those skilled in the art to fully understand how the present invention is specifically implemented, this section provides an explanatory description of the embodiments that expand upon the technical solutions of the claims.

[0042] This invention discloses a write-and-read heterogeneous dual-gate neuromorphic device and its fabrication method. The device structure, from bottom to top, comprises a bottom gate electrode, a gate insulating layer, an electrolyte layer, a charge trapping layer, an organic semiconductor layer, a horizontal gate electrode, and source / drain electrodes. The organic semiconductor layer serves as the conductive channel, and the charge trapping layer traps charges. This invention features a dual-gate structure with a horizontal gate and a bottom gate, enabling writing to one gate and reading from the other, effectively avoiding crosstalk effects.

[0043] Example 1: As Figure 1 As shown, a write-read heterogeneous dual-gate neuromorphic device includes a bottom gate electrode, a gate insulating layer, an electrolyte layer, a charge trapping layer, an organic semiconductor layer, a horizontal gate electrode, and source / drain electrodes. The organic semiconductor layer serves as a conductive channel, and the charge trapping layer is used to trap charges. A silicon wafer with a SiO2 surface is used as the substrate. The electrolyte layer is made of chitosan and lactic acid. The charge transport layer material is OTS, the organic semiconductor material is pentacene, and the electrode material is copper.

[0044] During device fabrication, the laboratory temperature was around 24°C and the humidity was below 50%. The vacuum evaporation process was carried out in a glove box filled with nitrogen.

[0045] The device fabrication process is as follows:

[0046] 1. Prepare a toluene solution of OTS by taking 15 μl of OTS and 15 ml of toluene and stirring until homogeneous.

[0047] 2. Prepare Si / SiO2 substrate, ultrasonically clean it; rinse with anhydrous ethanol, blow away moisture with a nitrogen gun, and finally dry in an 80℃ drying oven for 1 hour.

[0048] 3. Treat the silicon wafer processed in step 2 with ultraviolet ozone for 10 minutes, then spread the surface of the silicon wafer with chitosan / lactic acid solution, spin-coating for 1 minute at a speed of 3000 rpm; anneal the spin-coated silicon wafer at 110℃ for 30 minutes.

[0049] 4. Spin coat the silicon wafer surface completed in step 3 with OTS, spin coat at 3000 rpm for 30 seconds; anneal the spin-coated silicon wafer at 110℃ for 30 minutes.

[0050] 5. Place the silicon wafer from step 4 into a vacuum evaporation system and sequentially deposit 30nm pentacene and 50nm horizontal gate and source / drain electrodes. The evaporation temperature of the pentacene should not exceed 195℃, and the current should be controlled at around 150A when depositing the copper electrodes.

[0051] Example 2: The fabricated device was tested for transfer characteristic curves using a Keithley 2636B analyzer. Figure 2The transfer characteristic curve of the device during horizontal gate writing is shown below, using horizontal gate readout I. DS Source-drain voltage V DS =-1V, the transfer characteristic storage curve test scheme is: apply -25V gate voltage for 1s to write, apply 25V gate voltage for 1s to erase. The obtained data is plotted as follows: Figure 2 .

[0052] Example 3: The fabricated device was tested for transfer characteristic curves using a Keithley 2636B analyzer. Figure 3 This is the transfer characteristic curve of the device during bottom gate writing, using horizontal gate readout. DS Source-drain voltage V DS =-1V, the transfer characteristic storage curve test scheme is: apply -25V gate voltage for 1s to write, apply 25V gate voltage for 1s to erase. The obtained data is plotted as follows: Figure 3 .

[0053] Example 4: The fabricated device was tested for transfer characteristics using a Keithley 2636B analyzer. Figure 4 This is the transfer characteristic curve of the device during bottom-gate writing, using bottom-gate read-out I. DS Source-drain voltage V DS =-1V, the transfer characteristic storage curve test scheme is: apply -25V gate voltage for 1s to write, apply 25V gate voltage for 1s to erase. The obtained data is plotted as follows: Figure 4 .

[0054] Example 5: The fabricated device was tested for transfer characteristic curves using a Keithley 2636B analyzer. Figure 5 This is the transfer characteristic curve of the device during bottom gate writing, using horizontal gate readout. DS Source-drain voltage V DS =-1V, the transfer characteristic storage curve test scheme is: apply -25V gate voltage for 1s to write, apply 25V gate voltage for 1s to erase. The obtained data is plotted as follows: Figure 5 .

[0055] To demonstrate the inventiveness and technical value of the technical solution of this invention, this section provides specific product or related technology application examples of the technical solution claimed.

[0056] The neuromorphic device described in this invention can be used as a non-volatile memory or as a circuit element in neuromorphic circuits, replacing some of the functions of software simulation.

[0057] It should be noted that embodiments of the present invention can be implemented in hardware, software, or a combination of both. The hardware portion can be implemented using dedicated logic; the software portion can be stored in memory and executed by a suitable instruction execution system, such as a microprocessor or dedicated-design hardware. Those skilled in the art will understand that the above-described devices and methods can be implemented using computer-executable instructions and / or included in processor control code, for example, such code provided on a carrier medium such as a disk, CD, or DVD-ROM, a programmable memory such as read-only memory (firmware), or a data carrier such as an optical or electronic signal carrier. The devices and modules of the present invention can be implemented by hardware circuitry such as very large-scale integrated circuits or gate arrays, semiconductors such as logic chips, transistors, or programmable hardware devices such as field-programmable gate arrays, programmable logic devices, etc., or by software executed by various types of processors, or by a combination of the above-described hardware circuitry and software, such as firmware.

[0058] The embodiments of the present invention have achieved some positive results during the research and development or use process, and have indeed great advantages compared with the prior art. The following content describes them in conjunction with the data, charts and other information of the experimental process.

[0059] The fabricated device was tested for relevant electrical properties using a Keithley 2636B analyzer, and the obtained data were plotted. Figure 2 , Figure 3 , Figure 4 , Figure 5 See Table 1.

[0060] Figure 2 and Figure 3 This invention presents the transfer characteristic curves of a device during horizontal gate writing, using both horizontal gate and bottom gate readout methods. DS Source-drain voltage V DS =-1V, the transfer characteristic storage curve test scheme is: apply -25V gate voltage for 1 second for writing, apply 25V gate voltage for 1 second for erasing. Among them Figure 2 The transfer characteristic curve is shown when reading using a horizontal grid. Figure 3 The figure shows the transfer characteristic curves when using bottom-gate readout. It can be observed that the device current decreases during horizontal gate write, exhibiting a charge trapping effect, while the device has a larger storage window during bottom-gate readout.

[0061] Figure 4 and Figure 5 This invention provides transfer characteristic curves for bottom-gate writing of devices, using both bottom-gate and horizontal-gate readout methods. DS Source-drain voltage V DS =-1V, the transfer characteristic storage curve test scheme is: apply -25V gate voltage for 1 second for writing, apply 25V gate voltage for 1 second for erasing. Among them Figure 4 The transfer characteristic curve is shown when using bottom-gate readout. Figure 5 The figure shows the transfer characteristic curves when using horizontal gate readout. It can be observed that both readout currents increase during bottom gate write, exhibiting an electrical double-layer effect. The device has a larger memory window during horizontal gate readout.

[0062] Table 1 lists the storage window of the device under four write / read conditions. Bottom-gate write has a larger storage window, and the storage window under heterogeneous write and read conditions is slightly larger than that under homogeneous conditions.

[0063] Storage window / (V)

[0064] Horizontal grid reading Bottom gate reading Horizontal gate writing 2.41 3.76 Bottom gate writing 7.97 6.98

[0065] Table 1

[0066] All test results show that the neuromorphic device prepared by this invention can achieve heterogeneous writing and reading, that is, writing and reading operations are performed using different gates. The storage window of the device under heterogeneous conditions is slightly higher than that under homogeneous conditions. In addition, the device also exhibits two charge effects: charge trapping effect and electric double layer effect. Moreover, the device is simple to prepare and has low cost, which is conducive to its widespread research.

[0067] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any modifications, equivalent substitutions, and improvements made by those skilled in the art within the scope of the technology disclosed in the present invention, and within the spirit and principles of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A write and read heterogeneous dual-gate neuromorphic device, the neuromorphic device comprising a bottom gate electrode, a gate insulating layer, an electrolyte layer, a charge trapping layer, an organic semiconductor layer, a horizontal gate electrode, a source-drain electrode, characterized in that, The horizontal gate and the organic semiconductor layer of the neuromorphic device are located above the charge trapping layer and are separated from each other; The source-drain electrode is located above the organic semiconductor layer; The preparation method of the write-read heterogeneous double-gate neuromorphic device comprises the following steps: (1) preparing PS solution, OTS solution and PVDF solution; (2) preparing a plurality of Si / SiO2 substrates, ultrasonic cleaning and drying for standby; (3) ultraviolet ozone treatment of the above-mentioned substrates for 10 minutes, solution method spin coating of the electrolyte solution on the substrates, and thermal annealing on a hot stage; (4) spin coating of PS solution, OTS solution and PVDF solution on the substrates in step (3) respectively, and thermal annealing treatment; (5) placing the prepared substrates in step (4) into a vacuum evaporation system, and sequentially evaporating pentacene, horizontal gate and source-drain electrode; (6) testing the prepared device for related electrical properties; The solvent of the PS solution in step (1) is toluene, and the concentration is 3 mg / ml; the solute of the OTS solution is OTS, the solvent is toluene, and the ratio is 15 μl:15 ml; the solvent of the PVDF solution is NMP (N-methyl pyrrolidone), and the weight ratio of PVDF is 5%, stirring for 1-2 days, and preheating treatment before spin coating.

2. The write and read heterogeneous dual-gate neuromorphic device of claim 1, wherein, The substrate of the neuromorphic device is composed of a bottom gate electrode and a gate insulating layer; the material of the bottom gate electrode is Si, and the material of the gate insulating layer is SiO2, and the thickness of the gate insulating layer is 50 nm.

3. The write and read heterogeneous dual-gate neuromorphic device of claim 1, wherein, The material of the electrolyte layer is chitosan+ lactic acid; and the material of the charge trapping layer is selected from PS, OTS and PVDF.

4. The write and read heterogeneous dual-gate neuromorphic device of claim 1, wherein, The material of the organic semiconductor layer is pentacene, the organic semiconductor layer serves as a conductive channel, and the thickness of the thin film of the organic semiconductor layer is 30 nm; the materials of the horizontal gate electrode and the source-drain electrode are copper or gold, and the thickness is 50 nm.

5. The write and read heterogeneous dual-gate neuromorphic device of claim 1, wherein, The electrolyte layer and the charge trapping layer are formed into films by solution method spin coating; the organic semiconductor layer is formed into a film by vacuum evaporation method; and the preparation method of the horizontal gate and the source-drain electrode is thermal vacuum evaporation method.

6. The write and read heterogeneous dual-gate neuromorphic device of claim 1, wherein, The size of the substrate in step (2) is 2 cm×2 cm; the electrolyte in step (3) is chitosan mixed with lactic acid, the electrolyte solution is preheated and treated by ultrasonic before spin coating, the spin coating speed is 3000 revolutions / minute, spin coating is performed for 1 minute, the thermal annealing temperature is 110℃, and the annealing time is 20 minutes.

7. The write and read heterogeneous dual-gate neuromorphic device of claim 1, wherein, The spin coating speed is 3000 revolutions / minute, spin coating is performed for 30 seconds, the thermal annealing temperature is 110℃, and the annealing time is 20 minutes when the charge trapping layer is prepared in step (4).

8. The write and read heterogeneous dual-gate neuromorphic device of claim 1, wherein, The vacuum evaporation of the organic semiconductor material in step (5) is pentacene, and the evaporation rate is 0.1-0.2 nm / s The substrate is rotated during the evaporation process, and the vacuum degree is controlled to be 5x10 -4 Pa or below, and the film thickness is controlled to be 30 nm by using a crystal vibrating film thickness meter; the vacuum evaporation of the horizontal gate and source-drain electrode material in step (5) is one of copper or gold, and the evaporation rate is 0.1-0.2 nm / s The substrate is not rotated during the evaporation process, and the vacuum degree is controlled to be 5x10 -4 Pa or below, and the film thickness is controlled to be 50 nm by using a crystal vibrating film thickness meter.

Images