Semiconductor element and method for manufacturing the same

Abstract

A semiconductor device and a method for fabricating the same are disclosed. The method for fabricating the semiconductor device includes forming an intermetal dielectric layer on a substrate, forming a recess in the intermetal dielectric layer, forming a barrier layer in the recess, forming a seed layer on the barrier layer, performing an annealing process to form a metal silicide layer, forming a main body layer on the metal silicide layer, and forming a magnetic tunneling junction (MTJ) on the main body layer.

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor device and a method for fabricating the same, and more particularly, to a magnetoresistive random access memory (MRAM) and a method for fabricating the same. BACKGROUND

[0002] It is known that the magnetoresistance (MR) effect is an effect in which the resistance of a material changes with an applied magnetic field. The physical quantity is defined as the difference in resistance with and without a magnetic field divided by the original resistance, and is used to represent the resistance change rate. At present, the magnetoresistance effect has been successfully applied in the production of hard disks, and has important commercial application value. In addition, using the characteristic that the giant magnetoresistance material has different resistance values in different magnetization states, a magnetic random access memory (MRAM) can also be made. The advantage is that the stored data can be retained without power supply.

[0003] The above-mentioned magnetoresistance effect is also applied in the field of magnetic field sensors, for example, an electronic compass component in a mobile phone matched with a global positioning system (GPS), which is used to provide information such as the moving direction of the user. At present, there are various magnetic field sensing technologies on the market, such as anisotropic magnetoresistance (AMR) sensing elements, giant magnetoresistance (GMR) sensing elements, magnetic tunneling junction (MTJ) sensing elements, etc. However, the disadvantages of the above-mentioned prior art usually include: occupying a large chip area, expensive manufacturing process, high power consumption, insufficient sensitivity, and being easily affected by temperature changes, etc., and it is necessary to further improve. SUMMARY

[0004] One embodiment of the present application discloses a method for fabricating a semiconductor device, which mainly forms an intermetallic dielectric layer on a substrate, then forms a recess in the intermetallic dielectric layer, forms a barrier layer in the recess, forms a seed layer on the barrier layer, performs an annealing manufacturing process to form a silicided metal layer, forms a main body layer on the silicided metal layer, and then forms a magnetic tunneling junction (MTJ) on the main body layer.

[0005] Another embodiment of the present application discloses a semiconductor device, which mainly comprises an intermetal dielectric layer disposed on a substrate, a metal interconnect disposed in the intermetal dielectric layer, and a magnetic tunneling junction (MTJ) disposed on the metal interconnect. The metal interconnect comprises a barrier layer, a metal silicide layer disposed on the barrier layer, a seed layer disposed on the metal silicide layer, and a bulk layer disposed on the seed layer. BRIEF DESCRIPTION OF DRAWINGS

[0006] Figures 1 to 6 A schematic diagram of a method for fabricating an MRAM cell according to an embodiment of the present application.

[0007] List of principal elements:

[0008] 12: substrate

[0009] 14: MRAM region

[0010] 16: interlayer dielectric layer

[0011] 18: metal interconnect structure

[0012] 20: intermetal dielectric layer

[0013] 22: metal interconnect

[0014] 24: barrier layer

[0015] 26: metal layer

[0016] 28: stop layer

[0017] 30: intermetal dielectric layer

[0018] 32: recess

[0019] 34: barrier layer

[0020] 36: seed layer

[0021] 38: annealing fabrication process

[0022] 40: metal silicide layer

[0023] 42: bulk layer

[0024] 44: metal interconnect

[0025] 46: lower electrode

[0026] 48: MTJ stack structure

[0027] 50: upper electrode

[0028] 52: fixed layer

[0029] 54: barrier layer

[0030] 56: free layer

[0031] 58: MTJ

[0032] 60: capping layer

[0033] 62: intermetal dielectric layer

[0034] 64: metal interconnect

[0035] 66: stop layer

[0036] 68: barrier layer

[0037] 70: metal layer DETAILED DESCRIPTION

[0038] Reference will now be made to Figures 1 to 6 , Figures 1 to 6 a semiconductor device, and more particularly to an MRAM cell, in accordance with an embodiment of the present application. As shown in Figure 1 , a substrate 12, such as a substrate 12 formed of a semiconductor material selected from the group consisting of silicon, germanium, silicon- germanium composite, silicon carbide, gallium arsenide, etc., is first provided, wherein the substrate 12 preferably has an MRAM region 14 and a logic region (not shown) defined thereon.

[0039] Active (active) devices such as metal-oxide semiconductor (MOS) transistors, passive devices, conductive layers, and dielectric layers such as interlayer dielectric (ILD) 16 can be included on the substrate 12. More particularly, the substrate 12 can include planar or non-planar (e.g., fin- shaped structure transistors) MOS transistor devices, wherein the MOS transistors can include gate structures (e.g., metal gates) and source / drain regions, spacers, epitaxial layers, contact hole etch stop layers, etc., and the ILD 16 can be disposed on the substrate 12 and cover the MOS transistors, and the ILD 16 can have a plurality of contact plugs electrically connected to the gate and / or source / drain regions of the MOS transistors. Since the fabrication processes related to planar or non-planar transistors and ILD are well known in the art, further description is not provided herein.

[0040] A metal interconnect structure 18 is then formed on the ILD layer 16 to electrically connect the aforementioned contact plugs, wherein the metal interconnect structure 18 includes an intermetal dielectric layer 20 and metal interconnects 22 embedded in the intermetal dielectric layer 20. In the present embodiment, the metal interconnects 22 in the metal interconnect structure 18 preferably include a trench conductor, and the metal interconnects 22 in the metal interconnect structure 18 can be embedded in the intermetal dielectric layer 20 and electrically connected to each other according to a single damascene fabrication process or a dual damascene fabrication process. For example, each metal interconnect 22 can further include a barrier layer 24 and a metal layer 26, wherein the barrier layer 24 can be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN), and the metal layer 26 can be selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc., but is not limited thereto. Since the single damascene or dual damascene fabrication process is well known in the art, further description is not provided herein. In addition, in the present embodiment, the metal layer 26 in the metal interconnects 18 preferably includes copper, and the intermetal dielectric layer 20 preferably includes silicon oxide or an ultra low dielectric constant dielectric layer, but is not limited thereto.

[0041] A stop layer 28 and another intermetal dielectric layer 30 are then sequentially formed on the intermetal dielectric layer 20, and a photolithography and etching fabrication process is performed to remove a portion of the intermetal dielectric layer 30 to form at least one recess 32 in the intermetal dielectric layer 30. A barrier layer 34 and a seed layer 36 are then sequentially formed in each recess 32 but do not fill the recess 32. In the present embodiment, the barrier layer 34 preferably includes titanium, titanium nitride, or a combination thereof, and the seed layer 36 preferably includes tungsten. In the present embodiment, if the barrier layer 34 includes a double-layer composite structure composed of titanium and titanium nitride, the barrier layer 34 disposed in the lower layer preferably includes titanium and the barrier layer 34 disposed in the upper layer includes titanium nitride. In addition, the seed layer 36 can be formed by chemical vapor deposition fabrication process by introducing tungsten hexafluoride (WF6) and silane (SiH4) gases.

[0042] As Figure 2As shown, an anneal fabrication process 38 can then be performed to crystallize the core layer 36 composed of tungsten to form a metal silicide layer 40, wherein the metal silicide layer 40 preferably comprises tungsten silicide. In the present embodiment, the anneal fabrication process 38 is performed at a temperature of 600-700 degrees Celsius and preferably at about 650 degrees Celsius, and the anneal fabrication process 38 is performed for a time period of 20 seconds to 20 minutes. It is noted that only a portion of the core layer 36 is crystallized to form the metal silicide layer 40 during the anneal fabrication process 38 to form the metal silicide layer 40, and thus a portion of the core layer 36 remains on the top surface of the metal silicide layer 40 after the formation of the metal silicide layer 40. In addition, although the core layer 36 is preferably not reactive with the barrier layer 34, it is not excluded that a portion of the core layer 36 can react with a portion of the barrier layer 34 to form a compound such as tungsten nitride (WN) during the anneal fabrication process 38. In terms of thickness, the overall thickness of the core layer 36 can be slightly reduced and the thickness of the barrier layer 34 can be slightly reduced or not changed, but is not limited thereto. If a portion of the barrier layer 34 also reacts during the anneal fabrication process 38, the overall thickness of the barrier layer 34 can also be slightly reduced, and this variation is also within the scope of the present application. Figures 1 to 2 Figures 1 to 2 Figures 1 to 2

[0043] As shown, a main body layer 42 is then formed on the surface of the core layer 36 and fills the recesses 32. In the present embodiment, the main body layer 42 and the core layer 36 preferably comprise the same material, such as both comprising tungsten. Figure 3

[0044] As shown, a planarization fabrication process is then performed, such as a chemical mechanical polishing (CMP) fabrication process, to remove a portion of the main body layer 42, a portion of the core layer 36, a portion of the metal silicide layer 40, and a portion of the barrier layer 34, so that the top surfaces of the remaining barrier layer 34, metal silicide layer 40, core layer 36, and main body layer 42 are flush with the top surface of the intermetal dielectric layer 30 to form metal interconnects 44 in each of the recesses 32. Figure 4

[0045] ​​​​​Subsequently, a lower electrode 46, an MTJ stack structure 48, an upper electrode 50, and a patterned mask (not shown) are formed on the metal interconnect structure 18. In this embodiment, the MTJ stack structure 48 can be formed by first sequentially forming a pinned layer 52, a barrier layer 54, and a free layer 56 on the lower electrode 46. In this embodiment, the lower electrode 46 and the upper electrode 50 preferably contain conductive materials, such as, but not limited to, tantalum (Ta), tantalum nitride (TaN), platinum (Pt), copper (Cu), gold (Au), and aluminum (Al). The pinned layer 52 may contain ferromagnetic materials such as, but not limited to, cobalt-iron-boron (CoFeB), cobalt-iron (CoFe), iron (Fe), and cobalt (Co). Furthermore, the fixing layer 52 can also be made of an antiferromagnetic (AFM) material, such as iron-manganese (FeMn), platinum-manganese (PtMn), iridium-manganese (IrMn), nickel oxide (NiO), etc., to fix or restrict the magnetic moment direction of adjacent layers. The barrier layer 54 can be made of an insulating material containing oxides, such as aluminum oxide (AlO). x The free layer 56 can be made of ferromagnetic materials, such as iron, cobalt, nickel, or their alloys such as cobalt-iron-boron (CoFeB), but is not limited to these. The magnetization direction of the free layer 56 can be "freely" changed by an external magnetic field.

[0046] Subsequently, as Figure 5 As shown, a patterned mask is used as the mask to perform one or more etching processes to remove a portion of the upper electrode 50, a portion of the MTJ stack structure 48, a portion of the lower electrode 46, and a portion of the intermetallic dielectric layer 30 to form multiple MTJs 58 in the MRAM region 14. It is worth noting that the etching process performed on the patterned upper electrode 50, MTJ stack structure 48, lower electrode 46, and intermetallic dielectric layer 30 in this embodiment may include reactive ion etching (RIE) and / or ion beam etching (IBE). Due to the characteristics of ion beam etching, the remaining upper surface of the intermetallic dielectric layer 30 is preferably slightly lower than the upper surface of the metal interconnects 44, and the upper surface of the intermetallic dielectric layer 30 preferably presents an arc or curved surface. Furthermore, it should be noted that in this embodiment, when removing a portion of the intermetallic dielectric layer 30 using the ion beam etching process, a portion of the metal interconnects 44 is preferably removed simultaneously, so that the metal interconnects 44 form inclined sidewalls near the junctions of the MTJs 58.

[0047] Then Figure 6 As shown, a masking layer 60 is formed on the MTJ 58 and covers the surface of the intermetallic dielectric layer 30. An intermetallic dielectric layer 62 is formed on the masking layer 60. Then, one or more photolithography and etching processes are performed to remove part of the intermetallic dielectric layer 62 and part of the masking layer 60 to form contact holes (not shown). Next, conductive material is filled into each contact hole and a planarization process such as CMP is used to form metal interconnects 64 connecting to the upper electrode 50 below. Finally, another stop layer 66 is formed on the intermetallic dielectric layer 62 and covers the metal interconnects 64.

[0048] In this embodiment, the masking layer 60 preferably comprises silicon nitride, but other dielectric materials may be selected according to the fabrication process requirements, such as silicon oxide, silicon oxynitride, or silicon carbide. The stop layer 66 may be selected from the group consisting of nitrogen-doped carbide (NDC), silicon nitride, and silicon carbide (SiCN), and preferably comprises silicon carbide. As with the aforementioned metal interconnects 22, each metal interconnect 64 disposed in the intermetallic dielectric layer 62 may be embedded in the intermetallic dielectric layer 62 according to a single damascene fabrication process or a double damascene fabrication process. For example, each metal interconnect 64 may further include a barrier layer 68 and a metal layer 70. The barrier layer 68 may be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN), while the metal layer 70 may be selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium-aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc., but is not limited thereto. Since single-damascene or dual-damascene fabrication processes are well known in the art, they will not be described in detail here. This completes the fabrication of a semiconductor device according to an embodiment of the present invention.

[0049] Please refer to again Figure 6 , Figure 6 A schematic diagram of the structure of an MRAM cell according to an embodiment of the present invention is also disclosed. For example... Figure 6 As shown, the semiconductor device mainly includes an inter-metal dielectric layer 30 disposed on the substrate 12, a metal interconnect 44 disposed within the inter-metal dielectric layer 30, at least one MTJ 58 disposed directly above the metal interconnect 44, and another metal interconnect 64 connecting the upper electrode 50 above each MTJ 58. In this embodiment, the metal interconnect 44 directly below the MTJ 58 preferably includes a barrier layer 34, a metal silicide layer 40 disposed on the barrier layer 34, a nucleation layer 36 disposed on the metal silicide layer 40, and a host layer 42 disposed on the nucleation layer 36, while the metal interconnect 64 directly above the MTJ 58 only includes a barrier layer 68 and a metal layer 70.

[0050] As previously described, the seed layer 36 and the main body layer 42 comprise the same material, for example, both comprise tungsten, and the silicide layer 40 preferably comprises tungsten silicide. According to a preferred embodiment of the present application, forming the silicide layer between the barrier layer and the seed layer in the metal interconnect directly below the MTJ using an annealing fabrication process can effectively reduce the resistance of the entire element and thus improve the overall performance.

[0051] The above descriptions are only the preferred embodiments of the present application, and any equivalent variations and modifications made according to the claims of the present application should be covered by the scope of the present application.

Claims

1. A method of manufacturing a semiconductor device, characterized by, Comprising: forming an intermetal dielectric layer on a substrate; forming a recess in the intermetal dielectric layer; forming a barrier layer in the recess; forming a seed layer on the barrier layer using a chemical vapor deposition fabrication process; performing an anneal fabrication process to crystallize portions of the seed layer directly contacting the barrier layer to form a metal silicide layer; forming a bulk layer on the metal silicide layer; and forming a magnetic tunneling junction (MTJ) on the bulk layer.

2. The method of claim 1, further comprising: planarizing the bulk layer, the metal silicide layer, and the barrier layer to form a metal interconnect in the intermetal dielectric layer; and forming the magnetic tunneling junction on the metal interconnect.

3. The method of claim 1, wherein the anneal fabrication process temperature is between 600-700 degrees Celsius.

4. The method of claim 1, wherein the anneal fabrication process time is between 20 seconds and 20 minutes.

5. The method of claim 1, wherein the seed layer and the bulk layer comprise the same material.

6. The method of claim 1, wherein the seed layer comprises tungsten.

7. The method of claim 1, wherein the bulk layer comprises tungsten.

8. A semiconductor device produced by the method according to claim 1, characterized by Comprising: an intermetal dielectric layer on a substrate; a metal interconnect in the intermetal dielectric layer, wherein the metal interconnect comprises: a barrier layer; a metal silicide layer on the barrier layer; a seed layer on the metal silicide layer; and a bulk layer on the seed layer; and a magnetic tunneling junction (MTJ) on the metal interconnect.

9. The semiconductor element of claim 8, wherein the seed layer and the bulk layer comprise the same material.

10. The semiconductor element of claim 8, wherein the seed layer comprises tungsten.

11. The semiconductor element of claim 8, wherein the bulk layer comprises tungsten.

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