Display panel and display device

Abstract

A display panel and a display device, wherein the display panel includes: a display area and a non-display area; the display area includes: pixel units arranged in an array, at least one pixel unit includes: a first color sub-pixel, a second color sub-pixel and a third color sub-pixel, at least one sub-pixel includes: a pixel circuit and a light-emitting element, and the pixel circuit is connected to the anode of the light-emitting element; the non-display area includes: an anode voltage driving circuit, the anode voltage driving circuit is connected to the sub-pixel and is configured to provide an anode voltage control signal to the pixel circuit of the connected sub-pixel to provide a voltage signal to the anode of the light-emitting element; the anode voltage driving circuit includes: K anode voltage driving sub-circuits arranged along the row direction; each anode voltage driving sub-circuit is connected to at least one color sub-pixel, and different anode voltage driving sub-circuits are connected to sub-pixels of different colors.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to, but are not limited to, the field of display technology, and particularly to a display panel and a display device. Background Art

[0002] Organic Light Emitting Diodes (OLEDs) and Quantum-dot Light Emitting Diodes (QLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, extremely fast response times, thinness, flexibility, and low cost. With the continuous advancement of display technology, flexible displays using OLEDs or QLEDs as light-emitting elements and thin-film transistors (TFTs) for signal control have become mainstream products in the display field. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0004] In a first aspect, the present disclosure provides a display panel comprising: a display area and a non-display area; the display area comprising: pixel units arranged in an array, at least one pixel unit comprising: a first color sub-pixel, a second color sub-pixel, and a third color sub-pixel, the first color, the second color, and the third color being different colors, at least one sub-pixel comprising: a pixel circuit and a light-emitting element, the pixel circuit being connected to an anode of the light-emitting element; the non-display area comprising: an anode voltage driving circuit, the anode voltage driving circuit being connected to the sub-pixel and configured to provide an anode voltage control signal to the pixel circuit of the connected sub-pixel, thereby providing a voltage signal to the anode of the light-emitting element;

[0005] The anode voltage driving circuit includes: K anode voltage driving sub-circuits arranged along the row direction;

[0006] Each anode voltage driving subcircuit is connected to at least one color sub-pixel, different anode voltage driving subcircuits are connected to sub-pixels of different colors, and K is a positive integer greater than or equal to 2.

[0007] In some possible implementations, the display area further includes: 3N columns of data signal lines, M rows of scan signal lines, M rows of reset signal lines, and M rows of initial voltage lines, where M is the total number of rows of pixel units, and N is the total number of columns of pixel units;

[0008] The pixel circuit includes: first to seventh transistors and a storage capacitor;

[0009] a control electrode of the first transistor connected to the reset signal terminal, a first electrode of the first transistor connected to the initial voltage terminal, a second electrode of the first transistor connected to the second node, a control electrode of the second transistor connected to the scan signal terminal, a first electrode of the second transistor connected to the second node, and a second electrode of the second transistor connected to the third node; a control electrode of the third transistor connected to the second node, a first electrode of the third transistor connected to the first node, and a second electrode of the third transistor connected to the third node; a control electrode of the fourth transistor connected to the scan signal terminal, a first electrode of the fourth transistor connected to the data signal terminal, and a second electrode of the fourth transistor connected to the first node; a control electrode of the fifth transistor connected to the light-emitting signal terminal, a first electrode of the fifth transistor connected to the first power supply terminal, and a second electrode of the fifth transistor connected to the first node; a control electrode of the sixth transistor connected to the light-emitting signal terminal, a first electrode of the sixth transistor connected to the third node, and a second electrode of the sixth transistor connected to the light-emitting element; a control electrode of the seventh transistor connected to the anode voltage control terminal, a first electrode of the seventh transistor connected to the anode voltage signal terminal, and a second electrode of the seventh transistor connected to the anode of the light-emitting element; a first terminal of the storage capacitor connected to the first power supply terminal, and a second terminal of the storage capacitor connected to the second node;

[0010] For the pixel circuit of the sub-pixel in the i-th row and j-th column, the data signal terminal is connected to the data signal line in the j-th column, the scanning signal terminal is connected to the scanning signal line in the i-th row, the reset signal terminal is connected to the reset signal line in the i-th row, and the initial voltage terminal is connected to the initial voltage line in the i-th row, 1≤i≤M, 1≤j≤3N.

[0011] In some possible implementations, when K=2, the K anode voltage driving subcircuits are respectively: a first anode voltage driving subcircuit and a second anode voltage driving subcircuit; the first anode voltage driving subcircuit includes: M cascaded first anode voltage driving shift registers, and the second anode voltage driving subcircuit includes: M cascaded second anode voltage driving shift registers; the display area further includes: 2M rows of anode voltage control lines and 2M rows of anode voltage signal lines;

[0012] The 2i-1th row anode voltage control line is connected to the i-th stage first anode voltage driving shift register, and is connected to the anode voltage control terminals of the pixel circuits of the first color sub-pixels and the second color sub-pixels located in the i-th row;

[0013] The 2i-th row anode voltage control line is connected to the i-th stage second anode voltage driving shift register and is connected to the anode voltage control terminal of the pixel circuit of the third color sub-pixel located in the i-th row;

[0014] The 2i-1th row anode voltage signal line is connected to the anode voltage signal terminals of the pixel circuits of the first color sub-pixels and the second color sub-pixels located in the i-th row;

[0015] The 2i-th row anode voltage signal line is connected to the anode voltage signal terminal of the pixel circuit of the third color sub-pixel located in the i-th row.

[0016] In some possible implementations, when K=3, the K anode voltage driving subcircuits are respectively a first anode voltage driving subcircuit, a second anode voltage driving subcircuit, and a third anode voltage driving subcircuit; the first anode voltage driving subcircuit includes: M cascaded first anode voltage driving shift registers, the second anode voltage driving subcircuit includes: M cascaded second anode voltage driving shift registers, and the third anode voltage driving subcircuit includes: M cascaded third anode voltage driving shift registers; the display area further includes: 3M rows of anode voltage control lines and 3M rows of anode voltage signal lines;

[0017] The 3i-2th row anode voltage control line is connected to the i-th stage first anode voltage driving shift register and is connected to the anode voltage control terminal of the pixel circuit of the first color sub-pixel located in the i-th row;

[0018] The 3i-1th row anode voltage control line is connected to the i-th stage second anode voltage driving shift register and is connected to the anode voltage control terminal of the pixel circuit of the second color sub-pixel located in the i-th row;

[0019] The 3i-th row anode voltage control line is connected to the i-th stage third anode voltage driving shift register and is connected to the anode voltage control terminal of the pixel circuit of the third color sub-pixel located in the i-th row;

[0020] The anode voltage signal line in the 3i-2th row is connected to the anode voltage signal terminal of the pixel circuit of the first color sub-pixel located in the i-th row;

[0021] The anode voltage signal line in the 3i-1th row is connected to the anode voltage signal terminal of the pixel circuit of the second color sub-pixel located in the i-th row;

[0022] The 3i-th row anode voltage signal line is connected to the anode voltage signal terminal of the pixel circuit of the third color sub-pixel located in the i-th row.

[0023] In some possible implementations, when the sub-pixel performs display, the driving mode of each sub-pixel includes: a first driving mode, a second driving mode, and a third driving mode;

[0024] When the driving mode of the sub-pixel is the first driving mode, the pixel circuit is configured to continuously apply a driving current to the light-emitting element;

[0025] When the driving mode of the sub-pixel is the second driving mode, the pixel circuit is configured to periodically apply the driving current to the light-emitting element, and stop applying the driving current during an interval between any two adjacent applications of the driving current;

[0026] When the driving mode of the sub-pixel is the third driving mode, the pixel circuit is configured to periodically apply a driving current to the light-emitting element, and provide a negative bias signal to the anode of the light-emitting element during an interval between any two adjacent applications of the driving current, so that the light-emitting element does not emit light;

[0027] The sub-pixels connected to the same anode voltage drive shift register have the same driving mode.

[0028] In some possible implementations, when K=2, the driving modes of the first color sub-pixel and the second color sub-pixel are the same; the driving modes of the first color sub-pixel and the third color sub-pixel are different or the same;

[0029] When the driving modes of the first color sub-pixel and the third color sub-pixel located in the i-th row are the same, the second duty cycle of the anode voltage control signal output by the i-th level first anode voltage driving shift register and the i-th level second anode voltage driving shift register is different, and / or the voltages of the signals provided by the 2i-1-th row anode voltage signal line and the 2i-th row anode voltage signal line are different; wherein the second duty cycle is the ratio of the duration when the anode voltage control signal is an invalid level signal to the second time, and the second time is the sum of the duration when the anode voltage control signal is an invalid level signal and the duration when the anode voltage control signal is a valid level signal.

[0030] In some possible implementations, when K=3, the driving modes of at least two of the first color subpixel, the second color subpixel, and the third color subpixel are different, or the driving modes of the first color subpixel, the second color subpixel, and the third color subpixel are the same;

[0031] When the driving modes of the three color sub-pixels located in the i-th row are the same, the second duty cycles of at least two of the anode voltage control signals output by the i-th-stage first anode voltage driving shift register, the i-th-stage second anode voltage driving shift register, and the i-th-stage third anode voltage driving shift register are different, and / or the voltages of at least two of the signals provided by the 3i-2-th row anode voltage signal line, the 3i-1-th row anode voltage signal line, and the 3i-th row anode voltage signal line are different;

[0032] The second duty cycle is the ratio of the duration when the anode voltage control signal is an invalid level signal to the second time, and the second time is the sum of the duration when the anode voltage control signal is an invalid level signal and the duration when the anode voltage control signal is a valid level signal.

[0033] In some possible implementations, when the driving mode of the sub-pixel is the second driving mode or the third driving mode, the pixel circuit applies the driving current to the light-emitting element at a frequency of approximately 1 Hz to 360 Hz.

[0034] In some possible implementations, the non-display area further includes: a scan drive circuit, a reset drive circuit, and a light-emitting drive circuit;

[0035] a scan driving circuit connected to the sub-pixel and configured to provide a scan control signal to the pixel circuit of the connected sub-pixel to provide a data signal to the first node; a reset driving circuit connected to the sub-pixel and configured to provide a reset control signal to the pixel circuit of the connected sub-pixel to reset the second node; and a light-emitting driving circuit connected to the sub-pixel and configured to provide a light-emitting control signal to the pixel circuit of the connected sub-pixel to provide a driving current to the light-emitting element;

[0036] The light-emitting drive circuit is located on the side of the display area, the scan drive circuit is located on the side of the light-emitting drive circuit close to the display area, and the anode voltage drive circuit and the reset drive circuit are respectively located between the light-emitting drive circuit and the scan drive circuit and between the scan drive circuit and the display area;

[0037] The scan driving circuit includes: M cascaded scan shift registers, wherein the i-th stage scan shift register is connected to the i-th row scan signal line;

[0038] The reset driving circuit includes: M cascaded reset shift registers, and the i-th stage reset shift register is connected to the i-th row reset signal line.

[0039] In some possible implementations, the light-emitting driving circuit includes: M cascaded first light-emitting shift registers, and the display area further includes: M rows of light-emitting signal lines;

[0040] The light emitting signal line in the i-th row is connected to the i-th stage first light emitting shift register and is connected to the light emitting signal terminals of all sub-pixels in the i-th row.

[0041] In some possible implementations, the light-emitting driving circuit includes: K light-emitting driving sub-circuits arranged along a row direction;

[0042] When K=2, the K light-emitting driving sub-circuits are respectively: a first light-emitting driving sub-circuit and a second light-emitting driving sub-circuit; the first light-emitting driving sub-circuit includes: M cascaded first light-emitting shift registers, and the second light-emitting driving sub-circuit includes: M cascaded second light-emitting shift registers; the display area also includes: 2M rows of light-emitting signal lines;

[0043] The 2i-1th row of light-emitting signal lines is connected to the first light-emitting shift register of the i-th stage, and is also connected to the light-emitting signal terminals of the pixel circuits of the first color sub-pixels and the second color sub-pixels located in the i-th row;

[0044] The 2i-th row light-emitting signal line is connected to the second light-emitting shift register of the i-th stage, and is connected to the light-emitting signal terminal of the pixel circuit of the third color sub-pixel located in the i-th row;

[0045] The light-emitting control signal output by the first light-emitting shift register of the i-th stage and the light-emitting control signal output by the second light-emitting shift register of the i-th stage have different first duty ratios, wherein the first duty ratio is a ratio of a duration during which the light-emitting control signal is a valid level signal to a first time, and the first time is a sum of a duration during which the light-emitting control signal is a invalid level signal and a duration during which the light-emitting control signal is a valid level signal;

[0046] When K=3, the K light-emitting driving sub-circuits are respectively: a first light-emitting driving sub-circuit, a second light-emitting driving sub-circuit, and a third light-emitting driving sub-circuit; the first light-emitting driving sub-circuit includes: M cascaded first light-emitting shift registers, the second light-emitting driving sub-circuit includes: M cascaded second light-emitting shift registers, and the third light-emitting driving sub-circuit includes: M cascaded third light-emitting shift registers; the display area also includes: 3M rows of light-emitting signal lines;

[0047] The 3i-2th row of light-emitting signal lines is connected to the first light-emitting shift register of the i-th stage, and is also connected to the light-emitting signal terminal of the pixel circuit of the first color sub-pixel located in the i-th row;

[0048] The 3i-1th row of light-emitting signal lines is connected to the second light-emitting shift register of the i-th stage, and is also connected to the light-emitting signal terminals of the pixel circuits of the second color sub-pixels located in the i-th row;

[0049] The 3i-th row light-emitting signal line is connected to the third light-emitting shift register of the i-th stage, and is connected to the light-emitting signal terminal of the pixel circuit of the third color sub-pixel located in the i-th row;

[0050] The first duty ratios of the light control signal output by the i-th first light emitting shift register, the light control signal output by the i-th second light emitting shift register, and the light control signal output by the i-th third light emitting shift register are different.

[0051] In some possible implementations, the sum of the first duty cycle and the second duty cycle is less than 1;

[0052] The first duty cycle is approximately 30% to 99%.

[0053] In some possible implementations, the voltage value of the signal provided by the anode voltage signal line is approximately -0.1 volts to -10 volts, and the voltage value of the voltage signal provided by the anode voltage signal line is less than the reverse breakdown voltage of the light-emitting element.

[0054] In some possible implementations, for the pixel circuit of each sub-pixel, when the signal at the light-emitting signal end is a valid level signal, the signal at the anode voltage control end is an invalid level signal; when the signal at the anode voltage control end is a valid level signal, the signal at the light-emitting signal end is an invalid level signal; the duration that the signal at the light-emitting signal end is an invalid level signal is greater than the duration that the signal at the anode voltage control end is a valid level signal.

[0055] In some possible implementations, the anode voltage driven shift register includes: M1 bias transistors and M2 bias capacitors, and the anode voltage driven shift register includes: a first anode voltage driven shift register, a second anode voltage driven shift register, or a third anode voltage driven shift register;

[0056] The light emitting shift register includes: M3 light emitting transistors and M4 light emitting capacitors, and the light emitting shift register includes: a first light emitting shift register, a second light emitting shift register or a third light emitting shift register;

[0057] Each scan shift register includes: M5 scan transistors and M6 scan capacitors; each reset shift register includes: M5 reset transistors and M6 reset capacitors; the connection method between the M5 scan transistors and the M6 scan capacitors is the same as the connection method between the M5 reset transistors and the M6 reset capacitors, wherein M3 is not equal to M5, and M4 is not equal to M6;

[0058] M1 and M2 satisfy: M1 = M5, M2 = M6 or M1 = M3, M2 = M4;

[0059] When M1=M5 and M2=M6, the connection between the M1 bias transistors and the M2 bias capacitors is the same as the connection between the M5 scan transistors and the M6 scan capacitors;

[0060] When M1=M3 and M2=M4, the connection mode between the M1 bias transistors and the M2 bias capacitors is the same as the connection mode between the M3 light-emitting transistors and the M4 light-emitting capacitors.

[0061] In some possible implementations, for each sub-pixel, when M1=M3 and M2=M4, the difference between the duration of the signal at the light-emitting signal end being an invalid level signal and the duration of the signal at the anode voltage control end being a valid level signal is less than the threshold time difference, and the duration of the signal at the anode voltage control end being a valid level signal is greater than the duration of the signal at the scanning signal end being a valid level signal.

[0062] In some possible implementations, for each sub-pixel, when M1=M5 and M2=M6, the difference between the duration of the signal at the light-emitting signal end being an invalid level signal and the duration of the signal at the anode voltage control end being a valid level signal is greater than the threshold time difference, and the duration of the signal at the anode voltage control end being a valid level signal is equal to the duration of the signal at the scanning signal end being a valid level signal.

[0063] In some possible implementations, the non-display area further includes: a timing controller; the image displayed by the display panel includes N frames;

[0064] The timing controller is configured to provide a driving signal to the driving circuit so that the same sub-pixel can switch between different driving modes in different frames;

[0065] The driving circuit includes: an anode voltage driving circuit, a light emitting driving circuit, a scanning driving circuit and a reset driving circuit.

[0066] In a second aspect, the present disclosure further provides a display device, comprising: the above-mentioned display panel.

[0067] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0068] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation to the technical solution of the present disclosure.

[0069] Figure 1 A schematic structural diagram of a display panel provided in an embodiment of the present disclosure;

[0070] Figure 2 A schematic diagram of the structure of a display panel provided in an exemplary embodiment Figure 1 ;

[0071] Figure 3 A schematic diagram of a display panel structure provided by an exemplary embodiment Figure 2 ;

[0072] Figure 4 A schematic diagram of a pixel unit connection provided for an exemplary embodiment Figure 1 ;

[0073] Figure 5 A schematic diagram of a pixel unit connection provided for an exemplary embodiment Figure 2 ;

[0074] Figure 6 A schematic diagram of a pixel unit connection provided for an exemplary embodiment Figure 3 ;

[0075] Figure 7 A schematic diagram of a pixel unit connection provided for an exemplary embodiment Figure 4 ;

[0076] Figure 8 is a schematic diagram of a cross-sectional structure of a display panel;

[0077] Figure 9 is an equivalent circuit diagram of a pixel circuit;

[0078] Figure 10A The equivalent circuit diagram of an anode voltage driven shift register is shown below:

[0079] Figure 10B for Figure 10A The provided anode voltage drives the working timing diagram of the shift register;

[0080] Figure 11A The equivalent circuit diagram of the shift register driven by another anode voltage;

[0081] Figure 11B for Figure 11A The provided anode voltage drives the working timing diagram of the shift register;

[0082] Figure 12A A working timing of a pixel circuit Figure 1 ;

[0083] Figure 12B A working timing of a pixel circuit Figure 2 ;

[0084] Figure 13A The working timing of multiple sub-pixels in a pixel unit Figure 1 ;

[0085] Figure 13B The working timing of multiple sub-pixels in a pixel unit Figure 2 ;

[0086] Figure 14A The working timing of multiple sub-pixels in a pixel unit Figure 3 ;

[0087] Figure 14BThe working timing of multiple sub-pixels in a pixel unit Figure 4 ;

[0088] Figure 15A is an equivalent circuit diagram of a scanning shift register;

[0089] Figure 15B for Figure 15A The working timing diagram of the scan shift register provided;

[0090] Figure 16A is an equivalent circuit diagram of a reset shift register;

[0091] Figure 16B for Figure 16A The working timing diagram of the reset shift register is provided;

[0092] Figure 17A is an equivalent circuit diagram of a light-emitting shift register;

[0093] Figure 17B for Figure 17A The working timing diagram of the light-emitting shift register provided;

[0094] Figures 18 and 19 A waveform diagram of an input signal of a driving circuit provided by an exemplary embodiment;

[0095] Figures 20 to 33 A waveform diagram of an output signal of a driving circuit provided by an exemplary embodiment. DETAILED DESCRIPTION

[0096] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0097] In the drawings, the sizes of various components, layer thicknesses, or regions may be exaggerated for clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to these dimensions, and the shapes and sizes of the components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate idealized examples, and one embodiment of the present disclosure is not limited to the shapes or numerical values shown in the drawings.

[0098] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0099] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0100] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed connections, removable connections, or integral connections; they can refer to mechanical connections or connections; they can refer to direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure based on the specific circumstances.

[0101] In this specification, "connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0102] Those skilled in the art will understand that the transistors used in all embodiments of the present disclosure may be thin film transistors, field effect transistors, or other devices with the same characteristics. The thin film transistor may be an oxide semiconductor thin film transistor, a low-temperature polycrystalline silicon thin film transistor, an amorphous silicon thin film transistor, or a microcrystalline silicon thin film transistor. The thin film transistor may specifically be a bottom-gate thin film transistor or a top-gate thin film transistor, as long as the switching function can be achieved. Since the source and drain of the transistor used here are symmetrical, their source and drain can be interchanged.

[0103] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0104] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0105] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0106] The term "about" in the present disclosure refers to a numerical value that is not strictly defined and allows for process and measurement errors.

[0107] A display panel includes at least one color sub-pixel and a driving circuit. The at least one color sub-pixel may include a red sub-pixel, a blue sub-pixel, and a green sub-pixel. Each sub-pixel includes a pixel circuit and a light-emitting element. The driving circuit is configured to provide a driving signal to the pixel circuit, so that the pixel circuit drives the light-emitting element to emit light according to the driving signal.

[0108] Twelve 12.3-inch display panels manufactured from the same glass substrate and batch during the same period were selected and divided into four groups (A, B, C, and D), each containing three panels. The brightness and gamma voltage of each panel were adjusted to be consistent (within 2%). The luminance decay curves of different images (red, blue, green, and white) in each panel were tested at high temperature (85°C) for 1000 hours. The test conditions are shown in Table 1 (data for only one image per group is listed). In Table 1, CIE stands for Commission Internationale de L'Eclairage; CIEx represents the abscissa in the chromaticity diagram developed by the Commission Internationale de L'Eclairage; and CIEy represents the ordinate in the chromaticity diagram developed by the Commission Internationale de L'Eclairage. Drive mode CC indicates continuous application of drive current to the light-emitting element. Drive mode PC indicates periodic application of drive current to the light-emitting element, with the drive current being discontinued between any two consecutive application times. Driving mode AC means that a driving current is periodically applied to the light-emitting element, and a negative bias signal is provided to the anode of the light-emitting element in the interval between any two adjacent application times of the driving current so that the light-emitting element does not emit light. Duty is the ratio of the time when the driving current is applied to the sum of the time when the driving current is applied and the time when the driving current is not applied. The negative bias refers to the voltage value of the negative bias signal.

[0109] Table 1

[0110]

[0111]

[0112] According to the above conditions, the four groups ABCD were subjected to a high-temperature life test at 85°C. The life results of different sub-pixels R, G and B are shown in Table 2.

[0113] Table 2

[0114]

[0115] As shown in Table 2, after 1000 hours, using the CC drive mode lifespan as a reference, set at 100%, the lifespans of RGB in 85% Duty AC mode are 126%, 140%, and 136% of those in CC mode, respectively. The lifespans of RGB in 75% Duty AC mode are 105%, 112%, and 156% of those in CC mode, respectively. This shows that the lifespan of the blue subpixel in 75% Duty AC mode is superior to that in 85% Duty AC mode; the lifespans of the red and green subpixels in 85% Duty AC mode are superior to those in 75% Duty AC mode; and the lifespans of RGB in 75% Duty PC mode are inferior to those in CC mode. These experiments demonstrate that the conditions for maximizing the lifespan of different color subpixels vary.

[0116] In a display panel, sub-pixels of different colors are connected to the same driving circuit, which results in an inability to maximize the lifespan of the sub-pixels of different colors, thereby reducing the service life of the display panel.

[0117] Figure 1 A schematic diagram of the structure of a display panel provided in an embodiment of the present disclosure is shown. Figure 2 A schematic diagram of the structure of a display panel provided in an exemplary embodiment Figure 1 , Figure 3 A schematic diagram of a display panel structure provided by an exemplary embodiment Figure 2 , Figure 4 A schematic diagram of a pixel unit connection provided for an exemplary embodiment Figure 1 , Figure 5 A schematic diagram of a pixel unit connection provided for an exemplary embodiment Figure 2 , Figure 6 A schematic diagram of a pixel unit connection provided for an exemplary embodiment Figure 3 , Figure 7 A schematic diagram of a pixel unit connection provided for an exemplary embodiment Figure 4 .like Figures 1 to 7 As shown, the display panel provided by the embodiment of the present disclosure includes: a display area 100 and a non-display area 200. The display area 100 includes: pixel units P arranged in an array, at least one pixel unit includes: a first color sub-pixel P1, a second color sub-pixel P2 and a third color sub-pixel P3, and the first color, the second color and the third color are different colors. At least one sub-pixel includes: a pixel circuit and a light-emitting element, and the pixel circuit is connected to the anode of the light-emitting element. The non-display area 200 includes: an anode voltage driving circuit 10, and the anode voltage driving circuit 10 is connected to the sub-pixel, and is configured to provide an anode voltage control signal to the pixel circuit of the connected sub-pixel to provide a voltage signal to the anode of the light-emitting element. Figures 4 to 7 The description is made by taking a pixel unit located in the i-th row as an example.

[0118] In an exemplary embodiment, the anode voltage driving circuit 10 includes K anode voltage driving sub-circuits LC1 to LCK arranged along a row direction. Each anode voltage driving sub-circuit is connected to at least one color sub-pixel, and different anode voltage driving sub-circuits are connected to sub-pixels of different colors. K is a positive integer greater than or equal to 2.

[0119] In an exemplary embodiment, the display panel may be an OLED display panel.

[0120] In an exemplary embodiment, the first color, the second color, or the third color may be one of red, green, or blue. For example, the first color may be red, the second color may be blue, and the third color may be green, which is not limited in this disclosure.

[0121] In an exemplary embodiment, the shape of the sub-pixels in the pixel unit can be rectangular, diamond, pentagonal, or hexagonal. For example, three sub-pixels can be arranged horizontally, vertically, or in a triangular pattern, which is not limited in this disclosure.

[0122] In an exemplary embodiment, K can be 2 or 3. The value of K depends on the structure and material of the sub-pixels of different colors in the display panel, and this disclosure does not impose any limitation on this. Figure 2 The following is an example of K=3. Figure 3 The explanation is given by taking K=2 as an example.

[0123] In an exemplary embodiment, the anode voltage driving sub-circuit may be a single-sided driving sub-circuit or a double-sided driving sub-circuit. Figure 1 The description is given by taking the anode voltage driving subcircuit as a double-sided driving example.

[0124] In this embodiment, each anode voltage driving sub-circuit is connected to at least one color sub-pixel, and different anode voltage driving sub-circuits are connected to sub-pixels of different colors. Different anode voltage driving sub-circuits can provide anode voltage control signals to sub-pixels of different colors that can extend the lifespan of sub-pixels of different colors, thereby maximizing the lifespan of sub-pixels of different colors.

[0125] In an exemplary embodiment, the pixel units located in the first row and the pixel units located in the last row may not be displayed, and the pixel units located in the second row to the second-to-last row may be displayed, or the pixel units in all rows may be displayed. Exemplarily, when the pixel units located in the first row and the pixel units located in the last row are not displayed, the structure of the pixel units in the first row and the pixel units located in the last row is the same as that of the pixel units located in other rows, except that the pixel circuits of the sub-pixels in the pixel units in the first row and the pixel units in the last row do not output the driving circuit, and the light-emitting elements do not emit light.

[0126] Figure 8 This is a schematic diagram of the cross-sectional structure of a display panel, illustrating the structure of three sub-pixels of an OLED display panel. Figure 8 As shown, on a plane perpendicular to the display panel, the display panel may include a driving circuit layer 102 disposed on a substrate 101, a light-emitting structure layer 103 disposed on a side of the driving circuit layer 102 away from the substrate 101, and an encapsulation layer 104 disposed on a side of the light-emitting structure layer 103 away from the substrate 101. In some possible implementations, the display panel may include other film layers, such as spacers, etc., which are not limited in this disclosure.

[0127] In an exemplary embodiment, the substrate 101 may be a flexible substrate or a rigid substrate. The driving circuit layer 102 of each sub-pixel may include a plurality of transistors and storage capacitors constituting a pixel circuit. Figure 4 Only one transistor 101 and one storage capacitor 101A are used as examples. The light-emitting structure layer 103 may include an anode 301, a pixel definition layer 302, an organic light-emitting layer 303 and a cathode 304. The anode 301 is connected to the drain electrode of the driving transistor 210 through a via, the organic light-emitting layer 303 is connected to the anode 301, and the cathode 304 is connected to the organic light-emitting layer 303. The organic light-emitting layer 303 emits light of corresponding colors under the drive of the anode 301 and the cathode 304. The encapsulation layer 104 may include a stacked first encapsulation layer 401, a second encapsulation layer 402 and a third encapsulation layer 403. The first encapsulation layer 401 and the third encapsulation layer 403 may be made of inorganic materials, and the second encapsulation layer 402 may be made of organic materials. The second encapsulation layer 402 is arranged between the first encapsulation layer 401 and the third encapsulation layer 403 to ensure that external water vapor cannot enter the light-emitting structure layer 103.

[0128] In an exemplary embodiment, the organic light-emitting layer 303 may include a stacked hole injection layer (HIL), a hole transport layer (HTL), an electron block layer (EBL), an emitting layer (EML), a hole block layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, the hole injection layers of all sub-pixels may be a common layer connected together, the electron injection layers of all sub-pixels may be a common layer connected together, the hole transport layers of all sub-pixels may be a common layer connected together, the electron transport layers of all sub-pixels may be a common layer connected together, and the hole blocking layers of all sub-pixels may be a common layer connected together. The light-emitting layers of adjacent sub-pixels may have a small overlap or may be isolated, and the electron blocking layers of adjacent sub-pixels may have a small overlap or may be isolated.

[0129] The display panel provided by the embodiment of the present disclosure includes: a display area and a non-display area; the display area includes: pixel units arranged in an array, at least one pixel unit includes: a first color sub-pixel, a second color sub-pixel, and a third color sub-pixel, at least one sub-pixel includes: a pixel circuit and a light-emitting element, the pixel circuit being connected to the anode of the light-emitting element; the non-display area includes: an anode voltage driving circuit, the anode voltage driving circuit being connected to the sub-pixel and configured to provide an anode voltage control signal to the pixel circuit of the connected sub-pixel to provide a voltage signal to the anode of the light-emitting element; the anode voltage driving circuit includes: K anode voltage driving sub-circuits arranged along a row direction; each anode voltage driving sub-circuit is connected to at least one color sub-pixel, and different anode voltage driving sub-circuits are connected to sub-pixels of different colors. The present disclosure provides an anode voltage driving circuit including K anode voltage driving sub-circuits arranged along a row direction and connected to sub-pixels of different colors, thereby maximizing the lifespan of the sub-pixels of different colors, reducing the difference in brightness decay rates of the sub-pixels of different colors, and extending the service life of the display panel.

[0130] In an exemplary embodiment, the display area may further include: 3N columns of data signal lines, M rows of scan signal lines, M rows of reset signal lines and M rows of initial voltage lines, where M is the total number of rows of pixel units and N is the total number of columns of pixel units.

[0131] Figure 9 is an equivalent circuit diagram of a pixel circuit. Figure 9As shown, a pixel circuit provided by an exemplary embodiment may include: a first transistor T1 to a seventh transistor T7 and a storage capacitor C.

[0132] In an exemplary embodiment, the control electrode of the first transistor T1 is connected to the reset signal terminal RST, the first electrode of the first transistor T1 is connected to the initial signal terminal INIT, and the second electrode of the first transistor is connected to the second node N2. The control electrode of the second transistor T2 is connected to the scan signal terminal GATE, the first electrode of the second transistor T2 is connected to the second node N2, and the second electrode of the second transistor T2 is connected to the third node N3. The control electrode of the third transistor T3 is connected to the second node N2, that is, the control electrode of the third transistor T3 is connected to the second end of the storage capacitor C, the first electrode of the third transistor T3 is connected to the first node N1, and the second electrode of the third transistor T3 is connected to the third node N3. The control electrode of the fourth transistor T4 is connected to the scan signal terminal GATE, the first electrode of the fourth transistor T4 is connected to the data signal terminal DATA, and the second electrode of the fourth transistor T4 is connected to the first node N1. The control electrode of the fifth transistor T5 is connected to the emission signal terminal EM, the first electrode of the fifth transistor T5 is connected to the first power supply terminal VDD, and the second electrode of the fifth transistor T5 is connected to the first node N1. A control electrode of the sixth transistor T6 is connected to the light-emitting signal terminal EM, a first electrode of the sixth transistor T6 is connected to the third node N3, and a second electrode of the sixth transistor T6 is connected to the anode of the light-emitting element L. A control electrode of the seventh transistor T7 is connected to the anode voltage control terminal LC, a first electrode of the seventh transistor T7 is connected to the anode voltage signal terminal LS, and a second electrode of the seventh transistor T7 is connected to the anode of the light-emitting element L. A first end of the storage capacitor C is connected to the first power supply terminal VDD, and a second end of the storage capacitor C is connected to the second node N2, that is, the second end of the storage capacitor C is connected to the control electrode of the third transistor T3.

[0133] For the pixel circuit of the sub-pixel in the i-th row and j-th column, the data signal terminal is connected to the data signal line in the j-th column, the scanning signal terminal is connected to the scanning signal line in the i-th row, the reset signal terminal is connected to the reset signal line in the i-th row, and the initial voltage terminal is connected to the initial voltage line in the i-th row, 1≤i≤M, 1≤j≤3N.

[0134] In an exemplary embodiment, the pixel circuit is configured to receive the data voltage transmitted by the data signal line under the control of the scanning signal line, and output the corresponding current to the light-emitting element. The light-emitting element is configured to emit light of corresponding brightness in response to the current output by the pixel circuit of the sub-pixel in which it is located.

[0135] In an exemplary embodiment, the first power supply terminal VDD can continuously provide a high level signal, and the second power supply terminal VSS can continuously provide a low level signal. The voltage value of the signal at the initial signal terminal VINT is lower than the voltage value of the second power supply terminal VSS.

[0136] In an exemplary embodiment, the voltage of the signal at the second power supply terminal VSS is approximately -4.5V to -4V.

[0137] In an exemplary embodiment, the voltage of the signal at the initial signal terminal VINT is approximately -7 volts to -6.5 volts.

[0138] In an exemplary embodiment, the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be switching transistors. The third transistor T3 may be called a driving transistor, and the third transistor T3 determines a driving current flowing between the first power supply terminal VDD and the second power supply terminal VSS based on a potential difference between a control electrode and the first electrode.

[0139] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 may be a P-type transistor or an N-type transistor. Using the same type of transistors in the pixel circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield. For example, the first transistor T1 to the seventh transistor T7 may include a P-type transistor and an N-type transistor.

[0140] In an exemplary embodiment, Figure 2 and 3 As shown, when K=2, the K anode voltage driving sub-circuits are: a first anode voltage driving sub-circuit LC1 and a second anode voltage driving sub-circuit LC2. The first anode voltage driving sub-circuit includes: M cascaded first anode voltage driving shift registers LC1_1 to LC1_M, and the second anode voltage driving sub-circuit includes: M cascaded second anode voltage driving shift registers LC2_1 to LC2_M.

[0141] In an exemplary embodiment, Figure 4 and Figure 5 As shown, the display area may further include: 2M rows of anode voltage control lines L1 to L 2M and 2M rows of anode voltage signal lines V1 to V 2M .

[0142] In an exemplary embodiment, the anode voltage control line L of the 2i-1th row 2i-1 The anode voltage control line L2i is connected to the first anode voltage driving shift register LC1_i of the i-th stage and is connected to the anode voltage control terminals of the pixel circuits of the first color sub-pixel and the second color sub-pixel located in the i-th row. 2iThe anode voltage signal line V of the 2i-1th row is connected to the second anode voltage driving shift register LC2_i of the i-th stage and is connected to the anode voltage control terminal of the pixel circuit of the third color sub-pixel located in the i-th row. 2i-1 Connected to the anode voltage signal terminals of the pixel circuits of the first color sub-pixel and the second color sub-pixel located in the i-th row. 2i The anode voltage signal terminal is connected to the anode voltage signal terminal of the pixel circuit of the third color sub-pixel located in the i-th row.

[0143] In an exemplary embodiment, Figure 2 and Figure 3 As shown, when K = 3, the K anode voltage driving sub-circuits are the first anode voltage driving sub-circuit LC1, the second anode voltage driving sub-circuit LC2, and the third anode voltage driving sub-circuit LC3. The first anode voltage driving sub-circuit LC1 may include: M cascaded first anode voltage driving shift registers LC1_1 to LC1_M. The second anode voltage driving sub-circuit may include: M cascaded second anode voltage driving shift registers LC3_1 to LC3_M. The third anode voltage driving sub-circuit includes: M cascaded third anode voltage driving shift registers LC3_1 to LC3_M.

[0144] In an exemplary embodiment, Figure 4 and Figure 5 As shown, the display area may further include: 3M rows of anode voltage control lines L1 to L 3M and 3M rows of anode voltage signal lines V1 to V 3M .

[0145] In an exemplary embodiment, the anode voltage control line L of the 3i-2th row 3i-2 The anode voltage control line L3i-1 is connected to the first anode voltage driving shift register LC1_i of the i-th stage and is connected to the anode voltage control terminal of the pixel circuit of the first color sub-pixel located in the i-th row. 3i-1 The anode voltage control line L3i is connected to the second anode voltage driving shift register LC2_i of the i-th stage and is connected to the anode voltage control terminal of the pixel circuit of the second color sub-pixel located in the i-th row. 3i The anode voltage signal line V of the 3i-2nd row is connected to the third anode voltage driving shift register LC3_i and is connected to the anode voltage control terminal of the pixel circuit of the third color sub-pixel located in the i-th row. 3i-2 Connected to the anode voltage signal terminal of the pixel circuit of the first color sub-pixel located in the i-th row. 3i-1 Connected to the anode voltage signal terminal of the pixel circuit of the second color sub-pixel located in the i-th row.3i The anode voltage signal terminal is connected to the anode voltage signal terminal of the pixel circuit of the third color sub-pixel located in the i-th row.

[0146] Figure 10A The equivalent circuit diagram of an anode voltage driven shift register is shown in Figure 2. Figure 10A As shown, in an exemplary embodiment, the anode voltage driven shift register includes: first to tenth bias transistors LT1 to LT10 and first to third bias capacitors Lc1 to Lc3.

[0147] In an exemplary embodiment, the anode voltage driven shift register includes: a first anode voltage driven shift register, a second anode voltage driven shift register, or a third anode voltage driven shift register.

[0148] In an exemplary embodiment, a control electrode of the first bias transistor LT1 is connected to the first node L1, a first electrode of the first bias transistor LT1 is connected to the first power supply terminal VGH, and a second electrode of the first bias transistor LT1 is connected to the first electrode of the second bias transistor LT2. A control electrode of the second bias transistor LT1 is connected to the second clock signal terminal CB, and a second electrode of the second bias transistor LT2 is connected to the second node L2. A control electrode of the third bias transistor LT3 is connected to the second node L2, a first electrode of the third bias transistor LT3 is connected to the first node L1, and a second electrode of the third bias transistor LT3 is connected to the first clock signal terminal CK. A control electrode of the fourth bias transistor LT4 is connected to the first clock signal terminal CK, a first electrode of the fourth bias transistor LT4 is connected to the signal input terminal IN, and a second electrode of the fourth bias transistor LT4 is connected to the second node L2. A control electrode of the fifth bias transistor LT5 is connected to the first clock signal terminal CK, a first electrode of the fifth bias transistor LT5 is connected to the second power supply terminal VGL, and a second electrode of the fifth bias transistor LT5 is connected to the first node L1. A control electrode of the sixth bias transistor LT6 is connected to the first node L1, a first electrode of the sixth bias transistor LT6 is connected to the second clock signal terminal CB, a second electrode of the sixth bias transistor LT6 is connected to the first electrode of the seventh bias transistor LT7, and a second electrode of the sixth bias transistor LT6 is connected to the third node L3. A control electrode of the seventh bias transistor LT7 is connected to the second clock signal terminal CB, a first electrode of the seventh bias transistor LT7 is connected to the third node L3, and a second electrode of the seventh bias transistor LT7 is connected to the fourth node L4. A control electrode of the eighth bias transistor LT8 is connected to the first node L1, a first electrode of the eighth bias transistor LT8 is connected to the fourth node L4, and a second electrode of the eighth bias transistor LT8 is connected to the first power supply terminal VGH. A control electrode of the ninth bias transistor LT9 is connected to the fourth node L4, a first electrode of the ninth bias transistor LT9 is connected to the first power supply terminal VGH, and a second electrode of the ninth bias transistor LT9 is connected to the signal output terminal OUT. A control electrode of the tenth bias transistor LT10 is connected to the first node L1, a first electrode of the tenth bias transistor LT10 is connected to the signal output terminal OUT, and a second electrode of the tenth bias transistor LT10 is connected to the second power supply terminal VGL. A first plate of the first bias capacitor Lc1 is connected to the fourth node L4, and a second plate of the first bias capacitor Lc1 is connected to the first power supply terminal VGH. A first plate of the second bias capacitor Lc2 is connected to the first node L1, and a second plate of the second bias capacitor Lc2 is connected to the third node L3. A first plate of the third bias capacitor Lc3 is connected to the second node L2, and a second plate of the third bias capacitor Lc3 is connected to the second clock signal terminal CB.

[0149] In an exemplary embodiment, the first power supply terminal VGH may continuously provide a high-level signal, and the second power supply terminal VGL may continuously provide a low-level signal.

[0150] In an exemplary embodiment, the first bias transistor LT1 to the tenth bias transistor LT10 can be P-type transistors or N-type transistors. Using the same type of transistors in the light-emitting drive circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield.

[0151] Figure 10B for Figure 10A The provided anode voltage drives the working timing diagram of the shift register. Figure 10B It is taken as an example that the first bias transistor LT1 to the tenth bias transistor LT10 are P-type transistors. Figure 10B As shown, the working process of the anode voltage driven shift register provided by an exemplary embodiment may include:

[0152] In the first phase A1, the signals at the signal input terminal IN and the second clock signal terminal CB are low-level signals, and the signal at the first clock signal terminal CK is high-level. The signal at the second clock signal terminal CB is low-level, and the second bias transistor LT2 and the seventh bias transistor LT7 are turned on. The signal at the first clock signal terminal CK is high-level, and the fourth bias transistor LT4 and the fifth bias transistor LT5 are turned off. The signal at the signal input terminal IN cannot be written to the second node L2, and the signal at the second power supply terminal VGL cannot be written to the first node L1. The third bias transistor LT3, the sixth bias transistor LT6, the eighth bias transistor LT8, and the tenth bias transistor LT10 are turned off, and the signal output terminal OUT maintains the high-level signal from the previous phase.

[0153] In the second phase A2, the signals at the signal input terminal IN and the first clock signal terminal CK are low-level signals, while the signal at the second clock signal terminal CB is high-level. The signal at the second clock signal terminal CB is high-level, and the second bias transistor LT2 and the seventh bias transistor LT7 are turned off. The signal at the first clock signal terminal CK is low-level, and the fourth bias transistor LT4 and the fifth bias transistor LT5 are turned on. The low-level signal at the signal input terminal IN is written to the second node L2. The third bias transistor LT3, the eighth bias transistor LT8, and the tenth bias transistor LT10 are turned on. The signal at the first clock signal terminal CK is written to the first node L1. The high-level signal at the first power supply terminal VGH is written to the fourth node R4. The ninth bias transistor LT9 is turned off. The low-level signal at the second power supply terminal VGL is written to the signal output terminal OUT. The low-level signal at the second power supply terminal VGL is written to the first node L1. The first bias transistor LT1 and the sixth bias transistor LT6 are turned on. The high-level signal at the second clock signal terminal CB is written to the third node L3. Because the seventh bias transistor LT7 is turned off, the signal at the third node L3 cannot be written to the fourth node R4. In this stage, the signal output terminal OUT outputs a low-level signal.

[0154] In the third phase A3, the signals at the signal input terminal IN and the second clock signal terminal CB are low-level signals, while the signal at the first clock signal terminal CK is high-level. The signal at the first clock signal terminal CK is high-level, and the fourth bias transistor LT4 and the fifth bias transistor LT5 are turned off. The signal at the signal input terminal IN cannot be written to the second node L2, and the signal at the second power supply terminal VGL cannot be written to the first node L1. Due to the action of the third bias capacitor, the signal at the second node L2 remains low-level. The third bias transistor LT3, the eighth bias transistor LT8, and the tenth bias transistor LT10 are turned on, and the high-level signal at the first clock signal terminal CK is written to the first node L1. The first bias transistor LT1 and the sixth bias transistor LT6 are turned off, and the high-level signal at the first power supply terminal VGH is written to the fourth node R4. The low-level signal at the second power supply terminal VGL is written to the signal output terminal OUT. The signal at the third node L3 remains high, the signal at the second clock signal terminal CB remains low, the second bias transistor LT2 and the seventh bias transistor LT7 are turned on, the signal at the third node L3 is written to the fourth node R4, the signal at the fourth node R4 remains high, and the ninth bias transistor LT9 is turned off. During this stage, the signal output terminal OUT outputs a low signal.

[0155] In the fourth phase A4, the signal at the first clock signal terminal CK is a low-level signal, while the signals at the signal input terminal IN and the second clock signal terminal CB are high-level signals. The signal at the second clock signal terminal CB is a high-level signal, and the second bias transistor LT2 and the seventh bias transistor LT7 are turned off. The signal at the first clock signal terminal CK is a low-level signal, and the fourth bias transistor LT4 and the fifth bias transistor LT5 are turned on. The high-level signal at the signal input terminal IN is written to the second node L2. The third bias transistor LT3, the eighth bias transistor LT8, and the tenth bias transistor LT10 are turned off. The signal at the first clock signal terminal CK cannot be written to the first node L1, the signal at the first power supply terminal VGH cannot be written to the fourth node R4, and the signal at the second power supply terminal VGL cannot be written to the signal output terminal OUT. The low-level signal at the second power supply terminal VGL is written to the first node L1, the first bias transistor LT1 and the sixth bias transistor LT6 are turned on, and the signal at the second clock signal terminal CB is written to the third node L3. Because the seventh bias transistor LT7 is turned off, the signal at the third node L3 cannot be written to the fourth node R4. During this phase, the signal output terminal OUT maintains the low-level signal of the upshift phase.

[0156] In the fifth phase A5, the signal at the second clock signal terminal CB is low, while the signals at the signal input terminal IN and the first clock signal terminal CK are high. The signal at the first clock signal terminal CK is high, and the fourth bias transistor LT4 and the fifth bias transistor LT5 are turned off. The signal at the signal input terminal IN cannot be written to the second node L2, and the signal at the second power supply terminal VGL cannot be written to the first node L1. Due to the action of the third bias capacitor RC3, the signal at the second node L2 remains high from the previous phase. Due to the action of the second bias capacitor RC2, the signal at the first node L1 remains low from the previous phase. The first bias transistor LT1 and the sixth bias transistor LT6 are turned on, and the high-level signal at the first power supply terminal VGH is written to the second node L2, causing the second node L2 to remain high. The low-level signal at the second clock signal terminal CB is written to the third node L3, and the signal at the third node L3 is written to the fourth node R4. The ninth bias transistor R9 is turned on, and the high-level signal at the first power supply terminal VGH is written to the signal output terminal OUT. During this phase, the signal output terminal OUT outputs a high-level signal.

[0157] In the sixth phase A6, the signal at the first clock signal terminal CK is low, while the signals at the signal input terminal IN and the second clock signal terminal CB are high. The signal at the second clock signal terminal CB is high, and the second bias transistor LT2 and the seventh bias transistor LT7 are off. The signal at the first clock signal terminal CK is low, and the fourth bias transistor LT4 and the fifth bias transistor LT5 are turned on. The high-level signal at the signal input terminal IN is written to the second node L2. The third bias transistor LT3, the eighth bias transistor LT8, and the tenth bias transistor LT10 are turned off. The signal at the first clock signal terminal CK cannot be written to the first node L1, the signal at the first power supply terminal VGH cannot be written to the fourth node R4, and the signal at the second power supply terminal VGL cannot be written to the signal output terminal OUT. The low-level signal at the second power supply terminal VGL is written to the first node L1, the first bias transistor LT1 and the sixth bias transistor LT6 are turned on, and the signal at the second clock signal terminal CB is written to the third node L3. Because the seventh bias transistor LT7 is turned off, the signal at the third node L3 cannot be written to the fourth node R4. During this phase, the signal output terminal OUT maintains the high-level signal from the previous phase.

[0158] After the sixth stage A6, the anode voltage drives the shift register to perform the fifth stage and the sixth stage alternately until the signal at the signal input terminal IN is a low level signal.

[0159] The anode voltage driven shift register in the present disclosure has a 10T3C circuit structure, which can output a pulse signal with a long duration, and can bias the signal of the anode of the light-emitting element for a long time, thereby improving the service life of the display panel.

[0160] Figure 11A The equivalent circuit diagram of the shift register driven by another anode voltage is shown in Figure 2. Figure 11A As shown, in an exemplary embodiment, the anode voltage driven shift register includes: a first bias transistor LT1 to an eighth bias transistor LT8, a first bias capacitor Lc1 and a second bias capacitor Lc2.

[0161] In an exemplary embodiment, the anode voltage driven shift register may include: a first anode voltage driven shift register, a second anode voltage driven shift register, or a third anode voltage driven shift register.

[0162] In an exemplary embodiment, a control electrode of the first bias transistor LT1 is connected to the first clock signal terminal CK, a first electrode of the first bias transistor LT1 is connected to the signal input terminal IN, and a second electrode of the first bias transistor LT1 is connected to the first node L1. A control electrode of the second bias transistor LT2 is connected to the first node L1, a first electrode of the second bias transistor LT2 is connected to the second node L2, and a second electrode of the second bias transistor LT2 is connected to the first clock signal terminal CK. A control electrode of the third bias transistor LT3 is connected to the first clock signal terminal CK, a first electrode of the third bias transistor LT3 is connected to the second power supply terminal VGL, and a second electrode of the third bias transistor LT3 is connected to the second node L2. A control electrode of the fourth bias transistor LT4 is connected to the second node L2, a first electrode of the fourth bias transistor LT4 is connected to the first power supply terminal VGH, and a second electrode of the fourth bias transistor LT4 is connected to the signal output terminal OUT. A control electrode of the fifth bias transistor LT5 is connected to the third node L3, a first electrode of the fifth bias transistor LT5 is connected to the signal output terminal OUT, and a second electrode of the fifth bias transistor LT5 is connected to the second clock signal terminal CB. A control electrode of the sixth bias transistor LT6 is connected to the second node L2, a first electrode of the sixth bias transistor LT6 is connected to the first power supply terminal VGH, and a second electrode of the sixth bias transistor LT6 is connected to the first electrode of the seventh bias transistor LT7. A control electrode of the seventh bias transistor LT7 is connected to the second clock signal terminal CB, and a second electrode of the seventh bias transistor LT7 is connected to the first node L1. A control electrode of the eighth bias transistor LT8 is connected to the second power supply terminal VGL, a first electrode of the eighth bias transistor LT8 is connected to the first node L1, and a second electrode of the eighth bias transistor LT8 is connected to the third node L3. A first plate of the first bias capacitor Lc1 is connected to the first power supply terminal VGH, and a second plate of the first bias capacitor Lc1 is connected to the second node L2. A first plate of the second bias capacitor Lc2 is connected to the signal output terminal OUT, and a second plate of the second bias capacitor Lc2 is connected to the third node L3.

[0163] In an exemplary embodiment, the first power supply terminal VGH may continuously provide a high-level signal, and the second power supply terminal VGL may continuously provide a low-level signal.

[0164] In an exemplary embodiment, the first bias transistor LT1 to the eighth bias transistor LT8 can be P-type transistors or N-type transistors. Using the same type of transistors in the anode voltage-driven shift register can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield.

[0165] Figure 11B for Figure 11A The provided anode voltage drives the working timing diagram of the shift register. Figure 11BThe first bias transistor LT1 to the eighth bias transistor LT8 are P-type transistors as an example. Figure 11B As shown, the working process of the anode voltage driven shift register provided by an exemplary embodiment may include:

[0166] In the first phase B1, the signals at the signal input terminal IN and the first clock signal terminal CK are low-level signals, while the signal at the second clock signal terminal CB is high-level. The signal at the first clock signal terminal CK is low-level, the first bias transistor LT1 and the third bias transistor LT3 are turned on, and the eighth bias transistor LT8 remains on due to receiving the low-level signal from the second power supply terminal VGL. The signal at the signal input terminal IN is written to the first node L1, the signal at the first node L1 is written to the third node G3, the fifth bias transistor LT5 is turned on, and the signal at the second clock signal terminal CB is transmitted to the signal output terminal OUT via the fifth bias transistor LT5. Furthermore, the low-level signal from the second power supply terminal VGL is written to the second node L2, the fourth bias transistor LT4 and the sixth bias transistor LT6 are turned on, and the high-level signal from the first power supply terminal VGH is written to the signal output terminal OUT. Because the signal at the second clock signal terminal CB is high-level, the seventh bias transistor LT7 is turned off. During this phase, the output signal at the signal output terminal OUT is high-level.

[0167] In the second phase B2, the signals at the signal input terminal IN and the first clock signal terminal CK are high-level signals, while the signal at the second clock signal terminal CB is low-level. The signal at the first clock signal terminal CK is high-level, the first bias transistor LT1 and the third bias transistor LT3 are turned off, the first node L1 remains low-level, and the eighth bias transistor LT8 remains on due to receiving the low-level signal from the second power supply terminal VGL. Due to the bootstrap effect of the second bias capacitor GC2, the fifth bias transistor LT5 is turned on, and the signal at the second clock signal terminal CB is written to the signal output terminal OUT. Furthermore, the signal at the first clock signal terminal CK is high-level, the second bias transistor LT2 is turned on, and the signal at the first clock signal terminal CK is written to the second node L2. Consequently, the fourth bias transistor LT4 and the sixth bias transistor LT6 are both turned off. During this phase, the output signal at the signal output terminal OUT is low-level.

[0168] In the third phase B3, the signal at the first clock signal terminal CK is low, and the signals at the signal input terminal IN and the second clock signal terminal CB are high. The signal at the first clock signal terminal CK is low, the first bias transistor LT1 and the third bias transistor LT3 are conductive, the signal at the signal input terminal IN is written to the first node L1, and the second bias transistor LT2 is turned off. Because the eighth bias transistor LT8 is continuously conductive, the signal at the first node L1 is written to the third node G3, and the fifth bias transistor LT5 is turned off. The signal at the second power supply terminal VGL is written to the second node L2, the fourth bias transistor LT4 and the sixth bias transistor LT6 are conductive, and the high-level signal at the third power supply terminal VGH is written to the signal output terminal OUT. During this phase, the output signal at the signal output terminal OUT is high.

[0169] In the fourth phase B4, the signal at the second clock signal terminal CB is a low-level signal, while the signals at the signal input terminal IN and the first clock signal terminal CK are high-level signals. The signal at the first clock signal terminal CK is a high-level signal, and the first bias transistor LT1 and the third bias transistor LT3 are turned off. The first node L1 remains at the high-level signal from the previous phase, and the second bias transistor LT2 is turned off. Because the eighth bias transistor LT8 remains on, the signal at the first node L1 is written to the third node G3, and the fifth bias transistor LT5 is turned off. The second node L2 remains at a low-level signal, the fourth bias transistor LT4 and the sixth bias transistor LT6 are turned on, and the high-level signal at the third power supply terminal VGH is written to the signal output terminal OUT. During this phase, the output signal at the signal output terminal OUT is a high-level signal.

[0170] After the fourth phase B4, the anode voltage drives the shift register to perform the third phase and the fourth phase alternately until the signal at the signal input terminal IN is a low level signal.

[0171] Figure 12A A working timing of a pixel circuit Figure 1 , Figure 12B A working timing of a pixel circuit Figure 2 . Figure 12A The signal of the anode voltage control terminal in the working timing diagram is Figure 10A Provides the anode voltage that drives the shift register generated. Figure 12B The signal of the anode voltage control terminal in the working timing diagram is Figure 11A The anode voltage provided drives the shift register. Figure 12A The operation process of the pixel circuit of the example illustrates the exemplary embodiment of the present disclosure. Figure 9The pixel circuit includes 7 transistors (the first transistor T1 to the seventh transistor T7), a storage capacitor C and 8 signal input terminals (data signal terminal DATA, scan signal terminal GATE, reset signal terminal RST, initial signal terminal INIT, light emitting signal terminal EM, anode voltage control terminal LC and anode voltage signal terminal LS). Figure 12A The following description is based on the example of seven P-type transistors. The operation of the pixel circuit may include:

[0172] In the first phase C1, the signal at the anode voltage control terminal LC is a low-level signal, while the signals at the reset signal terminal RST, the scan signal terminal GATE, and the light-emitting signal terminal EM are high-level signals. The low-level signal at the anode voltage control terminal LC turns on the seventh transistor T7. The signal at the anode voltage signal terminal LS is supplied to the anode of the light-emitting element L, initializing (resetting) the anode of the light-emitting element L and clearing the pre-stored voltage within it. This completes the initialization and ensures that the light-emitting element L does not emit light. The high-level signals at the reset signal terminal RST, the scan signal terminal GATE, and the light-emitting signal terminal EM turn off the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6. During this phase, the light-emitting element L does not emit light.

[0173] In the second phase C2, the signals at the anode voltage control terminal LC and the reset signal terminal RST are low-level signals, while the signals at the scan signal terminal GATE and the light-emitting signal terminal EM are high-level signals. The signal at the anode voltage control terminal LC remains low-level, causing the seventh transistor T7 to remain on. The signal at the anode voltage signal terminal LS continues to be supplied to the anode of the light-emitting element L, continuously initializing (resetting) the anode of the light-emitting element L. The signal at the reset signal terminal RST is low-level, causing the first transistor T1 to turn on. The signal at the initialization signal line INIT is supplied to the second node N2, initializing the storage capacitor C and clearing the original data voltage in the storage capacitor. The signals at the scan signal terminal GATE and the light-emitting signal terminal EM are high-level signals, causing the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 to be turned off. During this phase, the light-emitting element L does not emit light.

[0174] In the third phase C3, also known as the data writing phase or threshold compensation phase, the signals at the anode voltage control terminal LC and the scan signal terminal GATE are low-level signals, the signals at the reset signal terminal RST and the emission signal terminal EM are high-level signals, and the data signal terminal DATA outputs the data voltage. During this phase, since the signal at the second node is low-level, the third transistor T3 is turned on. The signal at the anode voltage control terminal LC remains low-level, causing the seventh transistor T7 to remain on. The signal at the anode voltage signal terminal LS continues to be supplied to the anode of the light-emitting element L, continuously initializing (resetting) the anode of the light-emitting element L. The signal at the scan signal terminal GATE remains low-level, turning on the second transistor T2 and the fourth transistor T4. The second transistor T2 and the fourth transistor T4 are turned on, causing the data voltage output by the data signal terminal DATA to be supplied to the second node N2 via the first node N1, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2, until the voltage at the second node N2 reaches Vd-|Vth|, where Vd is the data voltage output by the data signal terminal DATA and Vth is the threshold voltage of the third transistor T3. The signals at the reset signal terminal RST and the light emitting signal terminal EM are high level signals, which turn off the first transistor T1, the fifth transistor T5 and the sixth transistor T6. In this stage, the light emitting element L does not emit light.

[0175] In the fourth phase C4, known as the light-emitting phase, the signal at the emission signal terminal EM is a low-level signal, while the signals at the anode voltage control terminal LC, the reset signal terminal RST, and the scanning signal terminal GATE are high-level signals. The low-level signal at the emission signal terminal EM turns on the fifth transistor T5 and the sixth transistor T6. The power supply voltage output by the first power supply terminal VDD provides a driving voltage to the anode of the light-emitting element L through the turned-on fifth transistor T5, the third transistor T3, and the sixth transistor T6, driving the light-emitting element L to emit light. The high-level signals at the anode voltage control terminal LC, the reset signal terminal RST, and the emission signal terminal EM turn off the first transistor T1, the second transistor T2, the fourth transistor T4, and the seventh transistor T7.

[0176] During the pixel circuit driving process, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between the control electrode and the first electrode of the third transistor T3. Since the voltage of the second node N2 is Vdata-|Vth|, the driving current of the third transistor T3 satisfies:

[0177] I=K*(Vgs-Vth) 2 =K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*[(Vdd-Vd] 2

[0178] Wherein, I is the driving current flowing through the third transistor T3, that is, the driving current driving the OLED, K is a constant, Vgs is the voltage difference between the control electrode and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vd is the data voltage output by the data signal terminal DATA, and Vdd is the power supply voltage output by the first power supply terminal VDD.

[0179] Figure 12B The working process of the pixel circuit of the example is similar to Figure 12A The working process of the pixel circuit of the example is similar, the only difference is that Figure 12B The signal of the anode voltage control terminal LC in the pixel circuit is a low-level signal only in the first stage and a high-level signal in the second and third stages, that is, the seventh transistor T7 is cut off in the second and third stages, and the signal of the anode voltage signal terminal cannot be written into the anode of the light-emitting element. Figure 12B The duration of the signal at the anode voltage control terminal LC of the pixel circuit being an effective level signal is less than Figure 12A The duration during which the signal at the anode voltage control terminal LC of the pixel circuit is a valid level signal.

[0180] In an exemplary embodiment, for the pixel circuit of each sub-pixel, when the signal at the emission signal terminal EM is an active-level signal, the signal at the anode voltage control terminal LC is an inactive-level signal; and when the signal at the anode voltage control terminal LC is an active-level signal, the signal at the emission signal terminal EM is an inactive-level signal. The duration that the signal at the emission signal terminal is an inactive-level signal is greater than the duration that the signal at the anode voltage control terminal is an active-level signal.

[0181] In an exemplary embodiment, when the sub-pixel is displayed, the driving mode of each sub-pixel may include: a first driving mode, a second driving mode and a third driving mode. Wherein, when the driving mode of the sub-pixel is the first driving mode, the pixel circuit is configured to continuously apply a driving current to the light-emitting element. When the driving mode of the sub-pixel is the second driving mode, the pixel circuit is configured to periodically apply a driving current to the light-emitting element, and stop applying the driving current within the interval between any two adjacent application times of the driving current. When the driving mode of the sub-pixel is the third driving mode, the pixel circuit is configured to periodically apply a driving current to the light-emitting element, and provide a negative bias signal to the anode of the light-emitting element within the interval between any two adjacent application times of the driving current, so that the light-emitting element does not emit light.

[0182] In an exemplary embodiment, the sub-pixels connected to the same anode voltage drive shift register have the same driving mode.

[0183] In an exemplary embodiment, when the driving mode of the sub-pixel is the second driving mode or the third driving mode, the frequency at which the pixel circuit applies the driving current to the light-emitting element may be approximately 1 Hz to 360 Hz.

[0184] In an exemplary embodiment, the driving mode of the same sub-pixel may be different at different temperatures.

[0185] In an exemplary embodiment, Figure 2 and Figure 3 As shown, the non-display area may further include: a light-emitting driving circuit 20, a reset driving circuit 30, and a scan driving circuit 40. The scan driving circuit 40 is connected to the sub-pixel and configured to provide a scan control signal to the pixel circuit of the connected sub-pixel to provide a data signal to the first node. The reset driving circuit 30 is connected to the sub-pixel and configured to provide a reset control signal to the pixel circuit of the connected sub-pixel to reset the second node. The light-emitting driving circuit 20 is connected to the sub-pixel and configured to provide a light-emitting control signal to the pixel circuit of the connected sub-pixel to provide a driving current to the light-emitting element.

[0186] In an exemplary embodiment, the light-emitting driving circuit is located on the side of the display area, the scanning driving circuit is located on the side of the light-emitting driving circuit close to the display area, and the anode voltage driving circuit and the reset driving circuit are respectively located between the light-emitting driving circuit and the scanning driving circuit and between the scanning driving circuit and the display area.

[0187] In an exemplary embodiment, the scan driving circuit includes: M cascaded scan shift registers, wherein the i-th stage scan shift register is connected to the i-th row scan signal line. The reset driving circuit includes: M cascaded reset shift registers, wherein the i-th stage reset shift register is connected to the i-th row reset signal line.

[0188] In an exemplary embodiment, the anode voltage driving circuit may be located between the light emitting driving circuit and the scan driving circuit, and the reset driving circuit may be located between the scan driving circuit and the display area, or the anode voltage driving circuit may be located between the scan driving circuit and the display area, and the reset driving circuit may be located between the light emitting driving circuit and the scan driving circuit. Figure 2 and Figure 3 The description is made by taking an example that the anode voltage driving circuit can be located between the scanning driving circuit and the display area, and the reset driving circuit is located between the light emitting driving circuit and the scanning driving circuit.

[0189] In an exemplary embodiment, the driving circuit can be a single-side driving circuit or a double-side driving circuit. The driving circuit includes: an anode voltage driving circuit 10 , a light emitting driving circuit 20 , a reset driving circuit 30 and a scan driving circuit 40 . Figure 2 and Figure 3The description is given by taking a driving circuit as a bilateral driving circuit as an example, and the present disclosure does not impose any limitation on this.

[0190] In an exemplary embodiment, the light emitting driving circuit may be located on the left and right sides of the display area, or may be located on the left side of the display area, or may be located on the right side of the display area.

[0191] In an exemplary embodiment, Figure 2 、 Figure 4 and Figure 6 As shown, the light driving circuit 20 includes: M cascaded first light shift registers EM1_1 to EM1_M. The display area may also include: M rows of light signal lines E1 to E M Among them, the luminous signal line E in the i-th row i It is connected to the first light-emitting shift register EM1_i of the i-th stage and is also connected to the light-emitting signal terminals of all sub-pixels located in the i-th row.

[0192] In an exemplary embodiment, Figure 2 As shown, the light emitting driving circuit 20 includes K light emitting driving sub-circuits EM1 to EMK arranged along a row direction.

[0193] In an exemplary embodiment, Figure 2 and Figure 5 As shown, when K=2, the K light-emitting driver sub-circuits are respectively: a first light-emitting driver sub-circuit EM1 and a second light-emitting driver sub-circuit EM2. The first light-emitting driver sub-circuit includes: M cascaded first light-emitting shift registers EM1_1 to EM1_M, and the second light-emitting driver sub-circuit includes: M cascaded second light-emitting shift registers EM2_1 to EM2_M.

[0194] In an exemplary embodiment, Figure 5 As shown, the display area may further include: 2M rows of light-emitting signal lines E1 to E 2M Among them, the 2i-1th row of light-emitting signal lines E 2i-1 The 2i-th row light emitting signal line E is connected to the first light emitting shift register EM1_i of the i-th stage and to the light emitting signal terminals of the pixel circuits of the first color sub-pixel and the second color sub-pixel located in the i-th row. 2i It is connected to the second light-emitting shift register EM2_i of the i-th stage and is also connected to the light-emitting signal terminal of the pixel circuit of the third color sub-pixel located in the i-th row.

[0195] In an exemplary embodiment, the light-emitting control signal output by the first light-emitting shift register of the i-th stage and the light-emitting control signal output by the second light-emitting shift register of the i-th stage have different first duty ratios. The first duty ratio is a ratio of a duration during which the light-emitting control signal is an active-level signal to a first time, and the first time is a sum of a duration during which the light-emitting control signal is an inactive-level signal and a duration during which the light-emitting control signal is an active-level signal.

[0196] In an exemplary embodiment, Figure 2 and Figure 7 As shown, when K=3, the K light-emitting driver sub-circuits are: a first light-emitting driver sub-circuit EM1, a second light-emitting driver sub-circuit EM2, and a third light-emitting driver sub-circuit EM3. The first light-emitting driver sub-circuit includes: M cascaded first light-emitting shift registers EM1_1 to EM1_M, the second light-emitting driver sub-circuit includes: M cascaded second light-emitting shift registers EM2_1 to EM2_M, and the third light-emitting driver sub-circuit includes: M cascaded third light-emitting shift registers EM3_1 to EM3_M.

[0197] In an exemplary embodiment, Figure 7 As shown, the display area may further include: 3M rows of light-emitting signal lines E1 to E 3M Among them, the 3i-2 row of light-emitting signal lines E 3i-2 The 3i-1st row light emitting signal line E is connected to the first light emitting shift register EM1_i of the i-th stage and to the light emitting signal terminal of the pixel circuit of the first color sub-pixel located in the i-th row. 3i-1 The 3i-th row light emitting signal line E is connected to the second light emitting shift register EM2_i of the i-th stage and to the light emitting signal terminal of the pixel circuit of the second color sub-pixel located in the i-th row. 3i It is connected to the third light-emitting shift register EM3_i of the i-th stage and is also connected to the light-emitting signal terminal of the pixel circuit of the third color sub-pixel located in the i-th row.

[0198] In an exemplary embodiment, the first duty cycles of the light control signal output by the i-th first light emitting shift register, the light control signal output by the i-th second light emitting shift register, and the light control signal output by the i-th third light emitting shift register are different.

[0199] In an exemplary embodiment, Figure 13A The working timing of multiple sub-pixels in a pixel unit Figure 1 , Figure 13B The working timing of multiple sub-pixels in a pixel unit Figure 2 . Figure 13A The following description is made by taking the example that sub-pixels in the same row are connected to the same light-emitting signal line. Figure 13BThis description uses the example of subpixels in the same row connected to two luminescence signal lines. LC_1 is the signal at the anode voltage control signal terminal of the first color subpixel, LC_2 is the signal at the anode voltage control signal terminal of the second color subpixel, and LC_3 is the signal at the anode voltage control signal terminal of the third color subpixel. EM_1 is the signal at the luminescence signal terminal of the first color subpixel, EM_2 is the signal at the luminescence signal terminal of the second color subpixel, and EM_3 is the signal at the luminescence signal terminal of the third color subpixel. Because the first and second color subpixels are connected to the same anode voltage drive shift register, LC_1 and LC_2 are the same signal. Because the first and second color subpixels are connected to the same luminescence shift register, EM_1 and EM_2 are the same signal.

[0200] When K=2, the driving modes of the first color sub-pixel and the second color sub-pixel are the same. The driving modes of the first color sub-pixel and the third color sub-pixel can be different or the same.

[0201] In an exemplary embodiment, when the driving modes of the first color sub-pixel and the third color sub-pixel are different, the driving mode of the first color sub-pixel can be one of three driving modes, and the driving mode of the third color sub-pixel can be a driving mode other than the driving mode of the first sub-pixel. For example, the driving mode of the first color sub-pixel can be the first driving mode, and the driving mode of the third color sub-pixel can be the second driving mode or the third driving mode, or, the driving mode of the first color sub-pixel can be the second driving mode, and the driving mode of the third color sub-pixel can be the first driving mode or the third driving mode, or, the driving mode of the first color sub-pixel can be the third driving mode, and the driving mode of the third color sub-pixel can be the first driving mode or the second driving mode.

[0202] When the driving modes of the first color subpixels and the third color subpixels located in the i-th row are the same, the second duty cycles of the anode voltage control signals output by the i-th-stage first anode voltage driving shift register and the i-th-stage second anode voltage driving shift register are different, and / or the voltages of the voltage signals provided by the anode voltage signal line in the 2i-1th row and the anode voltage signal line in the 2i-th row are different. The second duty cycle is a ratio of a duration during which the anode voltage control signal is an inactive level signal to a second time, where the second time is the sum of a duration during which the anode voltage control signal is an inactive level signal and a duration during which the anode voltage control signal is an active level signal. Figure 13A and Figure 13B The description is made by taking the example that the second duty ratios of the anode voltage control signals output by the i-th stage first anode voltage driven shift register and the i-th stage second anode voltage driven shift register are different.

[0203] In an exemplary embodiment, when the driving modes of the first color sub-pixel and the third color sub-pixel are the same, namely, the second driving mode, the anode voltage control signals output by the first anode voltage driving shift register and the second anode voltage driving shift register are different.

[0204] In an exemplary embodiment, when the driving modes of the first color sub-pixel and the third color sub-pixel are the same and both are the third driving mode, the anode voltage control signals output by the first anode voltage driving shift register and the second anode voltage driving shift register are different, and / or the voltages of the voltage signals provided by the 2i-1th row anode voltage signal line and the 2ith row anode voltage signal line are different.

[0205] In an exemplary embodiment, Figure 14A The working timing of multiple sub-pixels in a pixel unit Figure 3 , Figure 14B The working timing of multiple sub-pixels in a pixel unit Figure 4 . Figure 14A The following description is made by taking the example that sub-pixels in the same row are connected to the same light-emitting signal line. Figure 14B This description uses the example of sub-pixels in the same row connected to three emission signal lines. LC_1 represents the signal at the anode voltage control signal terminal of the first color sub-pixel, LC_2 represents the signal at the anode voltage control signal terminal of the second color sub-pixel, and LC_3 represents the signal at the anode voltage control signal terminal of the third color sub-pixel. EM_1 represents the signal at the emission signal terminal of the first color sub-pixel, EM_2 represents the signal at the emission signal terminal of the second color sub-pixel, and EM_3 represents the signal at the emission signal terminal of the third color sub-pixel. When K = 3, at least two of the first, second, and third color sub-pixels have different drive modes, or the first, second, and third color sub-pixels have the same drive mode.

[0206] In an exemplary embodiment, the driving modes of the first color sub-pixel, the second color sub-pixel, and the third color sub-pixel may all be different. The driving mode of the first color sub-pixel may be the first driving mode, the driving mode of the second color sub-pixel may be one of the second driving mode or the third driving mode, and the driving mode of the third color sub-pixel may be the other of the second driving mode or the third driving mode, or the driving mode of the first color sub-pixel may be the second driving mode, the driving mode of the second color sub-pixel may be one of the first driving mode or the third driving mode, and the driving mode of the third color sub-pixel may be the other of the first driving mode or the third driving mode, or the driving mode of the first color sub-pixel may be the third driving mode, the driving mode of the second color sub-pixel may be the other of the first driving mode or the second driving mode, and the driving mode of the third color sub-pixel may be the other of the first driving mode or the second driving mode. The driving modes of two of the first color sub-pixel, the second color sub-pixel, and the third color sub-pixel are the same and different from the driving mode of the other color sub-pixel. Taking the example that the driving modes of the second color sub-pixel and the third color sub-pixel are the same, the driving mode of the first color sub-pixel can be the first driving mode, and the driving mode of the second color sub-pixel can be the second driving mode or the third driving mode, or the driving mode of the first color sub-pixel can be the second driving mode, and the driving mode of the second color sub-pixel can be the first driving mode or the third driving mode, or the driving mode of the first color sub-pixel can be the third driving mode, and the driving mode of the second color sub-pixel can be the first driving mode or the second driving mode.

[0207] When the driving modes of the three color sub-pixels in the i-th row are the same, the second duty cycles of at least two of the anode voltage control signals output by the i-th-stage first anode voltage driving shift register, the i-th-stage second anode voltage driving shift register, and the i-th-stage third anode voltage driving shift register are different, and / or the voltages of at least two of the voltage signals provided by the anode voltage signal line in the 3i-2th row, the anode voltage signal line in the 3i-1th row, and the anode voltage signal line in the 3ith row are different. The second duty cycle is a ratio of a duration during which the anode voltage control signal is an inactive level signal to a second time, where the second time is the sum of a duration during which the anode voltage control signal is an inactive level signal and a duration during which the anode voltage control signal is an active level signal.

[0208] In an exemplary embodiment, when the driving modes of the first to third color sub-pixels are the same, namely, the second driving mode, the anode voltage control signals output by the first anode voltage driving shift register and the second anode voltage driving shift register are different.

[0209] In an exemplary embodiment, when the driving modes of the first color sub-pixel and the third color sub-pixel are the same and both are the third driving mode, the anode voltage control signals output by the first anode voltage driving shift register to the third anode voltage driving shift register are different, and / or the voltages of the voltage signals provided by the 3i-2th row anode voltage signal line to the 3ith row anode voltage signal line are different.

[0210] In an exemplary embodiment, the sum of the first duty cycle and the second duty cycle may be less than 1.

[0211] In an exemplary embodiment, the first duty cycle may be approximately 30% to 99%.

[0212] In an exemplary embodiment, the voltage value of the voltage signal provided by the anode voltage signal line is approximately -0.1V to -10V, and the voltage value of the voltage signal provided by the anode voltage signal line is less than the reverse breakdown voltage of the light emitting element.

[0213] In the present disclosure, the voltage value of the voltage signal provided by the anode voltage signal line is less than the reverse breakdown voltage of the light-emitting element, which can protect the light-emitting element and prevent the light-emitting element from being broken down.

[0214] In an exemplary embodiment, the operation process of the pixel circuit includes: a light-emitting phase and a non-light-emitting phase; when the signal at the light-emitting signal terminal is a valid level signal, the pixel circuit is in the light-emitting phase; when the signal at the light-emitting signal terminal is an invalid level signal, the pixel circuit is in the non-light-emitting phase. When the sub-pixel drive mode is the second drive mode or the third drive mode, the non-light-emitting phase includes: a first non-light-emitting sub-phase and multiple second non-light-emitting sub-phases; the light-emitting phase includes: multiple light-emitting sub-phases, the first non-light-emitting sub-phase occurring before the light-emitting phase, and the second non-light-emitting sub-phase occurring between adjacent light-emitting sub-phases; the light-emitting sub-phase is divided into L first time periods, and the second non-light-emitting sub-phase is divided into L second time periods; the signal at the anode voltage control terminal in the second non-light-emitting sub-phase is a valid level signal. For the mth light-emitting sub-phase and the nth second non-light-emitting sub-phase, the sth second time period occurs between the sth first time period and the s+1th first time period, and the tth first time period occurs between the t-1th second time period and the s+1th second time period.

[0215] The present disclosure can avoid flickering of the display panel and improve the display effect of the display panel by dividing the light-emitting sub-stage and the second non-light-emitting sub-stage when the driving mode of the sub-pixel is the second driving mode or the third driving mode.

[0216] In an exemplary embodiment, the non-display area may also be provided with a timing controller; the image displayed by the display panel includes N frames. The timing controller is configured to provide a driving signal to a driving circuit so that the same sub-pixel switches between different driving modes within different frames; the driving circuit includes: an anode voltage driving circuit, a light-emitting driving circuit, a scanning driving circuit, and a reset driving circuit.

[0217] The lifespan of sub-pixels of different colors will be different under different conditions. In the present disclosure, the timing controller can realize free switching between the first driving mode, the second driving mode and the third driving mode, which can improve the lifespan of sub-pixels of different colors under different conditions and extend the lifespan of white light in the display panel.

[0218] In an exemplary embodiment, the non-display area may further include a source driving circuit connected to the data signal line and configured to provide a data signal to the data signal line.

[0219] In an exemplary embodiment, the timing controller and the source driving circuit may be disposed on the upper side or the lower side of the display area.

[0220] In an exemplary embodiment, the timing controller can provide grayscale values and control signals suitable for the specifications of the source driver circuit to the source driver circuit, can provide clock signals, scan start signals, etc. suitable for the specifications of the scan driver circuit to the scan driver circuit, and can provide clock signals, emission stop signals, etc. suitable for the specifications of the light-emitting driver circuit to the light-emitting driver circuit.

[0221] In one exemplary embodiment, the source driving circuit may generate a data voltage to be supplied to the data signal line using a grayscale value and a control signal received from the timing controller.

[0222] In an exemplary embodiment, the scan driving circuit may generate a scan signal to be provided to the scan line by receiving a clock signal, a scan start signal, etc. from a timing controller. For example, the scan driving circuit may sequentially provide the scan signal to the scan line. For example, the scan driving circuit may be composed of a plurality of cascaded shift registers, and each shift register may sequentially generate the scan signal under the control of a clock signal.

[0223] In one exemplary embodiment, the light driving circuit may generate a light signal to be provided to the light signal line by receiving a clock signal from a timing controller, transmitting a stop signal, etc. For example, the light driving circuit may sequentially provide the light signal to the light signal line. For example, the light driving circuit may be composed of a plurality of cascaded shift registers, and each shift register may sequentially generate the light signal under the control of a clock signal.

[0224] In an exemplary embodiment, an anode voltage-driven shift register includes: M1 bias transistors and M2 bias capacitors. The anode voltage-driven shift register includes: a first anode voltage-driven shift register, a second anode voltage-driven shift register, or a third anode voltage-driven shift register. The light-emitting shift register includes: M3 light-emitting transistors and M4 light-emitting capacitors. The light-emitting shift register includes: a first light-emitting shift register, a second light-emitting shift register, or a third light-emitting shift register. Each scanning shift register includes: M5 scanning transistors and M6 scanning capacitors. Each reset shift register includes: M5 reset transistors and M6 reset capacitors. The connection between the M5 scanning transistors and the M6 scanning capacitors is the same as the connection between the M5 reset transistors and the M6 reset capacitors, wherein M3 is not equal to M5, and M4 is not equal to M6. M1 and M2 satisfy: M1 = M5, M2 = M6, or M1 = M3, M2 = M4.

[0225] In an exemplary embodiment, when M1 = M5 and M2 = M6, the connection mode between the M1 bias transistors and the M2 bias capacitors is the same as the connection mode between the M5 scan transistors and the M6 scan capacitors.

[0226] In an exemplary embodiment, when M1 = M3 and M2 = M4, the connection mode between the M1 bias transistors and the M2 bias capacitors is the same as the connection mode between the M3 light-emitting transistors and the M4 light-emitting capacitors.

[0227] In an exemplary embodiment, for each sub-pixel, when M1=M3 and M2=M4, the difference between the duration during which the signal at the light-emitting signal end is an invalid level signal and the duration during which the signal at the anode voltage control end is a valid level signal is less than the threshold time difference, and the duration during which the signal at the anode voltage control end is a valid level signal is greater than the duration during which the signal at the scanning signal end is a valid level signal.

[0228] In an exemplary embodiment, for each sub-pixel, when M1=M5 and M2=M6, the difference between the duration during which the signal at the light-emitting signal terminal is an invalid level signal and the duration during which the signal at the anode voltage control terminal is a valid level signal is greater than the threshold time difference, and the duration during which the signal at the anode voltage control terminal is a valid level signal is equal to the duration during which the signal at the scanning signal terminal is a valid level signal.

[0229] In an exemplary embodiment, Figures 2 to 7 As shown, the scan driving circuit includes: M cascaded scan shift registers GATE_1 to GATE_M, the i-th level scan shift register GATE_i and the i-th row scan signal line G i connect.

[0230] Figure 15A This is an equivalent circuit diagram of a scanning shift register. Figure 15A As shown, in an exemplary embodiment, each scan shift register includes: a first scan transistor GT1 to an eighth scan transistor GT8, a first scan capacitor GC1 and a second scan capacitor GC2. Figure 11A The connection between eight bias transistors and two bias capacitors is Figure 15A The connection between eight scanning transistors and two scanning capacitors is taken as an example for explanation.

[0231] In one exemplary embodiment, the control electrode of the first scanning transistor GT1 is connected to the first clock signal terminal CK, the first electrode of the first scanning transistor GT1 is connected to the signal input terminal IN, and the second electrode of the first scanning transistor GT1 is connected to the first node G1. The control electrode of the second scanning transistor GT2 is connected to the first node G1, the first electrode of the second scanning transistor GT2 is connected to the second node G2, and the second electrode of the second scanning transistor GT2 is connected to the first clock signal terminal CK. The control electrode of the third scanning transistor GT3 is connected to the first clock signal terminal CK, the first electrode of the third scanning transistor GT3 is connected to the second power supply terminal VGL, and the second electrode of the third scanning transistor GT3 is connected to the second node G2. The control electrode of the fourth scanning transistor GT4 is connected to the second node G2, the first electrode of the fourth scanning transistor GT4 is connected to the first power supply terminal VGH, and the second electrode of the fourth scanning transistor GT4 is connected to the signal output terminal OUT. The control electrode of the fifth scanning transistor GT5 is connected to the third node G3, the first electrode of the fifth scanning transistor GT5 is connected to the signal output terminal OUT, and the second electrode of the fifth scanning transistor GT5 is connected to the second clock signal terminal CB. The control electrode of the sixth scan transistor GT6 is connected to the second node G2, the first electrode of the sixth scan transistor GT6 is connected to the first power supply terminal VGH, and the second electrode of the sixth scan transistor GT6 is connected to the first electrode of the seventh scan transistor GT7. The control electrode of the seventh scan transistor GT7 is connected to the second clock signal terminal CB, and the second electrode of the seventh scan transistor GT7 is connected to the first node G1. The control electrode of the eighth scan transistor GT8 is connected to the second power supply terminal VGL, the first electrode of the eighth scan transistor GT8 is connected to the first node G1, and the second electrode of the eighth scan transistor GT8 is connected to the third node G3. The first plate of the first scan capacitor GC1 is connected to the first power supply terminal VGH, and the second plate of the first scan capacitor GC1 is connected to the second node G2. The first plate of the second scan capacitor GC2 is connected to the signal output terminal OUT, and the second plate of the second scan capacitor GC2 is connected to the third node G3.

[0232] In an exemplary embodiment, the first power supply terminal VGH may continuously provide a high-level signal, and the second power supply terminal VGL may continuously provide a low-level signal.

[0233] In an exemplary embodiment, the first to eighth scanning transistors GT1 to GT8 may be P-type transistors or N-type transistors. Using the same type of transistors in the scan drive circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield.

[0234] Figure 15B for Figure 15A The working timing diagram of the scan shift register is provided. Figure 15B The first scanning transistor GT1 to the eighth scanning transistor GT8 are P-type transistors. Figure 15B As shown, the working process of the scan shift register provided by an exemplary embodiment may include:

[0235] In the first stage D1, the signals at the signal input terminal IN and the first clock signal terminal CK are low-level signals, while the signal at the second clock signal terminal CB is high-level. The signal at the first clock signal terminal CK is low-level, the first scan transistor GT1 and the third scan transistor GT3 are turned on, and the eighth scan transistor GT8 remains on after receiving the low-level signal from the second power supply terminal VGL. The signal at the signal input terminal IN is written to the first node G1, the signal at the first node G1 is written to the third node G3, the fifth scan transistor GT5 is turned on, and the signal at the second clock signal terminal CB is transmitted to the signal output terminal OUT via the fifth scan transistor GT5. Furthermore, the low-level signal from the second power supply terminal VGL is written to the second node G2, the fourth scan transistor GT4 and the sixth scan transistor GT6 are turned on, and the high-level signal from the first power supply terminal VGH is written to the signal output terminal OUT. Because the signal at the second clock signal terminal CB is high-level, the seventh scan transistor GT7 is turned off. During this stage, the output signal at the signal output terminal OUT is high-level.

[0236] In the second stage D2, the signals at the signal input terminal IN and the first clock signal terminal CK are high-level signals, while the signal at the second clock signal terminal CB is low-level. The signal at the first clock signal terminal CK is high-level, the first scanning transistor GT1 and the third scanning transistor GT3 are turned off, the first node G1 remains low-level, and the eighth scanning transistor GT8, receiving the low-level signal from the second power supply terminal VGL, remains on. Due to the bootstrap effect of the second scanning capacitor GC2, the fifth scanning transistor GT5 is turned on, and the signal at the second clock signal terminal CB is written to the signal output terminal OUT. Furthermore, the signal at the first clock signal terminal CK is high-level, the second scanning transistor GT2 is turned on, and the signal at the first clock signal terminal CK is written to the second node G2. Consequently, the fourth scanning transistor GT4 and the sixth scanning transistor GT6 are both turned off. During this stage, the output signal at the signal output terminal OUT is low-level.

[0237] In the third stage D3, the signal at the first clock signal terminal CK is a low-level signal, and the signals at the signal input terminal IN and the second clock signal terminal CB are high-level signals. The signal at the first clock signal terminal CK is a low-level signal, the first scanning transistor GT1 and the third scanning transistor GT3 are turned on, the signal at the signal input terminal IN is written to the first node G1, and the second scanning transistor GT2 is turned off. Because the eighth scanning transistor GT8 is continuously turned on, the signal at the first node G1 is written to the third node G3, and the fifth scanning transistor GT5 is turned off. The signal at the second power supply terminal VGL is written to the second node G2, the fourth scanning transistor GT4 and the sixth scanning transistor GT6 are turned on, and the high-level signal at the third power supply terminal VGH is written to the signal output terminal OUT. During this stage, the output signal at the signal output terminal OUT is a high-level signal.

[0238] In the fourth stage D4, the signal at the second clock signal terminal CB is a low-level signal, while the signals at the signal input terminal IN and the first clock signal terminal CK are high-level signals. The signal at the first clock signal terminal CK is a high-level signal, the first scanning transistor GT1 and the third scanning transistor GT3 are turned off, the first node G1 remains at the high-level signal from the previous stage, and the second scanning transistor GT2 is turned off. Because the eighth scanning transistor GT8 remains on, the signal at the first node G1 is written to the third node G3, and the fifth scanning transistor GT5 is turned off. The second node G2 remains at a low-level signal, the fourth scanning transistor GT4 and the sixth scanning transistor GT6 are turned on, and the high-level signal at the third power supply terminal VGH is written to the signal output terminal OUT. During this stage, the output signal at the signal output terminal OUT is a high-level signal.

[0239] After the fourth stage D4, the third stage and the fourth stage of the scan shift register are performed alternately until the signal at the signal input terminal IN is a low level signal.

[0240] In an exemplary embodiment, Figures 2 to 7 As shown, the reset driving circuit 40 includes: M cascaded reset shift registers RST_1 to RST_M, the i-th stage reset shift register RST_i and the i-th row reset signal line R i connect.

[0241] Figure 16A This is an equivalent circuit diagram of a reset shift register. Figure 16A As shown, in an exemplary embodiment, each reset driving circuit includes: a first reset transistor RT1 to an eighth reset transistor RT8, a first reset capacitor RC1 and a second reset capacitor RC2.

[0242] In one exemplary embodiment, a control electrode of the first reset transistor RT1 is connected to the first clock signal terminal CK, a first electrode of the first reset transistor RT1 is connected to the signal input terminal IN, and a second electrode of the first reset transistor RT1 is connected to the first node R1. A control electrode of the second reset transistor RT2 is connected to the first node R1, a first electrode of the second reset transistor RT2 is connected to the second node R2, and a second electrode of the second reset transistor RT2 is connected to the first clock signal terminal CK. A control electrode of the third reset transistor RT3 is connected to the first clock signal terminal CK, a first electrode of the third reset transistor RT3 is connected to the second power supply terminal VGL, and a second electrode of the third reset transistor RT3 is connected to the second node R2. A control electrode of the fourth reset transistor RT4 is connected to the second node R2, a first electrode of the fourth reset transistor RT4 is connected to the first power supply terminal VGH, and a second electrode of the fourth reset transistor RT4 is connected to the signal output terminal OUT. A control electrode of the fifth reset transistor RT5 is connected to the third node R3, a first electrode of the fifth reset transistor RT5 is connected to the signal output terminal OUT, and a second electrode of the fifth reset transistor RT5 is connected to the second clock signal terminal CB. A control electrode of the sixth reset transistor RT6 is connected to the second node R2, a first electrode of the sixth reset transistor RT6 is connected to the first power supply terminal VGH, and a second electrode of the sixth reset transistor RT6 is connected to the first electrode of the seventh reset transistor RT7. A control electrode of the seventh reset transistor RT7 is connected to the second clock signal terminal CB, and a second electrode of the seventh reset transistor RT7 is connected to the first node R1. A control electrode of the eighth reset transistor RT8 is connected to the second power supply terminal VGL, a first electrode of the eighth reset transistor RT8 is connected to the first node R1, and a second electrode of the eighth reset transistor RT8 is connected to the third node R3. A first plate of the first reset capacitor RC3 is connected to the first power supply terminal VGH, and a second plate of the first reset capacitor RC1 is connected to the second node R2. A first plate of the second reset capacitor RC2 is connected to the signal output terminal OUT, and a second plate of the second reset capacitor RC2 is connected to the third node R3.

[0243] In an exemplary embodiment, the first power supply terminal VGH may continuously provide a high-level signal, and the second power supply terminal VGL may continuously provide a low-level signal.

[0244] In an exemplary embodiment, the first reset transistor RT1 to the eighteenth reset transistor RT8 can be P-type transistors or N-type transistors. Using the same type of transistors in the reset shift register can simplify the process, reduce the manufacturing difficulty of the display panel, and improve the product yield.

[0245] Figure 16B for Figure 16A The working timing diagram of the reset shift register is provided. Figure 16B It is taken as an example that the first reset transistor RT1 to the eighth reset transistor RT8 are P-type transistors. Figure 16B As shown, the working process of resetting the shift register provided by an exemplary embodiment may include:

[0246] In the first phase E1, the signals at the signal input terminal IN and the first clock signal terminal CK are low-level signals, while the signal at the second clock signal terminal CB is high-level. The signal at the first clock signal terminal CK is low-level, the first reset transistor RT1 and the third reset transistor RT3 are turned on, and the eighth reset transistor RT8 remains on after receiving the low-level signal from the second power supply terminal VGL. The signal at the signal input terminal IN is written to the first node R1, the signal at the first node R1 is written to the third node R3, the fifth reset transistor RT5 is turned on, and the signal at the second clock signal terminal CB is transmitted to the signal output terminal OUT via the fifth reset transistor RT5. Furthermore, the low-level signal from the second power supply terminal VGL is written to the second node R2, the fourth reset transistor RT4 and the sixth reset transistor RT6 are turned on, and the high-level signal from the first power supply terminal VGH is written to the signal output terminal OUT. Because the signal at the second clock signal terminal CB is high-level, the seventh reset transistor RT7 is turned off. During this phase, the output signal at the signal output terminal OUT is high-level.

[0247] In the second phase E2, the signals at the signal input terminal IN and the first clock signal terminal CK are high-level signals, while the signal at the second clock signal terminal CB is low-level. The signal at the first clock signal terminal CK is high-level, the first reset transistor RT1 and the third reset transistor RT3 are turned off, the first node R1 remains low-level, and the eighth reset transistor RT8 remains on, receiving the low-level signal from the second power supply terminal VGL. Due to the bootstrap effect of the fourth reset capacitor RC4, the fifth reset transistor RT5 is turned on, and the signal at the second clock signal terminal CB is written to the signal output terminal OUT. Furthermore, the signal at the first clock signal terminal CK is high-level, the second reset transistor RT2 is turned on, and the signal at the first clock signal terminal CK is written to the second node R2. Consequently, the fourth reset transistor RT4 and the sixth reset transistor RT6 are both turned off. During this phase, the output signal at the signal output terminal OUT is low-level.

[0248] In the third phase E3, the signal at the first clock signal terminal CK is a low-level signal, and the signals at the signal input terminal IN and the second clock signal terminal CB are high-level signals. The signal at the first clock signal terminal CK is a low-level signal, the first reset transistor RT1 and the third reset transistor RT3 are turned on, the signal at the signal input terminal IN is written to the first node R1, and the second reset transistor RT2 is turned off. Because the eighth reset transistor RT8 is continuously turned on, the signal at the first node R1 is written to the third node R3, and the fifth reset transistor RT5 is turned off. The signal at the second power supply terminal VGL is written to the second node R2, the fourth reset transistor RT4 and the sixth reset transistor RT6 are turned on, and the high-level signal at the third power supply terminal VGH is written to the signal output terminal OUT. During this phase, the output signal at the signal output terminal OUT is a high-level signal.

[0249] In the fourth phase E4, the signal at the second clock signal terminal CB is a low-level signal, while the signals at the signal input terminal IN and the first clock signal terminal CK are high-level signals. The signal at the first clock signal terminal CK is a high-level signal, the first reset transistor RT1 and the third reset transistor RT3 are turned off, the first node R1 remains at the high-level signal from the previous phase, and the second reset transistor RT2 is turned off. Because the eighth reset transistor RT8 remains on, the signal at the first node R1 is written to the third node R3, and the fifth reset transistor RT5 is turned off. The second node R2 remains at a low-level signal, the fourth reset transistor RT4 and the sixth reset transistor RT6 are turned on, and the high-level signal at the third power supply terminal VGH is written to the signal output terminal OUT. During this phase, the output signal at the signal output terminal OUT is a high-level signal.

[0250] After the fourth stage E4, the second reset shift register performs the third stage and the fourth stage alternately until the signal at the signal input terminal IN is a low level signal.

[0251] Figure 17AThis is an equivalent circuit diagram of a light-emitting shift register. Figure 17A As shown, the light emitting shift register includes: first to tenth light emitting transistors ET1 to ET10 and first to third light emitting capacitors EC1 to EC3. Figure 10A The connection between ten bias transistors and three bias capacitors is Figure 17A The connection method between the ten light-emitting transistors and the three light-emitting capacitors is the same as an example for explanation.

[0252] In an exemplary embodiment, the light emitting shift register may also be a 12T3C structure, and the anode voltage bias shift register may also be a 12T3C structure, which is not limited in the present disclosure.

[0253] In an exemplary embodiment, the light emitting shift register includes: a first light emitting shift register, a second light emitting shift register, or a third light emitting shift register.

[0254] In an exemplary embodiment, a control electrode of the first light-emitting transistor ET1 is connected to the first node E1, a first electrode of the first light-emitting transistor ET1 is connected to the first power supply terminal VGH, and a second electrode of the first light-emitting transistor ET1 is connected to the first electrode of the second light-emitting transistor ET2. A control electrode of the second light-emitting transistor ET1 is connected to the second clock signal terminal CB, and a second electrode of the second light-emitting transistor ET2 is connected to the second node E2. A control electrode of the third light-emitting transistor ET3 is connected to the second node E2, a first electrode of the third light-emitting transistor ET3 is connected to the first node E1, and a second electrode of the third light-emitting transistor ET3 is connected to the first clock signal terminal CK. A control electrode of the fourth light-emitting transistor ET4 is connected to the first clock signal terminal CK, a first electrode of the fourth light-emitting transistor ET4 is connected to the signal input terminal IN, and a second electrode of the fourth light-emitting transistor ET4 is connected to the second node E2. A control electrode of the fifth light-emitting transistor ET5 is connected to the first clock signal terminal CK, a first electrode of the fifth light-emitting transistor ET5 is connected to the second power supply terminal VGL, and a second electrode of the fifth light-emitting transistor ET5 is connected to the first node E1. The control electrode of the sixth light-emitting transistor ET6 is connected to the first node E1, the first electrode of the sixth light-emitting transistor ET6 is connected to the second clock signal terminal CB, the second electrode of the sixth light-emitting transistor ET6 is connected to the first electrode of the seventh light-emitting transistor ET7, and the second electrode of the sixth light-emitting transistor ET6 is connected to the third node E3. The control electrode of the seventh light-emitting transistor ET7 is connected to the second clock signal terminal CB, the first electrode of the seventh light-emitting transistor ET7 is connected to the third node E3, and the second electrode of the seventh light-emitting transistor ET7 is connected to the fourth node E4. The control electrode of the eighth light-emitting transistor ET8 is connected to the first node E1, the first electrode of the eighth light-emitting transistor ET8 is connected to the fourth node E4, and the second electrode of the eighth light-emitting transistor ET8 is connected to the first power supply terminal VGH. The control electrode of the ninth light-emitting transistor ET9 is connected to the fourth node E4, the first electrode of the ninth light-emitting transistor ET9 is connected to the first power supply terminal VGH, and the second electrode of the ninth light-emitting transistor ET9 is connected to the signal output terminal OUT. The control electrode of the tenth light-emitting transistor ET10 is connected to the first node E1, the first electrode of the tenth light-emitting transistor ET10 is connected to the signal output terminal OUT, and the second electrode of the tenth light-emitting transistor ET10 is connected to the second power supply terminal VGL. A first plate EC11 of the first light-emitting capacitor EC1 is connected to the fourth node E4, and a second plate EC12 of the first light-emitting capacitor EC1 is connected to the first power supply terminal VGH. A first plate EC21 of the second light-emitting capacitor EC2 is connected to the first node E1, and a second plate EC22 of the second light-emitting capacitor EC2 is connected to the third node E3. A first plate E31 of the third light-emitting capacitor EC3 is connected to the second node E2, and a second plate E32 of the third light-emitting capacitor EC3 is connected to the second clock signal terminal CB.

[0255] In an exemplary embodiment, the first power supply terminal VGH may continuously provide a high-level signal, and the second power supply terminal VGL may continuously provide a low-level signal.

[0256] In an exemplary embodiment, the first to tenth light-emitting transistors ET1 to ET10 may be P-type transistors or N-type transistors. Using the same type of transistors in the light-emitting drive circuit can simplify the process, reduce the manufacturing difficulty of the display panel, and improve the product yield.

[0257] Figure 17B for Figure 17A The working timing diagram of the luminous shift register is provided. Figure 17B Take the first light emitting transistor ET1 to the tenth light emitting transistor ET10 as an example, which are P-type transistors. Figure 17B As shown, the working process of the light emitting shift register provided by an exemplary embodiment may include:

[0258] In the first phase F1, the signals at the signal input terminal IN and the second clock signal terminal CB are low-level signals, while the signal at the first clock signal terminal CK is high-level. The signal at the first clock signal terminal CK is high-level, the fourth light-emitting transistor ET4 and the fifth light-emitting transistor ET5 are turned off, the signal at the signal input terminal IN cannot be written to the second node E2, and the signal at the second power supply terminal VGL cannot be written to the first node E1. Due to the action of the third light-emitting capacitor EC3, the signal at the second node E2 remains low-level. The third light-emitting transistor ET3, the eighth light-emitting transistor ET8, and the tenth light-emitting transistor ET10 are turned on. The high-level signal at the first clock signal terminal CK is written to the first node E1. The first light-emitting transistor ET1 and the sixth light-emitting transistor ET6 are turned off. The high-level signal at the first power supply terminal VGH is written to the fourth node E4, and the low-level signal at the second power supply terminal VGL is written to the signal output terminal OUT. The signal at the third node E3 remains high-level, the signal at the second clock signal terminal CB is low-level, the second light-emitting transistor ET2 and the seventh light-emitting transistor ET7 are turned on, the signal at the third node E3 is written to the fourth node E4, and the signal at the fourth node E4 remains high-level. The ninth light-emitting transistor ET9 is turned off. In this stage, the signal output terminal OUT outputs a low-level signal.

[0259] In the second phase F2, the signal at the first clock signal terminal CK is low, while the signals at the signal input terminal IN and the second clock signal terminal CB are high. The signal at the second clock signal terminal CB is high, and the second and seventh light-emitting transistors ET2 and ET7 are off. The signal at the first clock signal terminal CK is low, and the fourth and fifth light-emitting transistors ET4 and ET5 are turned on. The high-level signal at the signal input terminal IN is written to the second node E2. The third, eighth, and tenth light-emitting transistors ET3, ET8, and ET10 are turned off. The signal at the first clock signal terminal CK cannot be written to the first node E1, the signal at the first power supply terminal VGH cannot be written to the fourth node E4, and the signal at the second power supply terminal VGL cannot be written to the signal output terminal OUT. The low-level signal at the second power supply terminal VGL is written to the first node E1, the first and sixth light-emitting transistors ET1 and ET6 are turned on, and the signal at the second clock signal terminal CB is written to the third node E3. Because the seventh light-emitting transistor ET7 is turned off, the signal at the third node E3 cannot be written to the fourth node E4. During this phase, the signal output terminal OUT maintains the low-level signal of the upshift phase.

[0260] In the third phase F3, the signal at the second clock signal terminal CB is low, while the signals at the signal input terminal IN and the first clock signal terminal CK are high. The signal at the first clock signal terminal CK is high, and the fourth and fifth light-emitting transistors ET4 and ET5 are off. The signal at the signal input terminal IN cannot be written to the second node E2, and the signal at the second power supply terminal VGL cannot be written to the first node E1. Due to the action of the third light-emitting capacitor EC3, the signal at the second node E2 remains high, as it was in the previous phase. Due to the action of the second light-emitting capacitor EC2, the signal at the first node E1 remains low, as it was in the previous phase. The first and sixth light-emitting transistors ET1 and ET6 are turned on, and the high-level signal at the first power supply terminal VGH is written to the second node E2, causing it to remain high. The low-level signal at the second clock signal terminal CB is written to the third node E3, and the signal at the third node E3 is written to the fourth node E4. The ninth light-emitting transistor E9 is turned on, and the high-level signal at the first power supply terminal VGH is written to the signal output terminal OUT. During this phase, the signal output terminal OUT outputs a high-level signal.

[0261] In the fourth phase F4, the signal at the first clock signal terminal CK is low, while the signals at the signal input terminal IN and the second clock signal terminal CB are high. The signal at the second clock signal terminal CB is high, and the second light-emitting transistor ET2 and the seventh light-emitting transistor ET7 are off. The signal at the first clock signal terminal CK is low, and the fourth light-emitting transistor ET4 and the fifth light-emitting transistor ET5 are turned on. The high-level signal at the signal input terminal IN is written to the second node E2, while the third light-emitting transistor ET3, the eighth light-emitting transistor ET8, and the tenth light-emitting transistor ET10 are turned off. The signal at the first clock signal terminal CK cannot be written to the first node E1, the signal at the first power supply terminal VGH cannot be written to the fourth node E4, and the signal at the second power supply terminal VGL cannot be written to the signal output terminal OUT. The low-level signal at the second power supply terminal VGL is written to the first node E1, the first light-emitting transistor ET1 and the sixth light-emitting transistor ET6 are turned on, and the signal at the second clock signal terminal CB is written to the third node E3. Because the seventh light-emitting transistor ET7 is turned off, the signal at the third node E3 cannot be written to the fourth node E4. During this phase, the signal output terminal OUT maintains the high-level signal from the previous phase.

[0262] In the fifth stage F5, the signal at the first clock signal terminal CK is high, while the signals at the signal input terminal IN and the second clock signal terminal CB are low. The signal at the first clock signal terminal CK is high, and the fourth and fifth light-emitting transistors ET4 and ET5 are off. The signal at the signal input terminal IN cannot be written to the second node E2, and the signal at the second power supply terminal VGL cannot be written to the first node E1. Due to the action of the third light-emitting capacitor EC3, the signal at the second node E2 remains high, as it was in the previous stage. Due to the action of the second light-emitting capacitor EC2, the signal at the first node E1 remains low, as it was in the previous stage. The first and sixth light-emitting transistors ET1 and ET6 are turned on, and the high signal at the first power supply terminal VGH is written to the second node E2, causing it to remain high. The low signal at the second clock signal terminal CB is written to the third node E3, and the signal at the third node E3 is written to the fourth node E4. The ninth light-emitting transistor E9 is turned on, and the high signal at the first power supply terminal VGH is written to the signal output terminal OUT. During this stage, the signal output terminal OUT outputs a high signal.

[0263] In an exemplary embodiment, Figures 18 and 19 A waveform diagram of an input signal of a driving circuit provided by an exemplary embodiment is shown. Figures 20 to 33 The waveform diagram of the output signal of the driving circuit provided by an exemplary embodiment. Figures 18 to 33 The following example illustrates the resolution of 1920*720, the frequency of 60Hz, one frame of 733 lines, and the 1H time of 1 / 60 / 733=22.74us. Figures 18 to 33The signal waveforms in the figure are all measured waveforms.

[0264] like Figure 18 As shown in FIG, the waveform diagram of the input signal of the light-emitting driving circuit is located on the top, and the waveform diagram of the input signal of the scanning driving circuit is located on the bottom. Figure 19 As shown in FIG, the waveform diagram of the input signal of the light-emitting drive circuit is located on the top, and the waveform diagram of the input signal of the reset drive circuit is located on the bottom. Figure 20 As shown in FIG, the waveform diagram of the output signal of the light-emitting driving circuit is located on the top, and the waveform diagram of the output signal of the scanning driving circuit is located on the bottom. Figure 21 As shown, the waveform of the output signal of the light-emitting drive circuit is shown on the top, and the waveform of the output signal of the reset drive circuit is shown on the bottom. In one frame, the time for the input signal of the light-emitting drive circuit to be turned off is set to 9H (9*22.74≈204.64us, Figure 18 The measured value is 215.92us, which is consistent with the theoretical value). The opening time of the input signal of the reset drive circuit is 2H (45.47us, Figure 19 The measured value is 45.39us, which is consistent with the theoretical value). Figure 20 and Figure 21 As shown, the output signal of the reset driving circuit is earlier than the output signal of the scan driving circuit.

[0265] In an exemplary embodiment, Figures 22 to 27 The following is an example of a driving current duty cycle of 85%. Figure 22 and Figure 23 As shown, the waveform diagram of the output signal of the light-emitting driving circuit is located on the top, and the waveform diagram of the output signal of the scanning driving circuit is located on the bottom, wherein, Figure 23 Yes Figure 22 Magnified image of . Figure 22 and Figure 23 It can be seen that the output time of the scanning drive circuit is about 5.98 microseconds. Figure 24 and Figure 25 As shown, the waveform diagram of the output signal of the light-emitting drive circuit is located on the top, and the waveform diagram of the output signal of the reset drive circuit is located on the bottom, wherein, Figure 25 Yes Figure 24 Magnified image of . Figure 26 and Figure 27 As shown, the waveform of the output signal of the light-emitting driving circuit is located on the top, and the waveform of the output signal of the driving circuit that can output a pulse voltage is located below. The driving circuit of the pulse voltage, wherein, Figure 27 Yes Figure 26 Magnified image of .

[0266] In an exemplary embodiment, Figures 28 to 33 A waveform diagram of an output signal of a driving circuit provided by an exemplary embodiment. Figures 28 to 33 The following is an example of a driving current duty cycle of 75%. Figure 28 and Figure 29 As shown, the waveform diagram of the output signal of the light-emitting driving circuit is located on the top, and the waveform diagram of the output signal of the scanning driving circuit is located on the bottom, wherein, Figure 29 Yes Figure 28 Magnified image of . Figure 30 and Figure 31 As shown, the waveform diagram of the output signal of the light-emitting drive circuit is located on the top, and the waveform diagram of the output signal of the reset drive circuit is located on the bottom, wherein, Figure 31 Yes Figure 30 Magnified image of . Figure 32 and Figure 33 As shown, the waveform diagram of the output signal of the light-emitting driving circuit is located on the top, and the waveform diagram of the output signal of the driving circuit that can output a pulse voltage is located on the bottom, wherein, Figure 33 Yes Figure 32 Magnified image of .

[0267] An embodiment of the present disclosure further provides a display device, including: a display panel.

[0268] In an exemplary embodiment, the display device may be a monitor, a television, a mobile phone, a tablet computer, a navigator, a digital photo frame, a wearable display product, or any product or component with a display function.

[0269] The display panel is the display panel provided by any of the aforementioned embodiments, and the implementation principle and effect are similar, which will not be repeated here.

[0270] The drawings in this disclosure only relate to the structures involved in the embodiments of this disclosure, and other structures may refer to general designs.

[0271] For the sake of clarity, the thickness and size of layers or microstructures are exaggerated in the drawings used to describe the embodiments of the present disclosure. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, the element can be "directly on" or "under" the other element, or intervening elements may be present.

[0272] Although the embodiments disclosed in this disclosure are as described above, the contents described are merely embodiments adopted to facilitate understanding of the disclosure and are not intended to limit the disclosure. Any person skilled in the art to which the disclosure belongs may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope of the disclosure. However, the scope of patent protection of the disclosure shall still be based on the scope defined by the attached claims.

Claims

1. A display panel, comprising: Display area and non-display area; The display area includes: pixel units arranged in an array, at least one pixel unit includes: a first color sub-pixel, a second color sub-pixel, and a third color sub-pixel, the first color, the second color, and the third color being different colors, and at least one sub-pixel includes: a pixel circuit and a light-emitting element, the pixel circuit being connected to an anode of the light-emitting element; the non-display area includes: an anode voltage driving circuit, the anode voltage driving circuit being connected to the sub-pixel and configured to provide an anode voltage control signal to the pixel circuit of the connected sub-pixel, so as to provide a voltage signal to the anode of the light-emitting element; The anode voltage driving circuit includes: K anode voltage driving sub-circuits arranged along the row direction; Each anode voltage driving subcircuit is connected to at least one color sub-pixel, different anode voltage driving subcircuits are connected to sub-pixels of different colors, and K is a positive integer greater than or equal to 2; When the sub-pixel is displaying, the driving mode of each sub-pixel includes: a first driving mode, a second driving mode and a third driving mode; When the driving mode of the sub-pixel is the first driving mode, the pixel circuit is configured to continuously apply a driving current to the light-emitting element; When the driving mode of the sub-pixel is the second driving mode, the pixel circuit is configured to periodically apply the driving current to the light-emitting element, and stop applying the driving current during an interval between any two adjacent applications of the driving current; When the driving mode of the sub-pixel is the third driving mode, the pixel circuit is configured to periodically apply a driving current to the light-emitting element, and provide a negative bias signal to the anode of the light-emitting element during an interval between any two adjacent applications of the driving current, so that the light-emitting element does not emit light; The sub-pixels connected to the same anode voltage drive shift register have the same driving mode.

2. The display panel according to claim 1, wherein The display area further includes: 3N columns of data signal lines, M rows of scan signal lines, M rows of reset signal lines, and M rows of initial voltage lines, where M is the total number of rows of pixel units and N is the total number of columns of pixel units; The pixel circuit includes: first to seventh transistors and a storage capacitor; a control electrode of the first transistor connected to the reset signal terminal, a first electrode of the first transistor connected to the initial voltage terminal, a second electrode of the first transistor connected to the second node, a control electrode of the second transistor connected to the scan signal terminal, a first electrode of the second transistor connected to the second node, and a second electrode of the second transistor connected to the third node; a control electrode of the third transistor connected to the second node, a first electrode of the third transistor connected to the first node, and a second electrode of the third transistor connected to the third node; a control electrode of the fourth transistor connected to the scan signal terminal, a first electrode of the fourth transistor connected to the data signal terminal, and a second electrode of the fourth transistor connected to the first node; a control electrode of the fifth transistor connected to the light-emitting signal terminal, a first electrode of the fifth transistor connected to the first power supply terminal, and a second electrode of the fifth transistor connected to the first node; a control electrode of the sixth transistor connected to the light-emitting signal terminal, a first electrode of the sixth transistor connected to the third node, and a second electrode of the sixth transistor connected to the light-emitting element; a control electrode of the seventh transistor connected to the anode voltage control terminal, a first electrode of the seventh transistor connected to the anode voltage signal terminal, and a second electrode of the seventh transistor connected to the anode of the light-emitting element; a first terminal of the storage capacitor connected to the first power supply terminal, and a second terminal of the storage capacitor connected to the second node; For the pixel circuit of the sub-pixel in the i-th row and j-th column, the data signal terminal is connected to the data signal line in the j-th column, the scan signal terminal is connected to the scan signal line in the i-th row, the reset signal terminal is connected to the reset signal line in the i-th row, and the initial voltage terminal is connected to the initial voltage line in the i-th row. i M, 1 j 3N.

3. The display panel according to claim 2, wherein: When K=2, the K anode voltage driving sub-circuits are: a first anode voltage driving sub-circuit and a second anode voltage driving sub-circuit; The first anode voltage driving subcircuit includes: M cascaded first anode voltage driving shift registers, and the second anode voltage driving subcircuit includes: M cascaded second anode voltage driving shift registers; the display area also includes: 2M rows of anode voltage control lines and 2M rows of anode voltage signal lines; The 2i-1th row anode voltage control line is connected to the i-th stage first anode voltage driving shift register, and is connected to the anode voltage control terminals of the pixel circuits of the first color sub-pixels and the second color sub-pixels located in the i-th row; The 2i-th row anode voltage control line is connected to the i-th stage second anode voltage driving shift register and is connected to the anode voltage control terminal of the pixel circuit of the third color sub-pixel located in the i-th row; The 2i-1th row anode voltage signal line is connected to the anode voltage signal terminals of the pixel circuits of the first color sub-pixels and the second color sub-pixels located in the i-th row; The 2i-th row anode voltage signal line is connected to the anode voltage signal terminal of the pixel circuit of the third color sub-pixel located in the i-th row.

4. The display panel according to claim 2, wherein, when K=3, the K anode voltage driving sub-circuits are respectively: a first anode voltage driving sub-circuit, a second anode voltage driving sub-circuit, and a third anode voltage driving sub-circuit; The first anode voltage driving sub-circuit includes: M cascaded first anode voltage driving shift registers, the second anode voltage driving sub-circuit includes: M cascaded second anode voltage driving shift registers, and the third anode voltage driving sub-circuit includes: M cascaded third anode voltage driving shift registers; the display area also includes: 3M rows of anode voltage control lines and 3M rows of anode voltage signal lines; The 3i-2th row anode voltage control line is connected to the i-th stage first anode voltage driving shift register and is connected to the anode voltage control terminal of the pixel circuit of the first color sub-pixel located in the i-th row; The 3i-1th row anode voltage control line is connected to the i-th stage second anode voltage driving shift register and is connected to the anode voltage control terminal of the pixel circuit of the second color sub-pixel located in the i-th row; The 3i-th row anode voltage control line is connected to the i-th stage third anode voltage driving shift register and is connected to the anode voltage control terminal of the pixel circuit of the third color sub-pixel located in the i-th row; The anode voltage signal line in the 3i-2th row is connected to the anode voltage signal terminal of the pixel circuit of the first color sub-pixel located in the i-th row; The anode voltage signal line in the 3i-1th row is connected to the anode voltage signal terminal of the pixel circuit of the second color sub-pixel located in the i-th row; The 3i-th row anode voltage signal line is connected to the anode voltage signal terminal of the pixel circuit of the third color sub-pixel located in the i-th row.

5. The display panel according to claim 1, wherein: When K=2, the driving modes of the first color sub-pixel and the second color sub-pixel are the same; the driving modes of the first color sub-pixel and the third color sub-pixel are different or the same; When the driving modes of the first color sub-pixel and the third color sub-pixel located in the i-th row are the same, the second duty ratios of the anode voltage control signals output by the i-th stage first anode voltage driving shift register and the i-th stage second anode voltage driving shift register are different, and / or the voltages of the signals provided by the anode voltage signal line of the 2i-1-th row and the anode voltage signal line of the 2i-th row are different; The second duty cycle is the ratio of the duration when the anode voltage control signal is an invalid level signal to the second time, and the second time is the sum of the duration when the anode voltage control signal is an invalid level signal and the duration when the anode voltage control signal is a valid level signal. The display panel according to claim 1 , wherein: When K=3, the driving modes of at least two of the first color subpixel, the second color subpixel, and the third color subpixel are different, or the driving modes of the first color subpixel, the second color subpixel, and the third color subpixel are the same; When the driving modes of the three color sub-pixels located in the i-th row are the same, the second duty cycles of at least two of the anode voltage control signals output by the i-th-stage first anode voltage driving shift register, the i-th-stage second anode voltage driving shift register, and the i-th-stage third anode voltage driving shift register are different, and / or the voltages of at least two of the voltage signals provided by the 3i-2-th row anode voltage signal line, the 3i-1-th row anode voltage signal line, and the 3i-th row anode voltage signal line are different; The second duty cycle is the ratio of the duration when the anode voltage control signal is an invalid level signal to the second time, and the second time is the sum of the duration when the anode voltage control signal is an invalid level signal and the duration when the anode voltage control signal is a valid level signal.

7. The display panel according to claim 1, wherein: When the driving mode of the sub-pixel is the second driving mode or the third driving mode, the pixel circuit applies the driving current to the light-emitting element at a frequency of 1 Hz to 360 Hz.

8. The display panel according to claim 5 or 6, wherein: The non-display area further includes: a scan drive circuit, a reset drive circuit and a light emitting drive circuit; a scan driving circuit connected to the sub-pixel and configured to provide a scan control signal to the pixel circuit of the connected sub-pixel to provide a data signal to the first node; a reset driving circuit connected to the sub-pixel and configured to provide a reset control signal to the pixel circuit of the connected sub-pixel to reset the second node; and a light-emitting driving circuit connected to the sub-pixel and configured to provide a light-emitting control signal to the pixel circuit of the connected sub-pixel to provide a driving current to the light-emitting element; The light-emitting drive circuit is located on the side of the display area, the scan drive circuit is located on the side of the light-emitting drive circuit close to the display area, and the anode voltage drive circuit and the reset drive circuit are respectively located between the light-emitting drive circuit and the scan drive circuit and between the scan drive circuit and the display area; The scan driving circuit includes: M cascaded scan shift registers, wherein the i-th stage scan shift register is connected to the i-th row scan signal line; The reset driving circuit includes: M cascaded reset shift registers, and the i-th stage reset shift register is connected to the i-th row reset signal line.

9. The display panel according to claim 8, wherein: The light-emitting driving circuit includes: M cascaded first light-emitting shift registers, and the display area further includes: M rows of light-emitting signal lines; The light emitting signal line in the i-th row is connected to the i-th stage first light emitting shift register and is connected to the light emitting signal terminals of all sub-pixels in the i-th row.

10. The display panel according to claim 8, wherein: The light-emitting driving circuit includes: K light-emitting driving sub-circuits arranged along a row direction; When K=2, the K light-emitting driving sub-circuits are respectively: a first light-emitting driving sub-circuit and a second light-emitting driving sub-circuit; the first light-emitting driving sub-circuit includes: M cascaded first light-emitting shift registers, and the second light-emitting driving sub-circuit includes: M cascaded second light-emitting shift registers; the display area also includes: 2M rows of light-emitting signal lines; The 2i-1th row of light-emitting signal lines is connected to the first light-emitting shift register of the i-th stage, and is also connected to the light-emitting signal terminals of the pixel circuits of the first color sub-pixels and the second color sub-pixels located in the i-th row; The 2i-th row light-emitting signal line is connected to the second light-emitting shift register of the i-th stage, and is connected to the light-emitting signal terminal of the pixel circuit of the third color sub-pixel located in the i-th row; The light-emitting control signal output by the first light-emitting shift register of the i-th stage and the light-emitting control signal output by the second light-emitting shift register of the i-th stage have different first duty ratios, wherein the first duty ratio is a ratio of a duration during which the light-emitting control signal is a valid level signal to a first time, and the first time is a sum of a duration during which the light-emitting control signal is a invalid level signal and a duration during which the light-emitting control signal is a valid level signal; When K=3, the K light-emitting driving sub-circuits are respectively: a first light-emitting driving sub-circuit, a second light-emitting driving sub-circuit, and a third light-emitting driving sub-circuit; the first light-emitting driving sub-circuit includes: M cascaded first light-emitting shift registers, the second light-emitting driving sub-circuit includes: M cascaded second light-emitting shift registers, and the third light-emitting driving sub-circuit includes: M cascaded third light-emitting shift registers; the display area also includes: 3M rows of light-emitting signal lines; The 3i-2th row of light-emitting signal lines is connected to the first light-emitting shift register of the i-th stage, and is also connected to the light-emitting signal terminal of the pixel circuit of the first color sub-pixel located in the i-th row; The 3i-1th row of light-emitting signal lines is connected to the second light-emitting shift register of the i-th stage, and is also connected to the light-emitting signal terminals of the pixel circuits of the second color sub-pixels located in the i-th row; The 3i-th row light-emitting signal line is connected to the third light-emitting shift register of the i-th stage, and is connected to the light-emitting signal terminal of the pixel circuit of the third color sub-pixel located in the i-th row; The first duty ratios of the light control signal output by the i-th first light emitting shift register, the light control signal output by the i-th second light emitting shift register, and the light control signal output by the i-th third light emitting shift register are different.

11. The display panel according to claim 10, wherein: The sum of the first duty cycle and the second duty cycle is less than 1; The first duty cycle is 30% to 99%.

12. The display panel according to claim 5 or 6, wherein: The voltage value of the signal provided by the anode voltage signal line is -0.1 volt to -10 volt, and the voltage value of the signal provided by the anode voltage signal line is less than the reverse breakdown voltage of the light emitting element.

13. The display panel according to claim 1, wherein: For the pixel circuit of each sub-pixel, when the signal at the light-emitting signal end is a valid level signal, the signal at the anode voltage control end is an invalid level signal; when the signal at the anode voltage control end is a valid level signal, the signal at the light-emitting signal end is an invalid level signal; the duration that the signal at the light-emitting signal end is an invalid level signal is greater than the duration that the signal at the anode voltage control end is a valid level signal.

14. The display panel according to claim 1, wherein: The working process of the pixel circuit includes: a light-emitting stage and a non-light-emitting stage; when the signal at the light-emitting signal end is a valid level signal, the pixel circuit is in the light-emitting stage, and when the signal at the light-emitting signal end is an invalid level signal, the pixel circuit is in the non-light-emitting stage; When the driving mode of the sub-pixel is the second driving mode or the third driving mode, the non-light-emitting stage includes: a first non-light-emitting sub-stage and multiple second non-light-emitting sub-stages; the light-emitting stage includes: multiple light-emitting sub-stages, the first non-light-emitting sub-stage occurs before the light-emitting stage, and the second non-light-emitting sub-stage occurs between adjacent light-emitting sub-stages; the light-emitting sub-stage is divided into L first time periods, and the second non-light-emitting sub-stage is divided into L second time periods; the signal of the anode voltage control terminal in the second non-light-emitting sub-stage is a valid level signal; For the mth luminous sub-phase and the mth second non-luminous sub-phase, the sth second time period occurs between the sth first time period and the s+1th first time period, the tth first time period occurs between the t-1th second time period and the s+1th second time period, 1 m Q, 1 s L, 1 t L, Q are the number of luminescent sub-stages.

15. The display panel according to claim 9 or 10, wherein: The anode voltage driven shift register includes: M1 bias transistors and M2 bias capacitors, and the anode voltage driven shift register includes: a first anode voltage driven shift register, a second anode voltage driven shift register or a third anode voltage driven shift register; The light emitting shift register includes: M3 light emitting transistors and M4 light emitting capacitors, and the light emitting shift register includes: a first light emitting shift register, a second light emitting shift register or a third light emitting shift register; Each scan shift register includes: M5 scan transistors and M6 scan capacitors; each reset shift register includes: M5 reset transistors and M6 reset capacitors; the connection method between the M5 scan transistors and the M6 scan capacitors is the same as the connection method between the M5 reset transistors and the M6 reset capacitors, wherein M3 is not equal to M5, and M4 is not equal to M6; M1 and M2 satisfy: M1=M5, M2=M6 or M1=M3, M2=M4; When M1=M5 and M2=M6, the connection mode between the M1 bias transistors and the M2 bias capacitors is the same as the connection mode between the M5 scan transistors and the M6 scan capacitors; When M1=M3 and M2=M4, the connection mode between the M1 bias transistors and the M2 bias capacitors is the same as the connection mode between the M3 light-emitting transistors and the M4 light-emitting capacitors.

16. The display panel according to claim 15, wherein: For each sub-pixel, when M1=M3 and M2=M4, the difference between the duration when the signal at the light-emitting signal end is an invalid level signal and the duration when the signal at the anode voltage control end is a valid level signal is less than the threshold time difference, and the duration when the signal at the anode voltage control end is a valid level signal is greater than the duration when the signal at the scanning signal end is a valid level signal.

17. The display panel according to claim 15, wherein: For each sub-pixel, when M1=M5 and M2=M6, the difference between the duration of the signal at the light-emitting signal end being an invalid level signal and the duration of the signal at the anode voltage control end being a valid level signal is greater than the threshold time difference, and the duration of the signal at the anode voltage control end being a valid level signal is equal to the duration of the signal at the scanning signal end being a valid level signal.

18. The display panel according to claim 8, wherein: The non-display area further includes: a timing controller, and the image displayed by the display panel includes N frames; The timing controller is configured to provide a driving signal to the driving circuit so that the same sub-pixel can switch between different driving modes in different frames; The driving circuit includes: an anode voltage driving circuit, a light emitting driving circuit, a scanning driving circuit and a reset driving circuit.

19. A display device comprising: The display panel according to any one of claims 1 to 18.

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