Display substrate, preparation method thereof and display device

Abstract

The present disclosure provides a display substrate, a manufacturing method thereof and a display device. The display substrate comprises a display area, the display area comprises at least one pinning area; in a plane perpendicular to the display substrate, the pinning area comprises a planar layer arranged on a substrate, a partition layer arranged on a side of the planar layer away from the substrate, and an encapsulation structure layer arranged on a side of the partition layer away from the substrate; a pinning structure is arranged on the planar layer and the partition layer, and the encapsulation structure layer covers the pinning structure.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, the field of display technology, and particularly to a display substrate, a method for preparing the same, and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. With the continuous development of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and controlled by thin-film transistors (TFTs) have become the mainstream products in the display field. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0004] On one hand, this disclosure provides a display substrate including a display area, the display area including at least one pinning region; in a plane perpendicular to the display substrate, the pinning region includes a planarization layer disposed on a substrate, a partition layer disposed on the side of the planarization layer away from the substrate, and an encapsulation structure layer disposed on the side of the partition layer away from the substrate; pinning structures are disposed on the planarization layer and the partition layer, and the encapsulation structure layer covers the pinning structures.

[0005] In an exemplary embodiment, a partition groove is provided on the flat layer, and a partition hole is provided on the partition layer. The partition groove and the partition hole are connected. The partition layer located around the partition hole has a protrusion relative to the sidewall of the partition groove. The protrusion and the sidewall of the partition groove form an indented structure. The encapsulation structure layer covers the protrusion and the sidewall and bottom of the partition groove.

[0006] In an exemplary embodiment, the pinning area further includes a pixel definition layer disposed on the side of the partition layer away from the substrate, the pixel definition layer covering the edge of the partition layer away from the partition hole, the pixel definition layer having a partition opening that exposes the partition hole and the partition groove, and the encapsulation structure layer covering the partition opening.

[0007] In an exemplary embodiment, the pinning area further includes: an organic light-emitting layer disposed on the side of the partition layer away from the substrate and a cathode disposed on the side of the organic light-emitting layer away from the substrate, and an organic light-emitting block disposed at the bottom of the partition groove and a cathode block disposed on the side of the organic light-emitting block away from the substrate. The organic light-emitting layer and the organic light-emitting block are isolated from each other, and the cathode and the cathode block are isolated from each other. The encapsulation structure layer covers the cathode on the partition layer and the cathode block at the bottom of the partition groove.

[0008] In an exemplary embodiment, the encapsulation structure layer includes a first encapsulation layer of inorganic material, a second encapsulation layer of organic material, and a third encapsulation layer of inorganic material. The first encapsulation layer covers the protrusion and the sidewall and bottom of the partition groove. The second encapsulation layer is disposed on the side of the first encapsulation layer away from the substrate and fills the partition groove. The third encapsulation layer is disposed on the side of the second encapsulation layer away from the substrate.

[0009] In an exemplary embodiment, the planarization layer includes a first planarization layer, the partition layer is disposed on the side of the first planarization layer away from the substrate, and the partition groove is disposed on the first planarization layer.

[0010] In an exemplary embodiment, the planarization layer includes a first planarization layer and a second planarization layer disposed on the side of the first planarization layer away from the substrate, the partition layer is disposed on the side of the second planarization layer away from the substrate, and the partition groove is disposed on the second planarization layer.

[0011] In an exemplary embodiment, the display area includes a plurality of pixel units, and the pinning area is disposed between adjacent pixel units.

[0012] In an exemplary embodiment, at least one pixel unit includes a plurality of sub-pixels arranged sequentially along a first direction, and the pinning area is disposed between adjacent pixel units in a second direction, wherein the first direction intersects the second direction.

[0013] In an exemplary embodiment, at least one pixel unit includes a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel, and the pinning area is disposed at any one or more of the following locations: one side of the first sub-pixel in the second direction, one side of the second sub-pixel in the second direction, one side of the third sub-pixel in the second direction, and one side of the fourth sub-pixel in the second direction.

[0014] In an exemplary embodiment, the shape of the partition groove on a plane parallel to the display substrate includes any one or more of the following: square, rectangle, pentagon, hexagon, circle, ellipse, zigzag, arc, "T" shape, "L" shape, and "H" shape.

[0015] In an exemplary embodiment, the display substrate further includes a border region located on at least one side of the display area. The border region includes an isolation dam region and a crack dam region sequentially disposed along a direction away from the display area. In a plane perpendicular to the substrate, the isolation dam region includes a composite insulating layer disposed on the substrate, a power line disposed on the side of the composite insulating layer away from the substrate, a first connection electrode disposed on the side of the power line away from the substrate, a second connection electrode disposed on the side of the first connection electrode away from the substrate, and a first isolation dam and a second isolation dam disposed on the side of the second connection electrode away from the substrate. The second isolation dam is disposed on the side of the first isolation dam away from the display area. The crack dam region includes a composite insulating layer disposed on the substrate and a crack dam disposed on the side of the composite insulating layer away from the substrate. The composite insulating layer has multiple cracks, and the crack dam fills the multiple cracks.

[0016] In an exemplary embodiment, the edge of the power line away from the display area, the edge of the first connection electrode away from the display area, and the edge of the second connection electrode away from the display area are covered by the first isolation dam and / or the second isolation dam, and do not contact the encapsulation structure layer.

[0017] In an exemplary embodiment, the edge of the power line on the side away from the display area is covered by the crack dam, or by the first dam base in the second isolation dam, or by the second dam base in the second isolation dam, or by the first connecting electrode.

[0018] In an exemplary embodiment, the edge of the first connecting electrode on the side away from the display area is covered by the crack dam, or by the second dam base in the second isolation dam, or by the second connecting electrode.

[0019] In an exemplary embodiment, the edge of the second connection electrode on the side away from the display area is covered by the third dam base in the second isolation dam, or by the first isolation dam.

[0020] In an exemplary embodiment, the second isolation dam includes a first dam base, a second dam base, and a third dam base. The power line, the first connecting electrode, and the second connecting electrode are located in the isolation dam area. The first dam base is disposed on the side of the composite insulation layer away from the substrate and covers the edge of the power line away from the display area. The first connecting electrode is disposed on the side of the power line away from the substrate. The second dam base is disposed on the side of the power line away from the substrate and covers the edge of the first connecting electrode away from the display area. The orthographic projection of the second dam base on the substrate does not overlap with the orthographic projection of the first dam base on the substrate. The side of the second connecting electrode near the display area is erected on the side of the first connecting electrode away from the substrate, and the side of the second connecting electrode away from the display area is erected on the side of the second dam base away from the substrate. The third dam base is disposed on the side of the first and second dam bases away from the substrate and covers the edge of the second connecting electrode away from the display area.

[0021] In an exemplary embodiment, the second isolation dam includes a second dam base and a third dam base. The power line is located in the isolation dam area and the crack dam area. The first connecting electrode and the second connecting electrode are located in the isolation dam area. The crack dam covers the edge of the power line away from the display area. The first connecting electrode is disposed on the side of the power line away from the substrate. The second dam base is disposed on the side of the power line away from the substrate and covers the edge of the first connecting electrode away from the display area. The side of the second connecting electrode near the display area is erected on the side of the first connecting electrode away from the substrate, and the side of the second connecting electrode away from the display area is erected on the side of the second dam base away from the substrate. The third dam base is disposed on the side of the second dam base away from the substrate and covers the edge of the second connecting electrode away from the display area.

[0022] In an exemplary embodiment, the second isolation dam includes a third dam base, the power line and the first connecting electrode are located in the isolation dam area and the crack dam area, and the second connecting electrode is located in the isolation dam area; the crack dam covers the edge of the power line and the first connecting electrode away from the display area; the second connecting electrode is erected on the side of the first connecting electrode away from the substrate, and the third dam base is disposed on the side of the first connecting electrode away from the substrate and covers the edge of the second connecting electrode away from the display area.

[0023] In an exemplary embodiment, the second isolation dam includes at least a first dam base and a second dam base, with the power line, the first connecting electrode, and the second connecting electrode located in the isolation dam area; the first dam base is disposed on the side of the composite insulation layer away from the substrate and covers the edge of the power line away from the display area; the side of the first connecting electrode near the display area is attached to the side of the power line away from the substrate, and the side of the first connecting electrode away from the display area is attached to the side of the first dam base away from the substrate; the second dam base is disposed on the side of the first dam base away from the substrate and covers the edge of the first connecting electrode away from the display area; the second connecting electrode is attached to the side of the first connecting electrode away from the substrate, and the first isolation dam is disposed on the side of the first connecting electrode away from the substrate, covering the edge of the second connecting electrode away from the display area.

[0024] In an exemplary embodiment, the second isolation dam includes a second dam base and a third dam base, with the power line, the first connecting electrode, and the second connecting electrode located in the isolation dam area; the side of the first connecting electrode near the display area is disposed on the side of the power line away from the substrate, and the side of the first connecting electrode away from the display area is disposed on the side of the composite insulation layer away from the substrate, with the first connecting electrode covering the edge of the power line away from the display area; the second dam base is disposed on the side of the composite insulation layer away from the substrate and covers the edge of the first connecting electrode away from the display area; the side of the second connecting electrode near the display area is disposed on the side of the first connecting electrode away from the substrate, and the side of the second connecting electrode away from the display area is disposed on the side of the second dam base away from the substrate; the third dam base is disposed on the side of the second dam base away from the substrate and covers the edge of the second connecting electrode away from the display area.

[0025] In an exemplary embodiment, the orthographic projection of the edge of the power line on the side away from the display area onto the substrate lies within the range of the orthographic projection of the first isolation dam onto the substrate.

[0026] In an exemplary embodiment, the second isolation dam includes a first dam base and a third dam base, with the power line, the first connecting electrode, and the second connecting electrode located in the isolation dam area; the first connecting electrode is disposed on the side of the power line away from the substrate; the first dam base is disposed on the side of the composite insulation layer away from the substrate and covers the edge of the power line away from the display area; the first side of the second connecting electrode near the display area is disposed on the side of the first connecting electrode away from the substrate, the second side of the second connecting electrode away from the display area is disposed on the side of the first dam base away from the substrate, the area between the first side and the second side is disposed on the side of the power line away from the substrate, and the second connecting electrode covers the edge of the first connecting electrode away from the display area; the third dam base is disposed on the side of the first dam base away from the substrate and covers the edge of the second connecting electrode away from the display area.

[0027] In an exemplary embodiment, the orthographic projection of the edge of the first connecting electrode on the side away from the display area onto the substrate is within the range of the orthographic projection of the first isolation dam onto the substrate.

[0028] In an exemplary embodiment, the first dam foundation of the second isolation dam is disposed on the same layer as the first flat layer, the second dam foundation of the second isolation dam is disposed on the same layer as the second flat layer, the third dam foundation of the second isolation dam is disposed on the same layer as the pixel definition layer, and the first isolation dam is disposed on the same layer as the pixel definition layer.

[0029] On the other hand, this disclosure also provides a display device including the aforementioned display substrate.

[0030] In another aspect, this disclosure also provides a method for fabricating a display substrate, wherein the display substrate includes a display area, the display area including at least one pinned region; the fabrication method includes:

[0031] A planarization layer and a partition layer disposed on the planarization layer are sequentially formed on the substrate, and a stapling structure is disposed on the planarization layer and the partition layer;

[0032] An encapsulation structure layer is formed, which covers the pinning structure.

[0033] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0034] The accompanying drawings are provided to further illustrate the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure. The shapes and sizes of the components in the drawings do not reflect actual proportions and are only intended to illustrate the content of this disclosure.

[0035] Figure 1 This is a schematic diagram of the structure of a display device;

[0036] Figure 2 This is a schematic diagram of the structure of a display substrate;

[0037] Figure 3 This is a schematic diagram of the bonding area and the frame area in a display substrate;

[0038] Figure 4 This is a schematic cross-sectional view of a display area in a display substrate.

[0039] Figure 5 This is a schematic diagram of an equivalent circuit for a pixel driving circuit.

[0040] Figure 6 This is a timing diagram of a pixel driving circuit.

[0041] Figure 7 This is a schematic diagram of a planar structure of a display area, which is an exemplary embodiment of the present disclosure.

[0042] Figure 8 This is a schematic diagram of the planar structure of another display area as an exemplary embodiment of the present disclosure;

[0043] Figure 9a This is a schematic cross-sectional view of a display area as an exemplary embodiment of the present disclosure;

[0044] Figure 9b This is a schematic cross-sectional view of a border region as an exemplary embodiment of the present disclosure;

[0045] Figure 10a and Figure 10b A schematic diagram showing the formation of the driving structure layer pattern according to an exemplary embodiment of this disclosure;

[0046] Figure 11a and Figure 11b A schematic diagram of the formation of the first planarization layer pattern according to an exemplary embodiment of this disclosure;

[0047] Figure 12a and Figure 12b This is a schematic diagram showing the formation of the fourth conductive layer pattern according to an exemplary embodiment of the present disclosure;

[0048] Figure 13a and Figure 13b A schematic diagram of the second planarization layer pattern after forming an exemplary embodiment of this disclosure;

[0049] Figure 14a and Figure 14b This is a schematic diagram showing the formation of the stapled structure pattern according to an exemplary embodiment of the present disclosure;

[0050] Figure 15a and Figure 15b A schematic diagram showing the anode pattern formed according to an exemplary embodiment of this disclosure;

[0051] Figure 16a and Figure 16b A schematic diagram showing the pixel definition layer pattern formed according to an exemplary embodiment of this disclosure;

[0052] Figure 17a and Figure 17b This is a schematic diagram showing the formation of an organic light-emitting layer pattern according to an exemplary embodiment of the present disclosure;

[0053] Figure 18a and Figure 18b A schematic diagram showing the cathode pattern formed according to an exemplary embodiment of this disclosure;

[0054] Figure 19a and Figure 19b A schematic diagram showing the formation of the first encapsulation layer pattern according to an exemplary embodiment of this disclosure;

[0055] Figure 20a and Figure 20b A schematic diagram showing the formation of the second encapsulation layer pattern according to an exemplary embodiment of this disclosure;

[0056] Figure 21a and Figure 21b A schematic diagram showing the formation of the third encapsulation layer pattern according to an exemplary embodiment of this disclosure;

[0057] Figure 22 This is a schematic diagram of the structure of another display substrate as an exemplary embodiment of the present disclosure;

[0058] Figure 23 This is a schematic diagram of the structure of an isolation dam area on a display substrate;

[0059] Figure 24 This is a schematic diagram of the structure of an isolation dam area, which is an exemplary embodiment of the present disclosure.

[0060] Figure 25 This is a schematic diagram of another isolation dam area as an exemplary embodiment of the present disclosure;

[0061] Figure 26 This is a schematic diagram of the structure of another isolation dam area, as an exemplary embodiment of this disclosure;

[0062] Figure 27 This is a schematic diagram of the structure of another isolation dam area, as an exemplary embodiment of this disclosure;

[0063] Figure 28 This is a schematic diagram of the structure of another isolation dam area, as an exemplary embodiment of this disclosure;

[0064] Figure 29This is a schematic diagram of the structure of another isolation dam area, which is an exemplary embodiment of this disclosure.

[0065] Explanation of reference numerals in the attached figures:

[0066] 1—Glass carrier plate; 10—Substrate; 11—First insulating layer;

[0067] 13—Second insulating layer; 13—Third insulating layer; 14—Fourth insulating layer;

[0068] 15—First planarization layer; 16—Second planarization layer; 21—Anode;

[0069] 22—Pixel definition layer; 23—Organic light-emitting layer; 23-1—Organic light-emitting block;

[0070] 24—Cathode; 24-1—Cathode block; 25—September column;

[0071] 31—First encapsulation layer; 32—Second encapsulation layer; 33—Third encapsulation layer;

[0072] 50—Power supply line; 51—First connecting electrode; 52—Second connecting electrode;

[0073] 60—Partition layer; 61—Partition hole; 62—Partition groove;

[0074] 100—Display area; 101—First transistor; 102—First storage capacitor;

[0075] 103—Signal lead; 104—Anode connection electrode; 110—Pixel area;

[0076] 120—Pinning region; 200—Bonding region; 201—Second transistor;

[0077] 202—Second storage capacitor; 211—First fan-out region; 212—Bending region;

[0078] 213—Second Fan-Out Area; 214—Anti-static Area; 215—Driver Chip Area;

[0079] 216—Pin bonding area; 300—Border area; 301—Circuit area;

[0080] 302—Isolation dam area; 303—Fissure dam area; 400—Fissure dam;

[0081] 401—First dam foundation; 402—Second dam foundation; 403—Third dam foundation;

[0082] 410—First isolation dam; 420—Second isolation dam; 501—Driving structure layer;

[0083] 502—Light-emitting structural layer; 503—Encapsulation structural layer. Detailed Implementation

[0084] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of some known functions and components have been omitted. The accompanying drawings of the embodiments of this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to with reference to general designs.

[0085] The scale of the figures in this disclosure can be used as a reference in actual manufacturing processes, but is not limited thereto. For example, the aspect ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures. The figures described in this disclosure are only schematic diagrams of the structure, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0086] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0087] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0088] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0089] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0090] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" may sometimes be interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged.

[0091] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0092] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0093] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0094] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfers, curved edges, and other variations.

[0095] In this disclosure, “about” means a value that is not strictly limited and allows for process and measurement errors.

[0096] Figure 1 This is a schematic diagram of the structure of a display device. Figure 1 As shown, the display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is connected to the data driver, the scan driver, and the light-emitting driver. The data driver is connected to multiple data signal lines (D1 to Dn), the scan driver is connected to multiple scan signal lines (S1 to Sm), and the light-emitting driver is connected to multiple light-emitting signal lines (E1 to Eo). The pixel array may include multiple sub-pixels Pxij, where i and j can be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting device connected to the circuit unit. The circuit unit may include at least one scan signal line, at least one data signal line, at least one light-emitting signal line, and a pixel driving circuit. In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals of specifications suitable for the data driver to the data driver, provide clock signals, scan start signals, etc. of specifications suitable for the scan driver to the scan driver, and provide clock signals, emission stop signals, etc. of specifications suitable for the light-emitting driver to the light-emitting driver. The data driver can use grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to data signal lines D1, D2, D3, ..., Dn. For example, the data driver can sample grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to data signal lines D1 to Dn in pixel rows, where n can be a natural number. The scan driver can generate scan signals to be provided to scan signal lines S1, S2, S3, ..., Sm by receiving clock signals, scan start signals, etc., from the timing controller. For example, the scan driver can sequentially provide scan signals with on-level pulses to scan signal lines S1 to Sm. For example, the scan driver can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals in the form of on-level pulses to the next stage circuit under the control of a clock signal, where m can be a natural number. The light-emitting driver can generate transmit signals to be provided to light-emitting signal lines E1, E2, E3, ..., Eo by receiving clock signals, transmit stop signals, etc., from the timing controller. For example, an LED driver can sequentially provide transmit signals with cutoff level pulses to LED signal lines E1 to Eo. For example, the LED driver can be configured as a shift register and can generate transmit signals by sequentially transmitting transmit stop signals in the form of cutoff level pulses to the next stage circuit under the control of a clock signal, where o can be a natural number.

[0097] Figure 2 This is a schematic diagram of the structure of a display substrate. (Example) Figure 2 As shown, the display substrate may include a display area 100 and a non-display area surrounding the display area 100. The non-display area may include a bonding area 200 on one side of the display area 100 and a border area 300 on the other sides of the display area 100. In an exemplary embodiment, the display area 100 may include a plurality of sub-pixels arranged in a matrix. The sub-pixels may include pixel driving circuits and light-emitting devices. The bonding area 200 may include at least an isolation dam and a bonding circuit that connects the signal lines of the plurality of sub-pixels to an external driving device. The border area 300 may include at least an isolation dam, a gate driver on array (GOA) circuit, and power lines that transmit voltage signals to the plurality of sub-pixels. The bonding area 200 and the isolation dam of the border area 300 form a ring structure surrounding the display area 100.

[0098] Figure 3 This is a schematic diagram of the bonding area and the frame area in a display substrate. Figure 3 As shown, in an exemplary embodiment, in a plane parallel to the display substrate, the bonding area 200 may be located on one side of the display area 100. The bonding area 200 may include a first fan-out area 211, a bending area 212, a second fan-out area 213, an anti-static area 214, a driver chip area 215, and a bonding pin area 216 arranged sequentially along a direction away from the display area 100. The first fan-out area 211 may include at least multiple data connection lines, multiple touch leads, a first power line, and a second power line. The multiple data connection lines are configured to connect to the data lines of the display area 100 in a fan-out routing manner. The multiple touch leads are configured to connect to the touch electrodes of the display area 100. The first power line is configured to connect to the high-voltage power line (VDD) of the display area 100, and the second power line is configured to connect to the low-voltage power line (VSS) of the bezel area 300. The bending area 212 may include a composite insulating layer with grooves, configured to bend the bonding area 200 to the back of the display area 100. The second fan-out area 213 may include multiple data connection lines led out in a fan-out routing manner. The anti-static area 214 may include anti-static circuitry, configured to prevent electrostatic damage to the display substrate by eliminating static electricity. The driver chip area 215 may include an integrated circuit (IC), configured to connect to the multiple data connection lines. The bonding pin area 216 may include multiple bonding pads, configured to bond to an external flexible printed circuit (FPC).

[0099] In an exemplary embodiment, at least a portion of the first isolation dam 410 and the second isolation dam 420 may be disposed in the first fan-out area 211. The first isolation dam 410 and the second isolation dam 420 may extend along a direction parallel to the edge of the display area. The distance between the first isolation dam 410 and the edge of the display area is less than the distance between the second isolation dam 420 and the edge 110 of the display area. They are configured to block the organic layer in the encapsulation layer to prevent the organic layer from flowing to the bending area.

[0100] In an exemplary embodiment, within a plane parallel to the display substrate, the bezel region 300 may include a circuit region, an isolation dam region, and a crack dam region sequentially arranged along a direction away from the display region 100. The circuit region may include at least a gate driving circuit, which is connected to the first scan line and the second scan line of the pixel driving circuit in the display region 100. The isolation dam region may include at least a second power line, a first isolation dam 410, and a second isolation dam 420. The second power line extends along a direction parallel to the edge of the display region and is connected to the second power line VSS of the pixel driving circuit in the display region 100. The first isolation dam 410 and the second isolation dam 420 extend along a direction parallel to the edge of the display region. The first isolation dam 410 and the second isolation dam 420 of the bezel region 300 are integrally formed with the first isolation dam 410 and the second isolation dam 420 of the bonding region 200, and are synchronously fabricated using the same patterning process to form a ring structure surrounding the display region 100. The crack dam area includes multiple cracks set on the composite insulation layer. The multiple cracks are configured to reduce the stress on the display area 100 and the circuit area during the cutting process, and to cut the cracks so as to propagate them in the direction of the display area 100 and the circuit area, thereby avoiding affecting the film structure of the display area 100 and the circuit area.

[0101] Figure 4 This is a cross-sectional structural diagram of a display area in a display substrate, illustrating the structure of four sub-pixels in the display area. Figure 4 As shown, on a plane perpendicular to the display substrate, each sub-pixel in the display area may include a driving structure layer 501 disposed on the substrate 10, a light-emitting structure layer 502 disposed on the side of the driving structure layer 501 away from the substrate, and an encapsulation structure layer 503 disposed on the side of the light-emitting structure layer 502 away from the substrate.

[0102] In an exemplary embodiment, the driving structure layer 501 of each sub-pixel may include a pixel driving circuit composed of multiple transistors and a storage capacitor. In an exemplary embodiment, the driving structure layer 501 may include: a first insulating layer disposed on a substrate, a semiconductor layer disposed on the first insulating layer, a second insulating layer covering the semiconductor layer, a first conductive layer disposed on the second insulating layer, a third insulating layer covering the first conductive layer, a second conductive layer disposed on the third insulating layer, a fourth insulating layer covering the second conductive layer, a third conductive layer disposed on the fourth insulating layer, and a planarization layer covering the third conductive layer. The semiconductor layer may include at least multiple transistors, the first conductive layer may include at least the gate electrodes of multiple transistors and the first electrode of the storage capacitor, the second conductive layer may include at least the second electrode of the storage capacitor, and the third conductive layer may include at least the first and second electrodes of multiple transistors.

[0103] In an exemplary embodiment, the light-emitting structure layer 502 of each sub-pixel may include a light-emitting device composed of multiple film layers. These multiple film layers may include an anode 21, a pixel definition layer 22, an organic light-emitting layer 23, and a cathode 24. The anode 21 is connected to the pixel driving circuit, the organic light-emitting layer 23 is connected to the anode 21, and the cathode 24 is connected to the organic light-emitting layer 23. The organic light-emitting layer 23 emits light of a corresponding color under the drive of the anode 21 and the cathode 24. The encapsulation structure layer 503 may include a first encapsulation layer 31, a second encapsulation layer 32, and a third encapsulation layer 33 stacked together. The first encapsulation layer 31 and the third encapsulation layer 33 may be made of inorganic materials, while the second encapsulation layer 32 may be made of organic materials. The second encapsulation layer 32 is disposed between the first encapsulation layer 31 and the third encapsulation layer 33 to prevent external moisture from entering the light-emitting structure layer 502.

[0104] In an exemplary embodiment, the display area may further include a touch structure layer, which may include: a first conductive layer disposed on a third encapsulation layer, a touch insulating layer covering the first conductive layer, a second conductive layer disposed on the touch insulating layer, and a touch protective layer covering the second conductive layer.

[0105] In an exemplary embodiment, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, or 7T1C structure. Figure 5 This is a schematic diagram of an equivalent circuit for a pixel driving circuit. (Example) Figure 5 As shown, the pixel driving circuit may include 7 transistors (first transistor T1 to seventh transistor T7), 1 storage capacitor C, and 7 signal lines (data signal line D, first scan signal line S1, second scan signal line S2, light emission signal line E, initial signal line INIT, first power supply line VDD, and second power supply line VSS).

[0106] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, and a third node N3. The first node N1 is connected to the first terminal of the third transistor T3, the second terminal of the fourth transistor T4, and the second terminal of the fifth transistor T5, respectively. The second node N2 is connected to the second terminal of the first transistor, the first terminal of the second transistor T2, the control terminal of the third transistor T3, and the second terminal of the storage capacitor C, respectively. The third node N3 is connected to the second terminal of the second transistor T2, the second terminal of the third transistor T3, and the first terminal of the sixth transistor T6, respectively.

[0107] In an exemplary embodiment, the first end of the storage capacitor C is connected to the first power line VDD, and the second end of the storage capacitor C is connected to the second node N2, that is, the second end of the storage capacitor C is connected to the control electrode of the third transistor T3.

[0108] The control electrode of the first transistor T1 is connected to the second scan signal line S2, the first electrode of the first transistor T1 is connected to the initial signal line INIT, and the second electrode of the first transistor is connected to the second node N2. When the on-level scan signal is applied to the second scan signal line S2, the first transistor T1 transmits the initialization voltage to the control electrode of the third transistor T3 to initialize the charge of the control electrode of the third transistor T3.

[0109] The control electrode of the second transistor T2 is connected to the first scan signal line S1, the first electrode of the second transistor T2 is connected to the second node N2, and the second electrode of the second transistor T2 is connected to the third node N3. When a conduction-level scan signal is applied to the first scan signal line S1, the second transistor T2 connects the control electrode of the third transistor T3 to its second electrode.

[0110] The control electrode of the third transistor T3 is connected to the second node N2, meaning the control electrode of the third transistor T3 is connected to the second terminal of the storage capacitor C. The first electrode of the third transistor T3 is connected to the first node N1, and the second electrode of the third transistor T3 is connected to the third node N3. The third transistor T3 can be called the driving transistor. The amount of driving current flowing between the first power line VDD and the second power line VSS is determined by the potential difference between its control electrode and its first electrode.

[0111] The control electrode of the fourth transistor T4 is connected to the first scan signal line S1, the first electrode of the fourth transistor T4 is connected to the data signal line D, and the second electrode of the fourth transistor T4 is connected to the first node N1. The fourth transistor T4 can be called a switching transistor, scanning transistor, etc. When a conduction-level scan signal is applied to the first scan signal line S1, the fourth transistor T4 causes the data voltage of the data signal line D to be input to the pixel driving circuit.

[0112] The control electrode of the fifth transistor T5 is connected to the light-emitting signal line E, the first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the first node N1. The control electrode of the sixth transistor T6 is connected to the light-emitting signal line E, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light-emitting device. The fifth transistor T5 and the sixth transistor T6 can be referred to as light-emitting transistors. When a conduction-level light-emitting signal is applied to the light-emitting signal line E, the fifth transistor T5 and the sixth transistor T6 cause the light-emitting device to emit light by forming a driving current path between the first power supply line VDD and the second power supply line VSS.

[0113] The control electrode of the seventh transistor T7 is connected to the first scan signal line S1, the first electrode of the seventh transistor T7 is connected to the initial signal line INIT, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light-emitting device. When a conduction level scan signal is applied to the first scan signal line S1, the seventh transistor T7 transmits an initialization voltage to the first electrode of the light-emitting device to initialize or release the accumulated charge in the first electrode of the light-emitting device.

[0114] In an exemplary embodiment, the second electrode of the light-emitting device is connected to the second power line VSS, where the signal of the second power line VSS is a low-level signal, and the signal of the first power line VDD is a continuously high-level signal. The first scan signal line S1 is the scan signal line in the pixel driving circuit of this display row, and the second scan signal line S2 is the scan signal line in the pixel driving circuit of the previous display row. That is, for the nth display row, the first scan signal line S1 is S(n), and the second scan signal line S2 is S(n-1). The second scan signal line S2 of this display row and the first scan signal line S1 in the pixel driving circuit of the previous display row are the same signal line, which can reduce the signal lines of the display panel and realize a narrow bezel of the display panel.

[0115] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 can be either P-type transistors or N-type transistors. Using the same type of transistor in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield. In some possible implementations, the first transistor T1 to the seventh transistor T7 may include both P-type and N-type transistors.

[0116] In an exemplary embodiment, the first scan signal line S1, the second scan signal line S2, the light emission signal line E, and the initial signal line INIT extend in the horizontal direction, while the second power supply line VSS, the first power supply line VDD, and the data signal line D extend in the vertical direction.

[0117] In an exemplary embodiment, the light-emitting device may be an organic light-emitting diode (OLED), including a first electrode (anode), an organic light-emitting layer, and a second electrode (cathode) stacked together.

[0118] Figure 6 This is a timing diagram of a pixel driving circuit. The following is a breakdown of the circuit's operation. Figure 5 The operation of the example pixel driving circuit illustrates an exemplary embodiment of this disclosure. Figure 5 The pixel driving circuit includes 7 transistors (first transistor T1 to sixth transistor T7), 1 storage capacitor C, and 7 signal lines (data signal line D, first scan signal line S1, second scan signal line S2, light emission signal line E, initial signal line INIT, first power supply line VDD and second power supply line VSS). All 7 transistors are P-type transistors.

[0119] In an exemplary embodiment, the operation of the pixel driving circuit may include:

[0120] In the first stage A1, also known as the reset stage, the signal on the second scan signal line S2 is low, while the signals on the first scan signal line S1 and the light-emitting signal line E are high. The low signal on the second scan signal line S2 turns on the first transistor T1, and the initial signal line INIT is supplied to the second node N2 to initialize the storage capacitor C, clearing the original data voltage in the capacitor. The high signals on the first scan signal line S1 and the light-emitting signal line E turn off the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7; during this stage, the OLED does not emit light.

[0121] The second stage, A2, is called the data writing stage or threshold compensation stage. During this stage, the signal on the first scan signal line S1 is low, while the signals on the second scan signal line S2 and the light-emitting signal line E are high. The data signal line D outputs a data voltage. Because the second terminal of the storage capacitor C is low, the third transistor T3 is turned on. The low signal on the first scan signal line S1 turns on the second transistor T2, the fourth transistor T4, and the seventh transistor T7. The turn-on of the second transistor T2 and the fourth transistor T4 allows the data voltage output from the data signal line D to be supplied to the second node N2 via the first node N1, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2. The difference between the data voltage output from the data signal line D and the threshold voltage of the third transistor T3 is charged into the storage capacitor C. The voltage at the second terminal of the storage capacitor C (second node N2) is Vd - |Vth|, where Vd is the data voltage output from the data signal line D, and Vth is the threshold voltage of the third transistor T3. The seventh transistor T7 is turned on, providing the initial voltage of the initial signal line INIT to the first electrode of the OLED, initializing (resetting) the first electrode of the OLED, clearing its internal pre-stored voltage, completing the initialization, and ensuring that the OLED does not emit light. The signal of the second scan signal line S2 is a high-level signal, causing the first transistor T1 to turn off. The signal of the light emission signal line E is a high-level signal, causing the fifth transistor T5 and the sixth transistor T6 to turn off.

[0122] The third stage, A3, is called the light-emitting stage. During this stage, the light-emitting signal line E is at a low level, while the first scan signal line S1 and the second scan signal line S2 are at a high level. The low level of the light-emitting signal line E turns on the fifth transistor T5 and the sixth transistor T6. The power supply voltage output from the first power line VDD then provides a driving voltage to the first electrode of the OLED through the turned-on fifth transistor T5, third transistor T3, and sixth transistor T6, driving the OLED to emit light.

[0123] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and its first electrode. Since the voltage at the second node N2 is Vdata - |Vth|, the driving current of the third transistor T3 is:

[0124] I = K * (Vgs - Vth) 2 =K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*[(Vdd-Vd)] 2

[0125] Where I is the driving current flowing through the third transistor T3, which is the driving current driving the OLED, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vd is the data voltage output by the data signal line D, and Vdd is the power supply voltage output by the first power supply line VDD.

[0126] Currently, flexible OLED display devices, represented by foldable screens, have gradually entered the consumer market, but existing structures still suffer from insufficient lifespan due to encapsulation failure.

[0127] Studies have shown that a significant reason for the failure of existing encapsulation structures is the weak adhesion of the organic light-emitting layer (OLED) prepared using vapor deposition. During repeated bending and prolonged shear stress, peeling occurs between the film layers, creating voids. When cracks appear in the encapsulation layer, external water and oxygen can enter the voids and diffuse along the channels formed, eventually reaching the light-emitting structural layer and causing encapsulation failure. Since the adhesion of the OLED prepared using vapor deposition is determined by its physical properties, it is not easily improved significantly by modifying the process. Therefore, improving the adhesion between the OLED and other film layers, especially its resistance to shear stress, has become a crucial research topic.

[0128] An exemplary embodiment of this disclosure provides a display substrate including a display area, the display area including at least one pinning region; in a plane perpendicular to the display substrate, the pinning region includes a planarization layer disposed on a substrate, a partition layer disposed on the side of the planarization layer away from the substrate, and an encapsulation structure layer disposed on the side of the partition layer away from the substrate; pinning structures are disposed on the planarization layer and the partition layer, and the encapsulation structure layer covers the pinning structures.

[0129] In an exemplary embodiment, the pinning structure may include a partition groove disposed on the second flat layer and a partition hole disposed on the partition layer, wherein the partition hole and the partition groove are interconnected.

[0130] In an exemplary embodiment, the partition layer is provided with a partition hole, the flat layer is provided with a partition groove, the partition groove and the partition hole are connected, the partition layer located around the partition hole has a protrusion relative to the side wall of the partition groove, the protrusion and the side wall of the partition groove form an indented structure, and the encapsulation structure layer covers the protrusion as well as the side wall and bottom of the partition groove.

[0131] Figure 7 This is a schematic diagram of a planar structure of a display area as an exemplary embodiment of the present disclosure. Figure 7As shown, in an exemplary embodiment, the display area of ​​the display substrate may include a plurality of regularly arranged pixel units P. At least one pixel unit P may include a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and two third sub-pixels P3 and a fourth sub-pixel P4 emitting a third color light. Each of the four sub-pixels may include a circuit unit and a light-emitting device. The circuit unit may include a scan signal line, a data signal line, a light-emitting signal line, and a pixel driving circuit. The pixel driving circuit is connected to the scan signal line, the data signal line, and the light-emitting signal line, respectively. The pixel driving circuit is configured to receive the data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting signal line, and output a corresponding current to the light-emitting device. The light-emitting device in each sub-pixel is connected to the pixel driving circuit of the sub-pixel, and the light-emitting device is configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel.

[0132] In an exemplary embodiment, a plurality of pixel units arranged sequentially in the first direction X can be referred to as a pixel row, and a plurality of pixel units arranged sequentially in the vertical direction Y in the second direction can be referred to as a pixel column. The plurality of pixel rows and the plurality of pixel columns constitute a pixel array arranged in an array, and the first direction X and the second direction Y intersect.

[0133] In an exemplary embodiment, the first sub-pixel P1 can be a red sub-pixel (R) emitting red light, the second sub-pixel P2 can be a blue sub-pixel (B) emitting blue light, and the third sub-pixel P3 and the fourth sub-pixel P4 can be green sub-pixels (G) emitting green light. In an exemplary embodiment, the shape of the sub-pixels can be rectangular, rhomboid, pentagonal, or hexagonal, etc. In one exemplary embodiment, the four sub-pixels can be pentagonal and hexagonal respectively, arranged side-by-side, with the two pentagonal G sub-pixels located in the center of the pixel unit, and the hexagonal R sub-pixels and hexagonal B sub-pixels located on either side of the G sub-pixels in the first direction X. In another exemplary embodiment, the four sub-pixels can be arranged in a square, diamond, horizontally side-by-side, or vertically side-by-side manner, etc., and this disclosure does not limit the arrangement.

[0134] In an exemplary embodiment, the display area may include a plurality of spacer pillars 25, which may be respectively disposed between adjacent sub-pixels. The spacer pillars may be disposed at any one or more of the following locations: one side of the first sub-pixel P1 in the first direction X, one side of the second sub-pixel P2 in the first direction X, one side of the third sub-pixel P3 in the first direction X, and one side of the fourth sub-pixel P4 in the first direction X. For example, in the first direction X, the plurality of spacer pillars 25 may be respectively disposed between adjacent R sub-pixels and B sub-pixels, between R sub-pixels and G sub-pixels, and between B sub-pixels and G sub-pixels. In an exemplary embodiment, the spacer pillars 25 are configured to support a fine metal mask (FMM) in the vapor deposition process.

[0135] In an exemplary embodiment, the display area may include a plurality of pinning areas 120, which may be disposed between adjacent pixel units P. The pinning areas 120 are configured to cooperate with the encapsulation layer to form pinning points, thereby improving the film layer's ability to resist shear stress and preventing the film layer from peeling off.

[0136] In an exemplary embodiment, at least one pixel unit may include a plurality of sub-pixels arranged sequentially along a first direction X, and the pinning area may be arranged between adjacent pixel units P in a second direction Y.

[0137] In an exemplary embodiment, multiple pinning regions 120 can form multiple pinning rows, and each pinning row can include multiple pinning regions 120. The multiple pinning regions 120 can be arranged sequentially along a horizontal direction. The first pinning row can be located between the first pixel row and the second pixel row, and the second pinning row can be located between the second pixel row and the third pixel row; or, the first pinning row can be located between the second pixel row and the third pixel row, and the second pinning row can be located between the fifth pixel row and the sixth pixel row, etc., and this disclosure does not limit the scope of the invention.

[0138] In an exemplary embodiment, at least one pinning area 120 may be disposed at any one or more of the following locations: one side of the second direction Y of the first sub-pixel P1 (R sub-pixel), one side of the second direction Y of the second sub-pixel P2 (B sub-pixel), one side of the second direction Y of the third sub-pixel P3 (G sub-pixel), and one side of the second direction Y of the fourth sub-pixel P4 (G sub-pixel), without limitation herein.

[0139] In an exemplary embodiment, for a display area without spacers, at least one pinning area 120 may be located at any one or more of the following positions: one side of the first sub-pixel P1 in the first direction X, one side of the second sub-pixel P2 in the first direction X, one side of the third sub-pixel P3 in the first direction X, and one side of the fourth sub-pixel P4 in the first direction X. This disclosure does not limit the scope of the application.

[0140] In an exemplary embodiment, the shape of at least one pinning area 120 on a plane parallel to the display substrate may include any one or more of the following: square, rectangle, pentagon, hexagon, circle, ellipse, polygonal, arc, "T" shape, "L" shape, and "H" shape, which are not limited herein.

[0141] Figure 8 This is a schematic diagram of a planar structure of another display area as an exemplary embodiment of this disclosure. Figure 8 As shown, the structure of pixel unit P and spacer post 25 in the display area, and the layout relationship between pixel unit P, spacer post 25 and pinning area 120 can be compared with... Figure 7 The same as shown, except that the shape of the pinning area 120 is a broken line structure.

[0142] In an exemplary embodiment, the first sub-pixel P1 (R sub-pixel) and the second sub-pixel P2 (B sub-pixel) can be hexagonal. The length of the first sub-pixel P1 in the pixel column direction can be greater than the length of the second sub-pixel P2 in the pixel column direction, and the width of the first sub-pixel P1 in the pixel row direction can be less than the length of the second sub-pixel P2 in the pixel row direction. The pinning region 120 of the polyline structure can include a first sub-region 121 and a second sub-region 122. The ends of the first sub-region 121 and the second sub-region 122 that are close to each other are connected to form a polyline structure with a first included angle θ1.

[0143] In an exemplary embodiment, the pinning area 120 of the broken line structure can be set on one side of the pixel column direction of the second sub-pixel P2, and the two sides of the second sub-pixel P2 near the pinning area 120 can form a second included angle θ2. The first included angle θ1 of the pinning area 120 can be equal to the second included angle θ2 of the second sub-pixel P2.

[0144] In an exemplary embodiment, the pinning area 120 of the zigzag structure may include a plurality of sub-areas connected in sequence. The plurality of sub-areas extend in different directions to form a zigzag structure with multiple bends. The zigzag structure is snake-shaped and has multiple included angles. This disclosure does not limit the scope of the invention.

[0145] In an exemplary embodiment, the pinning area 120 with its zigzag structure can improve the stability of the pinning point.

[0146] Figure 9a This is a schematic cross-sectional view of a display area, representing an exemplary embodiment of the present disclosure. Figure 7A cross-sectional view along direction AA. In a plane parallel to the display substrate, the display area may include a pixel area 110 and a pinning area 120. In a plane perpendicular to the display substrate, the pixel area 110 may include a driving structure layer 501 disposed on the substrate 10, a light-emitting structure layer 502 disposed on the side of the driving structure layer 501 away from the substrate, and an encapsulation structure layer 503 disposed on the side of the light-emitting structure layer 502 away from the substrate. In an exemplary embodiment, the pixel area 110 may include a touch structure layer disposed on the side of the encapsulation structure layer away from the substrate; this disclosure is not limited thereto.

[0147] In an exemplary embodiment, in a plane perpendicular to the display substrate, the pinning area 120 may include a composite insulating layer disposed on the substrate 10, a first planarization layer 15 disposed on the side of the composite insulating layer away from the substrate, a second planarization layer 16 disposed on the side of the first planarization layer 15 away from the substrate, a partition layer 60 disposed on the side of the second planarization layer 16 away from the substrate 10, and an encapsulation structure layer 503 disposed on the side of the partition layer 60 away from the substrate.

[0148] In an exemplary embodiment, the composite insulating layer may include a first insulating layer 11, a second insulating layer 12, a third insulating layer 13, and a fourth insulating layer 14 stacked on the substrate 10.

[0149] In an exemplary embodiment, a partition hole is provided on the partition layer 60, and a partition groove is provided on the second flat layer 16. The partition groove and the partition hole are connected. The partition layer 60 located around the partition hole has a protrusion relative to the side wall of the partition groove. The protrusion and the side wall of the partition groove form an indented structure. The first encapsulation layer 31 in the encapsulation structure layer 503 covers the protrusion and the side wall and bottom of the partition groove.

[0150] In an exemplary embodiment, the pinning area 120 may further include a pixel definition layer 22 disposed on the side of the partition layer 60 away from the substrate. The pixel definition layer 22 covers the edge of the partition layer 60 away from the partition hole. The pixel definition layer 22 is provided with a partition opening that exposes the partition hole and the partition groove. The first encapsulation layer 31 in the encapsulation structure layer 503 covers the partition opening.

[0151] In an exemplary embodiment, the pinning area 120 may further include an organic light-emitting layer 23 disposed on the side of the partition layer 60 away from the substrate and a cathode 24 disposed on the side of the organic light-emitting layer 23 away from the substrate, as well as an organic light-emitting block 23-1 disposed at the bottom of the partition groove and a cathode block 24-1 disposed on the side of the organic light-emitting block 23-1 away from the substrate. The organic light-emitting layer 23 and the organic light-emitting block 23-1 are isolated from each other, and the cathode 24 and the cathode block 24-1 are isolated from each other. The first encapsulation layer 31 in the encapsulation structure layer 503 covers the cathode 24 and the organic light-emitting layer 23 on the partition layer 60 and the cathode block 24-1 and the organic light-emitting block 23-1 at the bottom of the partition groove.

[0152] In an exemplary embodiment, the encapsulation structure layer 503 may include a first encapsulation layer 31 of inorganic material, a second encapsulation layer 32 of organic material, and a third encapsulation layer 33 of inorganic material. The first encapsulation layer 31 covers the protrusion and the sidewalls and bottom of the partition groove. The second encapsulation layer 32 is disposed on the side of the first encapsulation layer 31 away from the substrate and fills the partition groove. The third encapsulation layer 33 is disposed on the side of the second encapsulation layer 32 away from the substrate.

[0153] Figure 9b This is a cross-sectional structural diagram of a bezel region according to an exemplary embodiment of the present disclosure. In a plane parallel to the display substrate, the bezel region may include a circuit region 301, an isolation dam region 302, and a crack dam region 303 arranged sequentially along a direction away from the display area. In an exemplary embodiment, the circuit region 301 and the isolation dam region 302 may not overlap, or they may partially overlap; this disclosure does not limit the scope of the invention.

[0154] In an exemplary embodiment, in a plane perpendicular to the display substrate, the isolation dam area 302 may include a composite insulating layer disposed on the substrate 10, a power line 50 disposed on the side of the composite insulating layer away from the substrate, a first connection electrode 51 disposed on the side of the power line 50 away from the substrate, a second connection electrode 52 disposed on the side of the first connection electrode 51 away from the substrate, and a first isolation dam 410 and a second isolation dam 420 disposed on the side of the second connection electrode 52 away from the substrate, wherein the second isolation dam 420 is disposed on the side of the first isolation dam 410 away from the display area.

[0155] In an exemplary embodiment, the second isolation dam 420 may include a first dam base 401, a second dam base 402, and a third dam base 403, with at least a portion of the power line 50, the first connecting electrode 51, and the second connecting electrode 52 located in the isolation dam area 302. The first dam base 401 is disposed on the side of the composite insulating layer away from the substrate and covers the edge of the power line 50 away from the display area. The orthographic projection of the edge of the power line 50 away from the display area onto the substrate is within the range of the orthographic projection of the first dam base 401 onto the substrate. The first connecting electrode 51 is disposed on the side of the power line 50 away from the substrate, and the orthographic projection of the first connecting electrode 51 onto the substrate does not overlap with the orthographic projection of the first dam base 401 onto the substrate.

[0156] In an exemplary embodiment, the edge of the power line 50 away from the display area, the edge of the first connection electrode 51 away from the display area, and the edge of the second connection electrode 52 away from the display area can be covered by the first isolation dam 410 and / or the second isolation dam 420, so as not to contact the encapsulation structure layer.

[0157] In an exemplary embodiment, the edge of the power line 50 on the side away from the display area can be covered by the crack dam 400, or by the first dam base 401 in the second isolation dam 420, or by the second dam base 402 in the second isolation dam 420, or by the first connecting electrode 51.

[0158] In an exemplary embodiment, the edge of the first connecting electrode 51 on the side away from the display area is covered by the crack dam 400, or it can be covered by the second dam base 402 in the second isolation dam 420, or it can be covered by the second connecting electrode 52.

[0159] In an exemplary embodiment, the edge of the second connection electrode 52 on the side away from the display area is covered by the third dam base 403 in the second isolation dam 420, or it can be covered by the first isolation dam 410.

[0160] In an exemplary embodiment, the second dam base 402 is disposed on the side of the power line 50 away from the substrate and covers the edge of the first connecting electrode 51 away from the display area. The orthographic projection of the edge of the first connecting electrode 51 away from the display area on the substrate is within the range of the orthographic projection of the second dam base 402 on the substrate. The orthographic projection of the second dam base 402 on the substrate does not overlap with the orthographic projection of the first dam base 401 on the substrate.

[0161] In an exemplary embodiment, the side of the second connecting electrode 52 closest to the display area is attached to the side of the first connecting electrode 51 furthest from the substrate, and the side of the second connecting electrode 52 furthest from the display area is attached to the side of the second dam base 402 furthest from the substrate. The orthographic projection of the edge of the second connecting electrode 52 furthest from the display area onto the substrate is within the range of the orthographic projection of the second dam base 402 onto the substrate.

[0162] In an exemplary embodiment, the third dam base 403 is disposed on the side of the first dam base 401 and the second dam base 402 away from the substrate, and covers the edge of the second connecting electrode 52 away from the display area. The orthographic projection of the edge of the second connecting electrode 52 away from the display area on the substrate is within the range of the orthographic projection of the third dam base 403 on the substrate. The orthographic projection of the third dam base 403 on the substrate at least partially overlaps with the orthographic projection of the first dam base 401 on the substrate, and the orthographic projection of the third dam base 403 on the substrate at least partially overlaps with the orthographic projection of the second dam base 402 on the substrate.

[0163] The following description uses the fabrication process of a display substrate as an example. The "patterning process" described in this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes processes such as organic material coating, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching. This disclosure does not limit the methods used. A "thin film" refers to a thin film made of a certain material on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0164] In an exemplary embodiment, in a plane direction parallel to the display substrate, the display substrate may include a display area 100 and a border area 300 located on at least one side of the display area 100. The display area 100 may include a pixel area 110 and a pinning area 120, and the border area 300 may include a circuit area 301, an isolation dam area 302, and a crack dam area 303. In an exemplary embodiment, the fabrication of a display substrate according to an exemplary embodiment of this disclosure may include the following steps.

[0165] (1) Preparing a substrate on a glass carrier plate. In an exemplary embodiment, the substrate may include a first flexible material layer, a first inorganic material layer, a second flexible material layer, and a second inorganic material layer stacked on the glass carrier plate. The materials of the first flexible material layer and the second flexible material layer may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer film, etc. The materials of the first inorganic material layer and the second inorganic material layer may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the substrate's resistance to water and oxygen. The first inorganic material layer and the second inorganic material layer may be referred to as a barrier layer or a buffer layer. In an exemplary embodiment, taking the stacked structure PI1 / Barrier1 / PI2 / Barrier2 as an example, its preparation process may include: firstly, coating a layer of polyimide on a glass substrate 1, curing it into a film to form a first flexible (PI1) layer; then depositing a barrier film on the first flexible layer to form a first barrier (Barrier1) layer covering the first flexible layer; then coating another layer of polyimide on the first barrier layer, curing it into a film to form a second flexible (PI2) layer; then depositing a barrier film on the second flexible layer to form a second barrier (Barrier2) layer covering the second flexible layer, thus completing the substrate preparation. In an exemplary embodiment, an amorphous silicon (a-Si) layer may be disposed between the first barrier layer and the second inorganic material layer. The substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked on the glass substrate. In an exemplary embodiment, during the formation of the first barrier layer, inorganic holes may be formed on the first barrier layer through a patterning process, and the positions of the inorganic holes may correspond to the positions of the subsequently formed through-holes. After this process, the display area, circuit area 301, isolation dam area 302, and crack dam area 303 all include the substrate.

[0166] (2) Patterns are fabricated on the substrate 10 for a driving structure layer of the display area, a circuit structure layer of the circuit area, an isolation structure layer of the isolation dam area, and a crack structure layer of the crack dam area. In an exemplary embodiment, the driving structure layer of the display area may include a first transistor 101 and a first storage capacitor 102 constituting a pixel driving circuit; the circuit structure layer of the circuit area 301 may include a second transistor 201 and a second storage capacitor 202 constituting a gate driving circuit; the isolation structure layer of the isolation dam area 302 may include a composite insulating layer disposed on the substrate and a power line 50 disposed on the composite insulating layer; and the crack structure layer of the crack dam area 303 may include a composite insulating layer having multiple cracks. In an exemplary embodiment, the composite insulating layer may include multiple stacked inorganic insulating layers.

[0167] In an exemplary embodiment, the process of preparing the driving structure layer of the display area, the circuit structure layer of the circuit area, the isolation structure layer of the isolation dam area, and the crack structure layer of the crack dam area may include:

[0168] A first insulating film and a semiconductor film are sequentially deposited on a substrate 10. The semiconductor film is patterned using a patterning process to form a first insulating layer 11 on the substrate 10, and a semiconductor layer pattern disposed on the first insulating layer 11. The semiconductor layer pattern includes at least a first active layer located in the display area and a second active layer located in the circuit area 301. After this process, the semiconductor films in the isolation dam region 302 and the crack dam region 303 are etched away. The isolation dam region 302 and the crack dam region 303 include the substrate 10 disposed on the glass carrier plate 1 and the first insulating layer 11 disposed on the substrate 10.

[0169] Subsequently, a second insulating film and a first conductive film are deposited sequentially. The first conductive film is patterned using a patterning process to form a second insulating layer 12 covering the semiconductor layer pattern, and a first conductive layer pattern disposed on the second insulating layer 12. The first conductive layer pattern includes at least a first gate electrode and a first capacitor electrode located in the display area, and a second gate electrode and a second capacitor electrode located in the circuit area 301. After this process, the first conductive film in the isolation dam region 302 and the crack dam region 303 is etched away. The isolation dam region 302 and the crack dam region 303 include a substrate 10, and a first insulating layer 11 and a second insulating layer 12 stacked on the substrate 10.

[0170] Subsequently, a third insulating film and a second conductive film are deposited sequentially. The second conductive film is patterned using a patterning process to form a third insulating layer 13 covering the pattern of the first conductive layer, and a second conductive layer pattern disposed on the third insulating layer 13. The second conductive layer pattern includes at least a third capacitor electrode located in the display area and a fourth capacitor electrode located in the circuit area 301. The position of the third capacitor electrode corresponds to the position of the first capacitor electrode, and the position of the fourth capacitor electrode corresponds to the position of the second capacitor electrode. After this process, the second conductive film of the isolation dam area 302 and the crack dam area 303 is etched away. The isolation dam area 302 and the crack dam area 303 include a substrate 10, and a first insulating layer 11, a second insulating layer 12, and a third insulating layer 13 stacked on the substrate 10.

[0171] Subsequently, a fourth insulating film is deposited and patterned using a patterning process to form a fourth insulating layer 14 covering the pattern of the second conductive layer. Multiple vias and through-holes are formed on the fourth insulating layer 14. The multiple vias may include a first active via located in the display area and a second active via located in the circuit area 301. The fourth insulating layer 14, the third insulating layer 13, and the second insulating layer 12 within the first and second active vias are etched away. The first active via exposes the source and drain regions at both ends of the first active layer, and the second active via exposes the source and drain regions at both ends of the second active layer. After this process, the isolation dam region 302 and the crack dam region 303 include a substrate 10 and a composite insulating layer disposed on the substrate 10. The composite insulating layer includes a first insulating layer 11, a second insulating layer 12, a third insulating layer 13, and a fourth insulating layer 14 stacked together.

[0172] Subsequently, a third conductive film is deposited and patterned using a patterning process to form a third conductive layer pattern on the fourth insulating layer 14. The third conductive layer pattern includes at least: a first source electrode, a first drain electrode, and a signal lead 103 located in the display area; and a second source electrode, a second drain electrode, and a power line 50 located in the bezel area. The first source electrode and the first drain electrode can be located in the pixel area 110 of the display area and are respectively connected to the first active layer through first active vias. The signal lead 103 can be located in the pinning area 120 of the display area. The second source electrode and the second drain electrode can be located in the circuit area 301 of the bezel area and are respectively connected to the second active layer through second active vias. The power line 50 can be located in the isolation dam area 302 of the bezel area, and the edge of the power line 50 closest to the display area can be located in the circuit area 301.

[0173] Subsequently, a crack pattern is formed in the crack dam region 303. In an exemplary embodiment, forming the crack pattern may include: forming a plurality of cracks 41 in the crack dam region 303 using a patterning process, wherein the fourth insulating layer 14, the third insulating layer 13, and the second insulating layer 12 in the plurality of cracks 41 are etched away, exposing the surface of the first insulating layer 11, such as... Figure 10a and Figure 10b As shown, Figure 10a The diagram illustrates the cross-sectional structure of the pixel area 110 and the pinning area 120 in the display area. Figure 7 Sectional view along the AA direction. Figure 10b The diagram illustrates the cross-sectional structure of the circuit area 301, the isolation dam area 302, and the crack dam area 303 within the border area.

[0174] In an exemplary embodiment, the formation of the crack pattern can be performed simultaneously with the process of forming the bend pattern in the bonding region.

[0175] At this point, the patterns of the driving structure layer, circuit structure layer, isolation structure layer, and crack structure layer are complete. In an exemplary embodiment, the first active layer, the first gate electrode, the first source electrode, and the first drain electrode constitute the first transistor 101 of the pixel driving circuit; the second active layer, the second gate electrode, the second source electrode, and the second drain electrode constitute the second transistor 201 of the gate driving circuit; the first capacitor electrode and the third capacitor electrode constitute the first storage capacitor 102 of the pixel driving circuit; and the second capacitor electrode and the fourth capacitor electrode constitute the second storage capacitor 202 of the gate driving circuit. In an exemplary embodiment, the first transistor 101 can be a driving transistor in the pixel driving circuit, and the second transistor 201 can be a switching transistor in the gate driving circuit.

[0176] In an exemplary embodiment, the first, second, third, and fourth insulating layers can be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be single-layer, multi-layer, or composite layers. The first insulating layer can be called a buffer layer, the second and third insulating layers can be called (GI) layers, and the fourth insulating layer can be called an interlayer insulating (ILD) layer. The first, second, and third conductive films can be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and can be single-layer structures or multi-layer composite structures, such as Ti / Al / Ti, etc. The active layer thin film can be made of various materials such as amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), hexathiophene, and polythiophene. In other words, this disclosure is applicable to transistors manufactured based on oxide technology, silicon technology, and organic technology.

[0177] (3) Forming the first planarization layer, the first dam foundation, and the cracked dam pattern. In an exemplary embodiment, forming the first planarization layer, the first dam foundation, and the cracked dam pattern may include: coating a first planarization film onto a substrate on which the aforementioned pattern is formed, and patterning the first planarization film using a patterning process to form the first planarization layer 15, the first dam foundation 401, and the cracked dam 400 pattern, such as... Figure 11a and Figure 11b As shown.

[0178] In an exemplary embodiment, the first flattening layer 15 may be located in the circuit area 301 of the display area and the border area, the first dam base 401 may be located in the isolation dam area 302 of the border area, and the crack dam 400 may be located in the crack dam area 303 of the border area.

[0179] In an exemplary embodiment, in the pixel area 110 of the display area, a first planarization layer 15 may cover the first source electrode and the first drain electrode. A first via K1 is provided on the first planarization layer 15. The first planarization layer 15 inside the first via K1 is removed to expose the surface of the first drain electrode. The first via K1 is configured to allow the subsequently formed anode connection electrode to be connected to the first drain electrode of the first transistor 101 through the via.

[0180] In an exemplary embodiment, in the pinning area 120 of the display area, the first flat layer 15 may cover the signal lead 103.

[0181] In an exemplary embodiment, in the circuit area 301 of the border area, the first planarization layer 15 may cover the second source electrode and the second drain electrode, and cover the edge of the power line 50 near the display area.

[0182] In an exemplary embodiment, in the isolation dam area 302 of the border area, the first dam base 401 may be located on the side of the power line 50 away from the display area. The first dam base 401 covers the edge of the power line 50 away from the display area, that is, the orthographic projection of the edge of the power line 50 away from the display area on the substrate is within the range of the orthographic projection of the first dam base 401 on the substrate. The first flat film in the area between the first dam base 401 and the circuit area 301 is removed, exposing the surface of the power line 50.

[0183] In an exemplary embodiment, the cross-sectional shape of the first dam foundation 401 may be trapezoidal in a plane perpendicular to the base.

[0184] In an exemplary embodiment, in the crack dam area 303 of the border region, a first flat film covers and fills a plurality of cracks 41 to form a crack dam 400. The first flat film in the area between the crack dam 400 and the first dam base 401 is removed, exposing the surface of the fourth insulating layer 14. That is, the crack dam 400 and the first dam base 401 are spaced apart, so that the subsequently formed first encapsulation layer directly contacts the fourth insulating layer 14 in this area, ensuring the encapsulation effect and process quality.

[0185] In an exemplary embodiment, the process may involve first forming a fifth insulating layer pattern of inorganic material, and then forming a first planarization layer pattern of organic material on the fifth insulating layer. This disclosure does not limit the scope of the invention.

[0186] In an exemplary embodiment, the first planarization layer may be made of an organic material, such as resin.

[0187] (4) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming a fourth conductive layer pattern may include: depositing a fourth conductive film on a substrate on which the aforementioned pattern is formed, patterning the fourth conductive film using a patterning process, and forming a fourth conductive layer pattern on the first planarization layer 15, such as... Figure 12a and Figure 12b As shown.

[0188] In an exemplary embodiment, the fourth conductive layer pattern includes at least: an anode connection electrode 104 located in the pixel area 110 of the display area and a first connection electrode 51 located in the isolation dam area 302 of the border area. The anode connection electrode 104 is connected to the first drain electrode through a first via K1, and at least a portion of the first connection electrode 51 is connected to the power line 50.

[0189] In an exemplary embodiment, the edge of the first connecting electrode 51 away from the display area can be located on the side of the first dam base 401 close to the display area and spaced a distance apart, and the orthographic projection of the first connecting electrode 51 on the substrate does not overlap with the orthographic projection of the first dam base 401 on the substrate.

[0190] In an exemplary embodiment, the edge of the first connecting electrode 51 near the display area can be mounted on the first planarization layer 15 of the circuit area 301, and the orthographic projection of the first connecting electrode 51 on the substrate at least partially overlaps with the orthographic projection of the first planarization layer 15 of the circuit area 301 on the substrate.

[0191] In an exemplary embodiment, the edge of the first connecting electrode 51 on the side away from the display area, relative to the edge of the power line 50 away from the display area, can be recessed toward the display area, so that the ends of the power line 50 and the first connecting electrode 51 form a stepped structure.

[0192] In some possible exemplary embodiments, corresponding signal lines and other structures may be provided on the first flat layer 15 of the pinning area 120, which is not limited herein.

[0193] (5) Forming a second planarization layer and a second dam foundation pattern. In an exemplary embodiment, forming the second planarization layer and the second dam foundation pattern may include: coating a second planarization film onto a substrate on which the aforementioned pattern is formed, and patterning the second planarization film using a patterning process to form the second planarization layer 16 and the second dam foundation 402 pattern, such as... Figure 13a and Figure 13b As shown.

[0194] In an exemplary embodiment, the second flattening layer 16 may be located in the circuit area 301 of the display area and the border area, and the second dam base 402 may be located in the isolation dam area 302 of the border area.

[0195] In an exemplary embodiment, in the pixel area 110 of the display area, a second planarization layer 16 may cover the anode connection electrode 104. A second via K2 is provided on the second planarization layer 16, and the second planarization layer 16 within the second via K2 is removed, exposing the surface of the anode connection electrode 104. The second via K2 is configured to allow a subsequently formed anode to be connected to the anode connection electrode 104 through the via. In the pinning area 120 of the display area, the second planarization layer 16 may be disposed on the first planarization layer 15. In the circuit area 301 of the border area, the second planarization layer 16 may be disposed on the first planarization layer 15, extending from the side away from the display area to the isolation dam area 302 and covering the edge of the first connection electrode 51 near the display area.

[0196] In an exemplary embodiment, in the isolation dam area 302 of the border area, the second dam base 402 can be located on the side of the first connecting electrode 51 away from the display area and spaced apart by a certain distance, that is, the second dam base 402 and the first dam base 401 are spaced apart, the orthographic projection of the second dam base 402 on the substrate does not overlap with the orthographic projection of the first dam base 401 on the substrate, and the area between the second dam base 402 and the first dam base 401 exposes the surface of the power line 50.

[0197] In an exemplary embodiment, the second dam base 402 covers the edge of the first connecting electrode 51 away from the display area, and the orthographic projection of the edge of the first connecting electrode 51 away from the display area on the substrate is within the range of the orthographic projection of the second dam base 402 on the substrate.

[0198] In an exemplary embodiment, since the edge of the power line 50 away from the display area is covered by the first dam base 401, and the edge of the first connecting electrode 51 away from the display area is covered by the second dam base 402, the edges of the power line and the first connecting electrode are covered by different dam bases, effectively preventing edge peeling failure. In an exemplary embodiment, since the edge of the first connecting electrode 51 near the display area is covered by the second planarization layer 16, edge peeling failure can also be effectively prevented.

[0199] In an exemplary embodiment, the cross-sectional shape of the second dam foundation 402 may be trapezoidal in a plane perpendicular to the base.

[0200] In an exemplary embodiment, the second planarization layer may be made of an organic material, such as resin.

[0201] In some possible exemplary embodiments, a second flat membrane may be provided on the fissure dam 400, which is not limited herein.

[0202] (6) Forming a pinning structure pattern. In an exemplary embodiment, forming a pinning structure pattern may include: depositing a barrier film on a substrate on which the aforementioned pattern is formed, patterning the barrier film using a patterning process, and forming a pinning structure pattern in the pinning area 120 of the display area. The pinning structure may include a barrier layer 60 disposed on a second planarization layer 16, the barrier layer 60 having a barrier hole 61, and the second planarization layer 16 in the area where the barrier layer 60 is located having a barrier groove 62, the barrier hole 61 and the barrier groove 62 being interconnected. Figure 14a and Figure 14b As shown.

[0203] In an exemplary embodiment, the process of forming the pinned structure pattern may include: depositing a barrier film on a substrate on which the aforementioned pattern is formed. Then, a layer of photoresist is coated onto the barrier film, and the photoresist is exposed using a mask. After development, fully exposed areas and unexposed areas are formed. The photoresist in the fully exposed areas is removed, while the photoresist in the unexposed areas is retained. Then, an etching process is used to etch the barrier film in the fully exposed areas, forming a barrier layer 60 disposed on a second planarization layer 16 and a barrier hole 61 located in the middle region of the barrier layer 60 in the pinned area 120 of the display area. The barrier hole 61 exposes the surface of the second planarization layer 16. Subsequently, the second planarization layer 16 exposed within the barrier hole 61 is further etched, forming a barrier groove 62 on the second planarization layer 16 in the region where the barrier layer 60 is located. The barrier hole 61 and the barrier groove 62 are interconnected.

[0204] In an exemplary embodiment, a dry etching process can be used for etching, employing a gas with a high organic / inorganic etching ratio, such as O2, CF4, or CHF3. Because the organic / inorganic etching ratio is high—that is, the etching rate of organic materials is greater than that of inorganic materials—lateral etching occurs in the partition groove 62 during the etching of the second planarization layer 16. The partition groove 62 extends outward relative to the partition hole 61 by a certain distance, forming a partition groove 62 with a lateral etching structure.

[0205] In an exemplary embodiment, the partition layer 60 located around the partition hole 61 has a protrusion relative to the sidewall of the partition groove 62. Relative to the protrusion, the sidewall of the partition groove 62 (the side closest to the partition hole 61) forms an indented structure. Relative to the sidewall of the partition groove 62, the protrusion forms an "eaves" structure. The partition layer 60, the partition hole 61, and the partition groove 62 constitute a stapling structure.

[0206] In an exemplary embodiment, the width of the partition layer 60 protruding from the edge of the opening on the partition groove 62 can be approximately 1 μm to 3 μm, that is, the partition groove 62 expands outward by 1 μm to 3 μm relative to the partition hole 61.

[0207] In an exemplary embodiment, the cross-sectional shape of the partition groove 62 in a plane perpendicular to the base can be an inverted trapezoidal shape, and the width of the upper opening of the partition groove 62 on the side away from the base is greater than the width of the lower opening of the partition groove 62 on the side closer to the base. In an exemplary embodiment, the side of the inverted trapezoidal partition groove 62 can be arc-shaped.

[0208] In an exemplary embodiment, the diameter of the partition hole 61 may be smaller than the diameter of the opening on the partition groove 62, and the orthographic projection of the opening of the partition hole 61 on the substrate may be within the range of the orthographic projection of the opening on the partition groove 62 on the substrate.

[0209] In an exemplary embodiment, the depth of the partition groove 62 may be less than or equal to the thickness of the second flat layer 16.

[0210] In exemplary embodiments, the partition layer may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, multiple layers, or a composite layer. In some possible exemplary embodiments, the partition layer may be made of a metallic material, which is not limited herein.

[0211] After this process, the structure of the pixel area 110 in the display area and the circuit area 310, isolation dam area 302 and crack dam area 303 in the border area can be the same as the structure after the previous process.

[0212] (7) Forming the anode and second connection electrode pattern. In an exemplary embodiment, forming the anode and second connection electrode pattern may include: depositing a conductive thin film on a substrate on which the aforementioned pattern is formed, and patterning the conductive thin film using a patterning process to form the anode 21 and second connection electrode 52 pattern, such as... Figure 15a and Figure 15b As shown.

[0213] In an exemplary embodiment, the anode 21 may be located on the second planarization layer 16 of the pixel area 110 in the display area, and the anode 21 is connected to the anode connection electrode 104 through the second via K2. Since the anode connection electrode 104 is connected to the first drain electrode of the first transistor 101 through the via, the anode 21 is connected to the first drain electrode of the first transistor 101 through the anode connection electrode 104.

[0214] In an exemplary embodiment, the second connecting electrode 52 may be located in the circuit area 301 and the isolation dam area 302 of the frame area. The side of the second connecting electrode 52 closest to the display area is located in the circuit area 301 and is mounted on the second planarization layer 16. The orthographic projection of the edge of the second connecting electrode 52 closest to the display area onto the substrate is within the range of the orthographic projection of the second planarization layer 16 onto the substrate. The side of the second connecting electrode 52 furthest from the display area is located in the isolation dam area 302 and covers a portion of the surface of the second dam base 402. The orthographic projection of the edge of the second connecting electrode 52 furthest from the display area onto the substrate is within the range of the orthographic projection of the second dam base 402 onto the substrate. The middle portion of the second connecting electrode 52 overlaps with the first connecting electrode 51, and the orthographic projection of the second connecting electrode 52 onto the substrate at least partially overlaps with the orthographic projection of the first connecting electrode 51 onto the substrate.

[0215] In an exemplary embodiment, the orthographic projection of the second connecting electrode 52 on the substrate does not overlap with the orthographic projection of the first dam foundation 401 on the substrate.

[0216] In an exemplary embodiment, the second connecting electrode 52 can completely cover the side surface of the second dam base 402 near the display area and partially cover the upper surface of the second dam base 402 away from the substrate. The second connecting electrode 52 is configured to connect with the subsequently formed cathode, thereby achieving a reliable connection between the cathode and the power line 50 through the second connecting electrode 52 and the first connecting electrode 51.

[0217] In an exemplary embodiment, the orthographic projection of the edge of the first connecting electrode 51 on the side away from the display area onto the substrate can be within the range of the orthographic projection of the second connecting electrode 52 on the substrate. That is, relative to the edge of the second connecting electrode 52 on the side away from the display area, the edge of the first connecting electrode 51 on the side away from the display area is recessed toward the display area.

[0218] Because the edge of the first connecting electrode 51 away from the display area is covered by the second dam base 402, and the second connecting electrode 52 covers part of the surface of the second dam base 402, the edge of the first connecting electrode 51 is sequentially covered by the second dam base 402 and the second connecting electrode 52. This multiple covering effectively prevents edge peeling failure of the first connecting electrode 51. Similarly, because the edge of the first connecting electrode 51 near the display area is covered by the second planarization layer 16, and the edge of the second planarization layer 16 away from the display area is covered by the second connecting electrode 52, this multiple covering effectively prevents edge peeling failure of the first connecting electrode 51.

[0219] In exemplary embodiments, the conductive thin film can be made of a metallic material or a transparent conductive material. The metallic material can include any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or alloys of the above metals. The transparent conductive material can include indium tin oxide (ITO) or indium zinc oxide (IZO). In exemplary embodiments, the conductive thin film can be a single-layer structure or a multi-layer composite structure, such as ITO / Al / ITO.

[0220] (8) Forming the pixel definition layer, the first isolation dam, and the third dam base pattern. In an exemplary embodiment, forming the pixel definition layer, the first isolation dam, and the second isolation dam pattern may include: coating a pixel definition film on a substrate on which the aforementioned pattern is formed, and patterning the pixel definition film using a patterning process to form the pixel definition layer 22, the first isolation dam 410, and the third dam base 403 pattern, such as... Figure 16a and Figure 16b As shown.

[0221] In an exemplary embodiment, a pixel definition layer 22 is formed in the circuit area 301 of the display area and the border area. The pixel definition layer 22 of the pixel area 100 has a first pixel opening K3, and the pixel definition layer 22 of the pinning area 120 has a second pixel opening K4. The pixel definition film in the first pixel opening K3 is removed to expose the surface of the anode 21, and the pixel definition film in the second pixel opening K4 is removed to expose the pinning structure. That is, the second pixel opening K4 exposes the partition hole 61, the partition groove 62, and the partition layer 60 around the partition hole 61.

[0222] In an exemplary embodiment, in the pinning area 120, the pixel definition layer 22 can cover the outer edge of the partition layer 60 away from the partition hole 61. The orthographic projection of the outer edge of the partition layer 60 away from the partition hole 61 on the substrate is within the range of the orthographic projection of the pixel definition layer 22 on the substrate, which can prevent the partition layer 60 from peeling off.

[0223] In an exemplary embodiment, a half-tone mask or gray-toned mask patterning process can be used to form a pattern of spacer pillars 25 when forming the pixel definition layer. The spacer pillars 25 can be disposed outside the pixel opening and are configured to support a fine metal mask in a subsequent vapor deposition process.

[0224] In an exemplary embodiment, the pixel definition layer 22 of the circuit region 301 covers the edge of the second connection electrode 52 near the display area, and the orthographic projection of the edge of the second connection electrode 52 near the display area on the substrate is within the range of the orthographic projection of the pixel definition layer 22 on the substrate.

[0225] In an exemplary embodiment, the first isolation dam 410 and the third dam foundation 403 may be located in the isolation dam area 302. The first isolation dam 410 may be located on the side of the second dam foundation 402 close to the display area, and the third dam foundation 403 may be located in the area where the first dam foundation 40 and the second dam foundation 402 are located.

[0226] In an exemplary embodiment, the first isolation dam 410 can be disposed on the second connecting electrode 52, and the orthographic projection of the first isolation dam 410 on the substrate is within the range of the orthographic projection of the second connecting electrode 52 on the substrate. Since this process uses a halftone or grayscale mask patterning process, the first isolation dam 410 can include a lower dam base and an upper dam base stacked together. The orthographic projection of the upper dam base on the substrate can be within the range of the orthographic projection of the lower dam base on the substrate, forming a stepped structure. In an exemplary embodiment, the cross-sectional shape of the upper dam base can be trapezoidal in a plane perpendicular to the substrate.

[0227] In an exemplary embodiment, the third dam foundation 403 may be disposed on the side of the first dam foundation 401 and the second dam foundation 402 away from the base, and fill the area between the first dam foundation 401 and the second dam foundation 402. The orthographic projection of the third dam foundation 403 on the base at least partially overlaps with the orthographic projections of the first dam foundation 401 and the second dam foundation 402 on the base.

[0228] In an exemplary embodiment, the third dam base 403 covers the edge of the second connecting electrode 52 away from the display area, meaning the orthographic projection of the edge of the second connecting electrode 52 away from the display area onto the substrate is within the range of the orthographic projection of the third dam base 403 onto the substrate. Since this process uses a halftone or grayscale mask patterning process, the third dam base 403 can include a lower dam base and an upper dam base stacked together. The orthographic projection of the upper dam base onto the substrate can be within the range of the orthographic projection of the lower dam base onto the substrate, forming a stepped structure. In an exemplary embodiment, the cross-sectional shape of the upper dam base can be trapezoidal in a plane perpendicular to the substrate.

[0229] In an exemplary embodiment, the orthographic projection of the edge of the power line 50 on the side away from the display area onto the substrate falls within the range of the orthographic projection of the third dam base 403 onto the substrate, and the orthographic projection of the edge of the first connecting electrode 51 on the side away from the display area onto the substrate also falls within the range of the orthographic projection of the third dam base 403 onto the substrate. Since the edge of the power line 50 is covered by the first dam base 401, the edge of the first connecting electrode 51 is covered by the second dam base 402, and the third dam base 403 covers both the first and second dam bases 401, a structure is formed that multiple layers cover the edges of the power line 50 and the first connecting electrode 51, effectively preventing peeling failure of the edges of the power line 50 and the first connecting electrode 51. Similarly, since the third dam base 403 covers the edge of the second connecting electrode 52 on the side away from the display area, and the pixel definition layer 22 of the circuit region 301 covers the edge of the second connecting electrode 52 on the side closer to the display area, peeling failure of the edge of the second connecting electrode 52 can be effectively prevented.

[0230] In an exemplary embodiment, the first dam base 40, the second dam base 402, and the third dam base 403 constitute the second isolation dam 420. The second isolation dam 420 is located on the side of the first isolation dam 410 away from the display area, and the orthographic projection of the first isolation dam 410 on the substrate does not overlap with the orthographic projection of the second isolation dam 420 on the substrate.

[0231] In an exemplary embodiment, the distance between the top surface of the second isolation dam 420 (the surface of the second isolation dam away from the substrate) and the substrate can be greater than the distance between the top surface of the first isolation dam 410 (the surface of the first isolation dam away from the substrate) and the substrate.

[0232] In an exemplary embodiment, the pixel definition layer may be made of polyimide, acrylic, or polyethylene terephthalate, etc. In a plane parallel to the display substrate, the shapes of the first pixel opening and the second pixel opening may be triangular, rectangular, polygonal, circular, or elliptical, etc. In a plane perpendicular to the display substrate, the cross-sectional shapes of the first pixel opening and the second pixel opening may be rectangular or trapezoidal, etc., and the cross-sectional shapes of the first isolation dam 410 and the second isolation dam 420 may be trapezoidal with a stepped structure.

[0233] (9) Forming an organic light-emitting layer and an organic light-emitting block pattern. In an exemplary embodiment, forming the organic light-emitting layer and the organic light-emitting block pattern may include: forming the organic light-emitting layer 23 and the organic light-emitting block 23-1 pattern on a substrate on which the aforementioned pattern is formed by vapor deposition or inkjet printing, such as... Figure 17a and Figure 17b As shown.

[0234] In an exemplary embodiment, the organic light-emitting layer 23 and the organic light-emitting block 23-1 can be formed in the display area, while no organic light-emitting layer is formed in the border area. The organic light-emitting layer 23 of the pixel area 100 is connected to the anode 21 through the first pixel opening K3, and the organic light-emitting layer 23 of the pinned area 120 is disposed on the pixel definition layer 22 and the partition layer 60. Since the partition groove 61 is a side-etched structure and the partition layer 60 has an "eaves" structure protruding from the opening of the partition groove 61, the organic light-emitting layer 23 of the pinned area 120 is broken at the "eaves" structure of the partition groove 61, and an organic light-emitting block 23-1 is formed at the bottom of the partition groove 61. The organic light-emitting block 23-1 is isolated from the organic light-emitting layer 23.

[0235] In an exemplary embodiment, the organic light-emitting layer may include an emissive layer (EML), and any one or more of the following: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, the organic light-emitting layer may be formed by vapor deposition using a fine metal mask (FMM).

[0236] In an exemplary embodiment, the organic light-emitting layer can be fabricated using the following method. First, a hole injection layer and a hole transport layer are sequentially deposited using an open mask to form a common layer of hole injection and hole transport layers on the display substrate. Then, an electron blocking layer and a red light-emitting layer are deposited on the red sub-pixel using a fine metal mask; an electron blocking layer and a green light-emitting layer are deposited on the green sub-pixel; and an electron blocking layer and a blue light-emitting layer are deposited on the blue sub-pixel. The electron blocking layers and light-emitting layers of adjacent sub-pixels may have a small amount of overlap (e.g., the overlapping portion occupies less than 10% of the area of ​​their respective light-emitting layer patterns), or they may be isolated. Subsequently, a hole blocking layer, an electron transport layer, and an electron injection layer are sequentially deposited using an open mask to form a common layer of hole blocking, electron transport, and electron injection layers on the display substrate.

[0237] In an exemplary embodiment, the electron blocking layer can serve as the microcavity conditioning layer of the light-emitting device. By designing the thickness of the electron blocking layer, the thickness of the organic light-emitting layer between the cathode and anode can be made to meet the design of the microcavity length. In some exemplary embodiments, the hole transport layer, hole blocking layer, or electron transport layer in the organic light-emitting layer can be used as the microcavity conditioning layer of the light-emitting device, and this disclosure does not limit this to any particular method.

[0238] In an exemplary embodiment, the light-emitting layer may include a host material and a guest material doped in the host material, with the doping ratio of the guest material ranging from 1% to 20%. Within this doping ratio range, on the one hand, the host material can effectively transfer exciton energy to the guest material to excite it to emit light; on the other hand, the host material "dilutes" the guest material, effectively improving fluorescence quenching caused by intermolecular collisions and energy-based collisions, thereby increasing luminous efficiency and device lifetime. In an exemplary embodiment, the doping ratio refers to the ratio of the mass of the guest material to the mass of the light-emitting layer, i.e., mass percentage. In an exemplary embodiment, the host material and the guest material can be deposited together using a multi-source evaporation process, ensuring uniform dispersion of both materials in the light-emitting layer. The doping ratio can be controlled by adjusting the evaporation rate of the guest material or by controlling the ratio of the evaporation rates of the host material and the guest material during the evaporation process. In an exemplary embodiment, the thickness of the light-emitting layer can be approximately 10 nm to 50 nm.

[0239] In an exemplary embodiment, the hole injection layer may be an inorganic oxide, such as molybdenum oxide, titanium oxide, vanadium oxide, rhenium oxide, ruthenium oxide, chromium oxide, zirconium oxide, hafnium oxide, tantalum oxide, silver oxide, tungsten oxide, or manganese oxide, or may be a dopant of a p-type dopant with a strong electron-withdrawing system and a hole transport material. In an exemplary embodiment, the thickness of the hole injection layer may be approximately 5 nm to 20 nm.

[0240] In an exemplary embodiment, the hole transport layer can be made of a material with high hole mobility, such as an aromatic amine compound, whose substituent groups can be carbazole, methyl fluorene, spirofluorene, dibenzothiophene, or furan, etc. In an exemplary embodiment, the thickness of the hole transport layer can be approximately 40 nm to 150 nm.

[0241] In an exemplary embodiment, the hole-blocking layer and the electron transport layer can be aromatic heterocyclic compounds, such as imidazole derivatives like benzimidazole derivatives, imidazopyridine derivatives, and benzimidazolephenanthridine derivatives; azine derivatives like pyrimidine derivatives and triazine derivatives; and compounds containing a nitrogen-containing six-membered ring structure such as quinoline derivatives, isoquinoline derivatives, and phenanthreneroline derivatives (including compounds with phosphine oxide substituents on the heterocycle). In an exemplary embodiment, the thickness of the hole-blocking layer can be approximately 5 nm to 15 nm, and the thickness of the electron transport layer can be approximately 20 nm to 50 nm.

[0242] In an exemplary embodiment, the electron injection layer may be made of an alkali metal or a metal, such as lithium fluoride (LiF), ytterbium (Yb), magnesium (Mg), or calcium (Ca), or compounds of these alkali metals or metals. In an exemplary embodiment, the thickness of the electron injection layer may be approximately 0.5 nm to 2 nm.

[0243] (10) Forming the cathode and cathode block pattern. In an exemplary embodiment, forming the cathode and cathode block pattern may include: forming the cathode 24 and cathode block 24-1 pattern on the substrate on which the aforementioned pattern is formed by an open mask vapor deposition method, such as... Figure 18a and Figure 18b As shown.

[0244] In an exemplary embodiment, the cathode 24 can be formed in the circuit region 301 and the isolation dam region 302 of the display area and the bezel area, and the cathode 24 can be an integral structure connected together. The cathode 24 of the pixel region 100 is connected to the organic light-emitting layer 23, realizing that the organic light-emitting layer 23 is simultaneously connected to the anode 21 and the cathode 24. The cathode 24 of the circuit region 301 is disposed on the pixel definition layer 22, and the cathode 24 of the isolation dam region 302 overlaps with the exposed second connection electrode 52. Since the cathode 24 overlaps with the second connection electrode 52, the second connection electrode 52 overlaps with the first connection electrode 51, and the first connection electrode 51 overlaps with the power line 50, the connection between the cathode 24 and the power line 50 is realized.

[0245] In an exemplary embodiment, the cathode 24 of the isolation dam region 302 is located on the side of the first isolation dam 410 closer to the display area, and the orthographic projection of the cathode 24 on the substrate does not overlap with the orthographic projections of the first isolation dam 410 and the second isolation dam 420 on the substrate. Alternatively, the cathode 24 of the isolation dam region 302 may completely enclose the first isolation dam 410 and partially enclose the second isolation dam 420. Alternatively, the cathode 24 of the isolation dam region 302 may completely enclose the first isolation dam 410 and the second isolation dam 420; this disclosure does not limit the scope of the embodiment.

[0246] In an exemplary embodiment, the cathode block 24-1 may be formed in the pinning area 120 of the display area. Since the partition groove 61 is a side-etched structure and the partition layer 60 has an "eaves" structure protruding from the opening on the partition groove 61, the cathode 24 in the pinning area 120 is broken at the "eaves" structure of the partition groove 61, and the cathode block 24-1 is formed on the organic light-emitting block 23-1 at the bottom of the partition groove 61. The cathode block 24-1 and the cathode 24 are isolated from each other.

[0247] In an exemplary embodiment, since the edge of the power line 50 is covered by the first dam base 401, the edge of the first connecting electrode 51 is covered by the second dam base 402, the third dam base 403 covers the first dam base 401 and the second dam base 402, and the cathode 24 completely or partially covers the second isolation dam 420, multiple coverings are formed on the edges of multiple conductive layers, which can effectively prevent the peeling failure of the edges of multiple conductive layers.

[0248] In an exemplary embodiment, the cathode may be any one or more of magnesium (Mg), silver (Ag), aluminum (Al), copper (Cu) and lithium (Li), or an alloy made of any one or more of the above metals.

[0249] In some possible exemplary embodiments, a cathode block can be formed in the fracture dam region 303 by means of the design of the mask plate, the cathode block covering the fracture dam 400, which is not limited herein.

[0250] In some possible exemplary embodiments, an optical coupling layer and an optical coupling block pattern can be formed after the cathode pattern is formed. The optical coupling layer is disposed on the cathode, and the optical coupling block is disposed on the cathode block. The refractive index of the optical coupling layer can be greater than that of the cathode, which is beneficial for light extraction and increases light extraction efficiency. The material of the optical coupling layer can be an organic material, an inorganic material, or a combination of organic and inorganic materials. It can be a single layer, a multilayer layer, or a composite layer, and this disclosure does not limit the specific application of the material.

[0251] At this point, the light-emitting structure layer of the display area is complete. In the pixel area 100, the light-emitting structure layer may include an anode 21, a pixel definition layer 22, an organic light-emitting layer 23, and a cathode 24, with the organic light-emitting layer 23 disposed between the anode 21 and the cathode 24.

[0252] (11) Forming a first encapsulation layer pattern. In an exemplary embodiment, forming the first encapsulation layer pattern may include: depositing a first encapsulation film on the substrate on which the aforementioned pattern is formed using an open mask in a deposition manner to form a first encapsulation layer 31 pattern, such as... Figure 19a and Figure 19b As shown.

[0253] In an exemplary embodiment, the first encapsulation layer 31 may be located in the circuit area 301 and the isolation dam area 302 of the display area and the bezel area. The first encapsulation layer 31 of the pixel area 110 is disposed on the cathode 24, and the first encapsulation layer 31 of the pinning area 120 wraps the pinning structure. In an exemplary embodiment, wrapping the pinning structure means that the first encapsulation layer 31 covers the upper surface of the cathode 24, covers the organic light-emitting layer 23 and the side surface of the cathode 24 facing the isolation hole 61, covers the side surface of the isolation layer 60 facing the isolation hole 61 and the lower surface facing the isolation groove 62, covers the inner wall of the isolation groove 62, and covers the cathode block 24-1 and the organic light-emitting block 23-1 at the bottom of the isolation groove 62, forming a complete wrapping of the pinning structure by the first encapsulation layer 31. By setting the pinning structure and having the pinning structure completely wrapped by the first encapsulation layer, the isolation groove forms pinning points on the encapsulation layer, which enhances the ability of the film layer to resist shear stress and can effectively prevent the film layer from peeling off.

[0254] In an exemplary embodiment, a first encapsulation layer 31 is disposed on the cathode 24 for the circuit region 301 and the isolation dam region 302, and the first encapsulation layer 31 of the isolation dam region 302 encapsulates the first isolation dam 410 and the second isolation dam 420. In the exemplary embodiment, encapsulating the first isolation dam 410 and the second isolation dam 420 means that the first encapsulation layer 31 covers all exposed surfaces of the first isolation dam 410 and the second isolation dam 420.

[0255] In an exemplary embodiment, the edge of the first encapsulation layer 31 on the side away from the display area can be located between the crack dam 400 and the second isolation dam 420, and the first encapsulation layer 31 overlaps with the exposed fourth insulating layer 14 to ensure encapsulation quality and effect.

[0256] (12) Forming a second encapsulation layer pattern. In an exemplary embodiment, forming the second encapsulation layer pattern may include: printing a second encapsulation material on a substrate on which the aforementioned pattern is formed using an inkjet printing process to form a second encapsulation layer 32 pattern, such as... Figure 20a and Figure 20b As shown.

[0257] In an exemplary embodiment, the second encapsulation layer 32 may be located on the side of the first isolation dam 410 closer to the display area in the circuit area 301 of the display area and the isolation dam area 302 of the border area. The second encapsulation layer 32 of the pixel area 110 and the pinning area 120 is disposed on the first encapsulation layer 31, and the second encapsulation layer 32 of the pinning area 120 fills the second pixel opening and the partition groove in the pinning structure.

[0258] In an exemplary embodiment, a second encapsulation layer 32 is disposed on a first encapsulation layer 31 in circuit region 301. In isolation dam region 302, a second encapsulation material is blocked by a first isolation dam 410 and is located on the side of the first isolation dam 410 closer to the display area.

[0259] (13) Forming a third encapsulation layer pattern. In an exemplary embodiment, forming the third encapsulation layer pattern may include: depositing a third encapsulation film on the substrate on which the aforementioned pattern is formed using an open mask in a deposition manner to form a third encapsulation layer 33 pattern, such as... Figure 21a and Figure 21b As shown.

[0260] In an exemplary embodiment, the third encapsulation layer 33 may be located in the circuit area 301 and the isolation dam area 302 of the display area and the bezel area. The third encapsulation layer 33 of the pixel area 110 and the pinned area 120 is disposed on the second encapsulation layer 32. In the circuit area 301 and the isolation dam area 302, on the side of the first isolation dam 410 closer to the display area, the third encapsulation layer 33 is disposed on the second encapsulation layer 32. In other areas of the isolation dam area 302, the third encapsulation layer 33 is disposed on the first encapsulation layer 31 that surrounds the first isolation dam 410 and the second isolation dam 420.

[0261] In an exemplary embodiment, the first and third encapsulation layers can be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be single-layer, multi-layer, or composite layers, ensuring that external water and oxygen cannot enter the light-emitting structure layer. The second encapsulation layer can be made of organic materials, such as resin, to encapsulate the various film layers of the display substrate, thereby improving structural stability and flatness.

[0262] This completes the encapsulation structure layer pattern. In the circuit area of ​​the display area and the bezel area, the encapsulation structure layer includes a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer, forming a stacked structure of inorganic / organic / inorganic materials. In the isolation dam area of ​​the bezel area, the encapsulation structure layer includes a first encapsulation layer and a third encapsulation layer, forming a stacked structure of inorganic / inorganic materials, which can further ensure the integrity of the encapsulation and effectively isolate external water and oxygen.

[0263] In an exemplary embodiment, after the encapsulation layer is prepared, a touch structure layer (TSP) can be formed on the encapsulation layer. The touch structure layer may include a touch electrode layer, or may include a touch electrode layer and a touch insulating layer, which is not limited herein.

[0264] In an exemplary embodiment, the fabrication process of the flexible display substrate may further include processes such as peeling off the substrate, attaching the back film, and cutting, which are not limited herein.

[0265] As can be seen from the structure and fabrication process of the display substrate in the exemplary embodiments of this disclosure, by setting a pinning area with a pinning structure in the display area, and the pinning structure being completely wrapped by the first encapsulation layer, the partition groove forms pinning points on the encapsulation layer, enhancing the film layer's ability to resist shear stress and effectively preventing film layer peeling failure. The pinning structure in the exemplary embodiments of this disclosure includes a partition groove and a partition layer of an eaves structure. The organic light-emitting layer and the cathode are disconnected at the eaves structure. The first encapsulation layer, by wrapping the partition layer and the inner wall of the partition groove, forms a structure near the pinning points consisting of two inorganic layers sandwiching the cathode and the organic light-emitting layer. This not only increases the adhesion of the organic light-emitting layer but also enhances the film layer's ability to resist shear stress, minimizing film layer peeling, preventing encapsulation failure, and improving product quality and lifespan. The fabrication process of the display substrate in the exemplary embodiments of this disclosure has good process compatibility, is simple to implement, easy to carry out, has high production efficiency, low production cost, and high yield.

[0266] The structure of the display substrate and its fabrication process as described in this exemplary embodiment are merely illustrative. In the exemplary embodiments, the corresponding structure and the patterning process may be modified or reduced as needed, and this disclosure does not limit the scope of the invention.

[0267] Figure 22 This is a schematic diagram of the structure of another display substrate according to an exemplary embodiment of the present disclosure. Figure 7 A cross-sectional view along the AA direction. This exemplary embodiment shows the main structure of the display substrate and... Figure 9a The structure of the dual-source drain metal layer (2SD) shown is basically the same, except that the display substrate in this exemplary embodiment is a single-source drain metal layer (1SD), as... Figure 22 As shown.

[0268] In an exemplary embodiment, the pixel region 110 may include a driving structure layer 501 disposed on the substrate 10, a light-emitting structure layer 502 disposed on the side of the driving structure layer 501 away from the substrate, and an encapsulation structure layer 503 disposed on the side of the light-emitting structure layer 502 away from the substrate.

[0269] In an exemplary embodiment, the pinning region 120 may include: a composite insulating layer disposed on a substrate 10; a signal lead 103 disposed on the side of the composite insulating layer away from the substrate; a first planarization layer 15 covering the signal lead 103; and a partition layer 60 disposed on the side of the first planarization layer 15 away from the substrate. The partition layer 60 has a partition hole, and the first planarization layer 15 has a partition groove 62. The partition hole and the partition groove 62 are interconnected, and the partition layer 60, the partition hole, and the partition groove 62 constitute a pinning structure. The pinning region 120 may also include: a pixel definition layer 22 covering the outer edge of the partition layer 60 away from the partition hole; an organic light-emitting layer 23 and a cathode 24 disposed on the side of the partition layer 60 and the pixel definition layer 22 away from the substrate; an organic light-emitting block and a cathode block disposed at the bottom of the partition groove 61; a first encapsulation layer 31 encapsulating the pinning structure; a second encapsulation layer 32 disposed on the side of the first encapsulation layer 31 away from the substrate; and a third encapsulation layer 33 disposed on the side of the second encapsulation layer 32 away from the substrate.

[0270] This exemplary embodiment, by setting a pinning structure in the display area and having the pinning structure completely wrapped by the first encapsulation layer, enables the partition groove to form pinning points on the encapsulation layer, which can also enhance the film layer's ability to resist shear stress and effectively prevent the film layer from peeling off.

[0271] In a certain display substrate, there is a problem not only of encapsulation failure in the display area due to film layer peeling, but also of encapsulation failure in the isolation dam area of ​​the frame due to conductive layer edge peeling. Research has found that conductive layer edge peeling in the isolation dam area is caused by over-etching of the conductive layer, which in turn is caused by the excessive height of the second isolation dam. Figure 23 This is a schematic diagram of the structure of an isolation dam area on a display substrate. Figure 23 As shown, the second isolation dam 420 of the isolation dam area is composed of multiple organic material layers and multiple conductive layers. The first flat dam base 421, which is disposed on the same layer as the first flat layer, covers the edge of the power line 50 away from the display area. The side of the first connecting electrode 51 away from the display area is placed on the first flat dam base 421. The second flat dam base 422, which is disposed on the same layer as the second flat layer, is disposed on the first flat dam base 421 and covers the edge of the first connecting electrode 51 away from the display area. The side of the second connecting electrode 52, which is disposed on the same layer as the anode, is placed on the second flat dam base 422 away from the display area. The third flat dam base 423, which is disposed on the same layer as the pixel definition layer, is disposed on the second flat dam base 422 and covers the edge of the second connecting electrode 52 away from the display area. According to Figure 23As shown in the structure, relative to the surface of the fourth insulating layer 14, the height of the first isolation dam 410 is h1+h2+h3+H3, the height of the second isolation dam 420 is H1+H2+H3, and the step difference ΔH between the side of the second connecting electrode 52 away from the display area and the side of the second connecting electrode 52 close to the display area is approximately (H1+H2)-(h1+h2+h3). Here, H1 is the thickness of the first flat dam base 421, H2 is the thickness of the second flat dam base 422, H3 is the thickness of the third flat dam base 423, h1 is the thickness of the power line 50, h2 is the thickness of the first connecting electrode 51, and h3 is the thickness of the second connecting electrode 52. Because the first and second planarization layers of organic material are thicker, and the power line and second connecting electrode of metallic material are thinner, the height of the second isolation dam 420 and the step difference ΔH between the second connecting electrode 52 are relatively large. With the introduction of requirements such as in-screen apertures (AA Holes), subsequent processes will perform dry etching in other areas. Although photoresist (PR) is used to shield the areas that do not need to be etched during dry etching, if the height of the second isolation dam 420 is too high and the step difference between the second connecting electrode 52 is too large, the photoresist in the area where the second isolation dam 420 is located becomes too thin and cannot effectively protect the film structure. This results in over-etching of the second connecting electrode 52 during dry etching, causing damage to the second connecting electrode 52 (step difference portion) on the sidewall of the second flat dam base 422, resulting in edge peeling and ultimately leading to encapsulation failure.

[0272] Figure 24 This is a schematic diagram of the structure of an isolation dam area, as an exemplary embodiment of this disclosure. Figure 16b Enlarged views of the central isolation dam area and the cracked dam area. (See attached image.) Figure 24 As shown, the second isolation dam 420 of the isolation dam area may include a first dam foundation 401, a second dam foundation 402, a third dam foundation 403, and the edging of three conductive layers.

[0273] In an exemplary embodiment, a power line 50 is disposed in an isolation dam area 302. A first dam base 401, disposed on the same layer as the first planarization layer, covers the edge of the power line 50 away from the display area. The orthographic projection of the edge of the power line 50 away from the display area onto the substrate is within the range of the orthographic projection of the first dam base 401 onto the substrate. A first connecting electrode 51 is disposed in the isolation dam area 302, overlapping the power line 50, but the edge of the first connecting electrode 51 away from the display area is recessed towards the display area relative to the edge of the power line 50 away from the display area. A second dam base 402, disposed on the same layer as the second planarization layer, is disposed side by side with the first dam base 401. The orthographic projection of the second dam base 402 onto the substrate does not overlap with the orthographic projection of the first dam base 401 onto the substrate. The second dam base 402 is disposed on the power line 50 and covers the edge of the first connecting electrode 51 away from the display area. The orthographic projection of the edge of the first connecting electrode 51 away from the display area onto the substrate is within the range of the orthographic projection of the second dam base 402 onto the substrate. A second connecting electrode 52, disposed on the same layer as the anode, is located in the isolation dam area 302. Its side closer to the display area rests on the first connecting electrode 51, while its side farther from the display area rests on the second dam base 402. A third dam base 403, disposed on the same layer as the pixel definition layer, is located on the first dam base 401 and the second dam base 402, and covers the edge of the second connecting electrode 52 on the side farther from the display area. The orthographic projection of the edge of the second connecting electrode 52 on the substrate lies within the range of the orthographic projection of the third dam base 403 on the substrate.

[0274] In an exemplary embodiment, the orthographic projection of the edge of the power line 50 on the side away from the display area onto the substrate may be within the range of the orthographic projection of the third dam base 403 on the substrate, the orthographic projection of the edge of the first connecting electrode 51 on the side away from the display area onto the substrate may be within the range of the orthographic projection of the third dam base 403 on the substrate, the orthographic projection of the third dam base 403 on the substrate at least partially overlaps with the orthographic projection of the first dam base 401 on the substrate, and the orthographic projection of the third dam base 403 on the substrate at least partially overlaps with the orthographic projection of the second dam base 402 on the substrate.

[0275] according to Figure 24As shown in the structure, relative to the surface of the fourth insulating layer 14, the height of the second isolation dam 420 is h1 + H2 + H3. The step difference ΔH between the side of the second connecting electrode 52 away from the display area and the side of the second connecting electrode 52 close to the display area is approximately H2 - h2, where H2 is the thickness of the second dam base 402, H3 is the thickness of the third dam base 403, h1 is the thickness of the power line 50, and h2 is the thickness of the first connecting electrode 51. This exemplary embodiment, by using two parallel dam bases to cover the edges of the power line 50 and the first connecting electrode 51 respectively, not only reduces the height of the second isolation dam 420 but also reduces the step difference ΔH of the second connecting electrode 52, avoiding over-etching of the second connecting electrode 52 during subsequent dry etching and preventing edge peeling.

[0276] In this exemplary embodiment, the edge of the power line 50 away from the display area is covered by the first dam base 401, the edge of the first connecting electrode 51 away from the display area is covered by the second dam base 402, and the edge of the second connecting electrode 52 away from the display area is covered by the third dam base 403, so that the edges of multiple conductive layers form multiple coverings, which can effectively prevent the peeling failure of the conductive layer edges.

[0277] Figure 25 This is a schematic diagram of another isolation dam area as an exemplary embodiment of this disclosure. Figure 25 As shown, the second isolation dam 420 of the isolation dam area may include a second dam foundation 402, a third dam foundation 403, and the edging of two conductive layers.

[0278] In an exemplary embodiment, a power line 50 is disposed in an isolation dam area 302 and a crack dam area 303. A crack dam 400, disposed on the same layer as the first planarization layer, covers the edge of the power line 50 away from the display area. The orthographic projection of the edge of the power line 50 away from the display area onto the substrate is within the range of the orthographic projection of the crack dam 400 onto the substrate. A first connecting electrode 51 is disposed in the isolation dam area 302 and overlaps the power line 50. A second dam base 402, disposed on the same layer as the second planarization layer, is disposed on the power line 50 and covers the edge of the first connecting electrode 51 away from the display area. The orthographic projection of the edge of the first connecting electrode 51 away from the display area onto the substrate is within the range of the orthographic projection of the second dam base 402 onto the substrate. A second connecting electrode 52, disposed on the same layer as the anode, is disposed in the isolation dam area 302. The side closer to the display area overlaps the first connecting electrode 51, and the side farther from the display area overlaps the second dam base 402. The orthographic projection of the edge of the second connecting electrode 52 away from the display area onto the substrate is within the range of the orthographic projection of the second dam base 402 onto the substrate. The third dam base 403, which is disposed on the same layer as the pixel definition layer, is disposed on the second dam base 402 and covers the edge of the second connecting electrode 52 away from the display area. The orthographic projection of the edge of the second connecting electrode 52 away from the display area on the substrate is within the range of the orthographic projection of the third dam base 403 on the substrate.

[0279] according to Figure 25 As can be seen from the structure shown, the height of the second isolation dam 420 relative to the surface of the fourth insulating layer 14 is h1+H2+H3, and the step difference ΔH between the side of the second connecting electrode 52 away from the display area and the side of the second connecting electrode 52 close to the display area is approximately H2-h2.

[0280] This exemplary embodiment extends the power line 50 to the crack dam area 303. The isolation dam area 302 only needs to be provided with a second dam base 402 and a third dam base 403 covering the edges of the first connecting electrode 51 and the second connecting electrode 52 respectively. Therefore, the second isolation dam 420 does not include the first dam base 401, which not only reduces the height of the second isolation dam 420, but also reduces the step difference ΔH of the second connecting electrode 52, avoiding over-etching of the second connecting electrode 52 in subsequent dry etching and avoiding edge peeling.

[0281] In this exemplary embodiment, the edge of the power line 50 away from the display area is covered by the crack dam 400, the edge of the first connecting electrode 51 away from the display area is covered by the second dam base 402, and the edge of the second connecting electrode 52 away from the display area is covered by the third dam base 403, which can effectively prevent the peeling failure of the conductive layer edge.

[0282] In this exemplary embodiment, the power line 50 extends into the crack dam area, which can effectively reduce the resistance of the power line 50 and effectively reduce the resistance voltage drop of the power line 50.

[0283] Figure 26 This is a schematic diagram of the structure of another isolation dam area, as an exemplary embodiment of this disclosure. Figure 26 As shown, the second isolation dam 420 of the isolation dam area may include a third dam foundation 403 and a conductive layer edging.

[0284] In an exemplary embodiment, a power line 50 is disposed in an isolation dam area 302 and a crack dam area 303. A first connecting electrode 51 is also disposed in the isolation dam area 302 and the crack dam area 303, overlapping the power line 50. A crack dam 400, disposed on the same layer as the first planarization layer, simultaneously covers the edges of the power line 50 and the first connecting electrode 51 on the side away from the display area. The orthographic projections of the edges of the power line 50 and the first connecting electrode 51 on the side away from the display area onto the substrate are within the range of the orthographic projection of the crack dam 400 onto the substrate. A second connecting electrode 52, disposed on the same layer as the anode, is disposed in the isolation dam area 302 and overlaps the first connecting electrode 51. A third dam base 403, disposed on the same layer as the pixel definition layer, is disposed on the second connecting electrode 52 and covers the edge of the second connecting electrode 52 on the side away from the display area. The orthographic projection of the edge of the second connecting electrode 52 on the side away from the display area onto the substrate is within the range of the orthographic projection of the third dam base 403 onto the substrate.

[0285] according to Figure 26 As can be seen from the structure shown, the height of the second isolation dam 420 relative to the surface of the fourth insulating layer 14 is h1+H2+H3, which is basically the same as the height of the first isolation dam 410. The second connecting electrode 52 has no step difference, that is, the step difference ΔH between the side of the second connecting electrode 52 away from the display area and the side of the second connecting electrode 52 close to the display area is about 0.

[0286] This exemplary embodiment extends the power line 50 and the first connecting electrode 51 to the crack dam region 303. The isolation dam region 302 only needs to be provided with a third dam base 403 covering the edge of the second connecting electrode 52. Therefore, the second isolation dam 420 does not include the first dam base 401 and the second dam base 402. This not only minimizes the height of the second isolation dam 420, but also minimizes the step difference ΔH of the second connecting electrode 52. This avoids over-etching of the second connecting electrode 52 in subsequent dry etching and avoids edge peeling.

[0287] In this exemplary embodiment, the edges of the power line 50 and the first connecting electrode 51 on the side away from the display area are covered by the crack dam 400, and the edge of the second connecting electrode 52 on the side away from the display area is covered by the third dam base 403, which can effectively prevent the peeling failure of the conductive layer edge.

[0288] In this exemplary embodiment, the power line 50 and the first connecting electrode 51 extend into the crack dam area, which can effectively reduce the resistance of the power line 50 and the first connecting electrode 51, and effectively reduce the resistance voltage drop of the power line 50 and the first connecting electrode 51.

[0289] Figure 27 This is a schematic diagram of the structure of another isolation dam area, as an exemplary embodiment of this disclosure. Figure 27 As shown, the second isolation dam 420 of the isolation dam area may include a first dam foundation 401, a second dam foundation 402, a third dam foundation 403, and an edging of two conductive layers.

[0290] In an exemplary embodiment, a power line 50 is disposed in an isolation dam area 302. A first dam base 401, disposed on the same layer as the first planarization layer, covers the edge of the power line 50 away from the display area. The orthographic projection of the edge of the power line 50 away from the display area onto the substrate is within the range of the orthographic projection of the first dam base 401 onto the substrate. A first connecting electrode 51 is disposed in the isolation dam area 302, with its side closer to the display area resting on the power line 50 and its side away from the display area resting on the first dam base 401. The orthographic projection of the edge of the first connecting electrode 51 away from the display area onto the substrate is within the range of the orthographic projection of the first dam base 401 onto the substrate. A second dam base 402, disposed on the same layer as the second planarization layer, is disposed on the first dam base 401 and covers the edge of the first connecting electrode 51 away from the display area. The orthographic projection of the edge of the first connecting electrode 51 away from the display area onto the substrate is within the range of the orthographic projection of the second dam base 402 onto the substrate. A second connecting electrode 52, disposed on the same layer as the anode, is located in the isolation dam area 302 and rests on the first connecting electrode 51. However, relative to the edge of the power line 50 away from the display area, the edge of the second connecting electrode 52 away from the display area is recessed towards the display area. The orthographic projection of the second connecting electrode 52 on the substrate does not overlap with the orthographic projections of the first dam base 401 and the second dam base 402 on the substrate. A third dam base 403 is disposed on the second dam base 402. A first isolation dam 410, disposed on the same layer as the pixel definition layer, is disposed on the first connecting electrode 51 and covers the edge of the second connecting electrode 52 away from the display area. The orthographic projection of the edge of the second connecting electrode 52 away from the display area on the substrate is within the range of the orthographic projection of the first isolation dam 410 on the substrate. In an exemplary embodiment, the third dam base 403 may be disposed on the same layer as the spacer pillar in the display area.

[0291] according to Figure 27 As can be seen from the structure shown, although the second isolation dam 420 is relatively high, the second connecting electrode 52 has no step difference, that is, the step difference ΔH between the side of the second connecting electrode 52 away from the display area and the side of the second connecting electrode 52 close to the display area is approximately 0.

[0292] This exemplary embodiment reduces the step size ΔH of the second connection electrode 52 by using the first isolation dam 410 to cover the edge of the second connection electrode 52 away from the display area, thereby avoiding over-etching of the second connection electrode 52 in subsequent dry etching and preventing edge peeling.

[0293] In this exemplary embodiment, the edge of the power line 50 away from the display area is covered by the first dam base 401, the edge of the first connecting electrode 51 away from the display area is covered by the second dam base 402, and the edge of the second connecting electrode 52 away from the display area is covered by the first isolation dam 410, which can effectively prevent the peeling failure of the conductive layer edge.

[0294] Figure 28 This is a schematic diagram of the structure of another isolation dam area, as an exemplary embodiment of this disclosure. Figure 28 As shown, the second isolation dam 420 of the isolation dam area may include a second dam foundation 402, a third dam foundation 403, and the edging of two conductive layers.

[0295] In an exemplary embodiment, the power line 50 and the first connecting electrode 51 are disposed in the isolation dam area 302. However, relative to the edge of the first connecting electrode 51 away from the display area, the edge of the power line 50 away from the display area is recessed towards the display area. This results in the first connecting electrode 51 being placed on the power line 50 near the display area and on the fourth insulating layer 14 away from the display area. The edge of the power line 50 away from the display area is covered by the first connecting electrode 51, and the orthographic projection of the edge of the power line 50 away from the display area onto the substrate is within the range of the orthographic projection of the first connecting electrode 51 onto the substrate. The second dam base 402, disposed on the same layer as the second planarization layer, is disposed on the fourth insulating layer 14 and covers the edge of the first connecting electrode 51 away from the display area. The orthographic projection of the edge of the first connecting electrode 51 away from the display area onto the substrate is within the range of the orthographic projection of the second dam base 402 onto the substrate. A second connecting electrode 52, disposed on the same layer as the anode, is located in the isolation dam area 302. Its side closer to the display area rests on the first connecting electrode 51, while its side farther from the display area rests on the second dam base 402. The orthographic projection of the edge of the second connecting electrode 52 on the substrate lies within the range of the orthographic projection of the second dam base 402 on the substrate. A third dam base 403, disposed on the same layer as the pixel definition layer, is located on the second dam base 402 and covers the edge of the second connecting electrode 52 on the side farther from the display area. The orthographic projection of the edge of the second connecting electrode 52 on the substrate lies within the range of the orthographic projection of the third dam base 403 on the substrate.

[0296] In an exemplary embodiment, the orthographic projection of the edge of the power line 50 on the side away from the display area onto the substrate may be within the range of the orthographic projection of the first isolation dam 410 onto the substrate.

[0297] according to Figure 28 As can be seen from the structure shown, the height of the second isolation dam 420 relative to the surface of the fourth insulating layer 14 is H2+H3, and the maximum step difference ΔH of the second connecting electrode 52 is approximately H2-h2.

[0298] This exemplary embodiment, by recessing the power line 50 toward the display area, only requires the second dam base 402 and the third dam base 403 to cover the edges of the first connecting electrode 51 and the second connecting electrode 52, respectively. Therefore, the second isolation dam 420 does not include the first dam base 401, which not only reduces the height of the second isolation dam 420, but also reduces the step difference ΔH of the second connecting electrode 52, avoiding over-etching of the second connecting electrode 52 in subsequent dry etching and preventing edge peeling.

[0299] In this exemplary embodiment, the edge of the power line 50 away from the display area is covered by the first connecting electrode 51, the edge of the first connecting electrode 51 away from the display area is covered by the second dam base 402, and the edge of the second connecting electrode 52 away from the display area is covered by the third dam base 403, which can effectively prevent the peeling failure of the conductive layer edge.

[0300] Figure 29 This is a schematic diagram of the structure of another isolation dam area, as an exemplary embodiment of this disclosure. Figure 29 As shown, the second isolation dam 420 of the isolation dam area may include a first dam foundation 401, a third dam foundation 403, and two conductive layers.

[0301] In an exemplary embodiment, the power line 50 is disposed in the isolation dam area 302. The first dam base 401, disposed on the same layer as the first flat layer, covers the edge of the power line 50 away from the display area. The orthographic projection of the edge of the power line 50 away from the display area onto the substrate is within the range of the orthographic projection of the first dam base 401 onto the substrate. The first connecting electrode 51 is disposed in the isolation dam area 302 and overlaps the power line 50. However, relative to the edge of the power line 50 away from the display area, the edge of the first connecting electrode 51 away from the display area is recessed towards the display area. The orthographic projection of the first connecting electrode 51 onto the substrate does not overlap with the orthographic projection of the first dam base 401 onto the substrate. The second connecting electrode 52 is disposed in the isolation dam area 302. The side of the second connecting electrode 52 closest to the display area is attached to the first connecting electrode 51, and the side of the second connecting electrode 52 furthest from the display area is attached to the first dam base 401. The orthographic projection of the edge of the second connecting electrode 52 furthest from the display area onto the substrate is within the range of the orthographic projection of the first dam base 401 onto the substrate. The middle region of the second connecting electrode 52 is attached to the power line 50, such that the edge of the first connecting electrode 51 furthest from the display area is covered by the second connecting electrode 52, and the orthographic projection of the edge of the first connecting electrode 51 furthest from the display area onto the substrate is within the range of the orthographic projection of the second connecting electrode 52 onto the substrate. The third dam base 403, disposed on the same layer as the pixel definition layer, is disposed on the first dam base 401 and covers the edge of the second connecting electrode 52 furthest from the display area. The orthographic projection of the edge of the second connecting electrode 52 furthest from the display area onto the substrate is within the range of the orthographic projection of the third dam base 403 onto the substrate.

[0302] In an exemplary embodiment, the orthographic projection of the edge of the first connecting electrode 51 on the side away from the display area onto the substrate may be within the range of the orthographic projection of the first isolation dam 410 onto the substrate.

[0303] according to Figure 29As can be seen from the structure shown, the height of the second isolation dam 420 relative to the surface of the fourth insulating layer 14 is H1+H3, the maximum step difference ΔH of the second connecting electrode 52 is approximately H1-h1, and H1 is the thickness of the first dam base 401.

[0304] In this exemplary embodiment, by recessing the first connecting electrode 51 toward the display area, the isolation dam area 302 only needs to have the first dam base 401 and the third dam base 403 respectively covering the edges of the power line 50 and the second connecting electrode 52. Therefore, the second isolation dam 420 does not include the second dam base 402, which not only reduces the height of the second isolation dam 420, but also reduces the step difference ΔH of the second connecting electrode 52, avoiding over-etching of the second connecting electrode 52 in subsequent dry etching and avoiding edge peeling.

[0305] In this exemplary embodiment, the edge of the power line 50 away from the display area is covered by the first dam base 401, the edge of the first connecting electrode 51 away from the display area is covered by the second connecting electrode 52, and the edge of the second connecting electrode 52 away from the display area is covered by the third dam base 403, which can effectively prevent the peeling failure of the conductive layer edge.

[0306] In an exemplary embodiment, Figures 24 to 29 In the structure shown, the width of the first isolation dam can be approximately 30 μm to 100 μm, the width of the second isolation dam can be approximately 30 μm to 100 μm, and the width of the edge of the first dam base, the second dam base, or the third dam base covering the edge of the power line, the edge of the first connecting electrode, or the edge of the second connecting electrode in the second isolation dam can be greater than 3 μm, the width being the dimension along the direction away from the display area. The thickness H1 of the first dam base can be approximately 1 μm to 3 μm, the thickness H2 of the second dam base can be approximately 1 μm to 3 μm, and the thickness H3 of the third dam base can be approximately 1 μm to 3 μm, the thickness being the dimension perpendicular to the substrate direction. The minimum spacing between the spaced-apart first dam base and the second dam base can be greater than 3 μm, the minimum spacing between the spaced-apart first isolation dam and the second isolation dam can be greater than 3 μm, and the minimum spacing between the spaced-apart second isolation dam and the crack dam can be greater than 3 μm.

[0307] In an exemplary embodiment, Figures 24 to 29 In the structure shown, the power line, the first connecting electrode, and the second connecting electrode near the edge of the display area can be compared with... Figure 9b The structures shown are the same, or the alternation of each edge can be adjusted accordingly; this disclosure does not limit this.

[0308] As can be seen from the structure of the display substrate in the exemplary embodiments of this disclosure, the exemplary embodiments of this disclosure, through the staggered structure of each conductive layer in the isolation dam area and the alternating arrangement of the edges of each conductive layer, not only reduce the height of the second isolation dam and reduce the step difference of the second connecting electrode, avoiding over-etching of the second connecting electrode in subsequent dry etching, avoiding damage to the second connecting electrode, and avoiding edge peeling, but also make the edges of multiple conductive layers form multiple coatings, which can further prevent the peeling failure of the conductive layer edges, improve structural reliability, and improve product quality and lifespan.

[0309] In exemplary embodiments, the display substrate of this disclosure can be applied to display devices with pixel driving circuits, such as OLED, quantum dot display (QLED), light-emitting diode display (Micro LED or Mini LED) or quantum dot light-emitting diode display (QDLED), etc., and this disclosure does not limit it.

[0310] This disclosure also provides a method for fabricating a display substrate to prepare the aforementioned display substrate. In an exemplary embodiment, the display substrate may include a display area, and the display area may include at least one pinned region; the fabrication method may include:

[0311] A flat layer and a partition layer disposed on the flat layer are sequentially formed on the substrate. The partition layer is provided with a partition hole, and the flat layer is provided with a partition groove. The partition groove and the partition hole are connected. The partition layer located around the partition hole has a protrusion relative to the side wall of the partition groove. The protrusion and the side wall of the partition groove form an indented structure.

[0312] An encapsulation structure layer is formed, which covers the protrusion and the sidewalls and bottom of the partition groove.

[0313] This disclosure also provides a display device, including the display substrate of the foregoing embodiments. The display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0314] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of this disclosure and is not intended to limit this disclosure. Any person skilled in the art may make any modifications and changes to the form and details of the implementation without departing from the spirit and scope of this disclosure; however, the scope of patent protection of this invention shall still be determined by the scope defined in the appended claims.

Claims

1. A display substrate, comprising a display area, the display area including at least one pinning region and a plurality of pixel units; the pinning region being disposed between adjacent pixel units; in a plane perpendicular to the display substrate, the pinning region including a planarization layer disposed on a substrate, a partition layer disposed on a side of the planarization layer away from the substrate, and an encapsulation structure layer disposed on a side of the partition layer away from the substrate; pinning structures are disposed on the planarization layer and the partition layer, and the encapsulation structure layer covers the pinning structures; in, A partition groove is provided on the planar layer, and a partition hole is provided on the partition layer. The partition groove and the partition hole are connected. The partition layer located around the partition hole has a protrusion relative to the side wall of the partition groove. The protrusion and the side wall of the partition groove form an indented structure. The encapsulation structure layer covers the protrusion, the side wall of the partition groove, and the bottom of the groove. The partition layer, the partition hole, and the partition groove constitute a stapling structure to improve the film layer's ability to resist shear stress and prevent the film layer from peeling off.

2. The display substrate according to claim 1, wherein, The pinning area further includes a pixel definition layer disposed on the side of the partition layer away from the substrate. The pixel definition layer covers the edge of the partition layer away from the partition hole. The pixel definition layer is provided with a partition opening, which exposes the partition hole and the partition groove. The encapsulation structure layer covers the partition opening.

3. The display substrate according to claim 1, wherein, The pinning area further includes: an organic light-emitting layer disposed on the side of the partition layer away from the substrate and a cathode disposed on the side of the organic light-emitting layer away from the substrate, and an organic light-emitting block disposed at the bottom of the partition groove and a cathode block disposed on the side of the organic light-emitting block away from the substrate. The organic light-emitting layer and the organic light-emitting block are isolated from each other, and the cathode and the cathode block are isolated from each other. The encapsulation structure layer covers the cathode on the partition layer and the cathode block at the bottom of the partition groove.

4. The display substrate according to claim 1, wherein, The encapsulation structure layer includes a first encapsulation layer of inorganic material, a second encapsulation layer of organic material, and a third encapsulation layer of inorganic material. The first encapsulation layer covers the protrusion and the sidewall and bottom of the partition groove. The second encapsulation layer is disposed on the side of the first encapsulation layer away from the substrate and fills the partition groove. The third encapsulation layer is disposed on the side of the second encapsulation layer away from the substrate.

5. The display substrate according to claim 1, wherein, The planarization layer includes a first planarization layer, the partition layer is disposed on the side of the first planarization layer away from the substrate, and the partition groove is disposed on the first planarization layer.

6. The display substrate according to claim 1, wherein, The planarization layer includes a first planarization layer and a second planarization layer disposed on the side of the first planarization layer away from the substrate, the partition layer is disposed on the side of the second planarization layer away from the substrate, and the partition groove is disposed on the second planarization layer.

7. The display substrate according to any one of claims 1-6, wherein, At least one pixel unit includes a plurality of sub-pixels arranged sequentially along a first direction, and the pinning area is disposed between adjacent pixel units in a second direction, wherein the first direction intersects the second direction.

8. The display substrate according to claim 7, wherein, At least one pixel unit includes a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel, and the pinning area is disposed at any one or more of the following locations: one side of the first sub-pixel in the second direction, one side of the second sub-pixel in the second direction, one side of the third sub-pixel in the second direction, and one side of the fourth sub-pixel in the second direction.

9. The display substrate according to any one of claims 1-6, wherein, On a plane parallel to the display substrate, the shape of the partition groove includes any one or more of the following: square, rectangle, pentagon, hexagon, circle, ellipse, zigzag, arc, "T" shape, "L" shape and "H" shape.

10. The display substrate according to any one of claims 1 to 6, wherein, The display substrate further includes a border region located on at least one side of the display area. The border region includes an isolation dam region and a crack dam region sequentially arranged along a direction away from the display area. In a plane perpendicular to the substrate, the isolation dam region includes a composite insulating layer disposed on the substrate, a power line disposed on the side of the composite insulating layer away from the substrate, a first connection electrode disposed on the side of the power line away from the substrate, a second connection electrode disposed on the side of the first connection electrode away from the substrate, and a first isolation dam and a second isolation dam disposed on the side of the second connection electrode away from the substrate. The second isolation dam is disposed on the side of the first isolation dam away from the display area. The crack dam region includes a composite insulating layer disposed on the substrate and a crack dam disposed on the side of the composite insulating layer away from the substrate. The composite insulating layer has multiple cracks, and the crack dam fills the multiple cracks.

11. The display substrate according to claim 10, wherein, The edges of the power line away from the display area, the edges of the first connecting electrode away from the display area, and the edges of the second connecting electrode away from the display area are covered by the first isolation dam and / or the second isolation dam, and do not contact the encapsulation structure layer.

12. The display substrate according to claim 11, wherein, The edge of the power line away from the display area is covered by the crack dam, or by the first dam base in the second isolation dam, or by the second dam base in the second isolation dam, or by the first connecting electrode.

13. The display substrate according to claim 11, wherein, The edge of the first connecting electrode on the side away from the display area is covered by the crack dam, or by the second dam base in the second isolation dam, or by the second connecting electrode.

14. The display substrate according to claim 11, wherein, The edge of the second connecting electrode on the side away from the display area is covered by the third dam base in the second isolation dam, or by the first isolation dam.

15. The display substrate according to any one of claims 11 to 14, wherein, The second isolation dam includes a first dam base, a second dam base, and a third dam base. The power line, the first connecting electrode, and the second connecting electrode are located in the isolation dam area. The first dam base is disposed on the side of the composite insulation layer away from the substrate and covers the edge of the power line away from the display area. The first connecting electrode is disposed on the side of the power line away from the substrate. The second dam base is disposed on the side of the power line away from the substrate and covers the edge of the first connecting electrode away from the display area. The orthographic projection of the second dam base on the substrate does not overlap with the orthographic projection of the first dam base on the substrate. The side of the second connecting electrode near the display area is erected on the side of the first connecting electrode away from the substrate, and the side of the second connecting electrode away from the display area is erected on the side of the second dam base away from the substrate. The third dam base is disposed on the side of the first and second dam bases away from the substrate and covers the edge of the second connecting electrode away from the display area.

16. The display substrate according to any one of claims 11 to 14, wherein, The second isolation dam includes a second dam base and a third dam base. The power line is located in the isolation dam area and the crack dam area. The first connecting electrode and the second connecting electrode are located in the isolation dam area. The crack dam covers the edge of the power line away from the display area. The first connecting electrode is disposed on the side of the power line away from the substrate. The second dam base is disposed on the side of the power line away from the substrate and covers the edge of the first connecting electrode away from the display area. The side of the second connecting electrode closest to the display area is erected on the side of the first connecting electrode furthest from the substrate, and the side of the second connecting electrode furthest from the display area is erected on the side of the second dam base furthest from the substrate; the third dam base is disposed on the side of the second dam base furthest from the substrate and covers the edge of the side of the second connecting electrode furthest from the display area.

17. The display substrate according to any one of claims 11 to 14, wherein, The second isolation dam includes a third dam base, the power line and the first connecting electrode are located in the isolation dam area and the crack dam area, and the second connecting electrode is located in the isolation dam area; the crack dam covers the edge of the power line and the first connecting electrode on the side away from the display area; The second connecting electrode is disposed on the side of the first connecting electrode away from the substrate, and the third dam base is disposed on the side of the first connecting electrode away from the substrate and covers the edge of the second connecting electrode away from the display area.

18. The display substrate according to any one of claims 11 to 14, wherein, The second isolation dam includes at least a first dam base and a second dam base, and the power line, the first connecting electrode and the second connecting electrode are located in the isolation dam area; the first dam base is disposed on the side of the composite insulation layer away from the substrate and covers the edge of the power line away from the display area. The side of the first connecting electrode closest to the display area is attached to the side of the power line away from the substrate, and the side of the first connecting electrode away from the display area is attached to the side of the first dam base away from the substrate; the second dam base is disposed on the side of the first dam base away from the substrate and covers the edge of the side of the first connecting electrode away from the display area. The second connection electrode is disposed on the side of the first connection electrode away from the substrate, and the first isolation dam is disposed on the side of the first connection electrode away from the substrate, and the first isolation dam covers the edge of the second connection electrode away from the display area.

19. The display substrate according to any one of claims 11 to 14, wherein, The second isolation dam includes a second dam base and a third dam base. The power line, the first connecting electrode, and the second connecting electrode are located in the isolation dam area. The side of the first connecting electrode closer to the display area is laid on the side of the power line away from the substrate, and the side of the first connecting electrode away from the display area is laid on the side of the composite insulation layer away from the substrate. The first connecting electrode covers the edge of the power line away from the display area. The second dam base is disposed on the side of the composite insulation layer away from the substrate and covers the edge of the first connecting electrode away from the display area. The side of the second connecting electrode closest to the display area is erected on the side of the first connecting electrode furthest from the substrate, and the side of the second connecting electrode furthest from the display area is erected on the side of the second dam base furthest from the substrate; the third dam base is disposed on the side of the second dam base furthest from the substrate and covers the edge of the side of the second connecting electrode furthest from the display area.

20. The display substrate according to claim 19, wherein, The orthographic projection of the edge of the power line on the side away from the display area onto the substrate is within the range of the orthographic projection of the first isolation dam onto the substrate.

21. The display substrate according to any one of claims 11 to 14, wherein, The second isolation dam includes a first dam base and a third dam base, and the power line, the first connecting electrode and the second connecting electrode are located in the isolation dam area; the first connecting electrode is laid on the side of the power line away from the substrate; the first dam base is disposed on the side of the composite insulation layer away from the substrate and covers the edge of the power line away from the display area. The second connecting electrode is positioned on the side of the first connecting electrode away from the substrate, near the first display area. The second connecting electrode is positioned on the side of the first dam away from the substrate, away from the display area. The area between the first and second sides is positioned on the side of the power line away from the substrate. The second connecting electrode covers the edge of the first connecting electrode away from the display area. The third dam is positioned on the side of the first dam away from the substrate and covers the edge of the second connecting electrode away from the display area.

22. The display substrate according to claim 21, wherein, The orthographic projection of the edge of the first connecting electrode on the side away from the display area onto the substrate is within the range of the orthographic projection of the first isolation dam onto the substrate.

23. The display substrate according to any one of claims 11 to 14, wherein, The first dam foundation of the second isolation dam is set on the same layer as the first flat layer, the second dam foundation of the second isolation dam is set on the same layer as the second flat layer, the third dam foundation of the second isolation dam is set on the same layer as the pixel definition layer, and the first isolation dam is set on the same layer as the pixel definition layer.

24. A display device comprising the display substrate according to any one of claims 1 to 23.

25. A method for manufacturing a display substrate, the display substrate comprising a display area, the display area comprising at least one pinned region and a plurality of pixel units; The pinning area is disposed between adjacent pixel units; the fabrication method includes: A planarization layer and a partition layer disposed on the planarization layer are sequentially formed on the substrate, and a stapling structure is disposed on the planarization layer and the partition layer; A packaging structure layer is formed, the packaging structure layer covering the pinning structure; The planarization layer has a partition groove and a partition hole. The partition groove and the partition hole are connected. The partition layer around the partition hole has a protrusion relative to the sidewall of the partition groove. The protrusion and the sidewall of the partition groove form an indented structure. The encapsulation structure layer covers the protrusion, the sidewall of the partition groove, and the bottom of the groove. The partition layer, the partition hole, and the partition groove constitute a stapling structure to improve the film layer's ability to resist shear stress and prevent the film layer from peeling off.

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