An electron beam lithography method and a semiconductor device

Abstract

The application relates to an electron beam lithography method and a semiconductor device, and belongs to the technical field of semiconductor device preparation. The method solves the problem that, in the prior art, the utilization of an auxiliary pattern to correct a proximity effect occupies extra layout area, which is not conducive to high-density integration of a device. The method comprises the following steps: step A: forming a photoresist layer on a substrate; step B: forming a device pattern and an auxiliary pattern on the photoresist layer through exposure and development, wherein the device pattern and the auxiliary pattern are exposed by using different levels of doses, so that the auxiliary pattern is not completely developed in the development process, and then the auxiliary pattern is not etched to the substrate in the subsequent etching process; step C: etching, to form the device pattern on the substrate; and step D: removing the photoresist remaining on the surface of the substrate. The method can not only correct the proximity effect, but also avoid the occupation of extra substrate area by the auxiliary pattern.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device fabrication technology, and in particular to an electron beam lithography method and a semiconductor device. Background Technology

[0002] Electron beam lithography is widely used in micro- and nano-fabrication. As pattern sizes shrink, the electron beam proximity effect becomes increasingly severe, leading to distortion in the lithographic patterns. The electron beam proximity effect primarily results in forward scattering of incident electrons from photoresist atoms and backscattering from substrate atoms. This causes the energy of the incident electrons to not be localized at the incident point, but rather to be laterally distributed within the photoresist, resulting in uneven energy distribution across the pattern and energy distribution outside the pattern itself. Existing techniques use auxiliary pattern exposure to modulate the energy distribution of the device areas on the pattern to correct energy deposition. However, existing methods for correcting the proximity effect using auxiliary patterns require additional pattern area, which is detrimental to high-density device integration. Summary of the Invention

[0003] Based on the above analysis, the present invention aims to provide an electron beam lithography method and semiconductor device to solve the problem that existing methods using auxiliary patterns to correct proximity effects occupy additional layout area, which is not conducive to high-density device integration.

[0004] On one hand, the present invention provides an electron beam lithography method, the method comprising the following steps:

[0005] Step A: Form a photoresist layer on the substrate;

[0006] Step B: Form device patterns and auxiliary patterns on the photoresist layer by exposure and development, wherein the device patterns and the auxiliary patterns are exposed with different dose levels so that the auxiliary patterns are not completely developed in the development process, thereby preventing the auxiliary patterns from being etched onto the substrate in the subsequent etching process.

[0007] Step C: Etching to form device patterns on the substrate;

[0008] Step D: Remove residual photoresist from the substrate surface.

[0009] Preferably, in step B, grayscale exposure technology is used to expose the device pattern and the auxiliary pattern with different levels of dose.

[0010] Preferably, in step B, the device pattern is exposed with a dose greater than or equal to the development threshold, and the auxiliary pattern is exposed with a dose less than the development threshold.

[0011] Preferably, in step B, the exposure dose of the auxiliary pattern is such that the remaining photoresist thickness after the auxiliary pattern is developed is sufficient to prevent the auxiliary pattern from being etched onto the substrate during subsequent etching processes.

[0012] Preferably, in step B, the exposure dose of the auxiliary pattern is such that the thickness of the photoresist remaining after the auxiliary pattern is developed is greater than or equal to the thickness of the auxiliary pattern etched during the subsequent etching process.

[0013] Preferably, step A further includes: baking the substrate coated with the photoresist layer and then cooling it to room temperature.

[0014] Preferably, in step B, the exposure is performed in an electron beam lithography machine.

[0015] Preferably, in step C, the etching is performed in a plasma etching machine.

[0016] Preferably, in step D, acetone immersion is used to remove residual photoresist on the substrate surface.

[0017] On the other hand, the present invention also provides a semiconductor device, which is prepared by the above-described electron beam lithography method.

[0018] Compared with the prior art, the present invention can achieve at least one of the following beneficial effects:

[0019] 1. This invention employs different exposure dose levels for the device pattern and auxiliary pattern to ensure that the auxiliary pattern is not fully developed during the development process. The undeveloped photoresist in the auxiliary pattern protects the underlying substrate from subsequent etching, preventing the auxiliary pattern from being etched onto the substrate. This solves the proximity effect problem caused by uneven pattern energy, while avoiding the need for additional substrate area due to the auxiliary pattern, thus facilitating the fabrication of large-area, high-density devices.

[0020] 2. The present invention uses grayscale exposure technology to expose the device pattern and the auxiliary pattern with different dose levels. Grayscale exposure technology makes the residual thickness of the photoresist after development different. The auxiliary pattern is exposed with energy less than the development threshold, so that the auxiliary pattern still has a certain photoresist thickness after development. Therefore, the auxiliary pattern will not be transferred to the substrate in subsequent etching, and will not affect the auxiliary pattern's correction of proximity effect.

[0021] In this invention, the above-described technical solutions can be combined with each other to achieve more preferred combinations. Other features and advantages of this invention will be set forth in the following description, and some advantages may become apparent from the description or be learned by practicing the invention. The objects and other advantages of this invention can be realized and obtained from what is particularly pointed out in the description and drawings. Attached Figure Description

[0022] The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Throughout the drawings, the same reference numerals denote the same parts.

[0023] Figure 1 The raster pattern after raster development without the use of auxiliary patterns;

[0024] Figure 2 The grating pattern without auxiliary patterns is developed and then etched onto the silicon wafer;

[0025] Figure 3 The raster pattern after raster development using auxiliary patterns;

[0026] Figure 4 This is a process diagram of the electron beam etching method of the present invention;

[0027] Figure 5 The grating pattern after exposure and development in Example 1;

[0028] Figure 6 The pattern of the silicon grating device obtained in Example 1;

[0029] Figure 7 This is a graph showing the thickness of PMMA950k photoresist remaining after development at different energies.

[0030] Figure label:

[0031] 1-Substrate; 2-Photoresist layer; 3-Device pattern; 4-Auxiliary pattern. Detailed Implementation

[0032] Preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings, which form part of this application and are used together with the embodiments of the present invention to illustrate the principles of the present invention, but are not intended to limit the scope of the present invention.

[0033] The electron beam lithography process is as follows: A layer of electron beam photoresist is spin-coated onto the substrate material. Then, an electron beam is used to draw a pattern on the photoresist. The photoresist areas irradiated by the electron beam dissolve in the developer (positive photoresist), while other areas do not undergo significant changes, ultimately forming the photoresist pattern. The negative photoresist process is the opposite: the irradiated photoresist areas are preserved in the developer, while other areas are dissolved, forming the photoresist pattern.

[0034] Due to electron scattering, the energy distribution in the photoresist varies, causing pattern distortion. Large or high-density pattern areas are greatly affected by the exposure of surrounding pixels, resulting in higher final energy. Conversely, small or low-density pattern areas have fewer exposed pixels around them, leading to relatively lower received energy. The end result is uneven energy distribution across the entire pattern area, causing pattern distortion after development.

[0035] By introducing additional exposure patterns (auxiliary patterns), the pattern energy distribution of the areas that actually need exposure can be modulated.

[0036] from Figure 1 As can be seen, without the auxiliary pattern, the uneven energy distribution is clearly visible after grating development. Due to this uneven energy distribution, the correct grating pattern cannot be obtained on the silicon wafer after etching, such as... Figure 2 As shown, the area within the dashed box is the area on the layout where the raster should exist. In addition to the loss of the graphic, the center cannot correctly reproduce the raster graphic.

[0037] Figure 3 The grating pattern is corrected using an auxiliary pattern. As can be seen, after development, the energy is evenly distributed and the grating pattern is complete.

[0038] Although auxiliary pattern exposure can modulate and correct energy without the need for any optimization software calculations, the auxiliary patterns in electron beam lithography are usually etched onto the substrate during the etching process, just like the device patterns, occupying additional layout area and ultimately affecting the usable area of ​​the substrate, which is not conducive to high-density device integration.

[0039] Therefore, the present invention provides an electron beam lithography method, such as... Figure 4 As shown, the method includes the following steps:

[0040] Step A: Form a photoresist layer 2 on substrate 1 to obtain... Figure 4 (a) structure in the text;

[0041] Step B: Device pattern 3 and auxiliary pattern 4 are formed on photoresist layer 2 through exposure and development. The device pattern 3 and auxiliary pattern 4 are exposed using different dose levels, so that auxiliary pattern 4 is not completely developed during the development process, thus preventing it from being etched onto substrate 1 during subsequent etching. Figure 4 (b) structure in the text;

[0042] Step C: Etching to form device pattern 3 on substrate 1;

[0043] Step D: Remove the residual photoresist from the surface of substrate 1 to obtain Figure 4 The (c) structure in the text.

[0044] Compared with existing technologies, this invention uses different dose levels for the exposure of the device pattern and the auxiliary pattern, ensuring that the auxiliary pattern is not fully developed during the development process. The undeveloped photoresist in the auxiliary pattern protects the underlying substrate from subsequent etching, thus preventing the auxiliary pattern from being etched onto the substrate. This solves the problem of proximity effect caused by uneven pattern energy, while avoiding the need for additional substrate area due to the auxiliary pattern, which is beneficial for the fabrication of large-area, high-density devices.

[0045] Specifically, in step B, grayscale exposure technology is used to expose the device pattern 3 and the auxiliary pattern 4 to different levels of dose.

[0046] Specifically, grayscale exposure technology refers to setting different grayscale values ​​for different areas, so that different areas of the photoresist are exposed with different exposure doses. This results in different energy absorption by different exposure areas within the photoresist, which in turn leads to different photoresist development rates and different thickness distributions after development in different areas.

[0047] This invention employs grayscale exposure technology to expose the device pattern and the auxiliary pattern with different dose levels. Grayscale exposure technology results in different residual thicknesses of the photoresist after development, ensuring that the auxiliary pattern still has a certain photoresist thickness after development. This prevents the auxiliary pattern from transferring onto the substrate during subsequent etching and also does not affect the auxiliary pattern's correction of proximity effect.

[0048] For example, in step B, the device pattern 3 is exposed with a dose greater than or equal to the development threshold, and the auxiliary pattern 4 is exposed with a dose less than the development threshold.

[0049] Furthermore, in step B, the exposure dose of the auxiliary pattern 4 is such that the photoresist thickness remaining after the auxiliary pattern 4 is developed is sufficient to prevent the auxiliary pattern 4 from being etched onto the substrate 1 during subsequent etching processes.

[0050] Furthermore, in step B, the exposure dose of the auxiliary pattern 4 is such that the thickness of the photoresist remaining after the auxiliary pattern 4 is developed is greater than or equal to the thickness of the auxiliary pattern 4 etched during the subsequent etching process.

[0051] For example, the dose used to expose the auxiliary pattern 4 is 30%-75% of the dose used to expose the device pattern 3.

[0052] In this invention, by setting the exposure dose of the required pattern in the device area to be greater than or equal to the full development threshold, and the exposure dose of the pattern in the auxiliary pattern area to be between less than the full development threshold and greater than the initial development threshold (i.e., the grayscale area, the transition area between full and incomplete development), the exposed pattern in the device pattern area can be fully developed after the photoresist is developed, while the auxiliary pattern area has a certain thickness of photoresist residue as needed. Specifically, the method for determining the exposure dose of the device pattern 3 and the auxiliary pattern 4 includes:

[0053] (1) Design a series of photoresist blocks of the same size and at equal intervals. Each photoresist block is exposed with a dose, and then the thickness of the residual photoresist in each block is measured after development.

[0054] (2) Obtain the relationship curve between exposure dose (exposure energy) and normalized residual photoresist thickness;

[0055] (3) Based on the relationship curve between exposure dose and normalized residual photoresist thickness, a uniform energy (greater than or equal to the development threshold) is used to expose the device pattern area, while the auxiliary pattern is exposed with the appropriate energy according to the residual photoresist thickness required in the subsequent etching process.

[0056] For example, the photoresist is PMMA 950K with a thickness of 900nm.

[0057] Figure 7 The curve showing the relationship between exposure dose and normalized residual photoresist thickness for PMMA 950K photoresist is presented. Figure 7 It can be seen that when the exposure dose is less than 100uC / cm 2 The residual photoresist thickness remained essentially unchanged, meaning the photoresist thickness did not decrease; when the exposure dose exceeded 100 μC / cm... 2 Less than 700uC / cm 2 The residual thickness of the photoresist decreases slowly but significantly with increasing exposure dose, meaning this dose range falls within the grayscale region. Within this grayscale region, the residual thickness of the photoresist can vary depending on the exposure dose. Specifically, the photoresist thickness begins to decrease at exposure energy values ​​(100 μC / cm²). 2 The initial development threshold is 700 μC / cm². 2The above indicates that the residual photoresist thickness is 0, meaning the photoresist has been completely developed, which is the complete development threshold (700 uC / cm). 2 Therefore, PMMA 950K photoresist can effectively control the residual thickness of the photoresist by controlling the exposure dose.

[0058] Specifically, for PMMA 950K photoresist, device pattern 3 uses a temperature greater than 800 μC / cm. 2 The exposure dose is set, and auxiliary pattern 4 is based on the required residual photoresist thickness during subsequent etching processes at 100 μC / cm. 2 -700uC / cm 2 Select the appropriate dose for exposure within the specified range.

[0059] For example, the substrate 1 is a silicon substrate.

[0060] For example, the device pattern 3 is a silicon grating structure.

[0061] For example, the thickness of the photoresist layer 2 is 800-1000nm, such as 850mm, 900mm, 950mm, etc.

[0062] In step A, forming a photoresist layer 2 on the substrate 1 includes: spin-coating a layer of photoresist onto the cleaned silicon substrate surface.

[0063] For example, step A further includes: baking the substrate 1 coated with photoresist layer 2 and then cooling it to room temperature.

[0064] Specifically, the silicon substrate coated with photoresist layer 2 is baked on a hot plate at 180-190°C for 3-5 minutes, and then cooled to room temperature.

[0065] For example, in step B, the exposure is performed in an electron beam lithography machine.

[0066] Specifically, the device is placed in an electron beam lithography machine, and the exposure doses of the device pattern 3 and the auxiliary pattern 4 are set respectively for exposure.

[0067] After exposure, the device is placed in the developer solution and developed at room temperature, and then fixed.

[0068] For example, the developing time is 80-100 seconds and the fixing time is 50-70 seconds.

[0069] For example, the developer is IPA:MIBK = 3:1 (volume ratio), and the fixing uses pure IPA.

[0070] For example, in step C, the etching is performed in a plasma etching machine.

[0071] Specifically, the developed and fixed device is placed in a plasma etching machine and etched using a silicon etching process, including: gas 1 is C4F8 with a flow rate of 45-50 SCCM; gas 2 is SF6 with a flow rate of 20-25 SCCM; etching power is 400-500W; temperature is 5-6℃; etching time is 110-130 seconds; and etching depth is 180-250nm.

[0072] For example, in step D, the residual photoresist on the surface of substrate 1 is removed by immersion in acetone.

[0073] Specifically, the etched device is immersed in acetone for 10-15 minutes to remove residual photoresist, then cleaned in IPA for 2-4 minutes, and finally rinsed with pure water.

[0074] On the other hand, the present invention also provides a semiconductor device, which is prepared by the above-described electron beam lithography method.

[0075] Specifically, the substrate of the semiconductor device has only the device pattern and no auxiliary patterns, resulting in high device integration density; furthermore, the device pattern is accurate and undistorted.

[0076] For example, the semiconductor device is a silicon grating device.

[0077] The electron beam lithography method and semiconductor device of the present invention will be further illustrated below through specific embodiments.

[0078] Example 1

[0079] This embodiment provides an electron beam lithography method for fabricating silicon grating devices, including:

[0080] Step A: Spin-coat a layer of PMMA 950k photoresist with a thickness of 900nm onto the cleaned silicon substrate surface. Bake the silicon substrate with the photoresist coating on a hot plate at 180℃ for 3 minutes, and then cool it to room temperature.

[0081] Step B: Place the device in an electron beam lithography machine. Use grayscale exposure technology to set the exposure dose for device pattern 3 and auxiliary pattern 4 respectively. Device pattern 3 and auxiliary pattern 4 are exposed with different dose levels to prevent auxiliary pattern 4 from being completely developed during the development process and to prevent auxiliary pattern 4 from being etched onto the substrate 1 in the subsequent etching process. Device pattern 3 is exposed with a dose equal to the development threshold, while auxiliary pattern 4 is exposed with a dose less than the development threshold. The exposure dose of device pattern 3 is 850 uC / cm. 2 The exposure dose for auxiliary pattern 4 is 600 uC / cm. 2 ;

[0082] The exposed device was placed in the developer solution and developed for 90 seconds at room temperature, followed by fixing for 60 seconds; the developer solution was IPA:MIBK = 3:1 (volume ratio), and the fixing was done with pure IPA.

[0083] Step C: Place the developed and fixed device into a plasma etching machine and perform etching using a silicon etching process, including: gas 1 is C4F8 with a flow rate of 45 SCCM; gas 2 is SF6 with a flow rate of 20 SCCM; etching power is 450W; temperature is 5℃; etching time is 120 seconds; and etching depth is 200nm.

[0084] Step D: Immerse the etched device in acetone for 10 minutes to remove residual photoresist, then clean it in IPA for 2 minutes, and finally rinse the device with pure water. The silicon grating device is obtained.

[0085] Figure 5 This is the grating pattern (device pattern) after exposure and development in this embodiment. It can be seen that the energy distribution of the grating pattern is uniform after development. Figure 6 The image shows the silicon grating device obtained in this embodiment. It can be seen that the grating pattern on the silicon grating device is correctly presented, and there are no auxiliary patterns around it. That is, the auxiliary patterns are not etched on the substrate, and the auxiliary patterns do not occupy additional substrate area, which is beneficial for high-density integration of the device.

[0086] Comparative Example 1

[0087] This comparative example provides an electron beam lithography method for fabricating silicon grating devices, including:

[0088] Step A: Spin-coat a layer of PMMA 950k photoresist with a thickness of 900nm onto the cleaned silicon substrate surface. Bake the silicon substrate with the photoresist coating on a hot plate at 180℃ for 3 minutes, and then cool it to room temperature.

[0089] Step B: Place the device in the electron beam lithography machine and set the exposure dose of device pattern 3 to 850 μC / cm. 2 Expose it;

[0090] The exposed device was placed in the developer solution and developed for 90 seconds at room temperature, followed by fixing for 60 seconds; the developer solution was IPA:MIBK = 3:1 (volume ratio), and the fixing was done with pure IPA.

[0091] Step C: Place the developed and fixed device into a plasma etching machine and perform etching using a silicon etching process, including: gas 1 is C4F8 with a flow rate of 45 SCCM; gas 2 is SF6 with a flow rate of 20 SCCM; etching power is 450W; temperature is 5℃; etching time is 120 seconds; and etching depth is 200nm.

[0092] Step D: Immerse the etched device in acetone for 10 minutes to remove residual photoresist, then clean it in IPA for 2 minutes, and finally rinse the device with pure water. The silicon grating device is obtained.

[0093] This comparative example does not use auxiliary graphics for proximity effect correction; the energy of the developed raster pattern is as follows: Figure 1 As shown, it can be seen that without an auxiliary pattern, the uneven energy distribution is clearly visible after grating development. Due to this uneven energy distribution, the correct grating pattern cannot be obtained on the silicon wafer after etching, as shown in the image. Figure 2 As shown.

[0094] Comparative Example 2

[0095] This comparative example provides an electron beam lithography method for fabricating silicon grating devices, including:

[0096] Step A: Spin-coat a layer of PMMA 950k photoresist with a thickness of 900nm onto the cleaned silicon substrate surface. Bake the silicon substrate with the photoresist coating on a hot plate at 180℃ for 3 minutes, and then cool it to room temperature.

[0097] Step B: Place the device in the electron beam lithography machine and set the exposure dose of device pattern 3 to 850 μC / cm. 2 The exposure dose for auxiliary pattern 4 is 850 uC / cm. 2 ;

[0098] The exposed device was placed in the developer solution and developed for 90 seconds at room temperature, followed by fixing for 60 seconds; the developer solution was IPA:MIBK = 3:1 (volume ratio), and the fixing was done with pure IPA.

[0099] Step C: Place the developed and fixed device into a plasma etching machine and perform etching using a silicon etching process, including: gas 1 is C4F8 with a flow rate of 45 SCCM; gas 2 is SF6 with a flow rate of 20 SCCM; etching power is 450W; temperature is 5℃; etching time is 120 seconds; and etching depth is 200nm.

[0100] Step D: Immerse the etched device in acetone for 10 minutes to remove residual photoresist, then clean it in IPA for 2 minutes, and finally rinse the device with pure water. The silicon grating device is obtained.

[0101] This comparison uses auxiliary graphics to correct for proximity effects. Figure 3The comparison model shows the grating pattern after correction using an auxiliary pattern. It can be seen that the energy is evenly distributed and the grating pattern is complete after development using the grating pattern corrected by the auxiliary pattern. However, since the device pattern and the auxiliary pattern are exposed with the same dose, the auxiliary pattern will also be etched onto the substrate during the etching process. The comparison model shows that the substrate of the silicon grating device has both the device pattern and the auxiliary pattern, which is not conducive to high-density integration of the device.

[0102] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.

Claims

1. An electron beam lithography method, characterized in that, The method includes the following steps: Step A: Form a photoresist layer (2) on the substrate (1); Step B: A device pattern (3) and an auxiliary pattern (4) are formed on the photoresist layer (2) by exposure and development. The device pattern (3) and the auxiliary pattern (4) are exposed with different dose levels so that the auxiliary pattern (4) is not fully developed in the development process. The undeveloped photoresist in the auxiliary pattern can protect the substrate below from subsequent etching, so that the auxiliary pattern (4) is not etched onto the substrate (1) in the subsequent etching process. This can both modulate the pattern energy distribution of the area that really needs to be exposed by the auxiliary pattern to solve the problem of proximity effect caused by uneven pattern energy, and at the same time, it will not occupy additional substrate area due to the introduction of the auxiliary pattern. Grayscale exposure technology is used to expose the device pattern (3) and the auxiliary pattern (4) with different dose levels; the dose of exposure of the auxiliary pattern (4) is such that the photoresist thickness remaining after the auxiliary pattern (4) is developed is sufficient to prevent the auxiliary pattern (4) from being etched onto the substrate (1) in the subsequent etching process; Step C: Etching to form device pattern (3) on substrate (1); Step D: Remove residual photoresist from the surface of substrate (1); The semiconductor device prepared by the electron beam lithography method has only the device pattern on the substrate and no auxiliary patterns around it, resulting in high device integration density; moreover, the device pattern is correct and undistorted.

2. The method according to claim 1, characterized in that, In step B, the device pattern (3) is exposed with a dose greater than or equal to the development threshold, and the auxiliary pattern (4) is exposed with a dose less than the development threshold.

3. The method according to claim 1, characterized in that, In step B, the exposure dose of the auxiliary pattern (4) is such that the thickness of the photoresist that remains after the auxiliary pattern (4) is developed is greater than or equal to the thickness of the auxiliary pattern (4) etched during the subsequent etching process.

4. The method according to claim 1, characterized in that, Step A also includes: baking the substrate (1) coated with photoresist layer (2) and then cooling it to room temperature.

5. The method according to claim 1, characterized in that, In step B, the exposure is performed in an electron beam lithography machine.

6. The method according to claim 1, characterized in that, In step C, the etching is performed in a plasma etching machine.

7. The method according to claim 1, characterized in that, In step D, the photoresist remaining on the surface of the substrate (1) is removed by immersion in acetone.

8. A semiconductor device, characterized in that, The semiconductor device is fabricated using the electron beam lithography method according to any one of claims 1-7.

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