Controller parameter determination method, device, test equipment and readable storage medium

Abstract

The embodiments of the present application provide a controller parameter determination method, apparatus, test equipment, and readable storage medium, relating to the field of computer technology. In the embodiments of the present application, the test equipment can perform cyclic testing on the controller under test. When the integrity of the latched data of the controller under test changes, the power-off sleep duration threshold of the controller under test in the previous test cycle or the power-off sleep duration threshold of the current test cycle can meet the requirement that the controller under test latches all data and the requirement that the controller under test stop working in a timely manner. Therefore, the most preferred sleep duration of the controller can be determined through the embodiments of the present application.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a controller parameter determination method, device, testing equipment, and readable storage medium. Background Art

[0002] Currently, when the controller stops working, it first enters the power-off state and then the power-down state. While in the power-off state, the controller can store important information in the storage unit, and the controller still consumes power. In the power-down state, the controller stops working and does not consume power.

[0003] In order to avoid unnecessary power consumption, the controller's power-off sleep state should be ended as soon as possible in practical applications. Therefore, how to determine a reasonable controller sleep time is an urgent problem that needs to be solved. Summary of the Invention

[0004] In view of this, embodiments of the present application provide a controller parameter determination method, apparatus, testing device, and readable storage medium to determine the most preferred sleep duration of the controller.

[0005] In a first aspect, a controller parameter determination method is provided, the method being applied to a test device, the method comprising:

[0006] Determining controller parameters of the controller to be tested in the current test cycle, wherein the controller parameters include a power-off sleep time threshold;

[0007] Powering on and waking up the controller under test;

[0008] Controlling the controller to be tested to enter a power-off dormant state so that a predetermined storage unit latches data;

[0009] In response to the duration of the controller under test entering the power-off sleep state reaching the power-off sleep duration threshold, cutting off power supply to the controller under test; and

[0010] In response to a change in the integrity of the latched data of the controller to be tested, target controller parameters are determined according to controller parameters of a previous test cycle or a current test cycle.

[0011] In a second aspect, a controller parameter testing system is provided, the system comprising:

[0012] The controller under test is configured to send data to a predetermined storage unit in response to entering a power-down dormant state;

[0013] The predetermined storage unit is configured to receive data sent by the controller to be tested; and

[0014] The test equipment is configured to perform the following steps:

[0015] Determining controller parameters of the controller to be tested in the current test cycle, wherein the controller parameters include a power-off sleep time threshold;

[0016] Powering on and waking up the controller under test;

[0017] Controlling the controller to be tested to enter a power-off dormant state so that a predetermined storage unit latches data;

[0018] In response to the duration of the controller under test entering the power-off sleep state reaching the power-off sleep duration threshold, cutting off power supply to the controller under test; and

[0019] In response to a change in the integrity of the latched data of the controller to be tested, target controller parameters are determined according to controller parameters of a previous test cycle or a current test cycle.

[0020] In a third aspect, a controller parameter determination device is provided, the device being applied to a test device, the device comprising:

[0021] A controller parameter determination module is used to determine the controller parameters of the controller to be tested in the current test cycle, wherein the controller parameters include a power-off sleep time threshold;

[0022] A power-on wake-up module, used for powering on and waking up the controller under test;

[0023] A power-off dormancy module, configured to control the controller to be tested to enter a power-off dormancy state, so that a predetermined storage unit latches data;

[0024] a power supply control module, configured to cut off power supply to the controller under test in response to a time duration during which the controller under test enters a power-off sleep state reaching a power-off sleep time duration threshold; and

[0025] The target controller parameter determination module is configured to determine target controller parameters according to controller parameters of a previous test cycle or a current test cycle in response to a change in the integrity of the latched data of the controller to be tested.

[0026] In a fourth aspect, an embodiment of the present application provides a testing device comprising a memory and a processor, wherein the memory is used to store one or more computer program instructions, wherein the one or more computer program instructions are executed by the processor to implement the method described in the first aspect.

[0027] In a fifth aspect, an embodiment of the present application provides a computer-readable storage medium on which computer program instructions are stored. When the computer program instructions are executed by a processor, the method described in the first aspect is implemented.

[0028] In a sixth aspect, an embodiment of the present application provides a computer program product, comprising a computer program / instruction, which, when executed by a processor, implements the method described in the first aspect.

[0029] In an embodiment of the present application, the test equipment can perform cyclic testing on the controller under test. When the integrity of the data latched by the controller under test changes, the power-off sleep duration threshold of the controller under test in the previous test cycle or the power-off sleep duration threshold of the current test cycle can both meet the requirement that the controller under test latches all data and meet the requirement that the controller under test stop working in a timely manner. Therefore, the embodiment of the present application can determine the optimal sleep duration for the controller. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above and other objects, features and advantages of the embodiments of the present application will become more apparent through the following description of the embodiments of the present application with reference to the accompanying drawings, in which:

[0031] Figure 1 A schematic diagram of a controller parameter determination system according to an embodiment of the present application;

[0032] Figure 2 This is a flow chart of a method for determining controller parameters according to an embodiment of the present application;

[0033] Figure 3 Schematic diagram of the controller to be tested according to an embodiment of the present application;

[0034] Figure 4 A schematic diagram of another controller to be tested according to an embodiment of the present application;

[0035] Figure 5 A schematic diagram of another controller to be tested according to an embodiment of the present application;

[0036] Figure 6 This is a flow chart of another controller parameter determination method according to an embodiment of the present application;

[0037] Figure 7 This is a flow chart of another controller parameter determination method according to an embodiment of the present application;

[0038] Figure 8 This is a schematic structural diagram of a device for determining controller parameters according to an embodiment of the present application;

[0039] Figure 9 A schematic diagram of the structure of a test device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0040] The present application is described below based on the following embodiments, but the present application is not limited to these embodiments. In the detailed description of the present application below, certain specific details are described in detail. Those skilled in the art can fully understand the present application without the description of these details. To avoid obscuring the essence of the present application, well-known methods, processes, procedures, components, and circuits are not described in detail.

[0041] Furthermore, persons of ordinary skill in the art will appreciate that the figures provided herein are for illustration purposes only and are not necessarily drawn to scale.

[0042] Unless the context clearly requires otherwise, words like “include”, “comprising” and the like in the specification should be interpreted as including rather than exclusive or exhaustive; that is, as “including but not limited to”.

[0043] In the description of this application, it should be understood that the terms "first", "second", etc. are used for descriptive purposes only and should not be understood to indicate or imply relative importance. In addition, in the description of this application, unless otherwise specified, "plurality" means two or more.

[0044] In related technologies, the duration of a controller's sleep state is typically manually determined based on past experience. However, this manually determined sleep duration is not always optimal. On the one hand, if the manually determined sleep duration is too long, the controller will consume excessive power. On the other hand, if the manually determined sleep duration is too short, the controller may have incomplete data latches or even lose data.

[0045] In order to solve the above problems, the present application provides a controller parameter determination system, specifically, Figure 1 As shown, the system includes: a controller to be tested 11 , a predetermined storage unit 12 and a testing device 13 .

[0046] The controller under test 11 may be configured to send data to a predetermined storage unit 12 in response to entering a power-down sleep state.

[0047] The predetermined storage unit 12 may be configured to receive and latch data sent by the controller under test 11 .

[0048] The test device 13 can determine the target controller parameters of the controller to be tested by a cyclic test, specifically, Figure 2 As shown, the test device 13 can be configured to perform the following steps:

[0049] In step 21 , controller parameters of the controller to be tested in the current test cycle are determined.

[0050] The controller parameter includes a power-off sleep time threshold, which may be a time threshold determined based on an initial value, and the initial value may be an applicable value, such as 50 milliseconds (ms).

[0051] In one case, the embodiment of the present application may first determine a larger power-off sleep time threshold, and then gradually shorten the power-off sleep time threshold in each test cycle until the target controller parameters are determined.

[0052] Specifically, in this case, step 21 can be executed as follows: in response to the data latched in the predetermined storage unit in the previous test cycle being complete data, the power-off sleep time threshold of the previous test cycle is shortened by a predetermined time to determine the power-off sleep time threshold of the current test cycle.

[0053] The predetermined time length may be an applicable value, such as 100 microseconds (μs).

[0054] In an embodiment of the present application, if the data latched by the controller under test into the predetermined storage unit in the previous test cycle is complete data, the power-off sleep time threshold representing the previous test cycle can ensure that the controller under test latches all data, but whether the sleep time of the controller under test reaches the shortest sleep time still needs further testing.

[0055] Therefore, the embodiment of the present application can further shorten the power-off sleep time threshold, and use the shortened power-off sleep time threshold as a controller parameter of the current test cycle.

[0056] In another case, the embodiment of the present application may first determine a smaller power-off sleep time threshold, and then gradually increase the power-off sleep time threshold in each test cycle until the target controller parameters are determined.

[0057] Specifically, in this case, step 21 can be executed as follows: in response to the data latched in the predetermined storage unit in the previous test cycle being incomplete data, the power-off sleep time threshold of the previous test cycle is increased by a predetermined time to determine the power-off sleep time threshold of the current test cycle.

[0058] In this embodiment of the present application, if the data latched by the controller under test into the predetermined storage unit in the previous test cycle is incomplete data, then the power-down sleep time threshold representing the previous test cycle cannot guarantee that the controller under test latches all the data. Therefore, in this embodiment of the present application, the power-down sleep time threshold can be further increased, and the increased power-down sleep time threshold can be used as a controller parameter for the current test cycle.

[0059] In step 22 , the controller under test is powered on to wake up.

[0060] Since the embodiment of the present application needs to determine the power-down sleep time threshold of the controller under test through periodic testing, the test equipment needs to power on and wake up the controller under test in each test cycle.

[0061] In a preferred embodiment, the test device can control the controller under test through the pins of the controller under test. Specifically, the controller under test may include a power supply pin and a sleep control pin. The sleep control pin can be used to control the controller under test to power down and power up.

[0062] Specifically, the power supply pin can be KL30, and the sleep control pin can be KL15. In actual applications, KL30 can be used to control whether the controller under test is in a powered state. If the controller under test needs to remain powered, KL30 pin must be continuously connected to a 12V power supply. KL15 can be used to control the on and off of the controller under test. When KL15 is connected to a 12V power supply, the controller under test enters a powered-on wake-up state. When KL15 is disconnected from the 12V power supply, the controller under test enters a powered-off sleep state.

[0063] Furthermore, in a preferred embodiment, the above step 22 may be performed as follows: powering on the power supply pin and the sleep control pin to put the controller under test in a power-on wake-up state.

[0064] For example, Figure 3 As shown, Figure 3 This is a schematic diagram of a controller under test according to an embodiment of the present application, wherein the schematic diagram includes: a controller under test 31 , wherein the controller under test 31 includes a power supply pin 311 and a sleep control pin 312 .

[0065] exist Figure 3 In the scenario shown, since the power supply pin 311 and the sleep control pin 312 are both in the power-on state, the controller to be tested 31 is in the power-on awake state.

[0066] In step 23 , the controller under test is controlled to enter a power-down sleep state, so that a predetermined storage unit latches data.

[0067] When the controller under test enters the power-on wake-up state, in order to further determine the power-down sleep time threshold applicable to the controller under test, the test equipment needs to control the controller under test to enter the power-down sleep state so that the predetermined storage unit latches data.

[0068] In a preferred embodiment, the test device can control the controller under test through the pins of the controller under test. Specifically, step 23 can be performed as follows: cutting off the current through the sleep control pin to put the controller under test into a power-off sleep state.

[0069] For example, Figure 4 As shown, Figure 4 Schematic diagram of a controller under test according to an embodiment of the present application, wherein the schematic diagram includes: a controller under test 41 , wherein the controller under test 41 includes a power supply pin 411 and a sleep control pin 412 .

[0070] exist Figure 4 In the illustrated scenario, since the power supply pin 411 is powered on and the sleep control pins 412 are not powered on, the controller under test 41 is in a power-down sleep state. Furthermore, the controller under test 41 in the power-down sleep state latches data into a predetermined storage unit.

[0071] In step 24 , in response to the time duration during which the controller under test enters the power-off sleep state reaching a power-off sleep time duration threshold, power supply to the controller under test is cut off.

[0072] When the controller under test enters a power-off sleep state, it will latch data into a predetermined storage unit. The data latched by the controller under test can be important data and parameters. For example, in a vehicle scenario, the data latched by the controller under test can be user-configured parameters. These parameters need to be locked into a predetermined storage unit after the controller under test stops working to avoid repeated user configuration.

[0073] In a preferred embodiment, the test device can control the controller under test through the pins of the controller under test. Specifically, step 24 can be performed as follows: cutting off the current passing through the power supply pin.

[0074] For example, Figure 5 As shown, Figure 5 This is a schematic diagram of a controller under test according to an embodiment of the present application, wherein the schematic diagram includes: a controller under test 51 , wherein the controller under test 51 includes a power supply pin 511 and a sleep control pin 512 .

[0075] exist Figure 5 In the illustrated scenario, since the power supply pin 511 is not powered, the controller under test 51 is in a power-off state. If the controller under test 51 has not completed the data latching process, the data in the predetermined storage unit is incomplete. If the controller under test 51 has completed the data latching process, the data in the predetermined storage unit is complete.

[0076] That is, after the test device cuts off the power supply of the controller to be tested, it can be determined whether the power-off sleep time threshold is the most preferred sleep time based on the integrity of the data in the predetermined storage unit.

[0077] In step 25 , in response to a change in the integrity of the latched data of the controller to be tested, target controller parameters are determined based on controller parameters of a previous test cycle or a current test cycle.

[0078] The integrity change of the latched data in the predetermined storage unit may be from complete latching to incomplete latching, or from incomplete latching to complete latching.

[0079] In an embodiment of the present application, the test equipment can perform cyclic testing on the controller under test. When the integrity of the data latched by the controller under test changes, the power-off sleep duration threshold of the controller under test in the previous test cycle or the power-off sleep duration threshold of the current test cycle can both meet the requirement that the controller under test latches all data and meet the requirement that the controller under test stop working in a timely manner. Therefore, the embodiment of the present application can determine the optimal sleep duration for the controller.

[0080] From the above implementation methods, it can be seen that steps 21 to 24 are steps executed in each test cycle. When the test equipment detects that the integrity of the latched data of the controller under test has changed, the test equipment can execute the above step 25 to determine the target controller parameters, which can be used as the sleep duration of the controller under test in actual applications.

[0081] It should be noted that in actual applications, since the amount of data to be stored by the controller each time it is in a power-down sleep state varies, the actual time it takes for the controller to latch data each time will vary.

[0082] However, since the amount of data stored in the controllers in the same usage scenario will not vary significantly, when determining the target controller parameters, the embodiment of the present application can perform a test based on the maximum latched data amount in the scenario to ensure that the target controller parameters can adapt to each controller in the scenario.

[0083] In practical applications, for the purpose of stability and safety, after the target controller parameters are determined, they can be appropriately increased and applied. This can maximize the capabilities of the controller under test while ensuring that over-design does not occur.

[0084] According to the above embodiments, the embodiment of the present application can first determine a larger power-down sleep time threshold, and then gradually shorten the power-down sleep time threshold in each test cycle until the target controller parameters are determined. Alternatively, a smaller power-down sleep time threshold can be first determined, and then gradually increase the power-down sleep time threshold in each test cycle until the target controller parameters are determined.

[0085] Specifically, in a preferred embodiment, step 25 can be executed as follows: in response to the data latched in the predetermined storage unit being incomplete data, and the data latched in the predetermined storage unit in the previous test cycle being complete data, the test is ended, and then the power-off sleep time threshold corresponding to the previous test cycle is determined as the target controller parameter.

[0086] That is, in the embodiment of the present application, the test device first determines a larger power-down sleep time threshold, and then gradually shortens the power-down sleep time threshold in each test cycle. Then, when the data latched by the controller under test in the current test cycle is incomplete data, and the data latched by the controller under test in the previous test cycle is complete data, the test device can determine the power-down sleep time threshold corresponding to the previous test cycle as the target controller parameter. The target controller parameter is the power-down sleep time of the controller under test in actual application.

[0087] Through the embodiments of the present application, the testing device can automatically perform cyclic testing to determine the target controller parameters, thereby improving the efficiency of determining the target controller parameters and determining a preferred target controller parameter.

[0088] In another preferred embodiment, step 25 can be executed as follows: in response to the data latched in the predetermined storage unit being complete data, and the data latched in the predetermined storage unit in the previous test cycle being incomplete data, the test is ended, and then the power-off sleep time threshold corresponding to the current test cycle is determined as the target controller parameter.

[0089] That is, in the embodiment of the present application, the test device first determines a relatively small power-off sleep time threshold, and then gradually increases the power-off sleep time threshold in each test cycle. Then, when the data latched by the controller under test in the current test cycle is complete data, and the data latched by the controller under test in the previous test cycle is incomplete data, the test device can determine the power-off sleep time threshold corresponding to the current test cycle as the target controller parameter, which is the power-off sleep time of the controller under test in actual application.

[0090] Through the embodiments of the present application, the testing device can also automatically perform cyclic testing to determine the target controller parameters, which improves the efficiency of determining the target controller parameters and can also determine a preferred target controller parameter.

[0091] In summary, when the integrity of the latched data of the controller under test changes, the power-off sleep duration threshold of the controller under test in the previous test cycle or the power-off sleep duration threshold of the current test cycle can both meet the requirement that the controller under test latches all data and the requirement that the controller under test stop working in a timely manner. Therefore, the embodiments of the present application can determine the optimal sleep duration for a controller.

[0092] Furthermore, based on the above embodiments, the present application provides an example of gradually determining the target controller parameters based on a larger initial value, such as Figure 6 As shown, the specific steps include:

[0093] In step 61 , the power-off sleep time threshold Y of the previous test cycle is shortened by a predetermined time, and the controller parameter X of the current test cycle is determined.

[0094] The controller parameter X represents the power-off sleep time threshold of the current test cycle of the controller to be tested. As can be seen from the above implementation, X can be determined by shortening Y.

[0095] In step 62, the power supply pin and the sleep control pin are connected to power on and wake up the controller to be tested.

[0096] Among them, the power-on wake-up state of the controller to be tested can refer to Figure 3 The status shown.

[0097] In step 63 , the current passing through the sleep control pin of the controller under test is cut off.

[0098] When the test equipment cuts off the current of the sleep control pin of the controller under test, the controller under test will enter the power-down sleep state and latch the data into the predetermined storage unit. The power-down sleep state of the controller under test can be referred to Figure 4 The status shown.

[0099] In step 64 , in response to the time duration of the controller under test entering the power-down sleep state reaching X, the current passing through the power supply pin of the controller under test is cut off.

[0100] The power-off status of the controller to be tested can be referenced Figure 5 The status shown.

[0101] In step 65, it is determined whether the data latched by the predetermined storage unit in the current test cycle is complete. If the data latched by the predetermined storage unit in the current test cycle is incomplete, that is, the predetermined storage unit has changed from being able to latch complete data in the previous test cycle to being unable to latch complete data, then step 66 is executed. If the data latched by the predetermined storage unit is still complete, then step 61 is executed, that is, the power-down sleep time threshold is shortened to continue the test.

[0102] In step 66, the power-off sleep time threshold Y corresponding to the previous test cycle is determined as the target controller parameter. If the predetermined storage unit changes from being able to latch complete data in the previous test cycle to being unable to latch complete data, then the power-off sleep time threshold representing the previous test cycle is the minimum duration that can ensure complete data latching. Therefore, the power-off sleep time threshold Y corresponding to the previous test cycle can be determined as the target controller parameter.

[0103] After the target controller parameters are determined, the target controller parameters can be applied to actual scenarios as the power-off sleep duration of the controller to be tested.

[0104] In an embodiment of the present application, the test equipment can perform cyclic testing on the controller under test. When the integrity of the data latched by the controller under test changes, the power-off sleep duration threshold of the controller under test in the previous test cycle or the power-off sleep duration threshold of the current test cycle can meet the requirement that the controller under test latches all data and also meet the requirement that the controller under test stop working in a timely manner. Therefore, the embodiment of the present application can determine the optimal sleep duration for a controller.

[0105] In another case, the embodiment of the present application provides an example of gradually determining the target controller parameters based on a smaller initial value, such as Figure 7 As shown, the specific steps include:

[0106] In step 71 , the power-down sleep time threshold Y of the previous test cycle is increased by a predetermined time, and the controller parameter X of the current test cycle is determined.

[0107] The controller parameter X represents the power-off sleep time threshold of the current test cycle of the controller to be tested. As can be seen from the above embodiment, X can be determined by adding Y.

[0108] In step 72, the power supply pin and the sleep control pin are connected to power on and wake up the controller to be tested.

[0109] Among them, the power-on wake-up state of the controller to be tested can refer to Figure 3 The status shown.

[0110] In step 73 , the current passing through the sleep control pin of the controller under test is cut off.

[0111] When the test equipment cuts off the current of the sleep control pin of the controller under test, the controller under test will enter the power-down sleep state and latch the data into the predetermined storage unit. The power-down sleep state of the controller under test can be referred to Figure 4 The status shown.

[0112] In step 74 , in response to the time duration of the controller under test entering the power-down sleep state reaching X, the current passing through the power supply pin of the controller under test is cut off.

[0113] The power-off status of the controller to be tested can be referenced Figure 5 The status shown.

[0114] In step 75, it is determined whether the data latched by the predetermined storage unit in the current test cycle is complete. If the data latched by the predetermined storage unit in the current test cycle is complete, that is, the predetermined storage unit has been able to latch complete data instead of being unable to latch complete data in the previous test cycle, then step 76 is executed. If the data latched by the predetermined storage unit is still incomplete, then step 71 is executed, that is, the power-off sleep time threshold is increased to continue testing.

[0115] In step 76, the power-off sleep time threshold X corresponding to the current test cycle is determined as the target controller parameter. If the predetermined storage unit is able to latch complete data instead of being unable to latch complete data in the previous test cycle, then the power-off sleep time threshold for the current test cycle is the minimum duration that can ensure complete data latching. Therefore, the power-off sleep time threshold X corresponding to the current test cycle can be determined as the target controller parameter.

[0116] After the target controller parameters are determined, the target controller parameters can be applied to actual scenarios as the power-off sleep duration of the controller to be tested.

[0117] In an embodiment of the present application, the test equipment can perform cyclic testing on the controller under test. When the integrity of the data latched by the controller under test changes, the power-off sleep duration threshold of the controller under test in the previous test cycle or the power-off sleep duration threshold of the current test cycle can meet the requirement that the controller under test latches all data and also meet the requirement that the controller under test stop working in a timely manner. Therefore, the embodiment of the present application can determine the optimal sleep duration for a controller.

[0118] Based on the same technical concept, the embodiment of the present application also provides a controller parameter determination device, such as Figure 8 As shown, the device includes: a controller parameter determination module 81 , a power-on wake-up module 82 , a power-off sleep module 83 , a power supply control module 84 and a target controller parameter determination module 85 .

[0119] A controller parameter determination module 81 is used to determine the controller parameters of the controller to be tested in the current test cycle, wherein the controller parameters include a power-off sleep time threshold;

[0120] A power-on wake-up module 82, configured to power-on and wake up the controller to be tested;

[0121] A power-off dormancy module 83 is used to control the controller to be tested to enter a power-off dormancy state so that a predetermined storage unit latches data;

[0122] a power supply control module 84 for cutting off power supply to the controller under test in response to the duration of the controller under test entering the power-off sleep state reaching the power-off sleep duration threshold; and

[0123] The target controller parameter determination module 85 is configured to determine target controller parameters according to controller parameters of a previous test cycle or a current test cycle in response to a change in the integrity of the latched data of the controller to be tested.

[0124] In some embodiments, the controller parameter determination module 81 is specifically configured to:

[0125] In response to the data latched by the predetermined storage unit in the previous test cycle being complete data, the power-off sleep time threshold of the previous test cycle is shortened by a predetermined time to determine the power-off sleep time threshold of the current test cycle.

[0126] In some embodiments, the target controller parameter determination module 85 is specifically configured to:

[0127] In response to the data latched by the predetermined storage unit being incomplete data, and the data latched by the predetermined storage unit in the previous test cycle being complete data, ending the test; and

[0128] The power-off sleep time threshold corresponding to the previous test cycle is determined as the target controller parameter.

[0129] In some embodiments, the controller parameter determination module 81 is specifically configured to:

[0130] In response to the data latched by the predetermined storage unit in the previous test cycle being incomplete data, the power-off sleep time threshold of the previous test cycle is increased by a predetermined time to determine the power-off sleep time threshold of the current test cycle.

[0131] In some embodiments, the target controller parameter determination module 85 is specifically configured to:

[0132] In response to the data latched by the predetermined storage unit being complete data and the data latched by the predetermined storage unit in the previous test cycle being incomplete data, ending the test; and

[0133] The power-off sleep time threshold corresponding to the current test cycle is determined as the target controller parameter.

[0134] In some embodiments, the controller under test includes a power supply pin and a sleep control pin, and the sleep control pin is used to control the power-down sleep state and the power-up wake-up state of the controller under test.

[0135] In some embodiments, the power-on wake-up module 82 is specifically configured to:

[0136] The power supply pin and the sleep control pin are powered on to put the controller under test into a power-on wake-up state.

[0137] In some embodiments, the power-off sleep module 83 is specifically configured to:

[0138] The current passing through the sleep control pin is cut off to put the controller under test into a power-off sleep state.

[0139] In some embodiments, the power supply control module 84 is specifically configured to:

[0140] Cut off the current passing through the power supply pin.

[0141] In an embodiment of the present application, the test equipment can perform cyclic testing on the controller under test. When the integrity of the data latched by the controller under test changes, the power-off sleep duration threshold of the controller under test in the previous test cycle or the power-off sleep duration threshold of the current test cycle can meet the requirement that the controller under test latches all data and also meet the requirement that the controller under test stop working in a timely manner. Therefore, the embodiment of the present application can determine the optimal sleep duration for a controller.

[0142] Figure 9 Schematic diagram of the test equipment of the embodiment of the present application. Figure 9 As shown, Figure 9 The test equipment shown is a general address query device, which includes a general computer hardware structure, which includes at least a processor 91 and a memory 92. The processor 91 and the memory 92 are connected via a bus 93. The memory 92 is suitable for storing instructions or programs executable by the processor 91. The processor 91 can be an independent microprocessor or a collection of one or more microprocessors. Thus, the processor 91 executes the instructions stored in the memory 92, thereby executing the method flow of the embodiment of the present application as described above to realize data processing and control of other devices. The bus 93 connects the above-mentioned multiple components together, and at the same time connects the above-mentioned components to the display controller 94 and the display device and the input / output (I / O) device 95. The input / output (I / O) device 95 can be a mouse, keyboard, modem, network interface, touch input device, somatosensory input device, printer and other devices known in the art. Typically, the input / output device 95 is connected to the system via an input / output (I / O) controller 96.

[0143] It will be understood by those skilled in the art that the embodiments of the present application may be provided as methods, devices (equipment), or computer program products. Therefore, the present application may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Furthermore, the present application may take the form of a computer program product implemented on one or more computer-readable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0144] The present application is described with reference to flowcharts of methods, apparatuses (devices), and computer program products according to embodiments of the present application. It should be understood that each process in the flowcharts can be implemented by computer program instructions.

[0145] These computer program instructions may be stored in a computer-readable memory that can direct a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device that implements the process Figure 1 A function specified in a process or multiple processes.

[0146] These computer program instructions can also be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device produce the instructions for implementing the process Figure 1 A device that specifies functions in a process or multiple processes.

[0147] Another embodiment of the present application relates to a non-volatile storage medium for storing a computer-readable program, wherein the computer-readable program is used to enable a computer to execute part or all of the above method embodiments.

[0148] That is, those skilled in the art will understand that all or part of the steps in the above-mentioned embodiments can be implemented by specifying relevant hardware through a program, which is stored in a storage medium and includes a number of instructions for causing a device (which may be a single-chip microcomputer, chip, etc.) or a processor to execute all or part of the steps of the methods described in the embodiments of the present application. The aforementioned storage medium includes: a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, etc., various media that can store program code.

[0149] Another embodiment of the present application relates to a computer program product, including a computer program / instruction, which can implement some or all of the above method embodiments when executed by a processor.

[0150] That is, those skilled in the art can understand that the embodiments of the present application can specify relevant hardware (including the processor itself) by executing a computer program product (computer program / instructions) through a processor, thereby implementing all or part of the steps in the above-mentioned embodiment method.

[0151] The foregoing is merely a preferred embodiment of the present application and is not intended to limit the present application. Persons skilled in the art will readily appreciate that various modifications and variations are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present application are intended to be within the scope of protection of the present application.

Claims

1. A controller parameter determination method, characterized in that: The method comprises: Determine controller parameters of the controller under test in the current test cycle, wherein the controller parameters include a power-off sleep time threshold; and power on to wake up the controller under test; Controlling the controller under test to enter a power-off dormant state so that the controller under test latches data into a predetermined storage unit; In response to the duration of the controller under test entering the power-off sleep state reaching the power-off sleep duration threshold, cutting off power supply to the controller under test; and determining target controller parameters based on controller parameters of a previous test cycle or a current test cycle in response to a change in the integrity of the latched data of the controller to be tested; The change in the integrity of the latched data of the controller under test includes: a change from complete latching to incomplete latching, or a change from incomplete latching to complete latching.

2. The method according to claim 1, characterized in that Determining the controller parameters of the controller to be tested in the current test cycle includes: In response to the data latched by the predetermined storage unit in the previous test cycle being complete data, the power-off sleep time threshold of the previous test cycle is shortened by a predetermined time to determine the power-off sleep time threshold of the current test cycle.

3. The method according to claim 2, characterized in that In response to a change in the integrity of the latched data of the controller to be tested, determining target controller parameters according to controller parameters of a previous test cycle or a current test cycle includes: In response to the data latched by the predetermined storage unit being incomplete data, and the data latched by the predetermined storage unit in the previous test cycle being complete data, ending the test; And the power-off sleep time threshold corresponding to the previous test cycle is determined as the target controller parameter.

4. The method according to claim 1, wherein The method of determining the controller parameters of the controller to be tested in the current test cycle includes: in response to the data latched in the predetermined storage unit in the previous test cycle being incomplete data, increasing the power-off sleep time threshold of the previous test cycle by a predetermined time to determine the power-off sleep time threshold of the current test cycle.

5. The method according to claim 4, characterized in that In response to a change in the integrity of the latched data of the controller to be tested, determining target controller parameters according to controller parameters of a previous test cycle or a current test cycle includes: In response to the data latched by the predetermined storage unit being complete data, and the data latched by the predetermined storage unit in the previous test cycle being incomplete data, ending the test; And the power-off sleep time threshold corresponding to the current test cycle is determined as the target controller parameter.

6. The method according to claim 1, wherein The controller under test includes a power supply pin and a sleep control pin, and the sleep control pin is used to control the power-down sleep state and the power-up wake-up state of the controller under test.

7. The method according to claim 6, characterized in that The powering on and waking up the controller to be tested includes: energizing the power supply pin and the sleep control pin to put the controller to be tested into a power-on awake state.

8. The method according to claim 6, characterized in that The controlling the controller to be tested to enter the power-down sleep state includes: cutting off the current passing through the sleep control pin, so that the controller to be tested is in the power-down sleep state.

9. The method according to claim 6, characterized in that Cutting off the power supply of the controller to be tested includes: cutting off the current passing through the power supply pin.

10. A controller parameter testing system, characterized in that: The system includes: a controller to be tested, configured to send data to a predetermined storage unit in response to entering a power-off sleep state; the predetermined storage unit is configured to receive data sent by the controller to be tested; and a test device, configured to perform the following steps: determining controller parameters of the controller to be tested in a current test cycle, the controller parameters including a power-off sleep duration threshold; powering on and waking up the controller to be tested; controlling the controller to be tested to enter a power-off sleep state so that a predetermined storage unit latches data; in response to the duration that the controller to be tested enters the power-off sleep state reaching the power-off sleep duration threshold, cutting off power supply to the controller to be tested; and in response to a change in the integrity of the latched data of the controller to be tested, determining target controller parameters based on the controller parameters of a previous test cycle or a current test cycle.

11. A controller parameter determination device, characterized in that: The device comprises: A controller parameter determination module is used to determine the controller parameters of the controller to be tested in the current test cycle, wherein the controller parameters include a power-off sleep time threshold; A power-on wake-up module, used for powering on and waking up the controller under test; a power-off dormancy module, configured to control the controller under test to enter a power-off dormancy state, so that the controller under test latches data into a predetermined storage unit; a power supply control module, configured to cut off power supply to the controller under test in response to a time duration during which the controller under test enters a power-off sleep state reaching a power-off sleep time duration threshold; and a target controller parameter determination module for determining target controller parameters based on controller parameters of a previous test cycle or a current test cycle in response to a change in the integrity of the latched data of the controller to be tested; The change in the integrity of the latched data of the controller under test includes: a change from complete latching to incomplete latching, or a change from incomplete latching to complete latching.

12. A test device comprising a memory and a processor, characterized in that: The memory is configured to store one or more computer program instructions, wherein the one or more computer program instructions are executed by the processor to implement the method according to any one of claims 1 to 9.

13. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method according to any one of claims 1 to 9 is implemented.

14. A computer program product comprising a computer program / instructions, characterized in that When the computer program / instructions are executed by a processor, the method according to any one of claims 1 to 9 is implemented.

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