Current bias generating circuit with controllable temperature coefficient and radio frequency power amplifier

Abstract

The present invention relates to a current bias generating circuit with a controllable temperature coefficient, comprising: a first current subtractor, whose first and second input terminals are connected to current sources Iz1 and Ip, respectively; an output terminal of the subtractor is connected to a first proportional amplifier and then to the input terminal of a current adder; a second current subtractor, whose first and second input terminals are connected to current sources Iz2 and Ip, respectively; an output terminal of the subtractor is connected to a second proportional amplifier and then to the input terminal of a current adder; the input terminal of the current adder is also connected to a current source Iz3; the output terminal of the current adder outputs a bias current source Io. The present invention provides a bias current Io with a controllable temperature coefficient, and the temperature coefficients of different temperature zones are independently controllable, thereby increasing the flexibility and precision of the bias current, providing more precise bias current control for a radio frequency power amplifier, and improving the performance of the radio frequency power amplifier.

Description

Technical Field

[0001] The present invention relates to the field of radio frequency amplification circuits, and more particularly to a current bias generating circuit with a controllable temperature coefficient and a radio frequency amplifier. Background Art

[0002] The current bias generation circuit generates a bias current to provide a stable bias for each module in the integrated circuit. In RF power amplifier (PA) design, the bias current provides the PA with a suitable operating point, enabling the PA to operate with high efficiency and high linearity.

[0003] Because the current of the power tube (HBT) of the RF PA is shown in Formula 1:

[0004] Formula 1: Ic = Is * exp(Vbe / Vt)

[0005] Where Is is the reverse saturation current of the HBT, Vbe is the base-emitter bias voltage, and Vt is the thermal voltage. According to the thermal voltage formula: Vt = kT / q, where T is the thermodynamic temperature, q is the charge per unit electron, and k is the Boltzmann constant, Vt has a positive temperature coefficient.

[0006] The transconductance gm of an HBT refers to the ratio between the change in output current and the change in input voltage, as shown in Formula 2.

[0007] Formula 2: gm = dIc / dVbe = Ic / Vt = Beta*Ib / Vt

[0008] Beta is the current gain of the HBT, Ib is the base bias current, and gm is an important design parameter of the PA. In order to ensure that it remains constant at different temperatures, Ib needs to have a positive temperature coefficient, that is, the bias current generated by the current bias generation circuit needs to have a positive temperature coefficient.

[0009] Existing current bias generation circuits provide bias current with a constant temperature coefficient, which maintains the bias current constant despite temperature changes; or provide bias current with a positive temperature coefficient, which is achieved by using the junction voltage difference between two BJTs (bipolar junction transistors) with different current densities in a bandgap (bandgap reference) structure. However, this solution can only provide a single positive temperature coefficient. Summary of the Invention

[0010] The technical problem to be solved by the present invention is to propose a current bias generating circuit and a radio frequency power amplifier with a controllable temperature coefficient in response to the above-mentioned defects of the prior art.

[0011] The technical solution adopted by the present invention to solve the technical problem is: a current bias generating circuit with controllable temperature coefficient is proposed, comprising: a first current subtractor, a second current subtractor, a first proportional amplifier, a second proportional amplifier and a current adder;

[0012] A first input terminal of the first current subtractor is connected to a current source Ip, a second input terminal of the first current subtractor is connected to a current source Iz1, an output terminal of the first current subtractor is connected to an input terminal of the first proportional amplifier, and an output terminal of the first proportional amplifier is connected to an input terminal of the current adder;

[0013] A first input terminal of the second current subtractor is connected to the current source Iz2, a second input terminal of the second current subtractor is connected to the current source Ip, an output terminal of the second current subtractor is connected to the input terminal of the second proportional amplifier, and an output terminal of the second proportional amplifier is connected to the input terminal of the current adder;

[0014] The input end of the current adder is also connected to the current source Iz3, and the output end of the current adder outputs the bias current source Io.

[0015] In some embodiments, the current source Ip is a current with an original positive temperature coefficient, and the current sources Iz1 , Iz2 , and Iz3 are three currents with constant temperature coefficients.

[0016] In some embodiments, the first current subtractor includes: a MOS transistor m1a, a MOS transistor m2a, a MOS transistor m3a, a MOS transistor m4a, a MOS transistor m5a, and a MOS transistor m6a;

[0017] The drain of the MOS transistor m1a is connected to the current source Ip, the gate of the MOS transistor m1a is short-circuited with the drain of the MOS transistor m1a and connected to the gate of the MOS transistor m2a, and the source of the MOS transistor m1a is grounded;

[0018] The drain of the MOS transistor m2a is connected to the drain of the MOS transistor m3a and to the input end of the first proportional amplifier, and the source of the MOS transistor m2a is grounded;

[0019] The source of the MOS transistor m3a is connected to the source of the MOS transistor m4a and connected to the system power supply. The gate of the MOS transistor m3a is connected to the gate of the MOS transistor m4a. The drain of the MOS transistor m4a is short-circuited with the gate of the MOS transistor m4a and connected to the drain of the MOS transistor m5a.

[0020] The gate of the MOS transistor m5a is connected to the gate of the MOS transistor m6a, the source of the MOS transistor m5a is grounded, the drain of the MOS transistor m6a is connected to the current source Iz1 and short-circuited with the gate of the MOS transistor m6a, and the source of the MOS transistor m6a is grounded.

[0021] In some embodiments, the second current subtractor includes: a MOS transistor m1b, a MOS transistor m2b, a MOS transistor m3b, a MOS transistor m4b, a MOS transistor m5b, and a MOS transistor m6b;

[0022] The drain of the MOS transistor m1b is connected to the current source Iz2, the gate of the MOS transistor m1b is short-circuited with the drain of the MOS transistor m1b and connected to the gate of the MOS transistor m2b, and the source of the MOS transistor m1b is grounded;

[0023] The drain of the MOS transistor m2b is connected to the drain of the MOS transistor m3b and to the input end of the second proportional amplifier, and the source of the MOS transistor m2b is grounded;

[0024] The source of the MOS transistor m3b is connected to the source of the MOS transistor m4b and is connected to the system power supply. The gate of the MOS transistor m3b is connected to the gate of the MOS transistor m4b. The drain of the MOS transistor m4b is short-circuited with the gate of the MOS transistor m4b and is connected to the drain of the MOS transistor m5b.

[0025] The gate of the MOS transistor m5b is connected to the gate of the MOS transistor m6b, the source of the MOS transistor m5b is grounded, the drain of the MOS transistor m6b is connected to the current source Ip and short-circuited with the gate of the MOS transistor m6b, and the source of the MOS transistor m6b is grounded.

[0026] In some embodiments, the first proportional amplifier includes: MOS transistor Mo, MOS transistor M1 ... MOS transistor Mm, where m is a natural number greater than 1;

[0027] The drain and gate of the MOS transistor Mo are connected to the drains of the MOS transistors m2a and m3a, and the source of the MOS transistor Mo is grounded;

[0028] The gates of the MOS transistors M1 to Mm are all connected to the gate of the MOS transistor M0, the drains of the MOS transistors M1 to Mm are all connected to the input end of the current adder, and the sources of the MOS transistors M1 to Mm are all grounded.

[0029] In some embodiments, the second proportional amplifier includes: a MOS transistor Qo, a MOS transistor Q1 ... a MOS transistor Qn, where n is a natural number greater than 2;

[0030] The drain and gate of the MOS transistor Qo are connected to the drains of the MOS transistors m2b and m3b, and the source of the MOS transistor Qo is connected to the system power supply;

[0031] The gates of the MOS transistors Q1 to Qn are all connected to the gate of the MOS transistor Q1, the drains of the MOS transistors Q1 to Qn are all connected to the input end of the current adder, and the sources of the MOS transistors Q1 to Qn are all connected to the system power supply.

[0032] In some embodiments, the current adder includes: a MOS transistor V1 and a MOS transistor V2;

[0033] The drain of the MOS transistor V1 is connected to the drains of the MOS transistors M1 ... MOS transistor Mm and the drains of the MOS transistors Q1 ... MOS transistor Qn. The drain of the MOS transistor V1 is also connected to the current source Iz3. The gate of the MOS transistor V1 is short-circuited with the drain of the MOS transistor V1. The gate of the MOS transistor V1 is also connected to the gate of the MOS transistor V2. The sources of the MOS transistor V1 and the MOS transistor V2 are grounded. The drain of the MOS transistor V2 outputs the bias current source Io.

[0034] The present invention further provides a radio frequency power amplifier, comprising: a current bias generating circuit with controllable temperature coefficient as described in any one of the above items.

[0035] The current bias generating circuit with a controllable temperature coefficient implemented in the present invention has the following beneficial effects: the circuit provides a bias current Io with a controllable temperature coefficient, and the temperature coefficients of different temperature zones are independently controllable, thereby increasing the flexibility and precision of the bias current, providing more precise bias current control for the RF power amplifier, and improving the performance of the RF power amplifier. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The present invention will be further described below with reference to the accompanying drawings and embodiments, in which:

[0037] Figure 1 It is a schematic diagram of a current bias generating circuit with controllable temperature coefficient of the present invention;

[0038] Figure 2 is a relationship diagram of the current source of the current bias generating circuit with controllable temperature coefficient of the present invention;

[0039] Figure 3 is a circuit diagram of a current bias generating circuit with controllable temperature coefficient according to the present invention;

[0040] Figure 4 yes Figure 1A circuit diagram of a first current subtractor of a current bias generating circuit with a controllable temperature coefficient;

[0041] Figure 5 yes Figure 1 A circuit diagram of a second current subtractor of a current bias generating circuit with a controllable temperature coefficient;

[0042] Figure 6 This is a circuit simulation diagram of the bias current and temperature of the current bias generating circuit with controllable temperature coefficient of the present invention. DETAILED DESCRIPTION

[0043] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0044] like Figure 1 As shown, the current bias generating circuit with controllable temperature coefficient of the present invention includes: a first current subtractor 100, a second current subtractor 200, a first proportional amplifier 300, a second proportional amplifier 400 and a current adder 500.

[0045] Specifically, the first input terminal of the first current subtractor 100 is connected to the current source Ip, the second input terminal of the first current subtractor 100 is connected to the current source Iz1, the output terminal of the first current subtractor 100 is connected to the input terminal of the first proportional amplifier 300, and the output terminal of the first proportional amplifier 300 is connected to the input terminal of the current adder 500; the first input terminal of the second current subtractor 200 is connected to the current source Iz2, the second input terminal of the second current subtractor 200 is connected to the current source Ip, the output terminal of the second current subtractor 200 is connected to the input terminal of the second proportional amplifier 400, and the output terminal of the second proportional amplifier 400 is connected to the input terminal of the current adder 500; the input terminal of the current adder 500 is also connected to the current source Iz3, and the output terminal of the current adder 500 outputs the bias current source Io.

[0046] The present invention divides the entire temperature range into a low temperature range, a high temperature range, and a normal temperature range, wherein the current source Ip is a current with an original positive temperature coefficient, and the current sources Iz1, Iz2, and Iz3 are three currents with constant temperature coefficients, and the value of Iz1 is the highest value of Ip in the low temperature range, the value of Iz2 is the lowest value of Ip in the low temperature range, and Iz3 is a certain value corresponding to Ip in the normal temperature range. Specifically, the relationship between the current sources Ip, Iz1, Iz2, and Iz3 is as follows: Figure 2 shown.

[0047] The current bias generating circuit with controllable temperature coefficient of the present invention provides a bias current Io with controllable temperature coefficient, and the temperature coefficients of different temperature zones are independently controllable, thereby increasing the flexibility and precision of the bias current, providing more precise bias current control for the RF power amplifier, and improving the performance of the RF power amplifier.

[0048] Furthermore, in some embodiments, the first current subtractor 100 adopts a simple current mirror circuit, and the first current subtractor 100 includes: a MOS transistor m1a, a MOS transistor m2a, a MOS transistor m3a, a MOS transistor m4a, a MOS transistor m5a, and a MOS transistor m6a.

[0049] Specifically, if Figure 3 As shown, the drain of the MOS transistor m1a (i.e., the first input terminal of the first current subtractor 100) is connected to the current source Ip, the gate of the MOS transistor m1a is short-circuited with the drain of the MOS transistor m1a and connected to the gate of the MOS transistor m2a, and the source of the MOS transistor m1a is grounded; the drain of the MOS transistor m2a is connected to the drain of the MOS transistor m3a and connected to the input terminal of the first proportional amplifier 300, and the source of the MOS transistor m2a is grounded; the source of the MOS transistor m3a is connected to the source of the MOS transistor m4a and connected to the input terminal of the first proportional amplifier 300. The system power supply Vcc is input, the gate of the MOS transistor m3a is connected to the gate of the MOS transistor m4a, the drain of the MOS transistor m4a is short-circuited with the gate of the MOS transistor m4a and connected to the drain of the MOS transistor m5a; the gate of the MOS transistor m5a is connected to the gate of the MOS transistor m6a, the source of the MOS transistor m5a is grounded, the drain of the MOS transistor m6a (that is, the second input terminal of the first current subtractor 100) is connected to the current source Iz1 and short-circuited with the gate of the MOS transistor m6a, and the source of the MOS transistor m6a is grounded.

[0050] Among them, m1a, m2a, m5a, and m6a are N-type MOS transistors, and m3a and m4a are P-type MOS transistors. MOS transistor m1a and MOS transistor m2a, MOS transistor m3a and MOS transistor m4a, and MOS transistor m5a and MOS transistor m6a form three current mirror circuits. MOS transistors m1a, MOS transistors m4a, and MOS transistor m6a act as diodes. When MOS transistor m2a is turned on and its drain current is Ip, MOS transistor m5a is turned on and its drain current is Iz1, and MOS transistor m3a is turned on and its drain current is Iz1, the output current of the drains of MOS transistors m2a and m3a (i.e., the output current of the first current subtractor 100) is Iz1-Ip.

[0051] Furthermore, in some embodiments, the second current subtractor 200 adopts a simple current mirror circuit, and the second current subtractor 200 includes: a MOS transistor m1b, a MOS transistor m2b, a MOS transistor m3b, a MOS transistor m4b, a MOS transistor m5b, and a MOS transistor m6b.

[0052] Specifically, the second current subtractor 200 adopts a simple current mirror circuit. The drain of the MOS transistor m1b (i.e., the first input terminal of the second current subtractor 200) is connected to the current source Iz2. The gate of the MOS transistor m1b is short-circuited with the drain of the MOS transistor m1b and connected to the gate of the MOS transistor m2b. The source of the MOS transistor m1b is grounded. The drain of the MOS transistor m2b is connected to the drain of the MOS transistor m3b and connected to the input terminal of the second proportional amplifier 400. The source of the MOS transistor m2b is grounded. The source of the MOS transistor m3b is connected to the MOS transistor m1b. The source of the MOS transistor m4b is connected to and connected to the system power supply Vcc, the gate of the MOS transistor m3b is connected to the gate of the MOS transistor m4b, the drain of the MOS transistor m4b is short-circuited with the gate of the MOS transistor m4b and connected to the drain of the MOS transistor m5b; the gate of the MOS transistor m5b is connected to the gate of the MOS transistor m6b, the source of the MOS transistor m5b is grounded, the drain of the MOS transistor m6b (that is, the second input terminal of the second current subtractor 200) is connected to the current source Ip and short-circuited with the gate of the MOS transistor m6b, and the source of the MOS transistor m6b is grounded.

[0053] Among them, m1b, m2b, m5b, and m6b are N-type MOS transistors, and m3b and m4b are P-type MOS transistors. MOS transistor m1b and MOS transistor m2b, MOS transistor m3b and MOS transistor m4b, and MOS transistor m5b and MOS transistor m6b form three current mirror circuits. MOS transistors m1b, MOS transistors m4b, and MOS transistor m6b act as diodes. When MOS transistor m2b is turned on and its drain current is Iz2, when MOS transistor m5b is turned on and its drain current is Iz2, when MOS transistor m3b is turned on and its drain current is Ip, then the output current of the drains of MOS transistors m2b and MOS transistor m3b (i.e., the output current of the second current subtractor 200) is Ip-Iz2.

[0054] Furthermore, in some embodiments, the first current subtractor 100 and the second current subtractor 200 use a cascode current mirror circuit.

[0055] Furthermore, in some embodiments, the first proportional amplifier 300 includes: MOS transistor Mo, MOS transistor M1 . . . MOS transistor Mm, where m is a natural number greater than 2.

[0056] Specifically, the drain and gate of the MOS transistor Mo are connected to the drains of the MOS transistors m2a and m3a, and the source of the MOS transistor Mo is grounded; the gates of the MOS transistors M1 to Mm are all connected to the gate of the MOS transistor Mo (that is, the output end of the first current subtractor 100), the drains of the MOS transistors M1 to Mm are all connected to the input end of the current adder 500, and the sources of the MOS transistors M1 to Mm are all grounded.

[0057] MOS transistor Mo, MOS transistors M1-MOS transistor Mm are all N-type MOS transistors. The gate and drain of MOS transistor Mo are short-circuited, acting as diodes. MOS transistors M1-MOS transistor Mm are conductive and output a current at their drains equal to the gate current (i.e., the output current Iz1-Ip of first current subtractor 100). That is, each drain of MOS transistors M1-MOS transistor Mm outputs current Iz1-Ip. Therefore, the output of first proportional amplifier 300 outputs m currents, and the output current value of first proportional amplifier 300 is m(Iz1-Ip).

[0058] Furthermore, in some embodiments, the second proportional amplifier 400 includes: a MOS transistor Qo, a MOS transistor Q1 . . . MOS transistor Qn, where n is a natural number greater than 2.

[0059] Specifically, the drain and gate of the MOS transistor Qo are connected to the drains of the MOS transistors m2b and m3b, and the source of the MOS transistor Qo is grounded; the gates of the MOS transistors Q1 to Qn are all connected to the gate of the MOS transistor Qo (that is, the output end of the second current subtractor 200), the drains of the MOS transistors Q1 to Qn are all connected to the input end of the current adder 500, and the sources of the MOS transistors Q1 to Qn are all grounded.

[0060] MOS transistor Qo, MOS transistors Q1-MOS transistor Qn are all P-type MOS transistors. The gate and drain of MOS transistor Qo are short-circuited, acting as a diode. MOS transistors Q1-MOS transistor Qn are conductive and output a current at their drains equal to the gate current (i.e., the output current Ip-Iz2 of the first current subtractor 100). That is, each drain of MOS transistors Q1-MOS transistor Qn outputs a current Ip-Iz2. Therefore, the output of second proportional amplifier 400 outputs n currents, and the output current value of second proportional amplifier 400 is n(Ip-Iz2).

[0061] Furthermore, in some embodiments, the current adder 500 includes: a MOS transistor V1 and a MOS transistor V2.

[0062] Specifically, the drain of the MOS transistor V1 is connected to the drains of the MOS transistors M1 ... MOS transistor Mm and the drains of the MOS transistors Q1 ... MOS transistor Qn. The drain of the MOS transistor V1 is also connected to the current source Iz3. The gate of the MOS transistor V1 is short-circuited with the drain of the MOS transistor V1. The gate of the MOS transistor V1 is also connected to the gate of the MOS transistor V2. The source of the MOS transistor V1 and the source of the MOS transistor V2 are grounded. The drain of the MOS transistor V2 outputs the bias current source Io.

[0063] Both MOS transistors V1 and V2 are N-type MOS transistors. The drain and gate of MOS transistor V1 are short-circuited, which is equivalent to a diode. MOS transistor V2 is turned on and the drain outputs a bias current Io. The value of current Io is equal to the current value of the gate of MOS transistor V2, that is, the input value of current adder 500. The value of bias current source Io is shown in Formula 3:

[0064] Formula 3: Io=Iz3-m(Iz1-Ip)+n(Ip-Iz2)

[0065] In the low temperature range, the current source Iz2>Iz1>Ip. At this time, the MOS transistor m3b pulls its own node to the system power supply Vcc, so that Ip-Iz2=0, and the MOS transistor Qo is turned off. That is, the output current of the second current subtractor 200 is 0, and the output current of the second proportional amplifier 400 is 0. The lower the temperature, the smaller the Ip value, the larger the difference (Iz1-Ip), and the larger the output current of the first current subtractor 100. The value of the bias current Io is shown in Formula 4:

[0066] Formula 4: Io = Iz3 - m(Iz1 - Ip)

[0067] When the value of Ip gradually approaches the lower limit Iz1 of the normal temperature range, the output of the first current subtractor 100 approaches 0. At this time, the value of the output bias current Io in the low temperature range is: Io=Iz3.

[0068] According to formula 4, the temperature coefficient of the bias current source Io in the low temperature range can be deduced as shown in formula 5:

[0069] Formula 5:

[0070] Where Ip and Io are the currents at room temperature, and their values ​​are equal. T is the temperature, and tcp is the positive temperature coefficient of the current Ip. Therefore, the temperature coefficient of the bias current Io in the low temperature range is a positive temperature coefficient, and this value can be controlled to be m times the positive temperature coefficient of the initial current Ip.

[0071] In the high temperature range, Ip>Iz2>Iz1. At this time, the MOS transistor m2a pulls the drain node down to the system ground GND, so that Iz1-Ip=0, and the MOS transistor Mo is turned off. That is, the output current of the first current subtractor 100 is 0, and the output current of the first proportional amplifier 300 is 0. In addition, the higher the temperature, the larger the Ip value, the larger the difference (Ip-Iz2), and the larger the output value of the second current subtractor 200. The value of the bias current Io is shown in Formula 6:

[0072] Formula 6: Io = Iz3 + n(Ip - Iz2)

[0073] When the value of Ip approaches the upper limit Iz2 of the normal temperature range, the output of the second current subtractor 200 approaches 0. At this time, the value of the output bias current Io in the low temperature range is: Io=Iz3.

[0074] According to formula 6, the temperature coefficient of the bias current source Io in the high temperature section can be deduced as shown in formula 7:

[0075] Formula 7:

[0076] Among them, Ip and Io are the currents at room temperature, and their values ​​are equal. T is the temperature, and tcp is the positive temperature coefficient of the current Ip. Therefore, the temperature coefficient of the bias current Io in the high temperature range is a positive temperature coefficient, and this value can be controlled to be n times the positive temperature coefficient value of the initial current Ip.

[0077] In the normal temperature range, the current source Iz2>Ip>Iz1, and the output currents of the first current subtractor 100 and the second current subtractor 200 are both 0. At this time, the output bias current Io=Iz3.

[0078] It is understandable that, according to actual needs, the upper and lower range values ​​of the normal temperature section can be adjusted by adjusting the amplitudes of Iz1 and Iz2.

[0079] Specifically, if Figure 6 As shown, Figure 6 : This is a circuit simulation diagram of the bias current and temperature of the present invention, wherein, in the low temperature section, the temperature coefficient of the bias current Io is m times the positive temperature coefficient value of the initial current Ip, that is, the amplification factor of the first proportional amplifier 300 is different, and the slope of the curve in the low temperature section is different; in the high temperature section, the temperature coefficient of the bias current Io is n times the positive temperature coefficient value of the initial current Ip, that is, the amplification factor of the second proportional amplifier 400 is different, and the slope of the curve in the low temperature section is different; in the normal temperature stage, the bias current Io = Iz3, the normal temperature stage is a horizontal line segment, and the two endpoint values ​​of the line segment are the values ​​of Iz1 and Iz2.

[0080] Optionally, both the first current subtractor 100 and the second current subtractor 200 adopt a simple current mirror circuit. In some embodiments, the first current subtractor 100 and the second current subtractor 200 may also adopt a cascode current mirror circuit structure.

[0081] Specifically, the first current subtractor 100 includes MOS transistors m1a-m6a and MOS transistors m1A-m6A, wherein the MOS transistors m1A, m2A, m5A and m6A are N-type MOS transistors, and m3A and m4A are P-type MOS transistors.

[0082] The drain of MOS transistor m1a is connected to current source Ip and short-circuited with its gate. The gate of MOS transistor m1a is connected to the gate of MOS transistor m2a. The source of MOS transistor m1a is connected to the drain of MOS transistor m1A. The drain and gate of MOS transistor m1A are short-circuited. The gate of MOS transistor m1A is connected to the gate of MOS transistor m2A. The source of MOS transistor m1A is grounded. The source of MOS transistor m2a is connected to the drain of MOS transistor m2A. The drain of MOS transistor m2a is connected to the drain of MOS transistor m3A. The drain of MOS transistor m2a is also connected to the input of first proportional amplifier 300 (i.e., the drain of MOS transistor Mo). The source of MOS transistor m2A is grounded. The drain current of MOS transistor m2a is the mirror current of current source Ip.

[0083] The drain of MOS transistor m6a is connected to current source Iz1. The drain and gate of MOS transistor m6a are short-circuited. The gate of MOS transistor m6a is connected to the gate of MOS transistor m5a. The source of MOS transistor m6a is connected to the drain of MOS transistor m6A. The drain and gate of MOS transistor m6A are short-circuited. The gate of MOS transistor m6A is connected to the gate of MOS transistor m5A. The source of MOS transistor m6A is grounded. The source of MOS transistor m5a is connected to the drain of MOS transistor m5A. The drain of MOS transistor m5a is connected to the drain of MOS transistor m4A. The source of MOS transistor m5A is grounded. The current in the drain of MOS transistor m5a is the mirror current of current source Iz1.

[0084] The drain and gate of MOS transistor m4A are short-circuited, the gate of MOS transistor m3A is connected to the gate of MOS transistor m4A, the source of MOS transistor m4A is connected to the drain of MOS transistor m4a, the drain and gate of MOS transistor m4a are short-circuited, the gate of MOS transistor m4a is connected to the gate of MOS transistor m3a, the sources of MOS transistors m4a and m3a are connected to the trigger system power supply Vcc, the source of MOS transistor m3A is connected to the drain of MOS transistor m3a, and the drain of MOS transistor m3A is connected to the drain of MOS transistor m2a and the input terminal of the first proportional amplifier 300 (i.e., the drain of MOS transistor Mo). The drain current of MOS transistor m3A is the mirror current of current source Iz1, and the output current of the first proportional amplifier circuit is Iz1-Ip.

[0085] Furthermore, in some embodiments, the second current subtractor 200 includes MOS transistors m1b-m6b and MOS transistors m1B-m6B, wherein MOS transistors m1B, m2B, m5B and m6B are N-type MOS transistors, and m3B and m4B are P-type MOS transistors.

[0086] The drain of MOS transistor m1b is connected to the current source Iz2 and short-circuited with the gate. The gate of MOS transistor m1b is connected to the gate of MOS transistor m2b. The source of MOS transistor m1b is connected to the drain of MOS transistor m1B. The drain and gate of MOS transistor m1B are short-circuited. The gate of MOS transistor m1B is connected to the gate of MOS transistor m2B. The source of MOS transistor m1B is grounded. The source of MOS transistor m2b is connected to the drain of MOS transistor m2B. The drain of MOS transistor m2b is connected to the drain of MOS transistor m3B. The drain of MOS transistor m2b is also connected to the input terminal of the second proportional amplifier 400 (i.e., the drain of MOS transistor Qo). The source of MOS transistor m2B is grounded. The drain current of MOS transistor m2b is the mirror current of current source Iz2.

[0087] The drain of MOS transistor m6b is connected to current source Ip, the drain and gate of MOS transistor m6b are short-circuited, the gate of MOS transistor m6b is connected to the gate of MOS transistor m5b, the source of MOS transistor m6b is connected to the drain of MOS transistor m6B, the drain and gate of MOS transistor m6B are short-circuited, the gate of MOS transistor m6B is connected to the gate of MOS transistor m5B, the source of MOS transistor m6B is grounded, the source of MOS transistor m5b is connected to the drain of MOS transistor m5B, the drain of MOS transistor m5b is connected to the drain of MOS transistor m4B, and the source of MOS transistor m5B is grounded. The current in the drain of MOS transistor m5b is the mirror current of current source Ip.

[0088] The drain and gate of MOS transistor m4B are short-circuited, the gate of MOS transistor m3B is connected to the gate of MOS transistor m4B, the source of MOS transistor m4B is connected to the drain of MOS transistor m4b, the drain and gate of MOS transistor m4b are short-circuited, the gate of MOS transistor m4b is connected to the gate of MOS transistor m3b, the sources of MOS transistors m4b and m3b are connected to the trigger system power supply Vcc, the source of MOS transistor m3B is connected to the drain of MOS transistor m3b, and the drain of MOS transistor m3B is connected to the drain of MOS transistor m2b and to the input terminal of the second proportional amplifier 400 (i.e., the drain of MOS transistor Qo). The drain current of MOS transistor m3B is the mirror current of current source Ip, and the output current of the first proportional amplifier circuit is Ip-Iz1.

[0089] Furthermore, the first proportional amplifier 300 , the second proportional amplifier 400 and the current adder 500 all adopt a simple current mirror circuit structure. In some embodiments, the first proportional amplifier 300 , the second proportional amplifier 400 and the current adder 500 may also adopt a cascode current mirror circuit structure.

[0090] The current bias generating circuit with a controllable temperature coefficient implemented in the present invention has the following beneficial effects: the circuit provides a bias current Io with a controllable temperature coefficient, and the temperature coefficients of different temperature zones are independently controllable, thereby increasing the flexibility and precision of the bias current, providing more precise bias current control for the RF power amplifier, and improving the performance of the RF power amplifier.

[0091] The present invention also provides a radio frequency power amplifier, the bias current of which is provided by the current bias generating circuit with controllable temperature coefficient disclosed in an embodiment of the present invention.

[0092] The above embodiments are intended only to illustrate the technical concepts and features of the present invention. Their purpose is to enable those skilled in the art to understand the present invention and implement it accordingly. They are not intended to limit the scope of protection of the present invention. All equivalent variations and modifications within the scope of the claims of the present invention are intended to be covered by the claims of the present invention.

[0093] It should be understood that those skilled in the art can make improvements or changes based on the above description, and all such improvements and changes should fall within the scope of protection of the appended claims of the present invention.

Claims

1. A current bias generating circuit with controllable temperature coefficient, characterized in that: include: a first current subtractor, a second current subtractor, a first proportional amplifier, a second proportional amplifier, and a current adder; A first input terminal of the first current subtractor is connected to a current source Ip, a second input terminal of the first current subtractor is connected to a current source Iz1, an output terminal of the first current subtractor is connected to an input terminal of the first proportional amplifier, and an output terminal of the first proportional amplifier is connected to an input terminal of the current adder; A first input terminal of the second current subtractor is connected to the current source Iz2, a second input terminal of the second current subtractor is connected to the current source Ip, an output terminal of the second current subtractor is connected to the input terminal of the second proportional amplifier, and an output terminal of the second proportional amplifier is connected to the input terminal of the current adder; The input end of the current adder is also connected to the current source Iz3, and the output end of the current adder outputs the bias current source Io; The first current subtractor and the second current subtractor both adopt current mirror circuits.

2. The current bias generating circuit with controllable temperature coefficient according to claim 1, characterized in that: The current source Ip is a current with an original positive temperature coefficient, and the current sources Iz1 , Iz2 and Iz3 are three currents with constant temperature coefficients.

3. The current bias generating circuit with controllable temperature coefficient according to claim 2, characterized in that: The first current subtractor includes: a MOS transistor m1a, a MOS transistor m2a, a MOS transistor m3a, a MOS transistor m4a, a MOS transistor m5a, and a MOS transistor m6a; The drain of the MOS transistor m1a is connected to the current source Ip, the gate of the MOS transistor m1a is short-circuited with the drain of the MOS transistor m1a and connected to the gate of the MOS transistor m2a, and the source of the MOS transistor m1a is grounded; The drain of the MOS transistor m2a is connected to the drain of the MOS transistor m3a and to the input end of the first proportional amplifier, and the source of the MOS transistor m2a is grounded; The source of the MOS transistor m3a is connected to the source of the MOS transistor m4a and connected to the system power supply. The gate of the MOS transistor m3a is connected to the gate of the MOS transistor m4a. The drain of the MOS transistor m4a is short-circuited with the gate of the MOS transistor m4a and connected to the drain of the MOS transistor m5a. The gate of the MOS transistor m5a is connected to the gate of the MOS transistor m6a, the source of the MOS transistor m5a is grounded, the drain of the MOS transistor m6a is connected to the current source Iz1 and short-circuited with the gate of the MOS transistor m6a, and the source of the MOS transistor m6a is grounded.

4. The current bias generating circuit with controllable temperature coefficient according to claim 3, characterized in that: The second current subtractor includes: a MOS transistor m1b, a MOS transistor m2b, a MOS transistor m3b, a MOS transistor m4b, a MOS transistor m5b and a MOS transistor m6b; The drain of the MOS transistor m1b is connected to the current source Iz2, the gate of the MOS transistor m1b is short-circuited with the drain of the MOS transistor m1b and connected to the gate of the MOS transistor m2b, and the source of the MOS transistor m1b is grounded; The drain of the MOS transistor m2b is connected to the drain of the MOS transistor m3b and to the input end of the second proportional amplifier, and the source of the MOS transistor m2b is grounded; The source of the MOS transistor m3b is connected to the source of the MOS transistor m4b and is connected to the system power supply. The gate of the MOS transistor m3b is connected to the gate of the MOS transistor m4b. The drain of the MOS transistor m4b is short-circuited with the gate of the MOS transistor m4b and is connected to the drain of the MOS transistor m5b. The gate of the MOS transistor m5b is connected to the gate of the MOS transistor m6b, the source of the MOS transistor m5b is grounded, the drain of the MOS transistor m6b is connected to the current source Ip and short-circuited with the gate of the MOS transistor m6b, and the source of the MOS transistor m6b is grounded.

5. The current bias generating circuit with controllable temperature coefficient according to claim 4, characterized in that: The first proportional amplifier includes: MOS transistor Mo, MOS transistor M1 ... MOS transistor Mm, where m is a natural number greater than 1; The drain and gate of the MOS transistor Mo are connected to the drains of the MOS transistors m2a and m3a, and the source of the MOS transistor Mo is grounded; The gates of the MOS transistors M1 to Mm are all connected to the gate of the MOS transistor M0, the drains of the MOS transistors M1 to Mm are all connected to the input end of the current adder, and the sources of the MOS transistors M1 to Mm are all grounded.

6. The current bias generating circuit with controllable temperature coefficient according to claim 5, characterized in that: The second proportional amplifier includes: a MOS transistor Qo, a MOS transistor Q1 ... a MOS transistor Qn, where n is a natural number greater than 2; The drain and gate of the MOS transistor Qo are connected to the drains of the MOS transistors m2b and m3b, and the source of the MOS transistor Qo is connected to the system power supply; The gates of the MOS transistors Q1 to Qn are all connected to the gate of the MOS transistor Q1, the drains of the MOS transistors Q1 to Qn are all connected to the input end of the current adder, and the sources of the MOS transistors Q1 to Qn are all connected to the system power supply.

7. The current bias generating circuit with controllable temperature coefficient according to claim 6, characterized in that: The current adder includes: a MOS tube V1 and a MOS tube V2; The drain of the MOS transistor V1 is connected to the drains of the MOS transistors M1 ... MOS transistor Mm and the drains of the MOS transistors Q1 ... MOS transistor Qn. The drain of the MOS transistor V1 is also connected to the current source Iz3. The gate of the MOS transistor V1 is short-circuited with the drain of the MOS transistor V1. The gate of the MOS transistor V1 is also connected to the gate of the MOS transistor V2. The sources of the MOS transistor V1 and the MOS transistor V2 are grounded. The drain of the MOS transistor V2 outputs the bias current source Io.

8. A radio frequency power amplifier, characterized in that: include: A current bias generating circuit with controllable temperature coefficient according to any one of claims 1 to 7.

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