A chip verification method and device, system, electronic equipment and storage medium

Abstract

Embodiments of the present application disclose a chip verification method and device, system, electronic equipment and storage medium, and relate to the technical field of electronic design automation, which can give full play to the large-scale and rapid verification advantages of a hardware verification platform while facilitating defect detection. The method is based on a hardware verification platform and includes: running a hardware simulation program of a chip to be verified; sending behavior information and behavior result information of the chip to be verified in program running to a software verification platform according to a preset strategy, so that the software verification platform verifies and reviews the chip to be verified according to the behavior information and the behavior result information. The present application is applicable to various chip verifications.

Description

Technical Field

[0001] This invention relates to the field of computers, and more particularly to a chip verification method, apparatus, system, electronic device, and storage medium. Background Technology

[0002] With the development and increasing scale of integrated circuits, verification has gradually become one of the biggest challenges in SOC (System on Chip) development.

[0003] Traditional software simulation methods can provide comprehensive verification coverage at the chip module level and offer high controllability. However, as chip complexity increases, the time required to simulate the overall chip operation using software simulation tools increases accordingly, and the time to find corner case bugs increases exponentially.

[0004] To address this verification challenge, a hardware emulation technique exists, which accelerates verification speed through hardware accelerators (emulators), FPGAs (Field-Programmable Gate Arrays), and other similar technologies. Specifically, emulation allows the circuit design to be verified to be ported onto a hardware accelerator, enabling the development of a verification platform and achieving simulation speeds from several kilohertz to several megahertz, representing a speedup of up to 100,000 times compared to traditional software simulation tools.

[0005] The introduction of emulators has solved the problems of slow testing speed and small test instruction size when conducting large-scale testing of chips before tape-out. However, compared with traditional verification simulation, many detection methods in hardware simulation, such as checkers and monitors, cannot be synthesized into specific circuits. Therefore, there are fewer error detection methods available in hardware simulation, making it difficult to discover some design defects of the chip to be verified. Summary of the Invention

[0006] In view of this, embodiments of the present invention provide a chip verification method, apparatus, system, electronic device, and computer-readable storage medium, which can fully leverage the advantages of large-scale and rapid verification of hardware verification platforms while facilitating defect detection.

[0007] In a first aspect, embodiments of the present invention provide a chip verification method based on a hardware verification platform, comprising: running a hardware simulation program for a chip to be verified; and sending behavioral information and behavioral result information of the chip to be verified during program execution to a software verification platform according to a preset strategy, so that the software verification platform verifies and reviews the chip to be verified based on the behavioral information and the behavioral result information.

[0008] In one implementation, sending the behavior information and behavior result information of the chip to be verified during program execution to the software verification platform according to a preset strategy includes: after each instruction in the hardware simulation program has been executed, sending the behavior information and behavior result information of the chip to be verified during program execution to the software verification platform.

[0009] In one implementation, the behavioral information includes at least one of the following: instruction exit information, instruction memory access information, and instruction interrupt information.

[0010] In one implementation, the memory access information of the instruction includes at least one of the following: the memory access order of at least one processor core, the memory type, the size of the accessed data, memory access information lost due to an abnormal situation, and memory information updated due to the predictive execution of the instruction.

[0011] In one embodiment, the actual execution order of instructions in the hardware simulation program of the chip to be verified includes out-of-order execution and / or predictive execution; the access order is the actual memory access order corresponding to the actual execution order of instructions in the hardware simulation program; sending the behavior information and behavior result information of the chip to be verified during program execution to the software verification platform includes: sending the actual memory access order corresponding to the actual execution order of instructions, and instruction order adjustment information to the software verification platform; or, determining the prescribed execution order of instructions based on the actual execution order of instructions and instruction order adjustment information, and sending the prescribed memory access order corresponding to the prescribed execution order to the software verification platform.

[0012] In one embodiment, the number of processor cores is at least two, including at least one first processor core and one second processor core, wherein the clock frequency of the first processor core is different from the clock frequency of the second processor core; the access order of the memory by the at least two processor cores is based on the access order of their respective clocks; sending the behavior information and behavior result information of the chip to be verified during program execution to the software verification platform includes: sending the access order based on the clocks of the processor cores and the clock differences of each processor core to the software verification platform, or synchronizing the access order based on the clock differences of each processor core to obtain a synchronization order, and sending the synchronization order to the software verification platform.

[0013] In one implementation, before sending the behavior information and behavior result information of the chip under test during program execution to the software verification platform according to a preset strategy, the method further includes: determining whether the instruction corresponding to the behavior information and the behavior result information is a predicted execution instruction; and in response to the instruction being a predicted execution instruction, determining whether the predicted execution instruction was successfully predicted. Sending the behavior information and behavior result information of the chip under test during program execution to the software verification platform according to the preset strategy includes: sending the behavior information and behavior result information to the software verification platform if the prediction is successful; and refusing to send the behavior information and behavior result information to the software verification platform if the prediction fails.

[0014] In one implementation, the behavior result information includes at least one of the following: fixed-point register information after instruction exit, floating-point register information after instruction exit, and status register information after instruction exit.

[0015] In one embodiment, after running the hardware simulation program of the chip to be verified, and before sending the behavior information and behavior result information of the chip to be verified during program execution to the software verification platform according to a preset strategy, the method further includes: obtaining the behavior information of each instruction when executing the hardware simulation program; obtaining the behavior result information corresponding to each instruction after executing the hardware simulation program; generating a verification data packet from the behavior information and the behavior result information according to a preset protocol; and sending the behavior information and behavior result information of the chip to be verified during program execution to the software verification platform includes sending the verification data packet to the software verification platform.

[0016] In one embodiment, sending the behavior information and behavior result information of the chip to be verified during program execution to the software verification platform includes: sending the behavior information and behavior result information of the chip to be verified during program execution to the software verification platform via DPI (Direct Programming Interface).

[0017] Secondly, embodiments of the present invention also provide a chip verification method based on a software verification platform, comprising: receiving behavioral information and behavioral result information of a chip to be verified running on the hardware verification platform sent by a hardware verification platform; running a reference model corresponding to the chip to be verified according to the behavioral information to obtain corresponding model result information; and verifying and reviewing the chip to be verified according to the behavioral result information and the model result information.

[0018] In one embodiment, receiving the behavior information and behavior result information of the chip to be verified running on the hardware verification platform sent by the hardware verification platform includes: receiving a verification data packet sent by the hardware verification platform, wherein the verification data packet is generated by the behavior information and the behavior result information according to a preset protocol; and parsing the verification data packet to obtain the behavior information and the behavior result information.

[0019] In one implementation, running the reference model corresponding to the chip to be verified based on the behavioral information includes: restoring the behavioral information to a behavioral sequence of the chip to be verified using a preset script; and using the behavioral sequence to drive the reference model to run.

[0020] In one embodiment, the step of verifying and reviewing the chip to be verified based on the behavioral result information and the model result information includes: comparing the behavioral result information with the model result information; and determining whether the chip to be verified has passed the verification based on the comparison result.

[0021] In one embodiment, the comparison result indicates that the chip to be verified has failed verification, and the method further includes: performing defect investigation on the chip to be verified based on the comparison result.

[0022] In one implementation, the behavioral information includes at least one of the following: instruction exit information, instruction memory access information, and instruction interrupt information.

[0023] In one embodiment, the memory access information of the instruction includes at least one of the following: the memory access order of at least one processor core, memory type, size of the accessed data, memory access information lost due to an abnormal situation, and memory information updated due to the predictive execution of the instruction; before verifying and reviewing the chip to be verified based on the behavioral result information and the model result information, the method further includes: detecting whether the chip to be verified has cache consistency defects and / or memory consistency defects based on the memory access information.

[0024] In one embodiment, the actual execution order of instructions in the hardware simulation program of the chip to be verified includes out-of-order execution and / or predictive execution; the access order is the actual memory access order corresponding to the actual execution order of instructions in the hardware simulation program; the step of detecting whether the chip to be verified has cache consistency defects and / or memory consistency defects based on the memory access information includes: determining the prescribed execution order of the instructions based on the actual execution order of the instructions and the instruction order adjustment information received in advance from the hardware verification platform; and detecting whether the chip to be verified has cache consistency defects and / or memory consistency defects based on the prescribed memory access order corresponding to the prescribed execution order of the instructions.

[0025] In one embodiment, the number of processor cores is at least two, including at least one first processor core and one second processor core, wherein the clock frequency of the first processor core is different from the clock frequency of the second processor core; the memory access order of the at least two processor cores is based on the access order of their respective clocks; the step of detecting whether the chip under test has cache consistency defects and / or memory consistency defects based on the memory access information includes: synchronizing the access order based on the clock differences of each processor core to obtain a synchronization order; and detecting whether the chip under test has cache consistency defects and / or memory consistency defects based on the synchronization order.

[0026] Thirdly, embodiments of the present invention also provide a chip verification apparatus, comprising: a first running unit for running a hardware simulation program of a chip to be verified; and a sending unit for sending behavioral information and behavioral result information of the chip to be verified during program execution to a software verification platform according to a preset strategy, so that the software verification platform verifies and reviews the chip to be verified based on the behavioral information and the behavioral result information.

[0027] In one embodiment, the sending unit is specifically used to send the behavior information and behavior result information of the chip to be verified during program execution to the software verification platform after each instruction in the hardware simulation program has been executed.

[0028] In one implementation, the behavioral information includes at least one of the following: instruction exit information, instruction memory access information, and instruction interrupt information.

[0029] In one implementation, the memory access information of the instruction includes at least one of the following: the memory access order of at least one processor core, the memory type, the size of the accessed data, memory access information lost due to an abnormal situation, and memory information updated due to the predictive execution of the instruction.

[0030] In one embodiment, the actual execution order of instructions in the hardware simulation program of the chip to be verified includes out-of-order execution and / or predictive execution; the access order is the actual memory access order corresponding to the actual execution order of instructions in the hardware simulation program; the sending unit is specifically used to: send the actual memory access order corresponding to the actual execution order of instructions, and instruction order adjustment information to the software verification platform; or, determine the prescribed execution order of instructions based on the actual execution order of instructions and instruction order adjustment information, and send the prescribed memory access order corresponding to the prescribed execution order to the software verification platform.

[0031] In one embodiment, the number of processor cores is at least two, including at least one first processor core and one second processor core, wherein the clock frequency of the first processor core is different from the clock frequency of the second processor core; the access order of the memory by the at least two processor cores is based on the access order of each processor core's own clock; the sending unit is specifically used to: send the access order based on each processor core's own clock and the clock difference of each processor core to the software verification platform, or, based on the clock difference of each processor core, synchronize the access order based on each processor core's own clock to obtain a synchronization order, and send the synchronization order to the software verification platform.

[0032] In one embodiment, the apparatus further includes: a first determining unit, configured to determine whether the instruction corresponding to the behavior information and the behavior result information is a predicted execution instruction before sending the behavior information and behavior result information of the chip to be verified during program execution to the software verification platform according to a preset strategy; a second determining unit, configured to determine whether the predicted execution instruction is successfully predicted in response to the instruction being a predicted execution instruction; and the sending unit, specifically configured to: send the behavior information and the behavior result information to the software verification platform if the prediction is successful; and refuse to send the behavior information and the behavior result information to the software verification platform if the prediction fails.

[0033] In one implementation, the behavior result information includes at least one of the following: fixed-point register information after instruction exit, floating-point register information after instruction exit, and status register information after instruction exit.

[0034] In one embodiment, the apparatus further includes: a first acquisition unit, configured to acquire behavior information of each instruction executed in the hardware simulation program before sending the behavior information and behavior result information of the chip under test during program execution to the software verification platform according to a preset strategy after running the hardware simulation program of the chip under test; a second acquisition unit, configured to acquire behavior result information corresponding to each instruction after executing the hardware simulation program; a generation unit, configured to generate a verification data packet from the behavior information and the behavior result information according to a preset protocol; and a sending unit, specifically configured to send the verification data packet to the software verification platform.

[0035] In one embodiment, the sending unit is specifically used to send the behavior information and behavior result information of the chip to be verified during program execution to the software verification platform via DPI.

[0036] Fourthly, embodiments of the present invention also provide a chip verification apparatus, comprising: a receiving unit for receiving behavioral information and behavioral result information of a chip to be verified running on the hardware verification platform, sent by a hardware verification platform; a second running unit for running a reference model corresponding to the chip to be verified according to the behavioral information to obtain corresponding model result information; and a verification unit for verifying and verifying the chip to be verified according to the behavioral result information and the model result information.

[0037] In one embodiment, the receiving unit includes: a receiving module, configured to receive a verification data packet sent by a hardware verification platform, the verification data packet being generated by the behavior information and the behavior result information according to a preset protocol; and a parsing module, configured to parse the verification data packet to obtain the behavior information and the behavior result information.

[0038] In one embodiment, the second running unit includes: a restoration module, used to restore the behavior information into a behavior sequence of the chip to be verified through a preset script; and a driving module, used to drive the reference model to run using the behavior sequence.

[0039] In one embodiment, the verification unit includes: a comparison module for comparing the behavioral result information with the model result information; and a determination module for determining whether the chip to be verified has passed verification based on the comparison result.

[0040] In one embodiment, the comparison result indicates that the chip to be verified has failed verification; the device further includes: a screening unit, used to screen for defects in the chip to be verified based on the comparison result.

[0041] In one implementation, the behavioral information includes at least one of the following: instruction exit information, instruction memory access information, and instruction interrupt information.

[0042] In one embodiment, the memory access information of the instruction includes at least one of the following: the memory access order of at least one processor core, the memory type, the size of the accessed data, memory access information lost due to an abnormal situation, and memory information updated due to the predictive execution of the instruction; the apparatus further includes: a detection unit, configured to detect whether the chip to be verified has cache consistency defects and / or memory consistency defects based on the memory access information before verifying and reviewing the chip to be verified based on the behavior result information and the model result information.

[0043] In one embodiment, the actual execution order of instructions in the hardware simulation program of the chip to be verified includes out-of-order execution and / or predictive execution; the access order is the actual memory access order corresponding to the actual execution order of instructions in the hardware simulation program; the detection unit includes: an order determination module, used to determine the prescribed execution order of instructions based on the actual execution order of instructions and instruction order adjustment information received in advance from the hardware verification platform; and a first detection module, used to detect whether the chip to be verified has cache consistency defects and / or memory consistency defects based on the prescribed memory access order corresponding to the prescribed execution order of instructions.

[0044] In one embodiment, the number of processor cores is at least two, including at least one first processor core and one second processor core, wherein the clock frequency of the first processor core is different from the clock frequency of the second processor core; the memory access order of the at least two processor cores is based on the access order of each processor core's own clock; the detection unit includes: a clock synchronization module, used to synchronize the access order based on the clock difference of each processor core to obtain a synchronization order; and a second detection module, used to detect whether the chip to be verified has cache consistency defects and / or memory consistency defects based on the synchronization order.

[0045] Fifthly, embodiments of the present invention also provide a chip verification system, including a hardware verification platform and a software verification platform; the hardware verification platform is communicatively connected to the software verification platform through a preset interface; wherein, the hardware verification platform is used to execute any chip verification method based on the hardware verification platform provided in the embodiments of the present invention, and the software verification platform is used to execute any chip verification method based on the software verification platform provided in the embodiments of the present invention.

[0046] In a sixth aspect, embodiments of the present invention also provide an electronic device, comprising: a housing, at least one processor, a memory, a circuit board, and a power supply circuit, wherein the circuit board is disposed within a space enclosed by the housing, and the processor and the memory are disposed on the circuit board; the power supply circuit is used to supply power to various circuits or devices of the above-mentioned electronic device; the memory is used to store executable program code; the at least one processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory, for executing any chip verification method provided by embodiments of the present invention.

[0047] In a seventh aspect, embodiments of the present invention also provide a computer-readable storage medium storing one or more programs that can be executed by one or more processors to implement any of the chip verification methods provided in the embodiments of the present invention.

[0048] The chip verification method, apparatus, system, electronic device, and computer-readable storage medium provided in the embodiments of the present invention can combine a hardware verification platform with a software verification platform. On the one hand, the simulation program of the chip to be verified can be run on the hardware verification platform, thereby realizing large-scale and rapid verification of the chip to be verified. On the other hand, the behavioral information and behavioral result information of the chip to be verified in the hardware verification can be sent to the software verification platform, so that the software verification platform can perform software verification of the same behavior of the chip to be verified. Thus, the diverse and comprehensive defect detection methods in the software verification method can be used to check for defects in the chip to be verified. Therefore, while giving full play to the advantages of large-scale and rapid verification of the hardware verification platform, it is convenient to perform defect detection. Attached Figure Description

[0049] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0050] Figure 1 A flowchart of a chip verification method provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of the processor core and memory in an embodiment of the present invention; Figure 3 Another flowchart of a chip verification method provided for an embodiment of the present invention; Figure 4 A detailed flowchart of a chip verification method provided for an embodiment of the present invention; Figure 5 A schematic diagram of a chip verification device provided for an embodiment of the present invention; Figure 6 Another schematic diagram of the chip verification device provided in the embodiments of the present invention; Figure 7 A schematic diagram of a chip verification system provided for an embodiment of the present invention; Figure 8 A schematic diagram of an electronic device provided as an embodiment of the present invention. Detailed Implementation

[0051] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0052] It should be understood that the described embodiments are merely some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0053] To enable those skilled in the art to better understand the technical concept, implementation scheme and beneficial technical effects of the embodiments of the present invention, detailed descriptions are provided below through specific embodiments.

[0054] As mentioned in the background section, although hardware emulation technology has solved the problems of slow testing speed and small test instruction size when conducting large-scale testing of chips before tape-out, compared with traditional software simulation verification, many detection methods in hardware simulation, such as checkers and monitors, cannot be synthesized into specific circuits. Therefore, there are fewer defect (bug) detection methods available in hardware simulation, making it difficult to discover some design defects of the chip to be verified.

[0055] To compensate for the above shortcomings, when using hardware simulation acceleration platforms for large-scale CPU testing, CPU verification engineers can add some self-verifying test cases when generating direct / random test cases for the CPU. These self-verifying test cases include CRC (Cyclic Redundancy Check) comparisons, running the same program multiple times to check for consistency, and adding "pass" and "failed" code segments to indicate that the test has been executed according to the verification engineer's design. However, while this solves the error detection problem to some extent, the granularity of verification is difficult to control when writing self-verifying test cases. If the granularity is too coarse, some errors in the chip being verified may be masked and not detected. If the granularity is too fine, the test cases may be terminated due to various minor issues, preventing them from completing and thus failing to fulfill their verification purpose.

[0056] Furthermore, with the increasing popularity of UVM (Universal Verification Methodology), a scheme has emerged that builds a host UVM on a hardware emulator. This involves running the simulation program for the chip to be verified on the hardware emulator and communicating with the host UVN at the transaction level. In this way, hardware emulation can reuse the checker and monitor developed on the host UVM's software verification platform, thus achieving the verification purpose. However, running the software and hardware verification platform's simulation programs simultaneously and maintaining transaction-level communication between them limits the hardware emulation speed to the software emulation speed.

[0057] Alternatively, engineers can have the hardware emulation accelerator report whether any assertion triggers meet the conditions during runtime. However, this method is similar to white-box testing, requiring verification engineers to anticipate potential test cases where problems might occur. But since CPU extreme case defects are often detected through random instruction sequences, it's difficult for verification engineers to anticipate and add corresponding assertions in advance.

[0058] In order to fully leverage the advantages of large-scale and rapid verification of hardware verification platforms while facilitating defect detection, the inventors discovered that hardware verification platforms can be combined with software verification platforms. On the one hand, the simulation program of the chip to be verified is run on the hardware verification platform, thereby achieving large-scale and rapid verification of the chip to be verified. On the other hand, the behavioral information and behavioral results of the chip to be verified during hardware verification can be sent to the software verification platform, so that the software verification platform can perform software-based verification of the same behavior of the chip to be verified. This allows the diverse and comprehensive defect detection methods in software verification to identify defects in the chip to be verified.

[0059] To enable those skilled in the art to better understand the technical concept, implementation scheme and beneficial effects of the embodiments of the present invention, detailed descriptions are provided below through specific embodiments.

[0060] In a first aspect, embodiments of the present invention provide a chip verification method that can fully leverage the advantages of large-scale and rapid verification of hardware verification platforms while facilitating defect detection.

[0061] like Figure 1 As shown, the chip verification method provided in the embodiments of the present invention is based on a hardware verification platform, and the method may include: S11. Run the hardware simulation program for the chip to be verified; In embodiments of the present invention, the hardware verification platform can be a platform that simulates the circuits or functional modules in the chip to be verified using hardware circuits or hardware devices. Specifically, the chip to be verified on the hardware verification platform refers to the chip simulated on the hardware verification platform. In this step, the hardware simulation program for the chip to be verified is run; that is, after simulating various structures and functions of the chip to be verified using the hardware verification platform, various test cases are run on the simulated chip to be verified. Because the hardware verification platform has a higher running speed than the software verification platform, large-scale test cases can be run quickly on the hardware verification platform to efficiently verify all aspects of the chip's functionality.

[0062] Optionally, in embodiments of the present invention, the chip to be verified may include integrated circuits of various functions and types, such as various application-specific integrated circuits, processors, etc.

[0063] S12. According to a preset strategy, send the behavior information and behavior result information of the chip to be verified during program execution to the software verification platform, so that the software verification platform can verify and review the chip to be verified based on the behavior information and the behavior result information.

[0064] In embodiments of the present invention, after the hardware verification platform runs the hardware simulation program, it can obtain the corresponding hardware verification results. Furthermore, it can send the behavioral information and behavioral result information of the chip to be verified in the hardware simulation program to the software verification platform, enabling the software verification platform to perform verification and review. The software verification platform can refer to a verification platform running on a host computer. The software verification platform can be implemented using various programming languages; for example, in one embodiment of the present invention, the software verification platform can be implemented using the C language.

[0065] Preset strategies may include the timing of sending behavioral information and behavioral result information to the software verification platform, as well as the information structure and organization of the behavioral information and behavioral result information. Behavioral information can refer to the specific operations performed during program execution, while behavioral result information can refer to the results or effects produced by these operations.

[0066] In embodiments of the present invention, the timing of sending behavioral information and behavioral result information can be varied. It can be sent in batches multiple times during the execution of the hardware simulation program, or it can be sent all at once after the hardware simulation program has finished running. This allows the software verification platform to verify and review the chip to be verified based on the behavioral information and behavioral result information. Optionally, in one embodiment of the present invention, the verification and review can be offline, meaning the hardware verification platform can continue subsequent simulation verification operations without waiting for the verification and review results from the software verification platform, thereby further improving verification efficiency. In another embodiment of the present invention, the verification and review can also be online, meaning the hardware verification platform can wait for the verification and review results from the software verification platform and determine whether to continue subsequent hardware simulation verification operations based on the verification and review results. In this way, although some verification speed will be sacrificed while waiting for the software verification platform, since the software verification platform in this embodiment of the invention is not a complex verification system built on traditional UVM, but verifies and reviews the corresponding behavioral information and behavioral result information in the hardware verification platform, the structure and program are more streamlined. Therefore, the software verification speed is still greatly improved compared with traditional UVM. This allows for the timely detection of problems in the chip to be verified while improving verification efficiency, without the need for a large amount of subsequent verification, effectively saving verification resources.

[0067] Optionally, the information structure and organization of behavioral information and behavioral result information can also be diverse. For example, in one embodiment of the present invention, behavioral information and behavioral result information can be acquired and statistically analyzed on an instruction-by-instruction basis. That is, the execution of each instruction involves acquiring and statistically analyzing which operations are involved and what results are produced, and the behavioral information and behavioral result information corresponding to each instruction are sent to the software verification platform respectively. In another embodiment of the present invention, behavioral information and behavioral result information can also be acquired and statistically analyzed on a clock cycle basis. That is, behavioral information and behavioral result information are acquired and statistically analyzed once in each clock cycle. In specific implementations, behavioral information and behavioral result information can be stored in the same file or in different files, and the embodiments of the present invention do not limit this.

[0068] The chip verification method provided in the embodiments of the present invention allows a hardware verification platform to run a hardware simulation program of the chip to be verified. According to a preset strategy, the hardware platform sends behavioral information and behavioral result information of the chip during program execution to a software verification platform, enabling the software verification platform to verify and review the chip based on this information. This combines the hardware and software verification platforms. On the one hand, the hardware verification platform can run the simulation program of the chip to be verified, enabling large-scale and rapid verification. On the other hand, it can send the behavioral information and behavioral result information of the chip during hardware verification to the software verification platform, allowing the software verification platform to perform software-based verification of the same behavior. This leverages the diverse and comprehensive defect detection methods available in software verification to identify defects in the chip. Therefore, while fully utilizing the advantages of large-scale and rapid verification of the hardware verification platform, it also facilitates defect detection.

[0069] Specifically, in one embodiment of the present invention, the behavioral information of the chip under test during program execution may include one or more of the following: instruction exit information, instruction memory access information, and instruction interrupt information. The instruction exit information may indicate the completion of an instruction execution, and the instruction memory access information may indicate that an instruction performs a memory access operation, such as reading or writing memory. The memory may include main memory and / or various levels of cache. For example, a schematic diagram of the processor core and memory structure of the chip under test can be shown as follows: Figure 2 As shown, instruction interrupt information indicates that the execution of an instruction has resulted in an interrupt. This behavioral information can be obtained by reading the corresponding logic units in the chip to be verified during hardware simulation. For example, the actual memory access behavior information during instruction execution can be extracted from the LSU (Memory Read / Write Unit), or interrupt information can be obtained from the interrupt handling unit, etc.

[0070] Among the various behavioral information of instructions, the memory access information of instructions involves the interaction between the processor and the memory. Based on this, in one embodiment of the present invention, when verifying the chip to be verified, the memory access information of instructions can be used to verify whether the chip to be verified has memory consistency defects and / or cache consistency defects.

[0071] Specifically, in one embodiment of the present invention, the memory access information of the instructions may include one or more of the following: the memory access order of at least one processor core, the memory type, the size of the accessed data, memory access information lost due to an exception, and memory information updated due to predictive execution of instructions. These factors may all affect the memory access of the processor core of the chip to be verified in the hardware verification platform. In order for the software verification platform to verify and review the chip to be verified based on the behavioral information and behavioral result information sent by the hardware verification platform, in the embodiments of the present invention, the above-mentioned memory access information can be used to accurately recover the interaction process between each processor core and the memory, so that the software verification platform can simulate the interaction process to verify and review the memory consistency and / or cache consistency of the chip to be verified.

[0072] Furthermore, with the development of computer technology, processors can not only execute instructions in their original, prescribed order, but also shuffle the prescribed order to perform out-of-order execution and / or predictive execution. Correspondingly, out-of-order execution and / or predictive execution involve the interaction between the processor and memory during the execution of each instruction. In this case, in order for the software verification platform to verify and review the memory consistency and / or cache consistency of the chip to be verified, in embodiments of the present invention, the hardware verification platform and / or software verification platform can restore the out-of-order and / or predictive execution instructions to their original, prescribed execution order, and then the software verification platform performs verification and review based on the restored prescribed execution order. To ensure that each instruction corresponds to its respective memory access information, the memory access information is also adjusted according to the adjustment of the instruction execution order.

[0073] For example, in one embodiment of the present invention, the actual execution order of instructions in the hardware simulation program of the chip to be verified may include out-of-order execution and / or predictive execution; the memory access order of the at least one processor core is specifically the actual memory access order corresponding to the actual execution order of instructions in the hardware simulation program; based on this, sending the behavior information and behavior result information of the chip to be verified during program execution to the software verification platform in step S12 may specifically include: sending the actual memory access order corresponding to the actual execution order of instructions, and the instruction order adjustment information to the software verification platform, so that the software verification platform can determine the prescribed memory access order corresponding to the prescribed execution order of instructions based on the actual memory access order and the order adjustment information, and verify and review the memory consistency and / or cache consistency of the chip to be verified based on the prescribed memory access order.

[0074] Optionally, in another embodiment of the present invention, the hardware verification platform may also determine the prescribed execution order of the instructions based on the actual execution order of the instructions and the instruction order adjustment information, and send the prescribed memory access order corresponding to the prescribed execution order to the software verification platform, so that the software verification platform can verify and review the memory consistency and / or cache consistency of the chip to be verified based on the prescribed memory access order.

[0075] In the embodiments of the present invention, in addition to out-of-order execution and / or predictive execution of instructions affecting the verification and review of the software verification platform, in multi-core processors, if the clock frequencies of each processor core are different, it will also affect the verification and review of the software verification platform, so special handling is required.

[0076] For example, in one embodiment of the present invention, the number of processor cores of the chip to be verified is at least two, and there is at least one first processor core and one second processor core, wherein the clock frequency of the first processor core is different from the clock frequency of the second processor core; the access order of the memory by the at least two processor cores is based on the access order of the individual clocks of the processor cores; based on this, sending the behavior information and behavior result information of the chip to be verified during program execution to the software verification platform in step S12 may include: sending the access order based on the individual clocks of the processor cores and the clock differences of each processor core to the software verification platform, so that the software verification platform can synchronize the access order based on the individual clocks of the processor cores according to the clock differences of each processor core, and verify memory consistency and / or cache consistency according to the synchronized access order.

[0077] Optionally, in another embodiment of the present invention, the hardware verification platform may also synchronize the access order based on the clock differences of each processor core to obtain a synchronization order, and send the synchronization order to the software verification platform.

[0078] Instruction execution produces certain results, yielding corresponding behavioral result information. This behavioral result information can be stored in various registers of the chip under test during hardware simulation and can be retrieved and accessed. For example, in one embodiment of the present invention, the behavioral result information of the chip under test during program execution may include one or more of the following: fixed-point register information after instruction exit, floating-point register information after instruction exit, status register information after instruction exit, etc. When retrieving behavioral result information, for example, fixed-point information of retire (exit) can be extracted from the RT (Completion Exit Unit), and floating-point information can be extracted from the FP (Floating-Point Unit), etc.

[0079] In order to obtain the aforementioned behavioral information and behavioral result information of the chip to be verified, in one embodiment of the present invention, a synthesizable monitor can be implemented based on SystemVerilog to collect the behavioral information and behavioral result information of the chip to be verified on a hardware verification platform.

[0080] After obtaining the behavior information and behavior result information of the chip under test during program execution, the behavior information and behavior result information of the chip under test during program execution can be sent to the software verification platform in step S12 according to a preset strategy. Specifically, in one embodiment of the present invention, sending the behavior information and behavior result information of the chip under test during program execution to the software verification platform according to the preset strategy may include: after each instruction in the hardware simulation program has finished running, sending the behavior information and behavior result information of the chip under test during program execution to the software verification platform. For example, after each instruction of the CPU has finished running, the behavior information and behavior result information generated by the CPU in this instruction cycle can be transmitted to the software verification platform through a monitor. In this way, by acquiring and sending information on the operations and results of each instruction at the instruction level, the actions and results of each instruction can be accurately grasped, without acquiring and sending too much information about the intermediate process of instruction execution and redundant information, and without omitting important behavior information and behavior result information.

[0081] To improve information transmission efficiency, in one embodiment of the present invention, after running the hardware simulation program of the chip to be verified in step S11 and before sending the behavior information and behavior result information of the chip to be verified during program execution to the software verification platform according to a preset strategy in step S12, the chip verification method provided by the embodiment of the present invention may further include: obtaining the behavior information of each instruction when executing the hardware simulation program; obtaining the behavior result information corresponding to each instruction after executing the hardware simulation program; and generating a verification data packet by generating the behavior information and the behavior result information according to a preset protocol. Based on this, step S12 sending the behavior information and behavior result information of the chip to be verified during program execution to the software verification platform may specifically include: sending the verification data packet to the software verification platform.

[0082] In this embodiment, since the various logic units and registers storing behavioral information and behavioral result information are updated as the program executes, the appropriate time can be chosen to obtain the behavioral information and behavioral result information for each instruction. For example, in this embodiment, the corresponding behavioral information is obtained when each instruction is executed, and the corresponding behavioral result information is obtained after each instruction is executed.

[0083] To facilitate information transmission, this embodiment further encapsulates the acquired behavioral information and behavioral result information. Following a pre-agreed protocol with the software verification platform, the behavioral information and behavioral result information are used to generate a verification data packet, which is then sent to the software verification platform. Optionally, these verification data packets can be sent after each instruction, in batches after several instructions, when the hardware verification platform is idle, or after the hardware simulation program on the hardware verification platform has finished running. This embodiment of the invention does not limit the specific actions taken in this regard. Optionally, the behavioral information and behavioral result information can be encapsulated in the same verification data packet or in different verification data packets.

[0084] In practice, the behavior information and result information of the chip to be verified during program execution can be sent to the software verification platform through DPI or other available interfaces.

[0085] Furthermore, in one or more embodiments of the present invention, there may be predictive execution of instructions. However, the behavioral information and behavioral result information corresponding to the predictive execution cannot take effect immediately. It is necessary to determine whether the current predictive instruction is executed correctly, that is, whether the prediction is successful, based on the execution status of the preceding instructions. If the prediction is successful, then the corresponding behavioral information and behavioral result information are valid and can be sent to the software verification platform. Otherwise, if the prediction fails, then the behavioral information and behavioral result information corresponding to the predictive instruction are invalid. Therefore, the prediction instruction is not sent to the software verification platform and must be re-executed.

[0086] For example, in one embodiment of the present invention, before sending the behavior information and behavior result information of the chip to be verified during program execution to the software verification platform in step S12 according to a preset strategy, the chip verification method provided by the embodiment of the present invention may further include: determining whether the instruction corresponding to the behavior information and the behavior result information is a predicted execution instruction; in response to the instruction being a predicted execution instruction, determining whether the predicted execution instruction was successfully predicted; based on this, step S12, sending the behavior information and behavior result information of the chip to be verified during program execution to the software verification platform according to a preset strategy, may specifically include: sending the behavior information and the behavior result information to the software verification platform if the prediction is successful; and refusing to send the behavior information and the behavior result information to the software verification platform if the prediction fails.

[0087] Accordingly, embodiments of the present invention also provide a chip verification method based on a software verification platform, which can fully leverage the advantages of large-scale and rapid verification of the hardware verification platform while facilitating defect detection.

[0088] like Figure 3As shown, the chip verification method provided in the embodiments of the present invention is based on a software verification platform, and the method may include: S21, Receive the behavior information and behavior result information of the chip to be verified running on the hardware verification platform, sent by the hardware verification platform; In embodiments of the present invention, the software verification platform may refer to a verification platform running on a host computer. The hardware verification platform may be a platform that uses hardware circuits or hardware devices to simulate the circuits or functional modules in the chip to be verified.

[0089] The software verification platform can receive behavioral information and behavioral result information generated by the chip under test during hardware verification from the hardware verification platform, and store the behavioral information and behavioral result information as files so that a software-based verification and review program can be run on the software verification platform. Optionally, the behavioral information and behavioral result information can be stored in the same file or in different files.

[0090] Because hardware verification platforms have a higher operating speed than software verification platforms, large-scale test cases can be run quickly on hardware verification platforms to efficiently verify all aspects of the chip's functionality. However, since hardware verification platforms have relatively few means for locating, finding, and analyzing defects, this step involves the software testing platform receiving behavioral information and behavioral result information from the hardware verification platform regarding the chip's operation on the hardware verification platform. This triggers the software verification platform to verify and review the relevant behaviors and results performed on the hardware verification platform. The behavioral information refers to the specific operations performed by the hardware simulation program on the hardware verification platform, while the behavioral result information refers to the results or effects produced by these operations.

[0091] S22, Run the reference model corresponding to the chip to be verified according to the behavior information to obtain the corresponding model result information; Upon receiving behavioral information from the hardware verification platform, in this step, the software verification platform can run a pre-set reference model corresponding to the chip to be verified based on the behavioral information, and obtain the model result information corresponding to the behavioral information based on the calculation of the reference model. In other words, in this step, software simulation can be used to calculate what result the behavioral information will produce, and obtain the model result information.

[0092] The reference model refers to a software-based simulation of various logics and functions of the chip under test to verify its correctness. Because software verification allows for the flexible configuration of various defect detection methods—such as checkers and monitors similar to those in UVM—it effectively compensates for the shortcomings of hardware verification platforms.

[0093] S23, the chip to be verified is verified and reviewed based on the behavioral result information and the model result information.

[0094] In this step, the chip to be verified can be verified and reviewed based on the behavioral result information sent by the hardware verification platform and the model result information calculated by the software verification platform based on the behavioral information. That is, it can be determined whether there are defects in the chip to be verified. If there are defects, further analysis and location of defects can be performed.

[0095] The chip verification method provided in the embodiments of the present invention allows a software verification platform to receive behavioral information and behavioral result information of the chip to be verified running on the hardware verification platform, sent by the hardware verification platform. Based on the behavioral information, a reference model corresponding to the chip to be verified is run to obtain corresponding model result information. The chip to be verified is then verified and reviewed based on the behavioral result information and the model result information. This combines the hardware verification platform and the software verification platform. On the one hand, the simulation program of the chip to be verified can be run on the hardware verification platform, thereby achieving large-scale and rapid verification of the chip. On the other hand, the software verification platform can receive the behavioral information and behavioral result information of the chip to be verified during hardware verification and verify the same behavior of the chip on the software verification platform. This allows for the use of diverse and comprehensive defect detection methods in software verification to identify defects in the chip to be verified. Therefore, while fully leveraging the advantages of large-scale and rapid verification of the hardware verification platform, defect detection is also facilitated.

[0096] Specifically, in step S21, the specific form of the behavioral information and behavioral result information received by the software verification platform can be pre-agreed upon by the software verification platform and the hardware verification platform, as long as both parties can recognize this behavioral information and behavioral result information. For example, in one embodiment of the present invention, receiving the behavioral information and behavioral result information of the chip to be verified running on the hardware verification platform sent by the hardware verification platform may specifically include: receiving a verification data packet sent by the hardware verification platform, the verification data packet being generated by the behavioral information and behavioral result information according to a preset protocol; and parsing the verification data packet to obtain the behavioral information and the behavioral result information. Optionally, the behavioral information and behavioral result information may be encapsulated in the same verification data packet or in different verification data packets.

[0097] After receiving the aforementioned behavioral information and behavioral result information, the software verification platform can run the reference model corresponding to the chip to be verified based on the behavioral information. Optionally, in one embodiment of the present invention, the reference model can be run offline, that is, the hardware verification platform does not need to wait for the verification review result of the software verification platform to continue subsequent simulation verification operations, thereby further improving verification efficiency. In another embodiment of the present invention, the reference model can also be run online, that is, the hardware verification platform can wait for the verification review result of the software verification platform and determine whether to continue subsequent hardware simulation verification operations based on the verification review result, thereby improving verification efficiency compared to the prior art while timely identifying problems with the chip to be verified without requiring extensive subsequent verification, effectively saving verification resources.

[0098] Specifically, in one embodiment of the present invention, step S22, running the reference model corresponding to the chip to be verified based on the behavioral information, may include: restoring the behavioral information to a behavioral sequence of the chip to be verified using a preset script; and using the behavioral sequence to drive the reference model to run. Optionally, the behavioral information may exist in various forms such as text and tables. To enable the software verification platform to run the reference model corresponding to the chip to be verified based on the behavioral information, the behavioral information may be further processed. For example, the behavioral information may be restored to a behavioral sequence of the chip to be verified, such as a first operation performed at a first moment, a second operation performed at a second moment, etc., so that the reference model corresponding to the chip to be verified can perform simulation calculations based on a series of behaviors in the behavioral sequence to obtain the model result information corresponding to the behavioral information. Optionally, the behavioral sequence may be based on any format or language that the software verification platform can recognize, such as Verilog.

[0099] After obtaining the model result information, the chip to be verified can be verified and reviewed in step S23 based on the behavioral result information and the model result information. Specifically, the verification and review operation may include: comparing the behavioral result information with the model result information; and determining whether the chip to be verified has passed verification based on the comparison result. For example, if the comparison result is that the behavioral result information and the model result information are consistent, it means that for the same chip behavior, the results obtained by hardware verification and software verification are consistent, and therefore it can be determined that the chip to be verified has passed verification; if the comparison result is that the behavioral result information and the model result information are inconsistent, it means that for the same chip behavior, the results obtained by hardware verification and software verification are inconsistent, and therefore it can be determined that the chip to be verified has failed verification (i.e., verification failed).

[0100] Furthermore, in one embodiment of the present invention, if the comparison result indicates that the chip to be verified has failed verification, the chip verification method provided by the embodiment of the present invention may further include: performing defect investigation on the chip to be verified based on the comparison result. That is, for chips that fail verification, the chip verification method provided by the embodiment of the present invention can also utilize various defect detection tools and methods built into the software verification platform to analyze the reasons for the failure, helping users find the chip defects that caused the verification failure, so that users can make corresponding modifications to the chip design to overcome the defect.

[0101] Furthermore, in addition to detecting whether the chip under test has passed verification based on behavioral result information and model result information, embodiments of the present invention can also utilize behavioral information to verify whether the chip under test has defects. For example, in one embodiment of the present invention, the behavioral information received by the software verification platform may include one or more of the following: instruction exit information, instruction memory access information, and instruction interrupt information. When the behavioral information includes instruction memory access information, the memory access information can also be used to verify the memory consistency and / or cache consistency of the chip under test.

[0102] For example, in one embodiment of the present invention, the memory access information of the instruction may include one or more of the following: the access order of memory by at least one processor core, memory type, size of the accessed data, memory access information lost due to an exception, and memory information updated due to the predictive execution of the instruction. Before verifying the chip to be verified based on the behavioral result information and the model result information, the chip verification method provided by the embodiment of the present invention may further include: detecting whether the chip to be verified has cache consistency defects and / or memory consistency defects based on the memory access information. That is, in the case of multi-core shared memory or multi-threaded shared memory, each processor core or different threads of the same processor core needs to comply with preset memory access rules. If these memory access rules are not followed, there may be problems such as inconsistent data reading from the same memory unit by multiple processor cores, or inconsistent cached data for the same memory unit in the caches of different processor cores. In this embodiment, the software verification platform can determine whether the chip to be verified has memory consistency and / or cache consistency defects based on whether the above memory access information conforms to the preset memory access rules.

[0103] For example, in one embodiment of the present invention, the actual execution order of instructions in the hardware simulation program of the chip to be verified includes out-of-order execution and / or predictive execution; the memory access order of the at least one processor core can be the actual memory access order corresponding to the actual execution order of instructions in the hardware simulation program; based on this, detecting whether the chip to be verified has cache consistency defects and / or memory consistency defects according to the memory access information can specifically include: determining the prescribed execution order of the instructions according to the actual execution order of the instructions and the instruction order adjustment information received in advance from the hardware verification platform; and detecting whether the chip to be verified has cache consistency defects and / or memory consistency defects according to the prescribed memory access order corresponding to the prescribed execution order of the instructions.

[0104] In the embodiments of the present invention, in addition to out-of-order execution and / or predictive execution of instructions affecting the verification and review of the software verification platform, in multi-core processors, if the clock frequencies of each processor core are different, it will also affect the verification and review of the software verification platform, so special handling is required.

[0105] For example, in one embodiment of the present invention, the chip to be verified has at least two processor cores, including at least one first processor core and one second processor core, wherein the clock frequency of the first processor core is different from the clock frequency of the second processor core; the memory access order of the at least two processor cores is based on the access order of their respective clocks; therefore, based on this, detecting whether the chip to be verified has cache consistency defects and / or memory consistency defects according to the memory access information may specifically include: synchronizing the access order based on the clock differences of each processor core to obtain a synchronization order; and detecting whether the chip to be verified has cache consistency defects and / or memory consistency defects according to the synchronization order.

[0106] The chip verification method provided by the present invention will be described in detail below through a specific embodiment.

[0107] like Figure 4 As shown, the chip verification method provided by the embodiments of the present invention may include: S301. Run the hardware simulation program of the chip to be verified on the hardware verification platform; Among them, the hardware verification platform can be based on the hardware simulation accelerator Emulator.

[0108] S302. When the hardware verification platform executes each instruction in the hardware simulation program, it obtains the behavior information of that instruction. Optionally, the instruction's behavioral information may include, for example, instruction exit information, instruction memory access information, etc. The instruction's memory access information may include one or more of the following: the memory access order of at least one processor core, memory type, size of the accessed data, memory access information lost due to exceptions, and memory information updated due to predictive execution of the instruction, etc.

[0109] S303. After executing each instruction in the hardware simulation program, the hardware verification platform obtains the behavioral result information corresponding to that instruction. Optionally, the result information may include fixed-point register information after instruction exit, floating-point register information after instruction exit, status register information after instruction exit, etc.

[0110] S304. The hardware verification platform generates a verification data packet based on the behavioral information and behavioral result information according to the preset protocol. Optionally, the hardware verification platform can first determine whether the instruction is a predicted execution instruction, and in response to the instruction being a predicted execution instruction, determine whether the predicted execution instruction was successfully predicted; if the prediction is successful, generate a verification data packet with the behavior information and behavior result information according to a preset protocol, so as to send the behavior information and behavior result information to the software verification platform; if the prediction fails, refuse to generate a verification data packet with the behavior information and behavior result information.

[0111] S305. The hardware verification platform sends verification data packets to the software verification platform through a direct programming interface. S306. The software verification platform receives and parses the verification data packet to obtain the behavior information and the behavior result information; S307. The software verification platform detects whether the chip under verification has cache consistency defects and / or memory consistency defects based on the memory access information in the behavioral information. S308, the software verification platform uses a preset script to restore behavioral information into the behavioral sequence of the chip to be verified; For example, the preset script could be a Python script.

[0112] S309. The software verification platform uses the behavioral sequence to drive the reference model corresponding to the chip to be verified to run. S310. The software verification platform compares the behavioral result information with the model result information obtained by running the reference model; S311. The software verification platform determines whether the chip to be verified has passed the verification based on the comparison results. S312, The software verification platform performs defect investigation on chips that fail verification.

[0113] Alternatively, various debugging tools, such as software tools like monitors and checkers, can be used to locate and analyze defects.

[0114] Accordingly, in a third aspect, embodiments of the present invention also provide a chip verification device that can fully leverage the advantages of large-scale and rapid verification of hardware verification platforms while facilitating defect detection.

[0115] like Figure 5 As shown, the chip verification apparatus provided in the embodiments of the present invention may include: The first running unit 41 is used to run the hardware simulation program of the chip to be verified; The sending unit 42 sends the behavior information and behavior result information of the chip to be verified during program execution to the software verification platform according to a preset strategy, so that the software verification platform can verify and review the chip to be verified based on the behavior information and the behavior result information.

[0116] The chip verification apparatus provided in the embodiments of the present invention can run a hardware simulation program of the chip to be verified and send behavioral information and behavioral result information of the chip to be verified during program execution to a software verification platform according to a preset strategy. This allows the software verification platform to verify and review the chip based on the behavioral information and behavioral result information. In this way, a hardware verification platform and a software verification platform can be combined. On the one hand, the simulation program of the chip to be verified can be run on the hardware verification platform, thereby achieving large-scale and rapid verification of the chip. On the other hand, the behavioral information and behavioral result information of the chip to be verified during hardware verification can be sent to the software verification platform, so that the software verification platform can perform software-based verification of the same behavior of the chip. This allows the diverse and comprehensive defect detection methods in software verification to identify defects in the chip to be verified. Therefore, while fully leveraging the advantages of large-scale and rapid verification of the hardware verification platform, it also facilitates defect detection.

[0117] In one embodiment, the sending unit 42 can be specifically used to send the behavior information and behavior result information of the chip to be verified during program execution to the software verification platform after each instruction in the hardware simulation program has been executed.

[0118] In one implementation, the behavioral information may include at least one of the following: instruction exit information, instruction memory access information, and instruction interrupt information.

[0119] In one implementation, the memory access information of the instruction includes at least one of the following: the memory access order of at least one processor core, the memory type, the size of the accessed data, memory access information lost due to an abnormal situation, and memory information updated due to the predictive execution of the instruction.

[0120] In one embodiment, the actual execution order of instructions in the hardware simulation program of the chip to be verified includes out-of-order execution and / or predictive execution; the access order is the actual memory access order corresponding to the actual execution order of instructions in the hardware simulation program; the sending unit 42 can be specifically used to: send the actual memory access order corresponding to the actual execution order of instructions and the instruction order adjustment information to the software verification platform; or, determine the prescribed execution order of instructions based on the actual execution order of instructions and the instruction order adjustment information, and send the prescribed memory access order corresponding to the prescribed execution order to the software verification platform.

[0121] In one embodiment, the number of processor cores is at least two, including at least one first processor core and one second processor core, wherein the clock frequency of the first processor core is different from the clock frequency of the second processor core; the access order of the memory by the at least two processor cores is based on the access order of their respective clocks; the sending unit 42 is specifically used to: send the access order based on the clocks of the processor cores and the clock differences of each processor core to the software verification platform, or, based on the clock differences of each processor core, synchronize the access order based on the clocks of the processor cores to obtain a synchronization order, and send the synchronization order to the software verification platform.

[0122] In one embodiment, the apparatus further includes: a first determining unit, configured to determine whether the instruction corresponding to the behavior information and the behavior result information is a predicted execution instruction before sending the behavior information and behavior result information of the chip to be verified during program execution to the software verification platform according to a preset strategy; a second determining unit, configured to determine whether the predicted execution instruction is successfully predicted in response to the instruction being a predicted execution instruction; and the sending unit, specifically configured to: send the behavior information and the behavior result information to the software verification platform if the prediction is successful; and refuse to send the behavior information and the behavior result information to the software verification platform if the prediction fails.

[0123] In one implementation, the behavior result information includes at least one of the following: fixed-point register information after instruction exit, floating-point register information after instruction exit, and status register information after instruction exit.

[0124] In one embodiment, the chip verification apparatus may further include: The first acquisition unit is used to acquire the behavior information of each instruction when executing the hardware simulation program after running the hardware simulation program of the chip to be verified, and before sending the behavior information and behavior result information of the chip to be verified during program execution to the software verification platform according to a preset strategy. The second acquisition unit acquires the behavior result information corresponding to each instruction after executing each instruction in the hardware simulation program; The generation unit is used to generate a verification data packet from the behavior information and the behavior result information according to a preset protocol; The sending unit 42 can be specifically used to send the verification data packet to the software verification platform.

[0125] In one embodiment, the sending unit 42 can be specifically used to send the behavior information and behavior result information of the chip to be verified during program execution to the software verification platform through the Direct Programming Interface (DPI).

[0126] Accordingly, in a fourth aspect, embodiments of the present invention also provide a chip verification apparatus that can fully leverage the advantages of large-scale and rapid verification of hardware verification platforms while facilitating defect detection.

[0127] like Figure 6 As shown, the chip verification apparatus provided in the embodiments of the present invention may include: The receiving unit 51 is used to receive the behavior information and behavior result information of the chip to be verified running on the hardware verification platform, which are sent by the hardware verification platform. The second running unit 52 runs the reference model corresponding to the chip to be verified according to the behavior information and obtains the corresponding model result information. The verification unit 53 is used to verify and verify the chip to be verified based on the behavior result information and the model result information.

[0128] The chip verification apparatus provided in the embodiments of the present invention can receive behavioral information and behavioral result information of the chip to be verified running on the hardware verification platform, sent by the hardware verification platform. Based on the behavioral information, it runs a reference model corresponding to the chip to be verified to obtain corresponding model result information. Based on the behavioral result information and the model result information, it verifies and reviews the chip to be verified. In this way, the hardware verification platform and the software verification platform can be combined. On the one hand, the simulation program of the chip to be verified can be run on the hardware verification platform, thereby achieving large-scale and rapid verification of the chip to be verified. On the other hand, the software verification platform can receive the behavioral information and behavioral result information of the chip to be verified in the hardware verification, and verify the same behavior of the chip to be verified on the software verification platform. This allows for the use of diverse and comprehensive defect detection methods in software verification to identify defects in the chip to be verified. Therefore, it can fully leverage the advantages of large-scale and rapid verification of the hardware verification platform while facilitating defect detection.

[0129] In one embodiment, the receiving unit 51 may include: The receiving module is used to receive the verification data packet sent by the hardware verification platform. The verification data packet is generated by the behavior information and the behavior result information according to a preset protocol. The parsing module is used to parse the verification data packet to obtain the behavior information and the behavior result information.

[0130] In one embodiment, the second operating unit 52 may include: The restoration module is used to restore the behavioral information into the behavioral sequence of the chip to be verified through a preset script. A driving module is used to drive the reference model to run using the behavior sequence.

[0131] In one embodiment, the review unit 53 may include: The comparison module is used to compare the behavioral result information with the model result information; The determination module is used to determine whether the chip to be verified has passed the verification based on the comparison results.

[0132] In one embodiment, the comparison result indicates that the chip to be verified has failed verification; the device may further include: a screening unit, used to screen for defects in the chip to be verified based on the comparison result.

[0133] In one implementation, the behavioral information may include at least one of the following: instruction exit information, instruction memory access information, and instruction interrupt information.

[0134] In one embodiment, the memory access information of the instruction may include at least one of the following: the memory access order of at least one processor core, the memory type, the size of the accessed data, memory access information lost due to an abnormal situation, and memory information updated due to the predictive execution of the instruction; the apparatus further includes: a detection unit, configured to detect whether the chip to be verified has cache consistency defects and / or memory consistency defects based on the memory access information before verifying and reviewing the chip to be verified based on the behavior result information and the model result information.

[0135] In one embodiment, the actual execution order of instructions in the hardware simulation program of the chip to be verified includes out-of-order execution and / or predictive execution; the access order is the actual memory access order corresponding to the actual execution order of instructions in the hardware simulation program; the detection unit includes: an order determination module, used to determine the prescribed execution order of instructions based on the actual execution order of instructions and instruction order adjustment information received in advance from the hardware verification platform; and a first detection module, used to detect whether the chip to be verified has cache consistency defects and / or memory consistency defects based on the prescribed memory access order corresponding to the prescribed execution order of instructions.

[0136] In one embodiment, the number of processor cores is at least two, including at least one first processor core and one second processor core, wherein the clock frequency of the first processor core is different from the clock frequency of the second processor core; the memory access order of the at least two processor cores is based on the access order of each processor core's own clock; the detection unit includes: a clock synchronization module, used to synchronize the access order based on the clock difference of each processor core to obtain a synchronization order; and a second detection module, used to detect whether the chip to be verified has cache consistency defects and / or memory consistency defects based on the synchronization order.

[0137] Accordingly, in a fifth aspect, embodiments of the present invention also provide a chip verification system, such as... Figure 7 As shown, the system may include a hardware verification platform 62 and a software verification platform 61; the hardware verification platform 62 is connected to the software verification platform 61 through a preset interface; wherein, the hardware verification platform 62 is used to execute any chip verification method based on the hardware verification platform in the foregoing embodiments, and the software verification platform is used to execute any chip verification method based on the software verification platform in the foregoing embodiments, thus also achieving the corresponding beneficial technical effects, which have been described in detail above and will not be repeated here.

[0138] Sixth aspect, such as Figure 8As shown, embodiments of the present invention also provide an electronic device, including: a housing 100, at least one processor 110, a memory 120, a circuit board 130, and a power supply circuit 140, wherein the circuit board 130 is disposed within the space enclosed by the housing 100, and the processor 110 and the memory 120 are disposed on the circuit board 130; the power supply circuit 140 is used to supply power to various circuits or devices of the above-mentioned electronic device; the memory 120 is used to store executable program code; the processor 110 runs a program corresponding to the executable program code by reading the executable program code stored in the memory 120, for executing any of the chip verification methods provided in the foregoing embodiments. The specific execution process of the processor 110 of the above steps and the steps further executed by the processor 110 by running the executable program code can be found in the description of the foregoing embodiments, and will not be repeated here.

[0139] Seventhly, embodiments of the present invention also provide a computer-readable storage medium storing one or more programs, which can be executed by one or more processors to implement any of the chip verification methods provided in the foregoing embodiments. The specific execution process of the processor on the above steps, and the steps further executed by the processor by running executable program code, can be found in the description of the foregoing embodiments, and will not be repeated here.

[0140] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0141] The various embodiments in this specification are described in a related manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.

[0142] In particular, the device embodiment is basically similar to the method embodiment, so the description is relatively simple. For relevant details, please refer to the description of the method embodiment.

[0143] For ease of description, the above apparatus is described by dividing it into various functional units / modules. Of course, in implementing this invention, the functions of each unit / module can be implemented in one or more software and / or hardware.

[0144] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0145] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A chip verification method, characterized in that, Based on a hardware verification platform, including: Run the hardware simulation program for the chip to be verified; According to a preset strategy, the behavior information and behavior result information of the chip to be verified during program execution are sent to the software verification platform, so that the software verification platform can verify and review the chip to be verified based on the behavior information and the behavior result information; wherein, the behavior information includes the operations performed during program execution, and the behavior result information includes the results or effects produced by the operations; the preset strategy includes the timing of sending the behavior information and the behavior result information to the software verification platform, or the information structure and organization form of the behavior information and the behavior result information; The behavioral information includes memory access information of instructions; the memory access information of instructions includes the memory access order of at least one processor core. The actual execution order of instructions in the hardware simulation program of the chip to be verified includes out-of-order execution and / or predictive execution; the access order is the actual memory access order corresponding to the actual execution order of instructions in the hardware simulation program. Sending the behavior information and behavior result information of the chip to be verified during program execution to the software verification platform includes: sending the actual memory access order corresponding to the actual execution order of the instructions, as well as the instruction order adjustment information, to the software verification platform; or, determining the prescribed execution order of the instructions based on the actual execution order of the instructions and the instruction order adjustment information, and sending the prescribed memory access order corresponding to the prescribed execution order to the software verification platform.

2. The method according to claim 1, characterized in that, The step of sending the behavior information and behavior result information of the chip to be verified during program execution to the software verification platform according to the preset strategy includes: After each instruction in the hardware simulation program is executed, the program sends the behavior information and behavior result information of the chip to be verified during the program execution to the software verification platform.

3. The method according to claim 1, characterized in that, The behavioral information also includes at least one of the following: instruction exit information, instruction interruption information.

4. The method according to claim 1, characterized in that, The memory access information of the instruction also includes at least one of the following: memory type, size of the accessed data, memory access information lost due to an abnormal situation, and memory information updated due to the predictive execution of the instruction.

5. The method according to claim 1, characterized in that, The number of processor cores is at least two, and there is at least one first processor core and one second processor core, wherein the clock frequency of the first processor core is different from the clock frequency of the second processor core. At least two processor cores access memory in an order based on their respective clock cycles. The step of sending the behavior information and behavior result information of the chip to be verified during program execution to the software verification platform includes: The access order based on the clock of each processor core and the clock difference of each processor core are sent to the software verification platform; or, the access order based on the clock difference of each processor core is synchronized to obtain a synchronization order, and the synchronization order is sent to the software verification platform.

6. The method according to claim 1, characterized in that, Before sending the behavior information and behavior result information of the chip to be verified during program execution to the software verification platform according to the preset strategy, the method further includes: Determine whether the instruction corresponding to the behavior information and the behavior result information is a predicted execution instruction; In response to the instruction being a predicted instruction, determine whether the predicted instruction was successfully predicted; The step of sending the behavior information and behavior result information of the chip to be verified during program execution to the software verification platform according to the preset strategy includes: sending the behavior information and behavior result information to the software verification platform when the prediction is successful; and refusing to send the behavior information and behavior result information to the software verification platform when the prediction fails.

7. The method according to claim 1, characterized in that, The behavioral outcome information includes at least one of the following: Fixed-point register information after instruction exit, floating-point register information after instruction exit, and status register information after instruction exit.

8. The method according to any one of claims 1 to 7, characterized in that, After running the hardware simulation program for the chip to be verified, and before sending the behavior information and behavior result information of the chip to be verified during program execution to the software verification platform according to a preset strategy, the method further includes: When executing each instruction in the hardware simulation program, obtain the behavior information of that instruction; After executing each instruction in the hardware simulation program, obtain the behavior result information corresponding to that instruction; According to a preset protocol, the behavioral information and the behavioral result information are used to generate a verification data packet; Sending the behavior information and behavior result information of the chip to be verified during program execution to the software verification platform includes sending the verification data packet to the software verification platform.

9. The method according to any one of claims 1 to 7, characterized in that, The step of sending the behavior information and behavior result information of the chip to be verified during program execution to the software verification platform includes: The chip under test is sent to the software verification platform via the Direct Programming Interface (DPI) to record the behavior and results of the chip during program execution.

10. A chip verification method, characterized in that, Based on a software verification platform, including: The system receives behavioral information and behavioral result information of the chip to be verified running on the hardware verification platform, sent by the hardware verification platform. The behavioral information includes the operations performed during program execution, and the behavioral result information includes the results or effects produced by the operations. Run the reference model corresponding to the chip to be verified based on the behavioral information to obtain the corresponding model result information; The chip to be verified is verified and reviewed based on the behavioral result information and the model result information. The behavioral information includes memory access information for instructions; The memory access information of the instruction includes the memory access order of at least one processor core. Before verifying and reviewing the chip to be verified based on the behavioral result information and the model result information, the method further includes: Based on the memory access information, detect whether the chip to be verified has cache consistency defects and / or memory consistency defects; The actual execution order of instructions in the hardware simulation program of the chip to be verified includes out-of-order execution and / or predictive execution; the access order is the actual memory access order corresponding to the actual execution order of instructions in the hardware simulation program. The step of detecting whether the chip under verification has cache consistency defects and / or memory consistency defects based on the memory access information includes: The prescribed execution order of the instructions is determined based on the actual execution order of the instructions and the instruction order adjustment information received in advance from the hardware verification platform. Based on the specified memory access order corresponding to the specified execution order of the instructions, the chip to be verified is detected to have cache consistency defects and / or memory consistency defects.

11. The method according to claim 10, characterized in that, The received hardware verification platform sends behavioral information and behavioral result information about the chip to be verified running on the hardware verification platform, including: Receive verification data packets sent by the hardware verification platform, wherein the verification data packets are generated by the behavior information and the behavior result information according to a preset protocol; The behavior information and the behavior result information are obtained by parsing the verification data packet.

12. The method according to claim 10, characterized in that, The step of running the reference model corresponding to the chip to be verified based on the behavioral information includes: The behavioral information is restored to the behavioral sequence of the chip to be verified using a preset script; The reference model is driven by the behavioral sequence.

13. The method according to claim 10, characterized in that, The verification and review of the chip to be verified based on the behavioral result information and the model result information includes: The behavioral outcome information is compared with the model outcome information; The verification results will determine whether the chip to be verified has passed.

14. The method according to claim 13, characterized in that, The comparison result indicates that the chip to be verified failed the verification. The method further includes: Based on the comparison results, the chip to be verified was inspected for defects.

15. The method according to claim 10, characterized in that, The behavioral information also includes at least one of the following: instruction exit information, instruction interruption information.

16. The method according to claim 10, characterized in that, The memory access information of the instruction also includes at least one of the following: memory type, size of the accessed data, memory access information lost due to an abnormal situation, and memory information updated due to the predictive execution of the instruction.

17. The method according to claim 10, characterized in that, The number of processor cores is at least two, and there is at least one first processor core and one second processor core, wherein the clock frequency of the first processor core is different from the clock frequency of the second processor core. At least two processor cores access memory in an order based on their respective clock cycles. The step of detecting whether the chip under verification has cache consistency defects and / or memory consistency defects based on the memory access information includes: Based on the clock differences of each processor core, the access order based on the clock of each processor core is synchronized to obtain the synchronization order. Based on the synchronization sequence, detect whether the chip to be verified has cache consistency defects and / or memory consistency defects.

18. A chip verification device, characterized in that, include: The first execution unit is used to run the hardware simulation program of the chip to be verified; The sending unit, according to a preset strategy, sends behavioral information and behavioral result information of the chip to be verified during program execution to the software verification platform, so that the software verification platform can verify and review the chip to be verified based on the behavioral information and the behavioral result information; wherein, the behavioral information includes the operations performed during program execution, and the behavioral result information includes the results or effects produced by the operations; the preset strategy includes the timing of sending the behavioral information and the behavioral result information to the software verification platform, or the information structure and organization form of the behavioral information and the behavioral result information; The behavioral information includes memory access information of instructions; the memory access information of instructions includes the memory access order of at least one processor core. The actual execution order of instructions in the hardware simulation program of the chip to be verified includes out-of-order execution and / or predictive execution; the access order is the actual memory access order corresponding to the actual execution order of instructions in the hardware simulation program. The sending unit is specifically configured to: send the actual memory access order corresponding to the actual execution order of the instructions, and the instruction order adjustment information, to the software verification platform; or, determine the prescribed execution order of the instructions based on the actual execution order of the instructions and the instruction order adjustment information, and send the prescribed memory access order corresponding to the prescribed execution order to the software verification platform.

19. The apparatus according to claim 18, characterized in that, The sending unit is specifically used to send the behavior information and behavior result information of the chip to be verified during program execution to the software verification platform after each instruction in the hardware simulation program has been executed.

20. The apparatus according to claim 18, characterized in that, The behavioral information also includes at least one of the following: instruction exit information, instruction interruption information.

21. The apparatus according to claim 18, characterized in that, The memory access information of the instruction also includes at least one of the following: memory type, size of the accessed data, memory access information lost due to an abnormal situation, and memory information updated due to the predictive execution of the instruction.

22. The apparatus according to claim 18, characterized in that, The number of processor cores is at least two, and there is at least one first processor core and one second processor core. The clock frequency of the first processor core is different from the clock frequency of the second processor core. The access order of the memory by the at least two processor cores is based on the access order of the individual clocks of the processor cores. The transmitting unit is specifically used for: The access order based on the clock of each processor core and the clock difference of each processor core are sent to the software verification platform; or, the access order based on the clock difference of each processor core is synchronized to obtain a synchronization order, and the synchronization order is sent to the software verification platform.

23. The apparatus according to claim 18, characterized in that, Also includes: The first determining unit is used to determine whether the instruction corresponding to the behavior information and the behavior result information is a predicted execution instruction before sending the behavior information and behavior result information of the chip to be verified during program execution to the software verification platform according to a preset strategy. The second determining unit is configured to determine whether the instruction to be executed is successfully predicted in response to the instruction being a predicted execution instruction. The sending unit is specifically configured to: send the behavior information and the behavior result information to the software verification platform when the prediction is successful; and refuse to send the behavior information and the behavior result information to the software verification platform when the prediction fails.

24. The apparatus according to claim 18, characterized in that, The behavioral result information includes at least one of the following: fixed-point register information after instruction exit, floating-point register information after instruction exit, and status register information after instruction exit.

25. The apparatus according to any one of claims 18 to 24, characterized in that, Also includes: The first acquisition unit is used to acquire the behavior information of each instruction when executing the hardware simulation program after running the hardware simulation program of the chip to be verified, before sending the behavior information and behavior result information of the chip to be verified during program execution to the software verification platform according to a preset strategy. The second acquisition unit acquires the behavior result information corresponding to each instruction after executing each instruction in the hardware simulation program; The generation unit is used to generate a verification data packet from the behavior information and the behavior result information according to a preset protocol; The sending unit is specifically used to send the verification data packet to the software verification platform.

26. The apparatus according to any one of claims 18 to 24, characterized in that, The sending unit is specifically used to send the behavior information and behavior result information of the chip to be verified during program execution to the software verification platform through the Direct Programming Interface (DPI).

27. A chip verification device, characterized in that, include: The receiving unit is used to receive behavioral information and behavioral result information of the chip to be verified running on the hardware verification platform, which are sent by the hardware verification platform; wherein, the behavioral information includes the operations performed during program execution, and the behavioral result information includes the results or effects produced by the operations; The second operation unit runs the reference model corresponding to the chip to be verified according to the behavioral information and obtains the corresponding model result information. The verification unit is used to verify and verify the chip to be verified based on the behavioral result information and the model result information. The behavioral information includes memory access information for instructions; The memory access information of the instruction includes the memory access order of at least one processor core. The actual execution order of instructions in the hardware simulation program of the chip to be verified includes out-of-order execution and / or predictive execution; the access order is the actual memory access order corresponding to the actual execution order of instructions in the hardware simulation program. The device further includes: a detection unit, configured to detect, based on the memory access information, whether the chip to be verified has cache consistency defects and / or memory consistency defects before verifying and reviewing the chip to be verified based on the behavior result information and the model result information; The detection unit includes: The sequence determination module is used to determine the prescribed execution order of the instructions based on the actual execution order of the instructions and the instruction order adjustment information received in advance from the hardware verification platform. The first detection module is used to detect whether the chip to be verified has cache consistency defects and / or memory consistency defects according to the specified memory access order corresponding to the specified execution order of the instructions.

28. The apparatus according to claim 27, characterized in that, The receiving unit includes: The receiving module is used to receive the verification data packet sent by the hardware verification platform. The verification data packet is generated by the behavior information and the behavior result information according to a preset protocol. The parsing module is used to parse the verification data packet to obtain the behavior information and the behavior result information.

29. The apparatus according to claim 27, characterized in that, The second operating unit includes: The restoration module is used to restore the behavioral information into the behavioral sequence of the chip to be verified through a preset script. A driving module is used to drive the reference model to run using the behavior sequence.

30. The apparatus according to claim 27, characterized in that, The review unit includes: The comparison module is used to compare the behavioral result information with the model result information; The determination module is used to determine whether the chip to be verified has passed the verification based on the comparison results.

31. The apparatus according to claim 30, characterized in that, The comparison result indicates that the chip to be verified failed the verification. The device further includes a screening unit, used to screen the chip to be verified for defects based on the comparison results.

32. The apparatus according to claim 30, characterized in that, The behavioral information also includes at least one of the following: instruction exit information, instruction interruption information.

33. The apparatus according to claim 27, characterized in that, The memory access information of the instruction also includes at least one of the following: memory type, size of the accessed data, memory access information lost due to an abnormal situation, and memory information updated due to the predictive execution of the instruction.

34. The apparatus according to claim 27, characterized in that, The number of processor cores is at least two, and there is at least one first processor core and one second processor core, wherein the clock frequency of the first processor core is different from the clock frequency of the second processor core. At least two processor cores access memory in an order based on their respective clock cycles. The detection unit includes: The clock synchronization module is used to synchronize the access order based on the clock differences of each processor core to obtain the synchronization order. The second detection module is used to detect whether the chip to be verified has cache consistency defects and / or memory consistency defects according to the synchronization order.

35. A chip verification system, characterized in that, It includes a hardware verification platform and a software verification platform; the hardware verification platform is communicatively connected to the software verification platform through a preset interface; wherein, the hardware verification platform is used to execute the chip verification method of any one of claims 1-9, and the software verification platform is used to execute the chip verification method of any one of claims 10-17.

36. An electronic device, characterized in that, include: The device comprises a housing, at least one processor, a memory, a circuit board, and a power supply circuit, wherein the circuit board is disposed within the space enclosed by the housing, and the processor and memory are disposed on the circuit board; the power supply circuit is used to supply power to various circuits or devices of the aforementioned electronic device; the memory is used to store executable program code; the at least one processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory, for executing the chip verification method of any one of claims 1-17.

37. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores one or more programs, which can be executed by one or more processors to implement the chip verification method according to any one of claims 1-17.

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