Mask handling method, electronic device, and storage medium

Abstract

Example embodiments of the present disclosure provide a mask plate processing method, an electronic device and a storage medium. The method comprises: obtaining a plurality of layout entities of a circuit layout on a plurality of mask plates, wherein each layout entity has a corresponding pattern shape; dividing the plurality of layout entities into a plurality of categories based on the pattern shape of the layout entity, so that the layout entities belonging to the same category have the same pattern shape; and storing the layout entities belonging to the same category in the same storage area in the memory based on the classification result. The processing method of the circuit layout on the mask plate according to the present disclosure can save storage resources and improve data retrieval speed.

Description

Technical Field

[0001] The embodiments of this disclosure primarily relate to the semiconductor field, and more specifically, to methods for processing photomasks, electronic devices, and storage media. Background Technology

[0002] An integrated circuit layout is a planar geometric description of the actual physical state of an integrated circuit. Integrated circuit layout processing is a crucial step in integrated circuit design and manufacturing. With the continuous advancement of semiconductor manufacturing processes, integrated circuits are becoming increasingly larger, and the layout files describing them are also growing larger. Without a tool that can quickly process integrated circuit layouts, the processing speed of related workflows or processes will be significantly reduced.

[0003] In traditional technologies, data is organized according to the actual logical layout of the layout file to facilitate user operations, but this has a negative impact on the data indexing speed. Summary of the Invention

[0004] According to an example embodiment of this disclosure, a mask processing scheme is provided to at least partially overcome the above or other potential drawbacks.

[0005] In a first aspect of this disclosure, a method for processing a photomask is provided. The method includes acquiring multiple layout entities of circuit layouts on multiple photomasks, wherein each layout entity has a corresponding pattern shape; classifying the multiple layout entities into multiple categories based on the pattern shapes of the layout entities, such that layout entities belonging to the same category have the same pattern shape; and storing layout entities belonging to the same category in the same storage area in a memory based on the classification results.

[0006] In some embodiments, storing layout entities belonging to the same category in the same storage area of ​​the memory based on the classification result includes: obtaining the spatial correlation between a first layout entity and a second layout entity belonging to the same category among a plurality of layout entities based on the classification result; and storing the first layout entity and the second layout entity belonging to the same category in the same storage area of ​​the memory at corresponding different storage addresses related to the spatial correlation.

[0007] In some embodiments, a first number of layout entities belonging to a first category are stored in a first unit of storage space, and a second number of layout entities belonging to a second category are stored in a second unit of storage space. The first unit of storage space includes a first number of storage addresses, and the second unit of storage space includes a second number of storage addresses. The first number is different from the second number, and the first unit of storage space and the second unit of storage space have the same storage space size.

[0008] In some embodiments, spatial correlation relates to the positional relationship between a first layout entity and a second layout entity, each of a plurality of masks corresponds to a semiconductor processing layer in the semiconductor fabrication process, and the spatial correlation between two layout entities belonging to the same mask is stronger than the spatial correlation between two layout entities not belonging to the same mask; and the circuit layout includes a plurality of functional units, each functional unit being located in a specific area of ​​a mask, or spanning the same area on multiple masks, and the spatial correlation between two layout entities belonging to the same functional unit is stronger than the spatial correlation between two layout entities not belonging to the same functional unit.

[0009] In some embodiments, the method further includes storing layout entities belonging to different categories in different storage areas of the memory based on the classification results.

[0010] In some embodiments, the layout entity also includes text information, which provides textual annotations to the layout entity, and the text information is stored in the same storage area in the memory.

[0011] In a second aspect of this disclosure, a method for processing a circuit layout on a mask is provided, comprising: acquiring layout operation information; reading at least a portion of data from a layout dataset of the circuit layout from a memory based on the layout operation information, the layout dataset including data about a plurality of masks, each of the plurality of masks including at least one layout entity, the layout entities in the layout dataset being stored in memory according to shape category; and generating operation result information based on at least a portion of the data.

[0012] In some embodiments, layout entities with the same shape are stored in the same storage area in the memory, wherein a first number of layout entities belonging to a first category are stored in a first unit storage space, and a second number of layout entities belonging to a second category are stored in a second unit storage space. The first unit storage space includes a first number of storage addresses, and the second unit storage space includes a second number of storage addresses. The first number is different from the second number, and the first unit storage space and the second unit storage space have the same storage space size.

[0013] In some embodiments, a first number of layout entities belonging to a first category among a plurality of layout entities are stored in a first unit of storage space based on the spatial association between every two layout entities; and a second number of layout entities belonging to a second category among a plurality of layout entities are stored in a second unit of storage space based on the spatial association between every two layout entities.

[0014] In some embodiments, reading at least a portion of the layout dataset of the circuit layout from memory includes: pre-loading corresponding layout entities of multiple categories from corresponding unit storage space into corresponding cache lines based on layout operation information.

[0015] In a third aspect of this disclosure, an electronic device is provided. The electronic device includes a processor and a memory coupled to the processor, the memory having instructions stored therein, the instructions causing the device to perform actions when executed by the processor. The actions include: acquiring a plurality of layout entities of circuit layouts on a plurality of photomasks, wherein each layout entity has a corresponding pattern shape; classifying the plurality of layout entities into a plurality of categories based on the pattern shapes of the layout entities, such that layout entities belonging to the same category have the same pattern shape; and storing layout entities belonging to the same category in the same storage region of the memory based on the classification results.

[0016] In a fourth aspect of this disclosure, an electronic device is provided, comprising: a processor; and a memory coupled to the processor, the memory having instructions stored therein, the instructions causing the device to perform actions when executed by the processor, the actions including: acquiring layout operation information; reading at least a portion of data from a layout dataset of circuit layouts from the memory based on the layout operation information, the layout dataset including data about a plurality of masks, each of the plurality of masks including at least one layout entity, the layout entities in the layout dataset being stored in the memory according to shape categories; and generating operation result information based on at least a portion of the data.

[0017] In a fifth aspect of this disclosure, a computer-readable storage medium is provided having a computer program stored thereon that, when executed by a processor, implements the method according to a first aspect of this disclosure.

[0018] In a sixth aspect of this disclosure, a computer-readable storage medium is provided having a computer program stored thereon that, when executed by a processor, implements the method according to a second aspect of this disclosure.

[0019] In the method according to this disclosure, different categories of entities have their own independent storage space, and different types of layout entities are not located in the same memory block. Since layout entities of the same category have the same storage space size, memory blocks for multiple layout entities of each type can have the same size, and each memory block can store an integer number of layout entities of the same type. Each layout entity is not stored across multiple memory blocks. Therefore, the size of each memory block can be the same as the size of each cache line. When writing data to memory, no blank storage space needs to be inserted, thus saving storage resources and improving data retrieval speed.

[0020] It should be understood that the description in the Summary of the Invention is not intended to limit the key or essential features of the embodiments of this disclosure, nor is it intended to restrict the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0021] The above and other features, advantages, and aspects of the embodiments of this disclosure will become more apparent from the accompanying drawings and the following detailed description. In the drawings, the same or similar reference numerals denote the same or similar elements, wherein:

[0022] Figure 1A and Figure 1B This illustrates how computer-accessible data is organized according to the design layout of the circuit diagram;

[0023] Figure 2 A schematic diagram of an example environment in which some embodiments of this disclosure can be implemented is shown;

[0024] Figure 3 A flowchart illustrating a method for processing a circuit layout of a mask according to some embodiments of the present disclosure is shown;

[0025] Figure 4 A schematic diagram of the hierarchical structure of layout entities on a mask according to some embodiments of the present disclosure is shown;

[0026] Figure 5 A schematic diagram illustrating the storage structure of different categories of layout entities according to some embodiments of the present disclosure is shown;

[0027] Figure 6 A schematic diagram illustrating the unit storage space of different categories of layout entities according to some embodiments of the present disclosure is shown;

[0028] Figure 7A A structural block diagram illustrating the retrieval of stored data according to some embodiments of the present disclosure is shown;

[0029] Figure 7B A flowchart illustrating a method for processing a circuit layout of a mask according to some embodiments of the present disclosure is shown; and

[0030] Figure 8 A block diagram of a computing device capable of implementing several embodiments of the present disclosure is shown. Detailed Implementation

[0031] Embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings. While some embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this disclosure. It should be understood that the accompanying drawings and embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of protection of this disclosure.

[0032] In the description of embodiments of this disclosure, the term "comprising" and similar terms should be understood as open-ended inclusion, i.e., "including but not limited to". The term "based on" should be understood as "at least partially based on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The terms "first", "second", etc., may refer to different or the same objects. Other explicit and implicit definitions may also be included below.

[0033] As mentioned earlier, in traditional technology, computer-accessible data is organized according to the design layout of the circuit layout. That is, the design layout of the circuit layout takes into account the actual physical conditions on the mask when organizing computer-accessible data. Each circuit board diagram on the mask includes multiple layout entities, and each layout entity has a corresponding pattern shape. These pattern shapes include, but are not limited to, trapezoids, rectangles, circles, squares, and polygons with more than pentagons, etc. Among them, polygons with more than pentagons can be a combination of multiple rectangles, such as an L-shaped pattern shape.

[0034] Computers need to store and retrieve these layout entities. In traditional techniques, when storing data, the computer's processor divides memory (such as main memory) into multiple memory blocks (units of storage space) according to the size of a cache line. In one example, a cache line is 64 bytes in size. During data prefetching, the computer's processor reads data from memory into a corresponding cache line, with the cache line's storage space size being the same as the memory block's storage size. In one example, data from a memory block is read into a cache line.

[0035] Different shapes of layout patterns have different storage sizes in memory. However, layout patterns of the same shape can have the same storage size in memory even if they have different physical dimensions. When the processor processes layout data, layout patterns of different shapes have different byte lengths, while layout patterns of the same shape have the same byte length regardless of their physical size.

[0036] If two layout entities with different patterns are adjacent to each other on a photomask, the computer will store their data in adjacent memory addresses because it organizes the data according to the actual circuit layout design. However, since different types of layout entities differ significantly, storing different types of data tightly in memory would cause the computer to automatically insert blank storage spaces between memory blocks of different types to align them, resulting in wasted space. Forcibly removing these blank storage spaces would lead to entities stored at the boundary of one memory block being stored across another adjacent memory block. This would require reading two cache lines simultaneously when prefetching the corresponding entity, reducing computer access efficiency.

[0037] The following will be referenced Figure 1A and Figure 1B This explains how to organize computer-accessible data according to the design layout of the circuit diagram.

[0038] Figure 1A This diagram illustrates two adjacent memory blocks 101 and 102 in a memory 100, such as memory. On the mask, trapezoid A and polygon B are adjacent, polygon B is adjacent to trapezoid C, trapezoid C is adjacent to polygon D, polygon D is adjacent to trapezoid E, and trapezoid E is adjacent to polygon F. Therefore, in organizing computer-accessible data according to the circuit layout design, in memory addresses, trapezoid A and polygon B are adjacent, polygon B is adjacent to trapezoid C, trapezoid C is adjacent to polygon D, polygon D is adjacent to trapezoid E, and trapezoid E is adjacent to polygon F. Since the storage size of a polygon is larger than that of a trapezoid, therefore... Figure 1A In memory block 101, blank memory space 105 needs to be filled to align memory block 101 with memory block 102. By filling the blank memory space 105, during data prefetching, the data in memory block 101 is read into cache line 103, and the data in memory block 102 is read into cache line 104. However, filling the blank memory space 105 results in wasted space and also slows down the processing speed.

[0039] like Figure 1BAs shown, the empty memory space 105 in memory block 101 is removed. Polygon D stored at the boundary of memory block 102 needs to be stored across adjacent memory blocks 101 and 102. Furthermore, empty padding space 106 is added to the other boundary of memory block 102 to align the dimensions of both memory blocks 101 and 102 with the dimensions of the two cache lines 103 and 104. When prefetching the corresponding entities (such as trapezoid A, polygon B, trapezoid C, polygon D, trapezoid E, and polygon F mentioned above), both cache lines 103 and 104 need to be read simultaneously, which will reduce computer access efficiency.

[0040] In view of this, the present disclosure aims to provide an improved solution.

[0041] According to embodiments of this disclosure, a method for processing a mask layout is provided. The method includes: acquiring multiple layout entities of a circuit layout on multiple masks, wherein each layout entity has a corresponding pattern shape; classifying the multiple layout entities into multiple categories based on the pattern shape of the layout entities, such that layout entities belonging to the same category have the same pattern shape; and storing layout entities belonging to the same category in the same storage area in a memory or storing layout entities belonging to different categories in different storage areas in a memory based on the classification results. In one example, layout entities of a first category may be entities with rectangular patterns, layout entities of a second category may be entities with trapezoidal patterns, all layout entities with trapezoidal patterns may be stored in one storage area, and all layout entities with rectangular patterns may be stored in another storage area.

[0042] In the method according to this disclosure, different categories of entities have their own independent storage space, and different types of layout entities are not located in the same memory block. Since layout entities of the same category have the same storage space size, memory blocks for a certain number of layout entities of each type can have the same size. Each memory block can store an integer number of layout entities of the same type, and each layout entity is not stored across multiple memory blocks. Therefore, the size of each memory block can be the same as the size of each cache line. When writing data, there is no need to insert blank storage space between or within memory blocks, thus saving storage resources and improving data retrieval speed.

[0043] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. (Reference) Figure 2 This illustrates a schematic diagram of an example environment 201 in which various embodiments of the present disclosure can be implemented. For example... Figure 2 As shown, the example environment 201 includes a computing device 210 and a client 220.

[0044] In some embodiments, the computing device 210 can interact with the client 220. For example, the computing device 210 can receive input messages from the client 220 and output feedback messages to the client 220. In some embodiments, the input messages from the client 220 can be multiple layout entities in a circuit layout. The computing device 210 can classify the layout entities in the input messages and calculate the spatial relationships between different layouts to store and retrieve the layout entities. The retrieval results for the layout entities can be displayed on the client 220.

[0045] In some embodiments, the computing device 210 may include, but is not limited to, a personal computer, a server computer, a handheld or laptop device, a mobile device (such as a mobile phone, a personal digital assistant PDA, a media player, etc.), a consumer electronics product, a minicomputer, a mainframe computer, cloud computing resources, etc.

[0046] It should be understood that the description of the structure and functionality of example environment 201 for illustrative purposes only is not intended to limit the scope of the topics described herein. The topics described herein may be implemented in different structures and / or functionalities.

[0047] The technical solutions described above are for illustrative purposes only and are not intended to limit the invention. It should be understood that the example environment 201 can also have many other implementations. To more clearly explain the principles of this disclosure, reference will be made below. Figure 2 Let me describe it in more detail.

[0048] Figure 3 A flowchart of a mask processing method 300 according to some embodiments of the present disclosure is shown. For example, method 300 may be performed by, for example... Figure 2 The method is implemented using the computing device 210 shown. It should be understood that method 300 may also include additional boxes not shown and / or some boxes shown may be omitted. The scope of this disclosure is not limited in this respect.

[0049] At box 302, multiple layout entities of the circuit layout on multiple masks are obtained, where each layout entity has a corresponding pattern shape. In some embodiments, the masks can be generated by dedicated EDA tools, etc. The masks can be used for subsequent photolithography processing. All layout entities of the circuit layout on the masks can be further obtained using EDA tools. These layout entities can be, but are not limited to, shapes such as: text information, trapezoids, rectangles, circles, squares, polygons larger than pentagons, etc. Each mask can include multiple layout entities, which can belong to multiple different functional units. Functional units can be defined according to the functions required by the user. Smaller functional units can be nested within larger functional units. In one example, a functional unit can be located in a specific area on a mask. In another example, a functional unit can span corresponding areas on multiple masks, which have the same position on the mask, that is, multiple areas stacked together in the vertical direction.

[0050] The following will be for reference Figure 4 To illustrate the hierarchical structure of the layout entities on photomasks 400A to 400C. For example... Figure 4 As shown, multiple layout entities include polygonal entities 401A to 401D, trapezoidal entities 402A to 402D, text information 403, and circular entity 404. One or more of these entities constitute a mask 400A to 400C, and each mask 400A to 400C may include different layout entities. The mask 400A, 400B, or 400C corresponds to a processing layer in the semiconductor fabrication process. It should be understood that the entities shown are merely exemplary, and different entities may be included depending on the structure of the semiconductor layer to be implemented.

[0051] like Figure 4 As shown, functional unit 40 can span multiple identical regions 41 on multiple masks 400A to 400C. In another example, functional unit 40 may also include only one region 41 on a single mask. The same functional unit 40 can have different layout entities on multiple regions of different masks 400A to 400C; that is, the layout entities in region 41 of the first mask 400A may be different from the layout entities in region 41 of the second mask 400B or 400C. The layout entities contained in each region can be defined according to the functionality to be implemented.

[0052] In one example, text information 403 is used to label each layout entity. This labeling information allows users to understand the layout more intuitively in natural language. For example, it indicates which functional unit a layout entity belongs to and what pattern feature it corresponds to, such as one or more functional patterns in a via, electrode wiring, or channel region. The text information can have any shape. In one example, the text information has a rectangular shape. All text information belongs to the same category. Text information is classified as an entity in a separate category, rather than based on shape.

[0053] At box 304, based on the pattern shape of the layout entities, multiple layout entities 401A to 404 are divided into multiple categories, such that layout entities belonging to the same category have the same pattern shape. For example, trapezoidal entities 402A and 402B have the same pattern shape, and these two trapezoidal entities belong to the same category. However, polygonal entities, trapezoidal entities, and circular entities belong to different categories. In this disclosure, the term "same pattern shape" simply means belonging to a uniform category; it can be the same shape but different sizes, or other specified high-similarity graphics.

[0054] At box 306, based on the classification results, layout entities belonging to the same category are stored in the same storage area in memory, or layout entities belonging to different categories are stored in different storage areas in memory.

[0055] The following will be for reference Figure 5 To illustrate the storage structure of different types of layout entities 500. Figure 5 Schematic diagrams illustrating the storage structures of different categories of layout entities according to some embodiments of this disclosure are shown. For example... Figure 5 As shown, circular entities are stored in the first storage area 501, polygonal entities are stored in the second storage area 502, and trapezoidal entities are stored in the third storage area 503. In one example, the mask 400 also includes text information 403, therefore the storage area also includes a fourth storage area 504 for the text information, which can have any shape. In one example, the text information has a rectangular shape. All the text information is stored in the same storage area 504. The text information is classified into a separate category of entities, rather than based on shape. It should be understood that the above storage areas are merely exemplary, and users can define their required storage space according to the types or number of types they classify.

[0056] Therefore, in the method according to this disclosure, different categories of entities have their own independent storage space, and different types of layout entities do not reside in the same memory block. Since layout entities of the same category have the same storage space size, memory blocks for a specific number of layout entities of each type (e.g., four trapezoidal entities or three polygonal entities) can have the same size, and each memory block can store an integer number of layout entities of the same type (e.g., each memory block stores four trapezoidal entities and each memory block stores three polygonal entities). Each layout entity is not stored across multiple memory blocks. Therefore, each memory...

[0057] The block size can be the same as the size of each cache line. When writing data, there is no need to insert blank storage space, and when prefetching data, only one cache line can be read, thus saving storage resources and improving data retrieval speed.

[0058] To better understand the advantages of the mask circuit layout processing method according to this disclosure, the following will refer to... Figure 6 Let me explain. Figure 6 A schematic diagram of the unit storage space of different categories of layout entities according to some embodiments of the present disclosure is shown.

[0059] 0 Figure 6 This illustrates two adjacent memory blocks 601 and 602 in a memory such as memory 600.

[0060] A memory block is a unit of storage space. For example... Figure 6 As shown, the storage space dimensions of the four trapezoidal entities A to D are the same as the storage space dimensions of the three polygonal entities E to G. Memory block 601

[0061] Four trapezoidal entities A to D are stored in memory block 602, and three polygonal entities E are stored in memory block 602.

[0062] Therefore, the number of layout entities stored in a memory block varies for different types of 5 layout entities, but by properly designing the storage size of the layout entities, the number of entities stored in each block can be increased.

[0063] An integer number of layout entities of the same type can be written into a memory block. When writing data, polygonal entities E at the edges of the memory block will not be... Figure 1B As shown, it is stored across two adjacent memory blocks, and no blank storage space needs to be filled. Therefore, when prefetching the corresponding entity,

[0064] For example, when fetching four trapezoidal entities, the data only needs to be read into cache line 603. When prefetching the corresponding zero entities, such as three polygonal entities, the data only needs to be read into cache line 604, which will improve computer access efficiency.

[0065] There are certain relationships between multiple layout entities of the same type within the same storage region. When storing multiple layout entities of the same type (e.g., four trapezoidal entities or three polygonal entities) within the same storage region, or more specifically, the same memory block, determining the storage addresses or storage order of these layout entities within the memory block requires considering these relationships.

[0066] Relationships between entities. Furthermore, although different types of layout entities are stored in different storage areas, they also have certain spatial relationships if they belong to the same mask or the same functional unit.

[0067] The following will be for reference Figure 4 This is used to illustrate the spatial relationships between different map entities.

[0068] like Figure 4 As shown, polygonal entities 401A and 401B on mask 400A belong to the same category and are located on the same functional unit. When calculating the position of polygonal entity 401A relative to polygonal entity 401B, for example, the position of polygonal entity 401A relative to the polygonal entity 401B can be calculated.

[0069] Information such as the orientation of polygon entity 401B and the distance between polygon entities 401A and 401B. Positional relationships may include other suitable parameters. Suitable parameters used to represent positional relationships can be defined according to user needs; positional relationships such as orientation and distance are merely exemplary parameters.

[0070] If polygonal entity 401B is the closest entity to polygonal entity 401A

[0071] Then, polygon entities 401A and 401B are stored adjacent to each other in the memory block. If another polygon entity (not shown) exists on the mask 400A, and this other polygon entity is farther away from polygon entity 401A than polygon entity 401B, then this other polygon entity is stored in the memory block at a position farther away from polygon entity 401A than polygon entity 401B.

[0072] like Figure 4 As shown, trapezoidal entities 402A and 402B on mask 400A belong to the same category 5, but are located on different functional units. First, determine whether trapezoidal entities 402A and 402B belong to the edge layout entities of the corresponding functional units. If these entities do not belong to the edge entities of these functional units, their spatial correlation is weak, and they are stored far apart in memory. If these trapezoidal entities 402A and 402B belong to these functional units...

[0073] If the edge entities of a function unit are adjacent, then the physical locations of these entities may be adjacent. In adjacent memory blocks representing different function units, these two trapezoidal entities may be stored adjacently.

[0074] like Figure 4 As shown, polygonal entity 401A on mask 400A and polygonal entity 401C on mask 400B or polygonal entity 401D on mask 400C belong to the same category, to different masks, but to the same functional unit.

[0075] The spatial correlation is also relatively strong, but weaker than the spatial correlation between polygonal entities 401A and 401B. Compared with polygonal entity 401B, polygonal entities 401C and 401D are stored in memory blocks at locations farther away from polygonal entity 401A than polygonal entity 401B.

[0076] like Figure 4 As shown, trapezoidal entity 402A on mask 400A and trapezoidal entity 402C on mask 400B belong to the same category, but are assigned to different masks and different functional units. Therefore, the spatial correlation between them is weak, and weaker than the spatial correlation between trapezoidal entities 402A and 402B. When a user searches for all trapezoidal entities located on different layers or masks, trapezoidal entities 402A and 402C will be retrieved simultaneously.

[0077] It should be noted that the value range of spatial correlation is continuous, not a binary attribute. That is, entities with smaller Euclidean distances have higher spatial correlations.

[0078] The greater the distance between entities, the lower their spatial correlation. In practical applications (when viewing a map or processing a layout on a computer), multiple entities within a local area are typically processed. Therefore, entities that do not belong to the same mask layer or have a large Euclidean distance on the same mask layer have low spatial correlation.

[0079] 0 as Figure 4 As shown, polygonal entity 401A and trapezoidal entity 402A on mask 400A belong to different categories but are located on the same functional unit. Although they are stored in different memory blocks, for example, on the same mask and within the same functional unit, if the user needs to retrieve all layout entities on mask 400A within functional unit 40, both polygonal entity 401A and trapezoidal entity 402A will be retrieved and displayed simultaneously.

[0080] 5 such as Figure 4As shown, polygonal entity 401A and trapezoidal entity 402B on mask 400A belong to different categories and are located on different functional units. They are stored in different memory blocks. If the user needs to retrieve all layout entities located on mask 400A, polygonal entity 401A and trapezoidal entity 402B will be retrieved simultaneously.

[0081] like Figure 4 As shown, polygonal entity 401A on mask 400A and trapezoidal entity 402D on mask 400B0 belong to different masks, belong to the same functional unit, but do not belong to the same category. When a user needs to retrieve all layout entities of a certain functional unit located on different masks, polygonal entity 401A and trapezoidal entity 402D will be retrieved and displayed simultaneously.

[0082] like Figure 4 As shown, the polygonal entity 401A on mask 400A and the trapezoidal entity 402C on mask 400B5 belong to different masks and different functional units.

[0083] They do not belong to the same category. When a user needs to retrieve all layout entities on different masks, polygonal entity 401A and trapezoidal entity 402C will be retrieved and displayed simultaneously.

[0084] Entities of the same type are stored closely together based on spatial affinity, such as being stored in the same memory block or the same storage region. When querying layout information, spatially adjacent information is easily retrieved together. According to the principle of locality of reference in computer access, applications tend to access values ​​that are closer together in memory when accessing memory. For example, when accessing polygon entity 401A, the application tends to retrieve other polygon entities stored together with polygon entity 401A in a unit storage space (e.g., a memory block) and load them all into the corresponding cache line. In this application, since each unit storage space includes an integer number of polygon entities, there is no need to fill empty storage space in the unit storage space (i.e., memory block), thus avoiding space waste and reducing the number of memory accesses. Furthermore, a layout entity is not stored across memory blocks, so only one memory block needs to be read. However, it should be understood that when the computer's access logic needs to load data into two memory lines, data in two memory blocks can be read simultaneously. Therefore, the classification and stacking method used in the embodiments of this disclosure for storing entities is highly optimized for the principle of locality of reference in computer access. Therefore, closely arranged entities based on categories can help improve information retrieval efficiency.

[0085] Figure 7AA structural block diagram illustrating the retrieval of stored data according to some embodiments of the present disclosure is shown. The position of each layout entity on the mask is known in advance. During data retrieval, layout operation information is first received via client 220, such as a user wanting to view or further modify layout entities on mask 400A. The computing device 210 then retrieves a dataset of layout entities on the mask from memory based on the layout operation information. For example, data regarding trapezoidal entities 402A and 402B is read from the corresponding memory block in third storage area 503, data regarding polygonal entities 401A and 401B is read from the corresponding memory block in second storage area 502, data regarding circular entity 404 is read from the corresponding memory block in first storage area 501, and data regarding text information is read from the corresponding memory block in fourth storage area 504. Finally, the retrieved layout entities are displayed to the user in the form of a mask.

[0086] like Figure 7A As shown, the structure may include a query interface 701. This query interface, based on constraints in a query statement, simulates or transforms the actual classification-based storage structure into an actual layout file, thereby retrieving information from multiple memory blocks in multiple storage areas. This forms a mask corresponding to a layer, or multiple stacked areas corresponding to a functional unit, that can be intuitively displayed to the client. The above examples illustrate displaying layout entities (e.g., trapezoidal entities 402A to 402D) in the form of layers or masks 400A to 400C, functional units 40, or entities of the same category. However, layout entities can also be retrieved according to other constraints. During the retrieval process, references are not involved. Figure 1A and 1B The described actual copy of the mask layout improves efficiency. The query interface 701 can convert the stored layout data into an actual layout file layout based on a query statement, that is, to retrieve layout entities scattered across multiple storage areas together, thus facilitating user querying and reading.

[0087] The following will be referenced Figure 7B This describes a method 700 for retrieving and displaying stored data based on layout operation information.

[0088] At box 702, layout operation information is received, for example, via client 220. This layout operation information could be, for example, viewing all layout entities on a mask, viewing all layout entities contained in a functional unit spanning multiple masks, viewing all layout entities of a category on a mask, or viewing layout entities at a specific location on the mask. The layout operation information can be freely defined by the user according to their needs.

[0089] At box 704, at least a portion of the layout dataset of the circuit layout is read from memory based on layout operation information. The layout dataset includes data about multiple masks, each mask including at least one layout entity, and the layout entities in the layout dataset are stored in the memory according to shape category. For example, if a user wants to view all trapezoidal entities on mask 400A, data about trapezoidal entities 402A and 402B is read from the corresponding memory blocks in the third storage area 503. The read data includes data about trapezoidal entities 402A and 402B. Reading at least a portion of the layout dataset of the circuit layout from memory based on layout operation information can be achieved, for example, by the query interface 701 described above, which can retrieve the required information from the corresponding storage address based on the layout operation information.

[0090] As described above, because layout entities are stored in the memory according to shape categories, different categories of entities have their own independent storage space, and different types of layout entities do not reside in the same memory block. Since layout entities of the same category have the same storage space size, memory blocks for a specific number of layout entities of each type (e.g., four trapezoidal entities or three polygonal entities) can have the same size. Each memory block can store an integer number of layout entities of the same type (e.g., each memory block stores four trapezoidal entities and each memory block stores three polygonal entities), and each layout entity is not stored across multiple memory blocks. Therefore, the size of each memory block can be the same as the size of each cache line. When writing data, no blank storage space needs to be inserted, and when prefetching data, only one cache line can be read, thus saving storage resources and improving data retrieval speed.

[0091] In box 706, operation result information is generated based on at least a portion of the data. For example, based on the retrieved data about trapezoidal entities 402A and 402B, trapezoidal entities 402A and 402B are displayed for user viewing. Generating operation result information based on the at least a portion of the data can be achieved, for example, by the query interface 701 described above, which organizes the retrieved information together for display to the user. Query interface 701 can convert the stored layout data into an actual layout file layout based on a query statement, that is, for example, retrieving layout entities scattered across multiple storage areas together, thereby facilitating user querying and reading.

[0092] Figure 8 A schematic block diagram of an example device 800 that can be used to implement embodiments of the present disclosure is shown. For example, Figure 2 The computing device 210 shown can be implemented by device 800. As shown, device 800 includes a central processing unit (CPU) 801, which can perform various appropriate actions and processes according to computer program instructions stored in read-only memory (ROM) 802 or loaded from storage unit 808 into random access memory (RAM) 803. RAM 803 may also store various programs and data required for the operation of device 800. CPU 801, ROM 802, and RAM 803 are interconnected via bus 804. Input / output (I / O) interface 805 is also connected to bus 804.

[0093] Multiple components in device 800 are connected to I / O interface 805, including: input unit 806, such as keyboard, mouse, etc.; output unit 807, such as various types of monitors, speakers, etc.; storage unit 808, such as disk, optical disk, etc.; and communication unit 809, such as network card, modem, wireless transceiver, etc. Communication unit 809 allows device 800 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0094] Processing unit 801 executes the various methods and processes described above, such as method 300. For example, in some embodiments, method 300 may be implemented as a computer software program tangibly contained in a machine-readable medium, such as storage unit 808. In some embodiments,

[0095] Part or all of the computer program may be loaded and / or installed onto the device 800 via ROM 802 and / or communication unit 809. When the computer program is loaded into RAM 803 and executed by CPU 801, one or more steps of the method 300 described above may be performed. Alternatively, in other embodiments, CPU 801 may be configured to perform method 300 by any other suitable means (e.g., by means of firmware).

[0096] The functions described above in this document can be performed at least in part by one or more hardware logic components. For example, exemplary types of hardware logic components that can be used, without limitation, include: field programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload programmable logic devices (CPLDs), and so on.

[0097] Program code used to implement the methods of this disclosure may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus, such that when executed by the processor or controller, the program code causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code may be fully or partially machine-executable, as...

[0098] A standalone software package may be executed partly on the machine and partly on a remote machine, or entirely on a remote machine or server.

[0099] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can also be a machine-readable signal medium.

[0100] Machine-readable storage media. Machine-readable media can include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0101] Furthermore, although the operations are described in a specific order, this should be understood as requiring that such operations be performed in the specific order shown or in sequential order, or requiring that all illustrated operations be performed to achieve the desired result. In certain environments, multitasking and parallel processing may be advantageous. Similarly, although several specific implementation details are included in the above discussion, these should not be construed as limiting the scope of this disclosure. Certain features described in the context of individual embodiments may also be implemented in combination in a single implementation. Conversely, various features described in the context of a single implementation may also be implemented individually or in any suitable sub-combination in multiple implementations.

[0102] Although the subject matter has been described using language specific to structural features and / or methodological logic, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. Rather, the specific features and actions described above are merely illustrative examples of implementing the claims.

Claims

1. A method for processing a circuit layout on a photomask, comprising: Obtain multiple layout entities of circuit layouts on multiple masks, where each layout entity has a corresponding pattern shape; Based on the pattern shape of the layout entities, the plurality of layout entities are divided into multiple categories, such that the layout entities belonging to the same category have the same pattern shape; Based on the classification results, the spatial correlation between the first and second map entities belonging to the same category among the multiple map entities is obtained; as well as The first and second layout entities belonging to the same category are stored in corresponding different storage addresses in the same storage region of the memory, which are related to the spatial association.

2. The method according to claim 1, wherein A first number of layout entities belonging to the first category are stored in a first unit of storage space, and a second number of layout entities belonging to the second category are stored in a second unit of storage space. The first unit of storage space includes the storage address of the first number, and the second unit of storage space includes the storage address of the second number. The first number is different from the second number, and the first unit of storage space and the second unit of storage space have the same storage space size.

3. The method according to claim 1, wherein the spatial correlation is related to the positional relationship between the first map entity and the second map entity. Each of the plurality of photomasks corresponds to each semiconductor processing layer in the semiconductor fabrication process, wherein the spatial correlation between two layout entities belonging to the same photomask is stronger than the spatial correlation between two layout entities not belonging to the same photomask; and The circuit layout includes multiple functional units, each located in a corresponding area on a mask or spanning the same area on multiple masks, wherein the spatial correlation between two layout entities belonging to the same functional unit is stronger than the spatial correlation between two layout entities not belonging to the same functional unit.

4. The method according to claim 1, further comprising: Based on the classification results, map entities belonging to different categories are stored in different storage areas in the memory.

5. The method according to claim 1, wherein the layout entity further includes text information, the text information providing textual annotations to the layout entity, and the text information being stored in the same storage area in the memory.

6. A method for processing a circuit layout on a photomask, comprising: Obtain map operation information; Based on the layout operation information, at least a portion of the data in the layout dataset of the circuit layout is read from the memory. The layout dataset includes data about multiple masks, each of which includes at least one layout entity. The layout entities in the layout dataset are stored in the memory according to shape categories, wherein layout entities belonging to the same category among the multiple layout entities are stored in the same unit of storage space based on the spatial association between every two layout entities. as well as Based on at least a portion of the data, operation result information is generated.

7. The method of claim 6, wherein layout entities having the same shape are stored in the same storage region in the memory, wherein A first number of layout entities belonging to the first category among the plurality of layout entities are stored in a first unit of storage space. The second number of layout entities belonging to the second category are stored in the second unit of storage space. The first unit of storage space includes the first number of storage addresses, the second unit of storage space includes the second number of storage addresses, the first number is different from the second number, and The first unit of storage space and the second unit of storage space have the same storage space size.

8. The method of claim 7, wherein a first number of layout entities belonging to a first category among the plurality of layout entities are stored in the first unit storage space based on the spatial association between every two layout entities; and A second number of layout entities belonging to the second category among the plurality of layout entities are stored in the second unit storage space based on the spatial association between every two layout entities.

9. The method of claim 7, wherein reading at least a portion of the layout dataset of the circuit layout from the memory comprises: Based on the layout operation information, the corresponding layout entities of multiple categories are pre-stored from the corresponding unit storage space into the corresponding cache line.

10. An electronic device, comprising: processor; as well as A memory coupled to a processor, the memory having instructions stored therein, which, when executed by the processor, cause the device to perform actions, including: Obtain multiple layout entities of circuit layouts on multiple masks, where each layout entity has a corresponding pattern shape; Based on the pattern shape of the layout entities, the plurality of layout entities are divided into multiple categories, such that the layout entities belonging to the same category have the same pattern shape; Based on the classification results, the spatial correlation between first and second map entities belonging to the same category among the multiple map entities is obtained; and The first and second layout entities belonging to the same category are stored in corresponding different storage addresses related to the spatial association within the same storage region of the memory.

11. An electronic device, comprising: processor; as well as A memory coupled to a processor, the memory having instructions stored therein, which, when executed by the processor, cause the device to perform actions, including: Obtain map operation information; Based on the layout operation information, at least a portion of the layout dataset of the circuit layout is read from memory. The layout dataset includes data about multiple photomasks, each of which includes at least one layout entity. The layout entities in the layout dataset are stored in the memory according to shape categories, wherein layout entities belonging to the same category are stored in the same unit of storage space based on the spatial association between any two layout entities. Based on at least a portion of the data, operation result information is generated.

12. A computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the method according to any one of claims 1-5.

13. A computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the method according to any one of claims 6 to 9.

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