Pixel circuit, pixel driving method and display device

Abstract

The present invention provides a pixel circuit, a pixel driving method, and a display device. The pixel circuit includes a light-emitting element, a driving circuit, a first energy storage circuit, a second energy storage circuit, a switch control circuit, and a data writing circuit. The data writing circuit writes a data voltage to a second node under the control of a write control signal. The first end of the first energy storage circuit is electrically connected to the second node, and the second end of the first energy storage circuit is electrically connected to the first node. The switch control circuit controls whether the first node is electrically connected to the first voltage end through the second energy storage circuit under the control of a switch control signal. The second energy storage circuit is used to store electrical energy. The present invention divides the data voltage using a controllable voltage divider ratio capacitor circuit, ensuring drive control with a larger brightness dynamic range in high brightness mode while achieving drive control with a smaller grayscale difference in low brightness display mode.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a pixel circuit, a pixel driving method and a display device. Background Art

[0002] In related technologies, the data voltages provided by display signal driver integrated circuits (DrICs) must ensure a sufficiently large dynamic range of display brightness required for both indoor and outdoor environments, within a specific pixel circuit design. Due to current technical limitations such as DrICs' output accuracy, the minimum output fluctuation range of DrICs typically cannot meet the sufficiently small grayscale brightness differences required for low-brightness displays in darkroom environments. Summary of the Invention

[0003] The main purpose of the present invention is to provide a pixel circuit, a pixel driving method and a display device to solve the problem that the minimum output variation amplitude of the display signal driving integrated circuit is usually unable to meet the requirement of sufficiently small grayscale brightness difference required for low brightness level display in a dark room environment due to technical limitations.

[0004] In one aspect, an embodiment of the present invention provides a pixel circuit, including a light-emitting element, a driving circuit, a first energy storage circuit, a second energy storage circuit, a switch control circuit, and a data writing circuit;

[0005] The control terminal of the driving circuit is electrically connected to the first node, the first terminal of the driving circuit is electrically connected to the power supply voltage terminal, and the second terminal of the driving circuit is electrically connected to the light-emitting element. The driving circuit is used to drive the light-emitting element under the control of the potential of the control terminal;

[0006] The data writing circuit is electrically connected to the write control terminal, the data line and the second node respectively, and is used to write the data voltage provided by the data line into the second node under the control of the write control signal provided by the write control terminal;

[0007] A first end of the first energy storage circuit is electrically connected to the second node, a second end of the first energy storage circuit is electrically connected to the first node, and the first energy storage circuit is used to store electrical energy;

[0008] The switch control circuit is electrically connected to the switch control terminal, the second energy tank circuit and the first voltage terminal respectively, and is used to control whether the first node is electrically connected to the first voltage terminal through the second energy tank circuit under the control of the switch control signal provided by the switch control terminal;

[0009] The second energy storage circuit is used to store electrical energy.

[0010] Optionally, the control end of the switch control circuit is electrically connected to the switch control end, the first end of the switch control circuit is electrically connected to the first node, and the second end of the switch control circuit is electrically connected to the first end of the second energy tank circuit, and the switch control circuit is used to control the connection or disconnection between the first node and the first end of the second energy tank circuit under the control of the switch control signal;

[0011] The second end of the second energy storage circuit is electrically connected to the first voltage end.

[0012] Optionally, the first end of the second energy storage circuit is electrically connected to the first node;

[0013] The control end of the switch control circuit is electrically connected to the switch control end, the first end of the switch control circuit is electrically connected to the second end of the second energy storage circuit, and the second end of the switch control circuit is electrically connected to the first voltage end. The switch control circuit is used to control the connection or disconnection between the second end of the second energy storage circuit and the first voltage end under the control of the switch control signal.

[0014] Optionally, the switch control circuit further includes a third terminal;

[0015] The third terminal of the switch control circuit is electrically connected to the second node. The switch control circuit is further configured to control the connection or disconnection between the second node and the second terminal of the second energy storage circuit under the control of the switch control signal.

[0016] Optionally, the pixel circuit according to at least one embodiment of the present invention further includes a third energy storage circuit;

[0017] A first end of the third energy storage circuit is electrically connected to the first node, a second end of the third energy storage circuit is electrically connected to the first voltage end, and the third energy storage circuit is used to store electrical energy.

[0018] Optionally, the pixel circuit according to at least one embodiment of the present invention further includes a third energy storage circuit;

[0019] A first end of the third energy storage circuit is electrically connected to the first node, a second end of the third energy storage circuit is electrically connected to the first voltage end, and the third energy storage circuit is used to store electrical energy.

[0020] Optionally, the switch control circuit includes a switch element; the first energy storage circuit includes a first capacitor, and the second energy storage circuit includes a second capacitor;

[0021] The control end of the switch element is electrically connected to the switch control end, the first end of the switch element is electrically connected to the first node, and the second end of the switch element is electrically connected to the first end of the second capacitor; the switch element is used to control the connection or disconnection between the first end of the switch element and the second end of the switch element under the control of the switch control signal;

[0022] A first end of the first capacitor is electrically connected to the second node, and a second end of the first capacitor is electrically connected to the first node;

[0023] The second terminal of the second capacitor is electrically connected to the first voltage terminal.

[0024] Optionally, the switch control circuit includes a switch element; the first energy storage circuit includes a first capacitor, and the second energy storage circuit includes a second capacitor;

[0025] The control end of the switch element is electrically connected to the switch control end, the first end of the switch element is electrically connected to the second end of the second capacitor, and the second end of the switch element is electrically connected to the first voltage end; the switch element is used to control the connection or disconnection between the first end of the switch element and the second end of the switch element under the control of the switch control signal;

[0026] A first end of the first capacitor is electrically connected to the second node, and a second end of the first capacitor is electrically connected to the first node;

[0027] A first terminal of the second capacitor is electrically connected to the first node.

[0028] Optionally, the switch control circuit includes a double-throw switch element; the first energy tank circuit includes a first capacitor, and the second energy tank circuit includes a second capacitor; a first end of the first capacitor is electrically connected to the second node, and a second end of the first capacitor is electrically connected to the first node;

[0029] The first end of the second capacitor is electrically connected to the first node;

[0030] The control end of the double-throw switch element is electrically connected to the switch control end, the first end of the double-throw switch element is electrically connected to the second end of the second capacitor, the second end of the double-throw switch element is electrically connected to the first voltage end, and the third end of the double-throw switch element is electrically connected to the second node;

[0031] The double-throw switch element is used to control the communication between the first end of the double-throw switch element and the second end of the double-throw switch element or the third end of the double-throw switch element under the control of the switch control signal.

[0032] Optionally, the third energy storage circuit includes a third capacitor;

[0033] A first end of the third capacitor is electrically connected to the first node, and a second end of the third capacitor is electrically connected to the first voltage end.

[0034] Optionally, the pixel circuit according to at least one embodiment of the present invention further includes a first initialization circuit, a second initialization circuit, a voltage control circuit, a compensation control circuit, and a light emitting control circuit;

[0035] The first initialization circuit is electrically connected to the initial control terminal, the reference voltage terminal and the second node respectively, and is used to control the reference voltage terminal to provide a reference voltage to the second node under the control of an initial control signal provided by the initial control terminal;

[0036] The second initialization circuit is electrically connected to the initial control terminal, the initial voltage terminal and the first node respectively, and is configured to control the initial voltage terminal to provide an initial voltage to the first node under the control of the initial control signal;

[0037] The voltage control circuit is electrically connected to the light-emitting control terminal, the reference voltage terminal and the second node respectively, and is used to control the reference voltage terminal to provide a reference voltage to the second node under the control of the light-emitting control signal provided by the light-emitting control terminal;

[0038] The compensation control circuit is electrically connected to the compensation control terminal, the first node and the second terminal of the driving circuit respectively, and is used to control the connection or disconnection of the first node and the second terminal of the driving circuit under the control of the compensation control signal provided by the compensation control terminal;

[0039] The light emitting control circuit is electrically connected to the light emitting control terminal, the second terminal of the driving circuit and the first electrode of the light emitting element respectively, and is used to control the connection or disconnection between the second terminal of the driving circuit and the first electrode of the light emitting element under the control of the light emitting control signal;

[0040] The second electrode of the light emitting element is electrically connected to the second voltage end.

[0041] Optionally, the compensation control terminal and the write control terminal are the same control terminal; the drive circuit includes a drive transistor, the data write circuit includes a first transistor, the compensation control circuit includes a second transistor, the first initialization circuit includes a third transistor, the second initialization circuit includes a fourth transistor, the voltage control circuit includes a fifth transistor, and the light emitting control circuit includes a sixth transistor; the light emitting element is an organic light emitting diode;

[0042] The gate of the driving transistor is electrically connected to the first node, and the first electrode of the driving transistor is electrically connected to the power supply voltage terminal;

[0043] The gate of the first transistor is electrically connected to the write control terminal, the first electrode of the first transistor is electrically connected to the data line, and the second electrode of the first transistor is electrically connected to the second node;

[0044] The gate of the second transistor is electrically connected to the write control terminal, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the second electrode of the drive transistor;

[0045] The gate of the third transistor is electrically connected to the initial control terminal, the first electrode of the third transistor is electrically connected to the second node, and the second electrode of the third transistor is electrically connected to the reference voltage terminal;

[0046] The gate of the fourth transistor is electrically connected to the initial control terminal, the first electrode of the fourth transistor is electrically connected to the first node, and the second electrode of the fourth transistor is electrically connected to the initial voltage terminal;

[0047] The gate of the fifth transistor is electrically connected to the light emitting control terminal, the first electrode of the fifth transistor is electrically connected to the second node, and the second electrode of the fifth transistor is electrically connected to the reference voltage terminal;

[0048] The gate of the sixth transistor is electrically connected to the light emitting control terminal, the first electrode of the sixth transistor is electrically connected to the second electrode of the driving transistor, and the second electrode of the sixth transistor is electrically connected to the anode of the organic light emitting diode;

[0049] The cathode of the organic light emitting diode is electrically connected to the second voltage terminal.

[0050] Optionally, the pixel circuit according to at least one embodiment of the present invention further includes a first initialization circuit, a second initialization circuit, a compensation control circuit, and a light emitting control circuit;

[0051] The first initialization circuit is electrically connected to the first initial control terminal, the reference voltage terminal and the second node respectively, and is used to control the reference voltage terminal to provide a reference voltage to the second node under the control of a first initial control signal provided by the first initial control terminal;

[0052] The second initialization circuit is electrically connected to the second initial control terminal, the initial voltage terminal and the first node respectively, and is configured to control the initial voltage terminal to provide an initial voltage to the first node under the control of a second initial control signal provided by the second initial control terminal;

[0053] The compensation control circuit is electrically connected to the compensation control terminal, the first node and the second terminal of the driving circuit respectively, and is used to control the connection or disconnection of the first node and the second terminal of the driving circuit under the control of the compensation control signal provided by the compensation control terminal;

[0054] The light emitting control circuit is electrically connected to the light emitting control terminal, the second terminal of the driving circuit and the first electrode of the light emitting element respectively, and is used to control the connection or disconnection between the second terminal of the driving circuit and the first electrode of the light emitting element under the control of the light emitting control signal;

[0055] The second electrode of the light emitting element is electrically connected to the second voltage end.

[0056] Optionally, the compensation control terminal and the first initial control terminal are the same control terminal; the driving circuit includes a driving transistor, the data writing circuit includes a first transistor, the compensation control circuit includes a second transistor, the first initialization circuit includes a third transistor, the second initialization circuit includes a fourth transistor, and the light emitting control circuit includes a sixth transistor; and the light emitting element is an organic light emitting diode;

[0057] The gate of the driving transistor is electrically connected to the first node, and the first electrode of the driving transistor is electrically connected to the power supply voltage terminal;

[0058] The gate of the first transistor is electrically connected to the write control terminal, the first electrode of the first transistor is electrically connected to the data line, and the second electrode of the first transistor is electrically connected to the second node;

[0059] The gate of the second transistor is electrically connected to the first initial control terminal, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the second electrode of the driving transistor;

[0060] The gate of the third transistor is electrically connected to the first initial control terminal, the first electrode of the third transistor is electrically connected to the second node, and the second electrode of the third transistor is electrically connected to the reference voltage terminal;

[0061] The gate of the fourth transistor is electrically connected to the second initial control terminal, the first electrode of the fourth transistor is electrically connected to the first node, and the second electrode of the fourth transistor is electrically connected to the initial voltage terminal;

[0062] The gate of the sixth transistor is electrically connected to the light emitting control terminal, the first electrode of the sixth transistor is electrically connected to the second electrode of the driving transistor, and the second electrode of the sixth transistor is electrically connected to the anode of the organic light emitting diode;

[0063] The cathode of the organic light emitting diode is electrically connected to the second voltage terminal.

[0064] In a second aspect, an embodiment of the present invention provides a pixel driving method, which is applied to the above-mentioned pixel circuit. The pixel driving method includes:

[0065] The driving circuit is used to drive the light emitting element under the control of the potential of the control terminal;

[0066] The data writing circuit writes the data voltage provided by the data line into the second node under the control of the write control signal;

[0067] The first energy storage circuit stores electrical energy; the second energy storage circuit stores electrical energy

[0068] Under the control of the switch control signal, the switch control circuit controls whether the first node is electrically connected to the first voltage terminal through the second energy storage circuit.

[0069] Optionally, the step of the switch control circuit controlling, under the control of the switch control signal, whether the first node is electrically connected to the first voltage terminal through the second energy storage circuit includes:

[0070] In the first display mode, the switch control circuit controls the first node to not be electrically connected to the first voltage terminal through the second energy storage circuit under the control of the switch control signal;

[0071] In the second display mode, the switch control circuit controls the first node to be electrically connected to the first voltage terminal through the second energy storage circuit under the control of the switch control signal.

[0072] In a third aspect, an embodiment of the present invention provides a display device comprising the above-mentioned pixel circuit.

[0073] The pixel circuit, pixel driving circuit and display device described in the embodiments of the present invention perform voltage division conversion on the data voltage through a controllable voltage division ratio capacitor circuit (the controllable voltage division ratio capacitor circuit may include a switch control circuit, a first energy storage circuit and a second energy storage circuit), thereby ensuring driving control of a larger brightness dynamic range in a high-brightness mode while achieving driving control of a smaller grayscale difference in a low-brightness display mode. BRIEF DESCRIPTION OF THE DRAWINGS

[0074] Figure 1 is a structural diagram of a pixel circuit according to at least one embodiment of the present invention;

[0075] Figure 2 is a structural diagram of a pixel circuit according to at least one embodiment of the present invention;

[0076] Figure 3 is a circuit diagram of a pixel circuit according to at least one embodiment of the present invention;

[0077] Figure 4 yes Figure 3 A circuit diagram of at least one embodiment of a pixel circuit shown;

[0078] Figure 5is a circuit diagram of a pixel circuit according to at least one embodiment of the present invention;

[0079] Figure 6 is a circuit diagram of a pixel circuit according to at least one embodiment of the present invention;

[0080] Figure 7 is a structural diagram of a pixel circuit according to at least one embodiment of the present invention;

[0081] Figure 8 is a circuit diagram of a pixel circuit according to at least one embodiment of the present invention;

[0082] Figure 9 is a circuit diagram of at least one embodiment of a double-throw switching element;

[0083] Figure 10 is a circuit diagram of a pixel circuit according to at least one embodiment of the present invention;

[0084] Figure 11 is a circuit diagram of at least one embodiment of a double-throw switching element;

[0085] Figure 12 is a structural diagram of a pixel circuit according to at least one embodiment of the present invention;

[0086] Figure 13 is a structural diagram of a pixel circuit according to at least one embodiment of the present invention;

[0087] Figure 14 is a circuit diagram of a pixel circuit according to at least one embodiment of the present invention;

[0088] Figure 15 is a circuit diagram of a pixel circuit according to at least one embodiment of the present invention;

[0089] Figure 16 is a circuit diagram of a pixel circuit according to at least one embodiment of the present invention;

[0090] Figure 17 is a circuit diagram of a pixel circuit according to at least one embodiment of the present invention;

[0091] Figure 18 is a circuit diagram of a pixel circuit according to at least one embodiment of the present invention;

[0092] Figure 19 This invention Figure 18 An operation timing diagram of at least one embodiment of the pixel circuit shown;

[0093] Figure 20 is a circuit diagram of a pixel circuit according to at least one embodiment of the present invention;

[0094] Figure 21is a structural diagram of a pixel circuit according to at least one embodiment of the present invention;

[0095] Figure 22 is a circuit diagram of a pixel circuit according to at least one embodiment of the present invention DETAILED DESCRIPTION

[0096] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0097] The transistors used in all embodiments of the present invention may be thin film transistors, field effect transistors, or other devices with the same characteristics. In the embodiments of the present invention, to distinguish the two electrodes of the transistor except the gate, one electrode is referred to as the first electrode and the other electrode is referred to as the second electrode.

[0098] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the first electrode may be a source electrode, and the second electrode may be a drain electrode.

[0099] The pixel circuit described in the embodiment of the present invention includes a light-emitting element, a driving circuit, a first energy storage circuit, a second energy storage circuit, a switch control circuit and a data writing circuit;

[0100] The control terminal of the driving circuit is electrically connected to the first node, the first terminal of the driving circuit is electrically connected to the power supply voltage terminal, and the second terminal of the driving circuit is electrically connected to the light-emitting element. The driving circuit is used to drive the light-emitting element under the control of the potential of the control terminal;

[0101] The data writing circuit is electrically connected to the write control terminal, the data line and the second node respectively, and is used to write the data voltage provided by the data line into the second node under the control of the write control signal provided by the write control terminal;

[0102] A first end of the first energy storage circuit is electrically connected to the second node, a second end of the first energy storage circuit is electrically connected to the first node, and the first energy storage circuit is used to store electrical energy;

[0103] The switch control circuit is electrically connected to the switch control terminal, the second energy tank circuit and the first voltage terminal respectively, and is used to control whether the first node is electrically connected to the first voltage terminal through the second energy tank circuit under the control of the switch control signal provided by the switch control terminal;

[0104] The second energy storage circuit is used to store electrical energy.

[0105] The pixel circuit described in the embodiment of the present invention performs voltage division conversion on the data voltage through a controllable voltage division ratio capacitor circuit (the controllable voltage division ratio capacitor circuit may include a switch control circuit, a first energy storage circuit, and a second energy storage circuit), thereby ensuring drive control of a larger brightness dynamic range in high brightness mode while achieving drive control of a smaller grayscale difference in low brightness display mode.

[0106] The embodiment of the present invention proposes a signal coupling, voltage division, and holding capacitor circuit with a controllable voltage division ratio. After the circuit is embedded in the pixel circuit, it can achieve the minimum variation amplitude and maximum dynamic amplitude of the data voltage through mode control, respectively adapting to low and high brightness mode display.

[0107] The embodiment of the present invention can realize the display of different minimum grayscale differences and brightness dynamic amplitudes through a controllable voltage divider ratio capacitor circuit, that is, a pixel circuit, to adapt to high brightness mode display and low brightness mode display respectively.

[0108] In at least one embodiment of the present invention, the control terminal of the switch control circuit is electrically connected to the switch control terminal, the first terminal of the switch control circuit is electrically connected to the first node, and the second terminal of the switch control circuit is electrically connected to the first terminal of the second energy tank circuit. The switch control circuit is configured to control connection or disconnection between the first node and the first terminal of the second energy tank circuit under the control of the switch control signal;

[0109] The second end of the second energy storage circuit is electrically connected to the first voltage end.

[0110] Optionally, the switch control circuit includes a switch element; the first energy storage circuit includes a first capacitor, and the second energy storage circuit includes a second capacitor;

[0111] The control end of the switch element is electrically connected to the switch control end, the first end of the switch element is electrically connected to the first node, and the second end of the switch element is electrically connected to the first end of the second capacitor; the switch element is used to control the connection or disconnection between the first end of the switch element and the second end of the switch element under the control of the switch control signal;

[0112] A first end of the first capacitor is electrically connected to the second node, and a second end of the first capacitor is electrically connected to the first node;

[0113] The second terminal of the second capacitor is electrically connected to the first voltage terminal.

[0114] like Figure 1As shown, the pixel circuit according to at least one embodiment of the present invention includes a light emitting element EL, a driving circuit 10, a first energy storage circuit 11, a second energy storage circuit 12, a switch control circuit 13 and a data writing circuit 14;

[0115] The control terminal of the driving circuit 10 is electrically connected to the first node N1, the first terminal of the driving circuit 10 is electrically connected to the power supply voltage terminal Vdd, and the second terminal of the driving circuit 10 is electrically connected to the light emitting element EL. The driving circuit 10 is used to drive the light emitting element EL under the control of the potential of the control terminal.

[0116] The data writing circuit 14 is electrically connected to the writing control terminal S1, the data line DT and the second node N2, and is used to write the data voltage Vdt provided by the data line DT into the second node N2 under the control of the writing control signal provided by the writing control terminal S1;

[0117] A first end of the first energy storage circuit 11 is electrically connected to the second node N2, a second end of the first energy storage circuit 11 is electrically connected to the first node N1, and the first energy storage circuit 11 is used to store electrical energy;

[0118] The control end of the switch control circuit 13 is electrically connected to the switch control end M, the first end of the switch control circuit 13 is electrically connected to the first node N1, and the second end of the switch control circuit 13 is electrically connected to the first end of the second energy tank circuit 12. The switch control circuit 13 is used to control the connection or disconnection between the first node N1 and the first end of the second energy tank circuit 12 under the control of the switch control signal;

[0119] The second end of the second energy storage circuit 12 is electrically connected to the first voltage end V1 .

[0120] In a specific implementation, the first voltage terminal may be the same voltage terminal as the power supply voltage terminal, or the first voltage terminal may be a different voltage terminal from the power supply voltage terminal.

[0121] The present invention Figure 1 At least one embodiment of the pixel circuit shown is in operation.

[0122] In the high brightness mode, the switch control circuit 13 controls the first node N1 to be disconnected from the first end of the second energy storage circuit 12 under the control of the switch control signal provided by the switch control terminal M, so that the second energy storage circuit 12 is single-ended and floats without participating in the pixel circuit-related working process;

[0123] In low brightness mode, the switch control circuit 13 controls the connection between the first node N1 and the first end of the second energy storage circuit 12, one end of the second energy storage circuit 12 and the first node N1, and the other end of the second energy storage circuit 12 is electrically connected to the first voltage end V1 under the control of the switch control signal provided by the switch control end M.

[0124] In at least one embodiment of the present invention, the first end of the second energy storage circuit is electrically connected to the first node;

[0125] The control end of the switch control circuit is electrically connected to the switch control end, the first end of the switch control circuit is electrically connected to the second end of the second energy storage circuit, and the second end of the switch control circuit is electrically connected to the first voltage end. The switch control circuit is used to control the connection or disconnection between the second end of the second energy storage circuit and the first voltage end under the control of the switch control signal.

[0126] Optionally, the switch control circuit includes a switch element; the first energy storage circuit includes a first capacitor, and the second energy storage circuit includes a second capacitor;

[0127] The control end of the switch element is electrically connected to the switch control end, the first end of the switch element is electrically connected to the second end of the second capacitor, and the second end of the switch element is electrically connected to the first voltage end; the switch element is used to control the connection or disconnection between the first end of the switch element and the second end of the switch element under the control of the switch control signal;

[0128] A first end of the first capacitor is electrically connected to the second node, and a second end of the first capacitor is electrically connected to the first node;

[0129] A first terminal of the second capacitor is electrically connected to the first node.

[0130] like Figure 2 As shown, the pixel circuit according to at least one embodiment of the present invention includes a light emitting element EL, a driving circuit 10, a first energy storage circuit 11, a second energy storage circuit 12, a switch control circuit 13 and a data writing circuit 14;

[0131] The control terminal of the driving circuit 10 is electrically connected to the first node N1, the first terminal of the driving circuit 10 is electrically connected to the power supply voltage terminal Vdd, and the second terminal of the driving circuit 10 is electrically connected to the light emitting element EL. The driving circuit 10 is used to drive the light emitting element EL under the control of the potential of the control terminal.

[0132] The data writing circuit 14 is electrically connected to the writing control terminal S1, the data line DT and the second node N2, and is used to write the data voltage Vdt provided by the data line DT into the second node N2 under the control of the writing control signal provided by the writing control terminal S1;

[0133] A first end of the first energy storage circuit 11 is electrically connected to the second node N2, a second end of the first energy storage circuit 11 is electrically connected to the first node N1, and the first energy storage circuit 11 is used to store electrical energy;

[0134] The first end of the second energy storage circuit 12 is electrically connected to the first node N1;

[0135] The control end of the switch control circuit 13 is electrically connected to the switch control end M, the first end of the switch control circuit 13 is electrically connected to the second end of the second energy storage circuit 12, and the second end of the switch control circuit 13 is electrically connected to the first voltage end V1. The switch control circuit 13 is used to control the connection or disconnection between the second end of the second energy storage circuit 12 and the first voltage end V1 under the control of the switch control signal M.

[0136] The present invention Figure 2 At least one embodiment of the pixel circuit shown is in operation.

[0137] In the high brightness mode, the switch control circuit 13 controls the second end of the second energy storage circuit 12 to be disconnected from the first voltage end V1 under the control of the switch control signal provided by the switch control end M, and the second energy storage circuit 12 is single-ended and floats without participating in the pixel circuit-related working process;

[0138] In the low brightness mode, the switch control circuit 13 controls the second end of the second energy storage circuit 12 to be connected to the first voltage end V1 under the control of the switch control signal provided by the switch control end M, one end of the second energy storage circuit 12 is electrically connected to the first node N1, and the other end of the second energy storage circuit 12 is connected to the first voltage end V1.

[0139] like Figure 3 As shown, in Figure 1 Based on at least one embodiment of the pixel circuit shown, the switch control circuit includes a switch element; the switch element is a switch transistor T9;

[0140] The first energy storage circuit includes a first capacitor C1, and the second energy storage circuit includes a second capacitor C2;

[0141] The gate of the switch transistor T9 is electrically connected to the switch control terminal M, the source of the switch transistor T9 is electrically connected to the first node N1, and the drain of the switch transistor T9 is electrically connected to the first end of the second capacitor C2;

[0142] A first end of the first capacitor C1 is electrically connected to the second node N2, and a second end of the first capacitor C1 is electrically connected to the first node N1;

[0143] The second end of the second capacitor C2 is electrically connected to the power supply voltage terminal Vdd;

[0144] The driving circuit includes a driving transistor T0, the data writing circuit includes a first transistor T1, and at least one embodiment of the pixel circuit may further include a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a sixth transistor T6; the light-emitting element is an organic light-emitting diode O1;

[0145] The gate of the driving transistor T0 is electrically connected to the first node N1, and the source of the driving transistor T0 is electrically connected to the power supply voltage terminal Vdd;

[0146] The gate of the first transistor T1 is electrically connected to the write control terminal S1, the source of the first transistor T1 is electrically connected to the data line DT, and the drain of the first transistor T1 is electrically connected to the second node N2;

[0147] The gate of the second transistor T2 is electrically connected to the write control terminal S1, the source of the second transistor T2 is electrically connected to the first node N1, and the drain of the second transistor T2 is electrically connected to the drain of the driving transistor T0;

[0148] The gate of the third transistor T3 is electrically connected to the initial control terminal S3, the source of the third transistor T3 is electrically connected to the second node N2, and the drain of the third transistor T3 is electrically connected to the reference voltage terminal VR; the reference voltage terminal VR is used to provide a reference voltage Vref;

[0149] The gate of the fourth transistor T4 is electrically connected to the initial control terminal S3, the source of the fourth transistor T4 is electrically connected to the first node N1, and the drain of the fourth transistor T4 is electrically connected to the initial voltage terminal I1; the initial voltage terminal I1 is used to provide an initial voltage Vint;

[0150] The gate of the fifth transistor T5 is electrically connected to the light emitting control terminal EM, the source of the fifth transistor T5 is electrically connected to the second node N2, and the drain of the fifth transistor T5 is electrically connected to the reference voltage terminal VR;

[0151] The gate of the sixth transistor T6 is electrically connected to the light emitting control terminal EM, the source of the sixth transistor T6 is electrically connected to the drain of the driving transistor T0, and the drain of the sixth transistor T6 is electrically connected to the anode of the organic light emitting diode O1;

[0152] The cathode of the organic light emitting diode O1 is electrically connected to the low voltage terminal Vss.

[0153] exist Figure 3 In at least one embodiment of the pixel circuit shown, the second voltage terminal is a low voltage terminal Vss, but the present invention is not limited thereto.

[0154] exist Figure 3 In at least one embodiment of the pixel circuit shown, all transistors are p-type transistors, but the present invention is not limited thereto.

[0155] like Figure 4 As shown, Figure 3 When at least one embodiment of the pixel circuit shown is in operation, a display cycle may include a reset phase t1, a threshold voltage detection phase t2, and a signal superposition phase t3, which are arranged in sequence;

[0156] In the reset phase t1, EM provides a high voltage signal, S1 provides a high voltage signal, S3 provides a low voltage signal, T3 and T4 are both turned on to write the initial voltage Vint provided by I1 into the first node N1 and the reference voltage Vref provided by the reference voltage VR to the second node N2;

[0157] In the threshold voltage detection phase t2, EM provides a high voltage signal, S1 provides a low voltage signal, S3 provides a high voltage signal, T1 and T2 are turned on, DT provides a data voltage Vdt, and Vdt is written into the second node N2; the first node N1 is connected to the drain of T0; the potential of N1 is Vd+Vth, where Vd is the voltage value of the power supply voltage provided by the power supply voltage terminal Vdd, and Vth is the threshold voltage of T0;

[0158] In the signal superposition phase t3, EM provides a low voltage signal, S1 and S3 both provide high voltage signals, and T5 is turned on to write the reference voltage Vref provided by the reference voltage terminal VR into the second node N2;

[0159] In the signal superposition stage t3,

[0160] When M provides a high voltage signal, T9 is turned off, the first end of C2 is disconnected from the first node N1, the first end of C2 is floating, C2 does not participate in the operation of the pixel circuit, the voltage change δVN2 of N2 is equal to the voltage change δVN1 of N1, δVN2 is equal to Vref-Vdt, δVN1 is equal to Vref-Vdt, and the potential of N1 is Vd+Vth+Vref-Vdt; at this time, δVN2 is equal to δVN1, so that a larger brightness dynamic range drive control can be achieved in high brightness mode;

[0161] When M provides a low voltage signal, T9 is turned on, the first end of C2 is connected to the first node N1, δVN2 is equal to Vref-Vdt, δVN1 is equal to K1×δVN2, K1 is equal to C1z / (C1z+C2z), and the potential of N1 is Vd+Vth+K1×(Vref-Vdt), where K1 is a first voltage coefficient, C1z is the capacitance value of C1, and C2z is the capacitance value of C2; K1 is greater than 0 and less than 1, so that smaller grayscale difference driving control can be achieved in low brightness display mode;

[0162] In the signal superposition stage t3, EM provides a low voltage signal, T6 is turned on, and T0 drives O1 to emit light.

[0163] exist Figure 3 In at least one embodiment of the pixel circuit shown, the first voltage terminal and the power voltage terminal Vdd are the same voltage terminal, but the present invention is not limited thereto.

[0164] like Figure 5 As shown, in Figure 1 Based on at least one embodiment of the pixel circuit shown,

[0165] The driving circuit includes a driving transistor T0, the data writing circuit includes a first transistor T1; the switch control circuit includes a switch element K0; the first energy storage circuit includes a first capacitor C1, and the second energy storage circuit includes a second capacitor C2;

[0166] The gate of the driving transistor T0 is electrically connected to the first node N1, the source of the driving transistor T0 is electrically connected to the power supply voltage terminal Vdd, and the drain of the driving transistor T0 is electrically connected to the light emitting element EL;

[0167] The control terminal of the switch element K0 is electrically connected to the switch control terminal M, the first terminal of the switch element K0 is electrically connected to the first node N1, and the second terminal of the switch element K0 is electrically connected to the first terminal of the second capacitor C2; the switch element K0 is used to control the connection or disconnection between the first terminal of the switch element K0 and the second terminal of the switch element K0 under the control of the switch control signal;

[0168] A first end of the first capacitor C1 is electrically connected to the second node N2, and a second end of the first capacitor C1 is electrically connected to the first node N1;

[0169] The second end of the second capacitor C2 is electrically connected to the reference potential terminal FX; the reference potential terminal FX is used to provide a reference potential Vfx;

[0170] A gate of the first transistor T1 is electrically connected to the write control terminal S1 , a source of the first transistor T1 is electrically connected to the data line DT, and a drain of the first transistor T1 is electrically connected to the second node N2 .

[0171] exist Figure 5 In at least one embodiment of the pixel circuit shown, T1 may be a p-type transistor.

[0172] The present invention Figure 5 At least one embodiment of the pixel circuit shown is in operation.

[0173] In high brightness mode, by controlling the switch control signal provided by the switch control terminal M, K0 is turned off, and C2 is single-ended and floating due to the disconnection of the loop and does not participate in the operation process of the pixel circuit. In the signal superposition stage, the voltage change δVN2 of the second node N2 is coupled to the first node N1 through C1, δVN1 is equal to δVN2, and the coupling voltage division ratio is N1. Then, the first node N1 is maintained by the first capacitor C1 based on the potential of N2, and the capacitance is maintained at C1z. After the potential of the second node N2 jumps, the potential of the second node N2 needs to be maintained;

[0174] In low brightness mode, by controlling the switch control signal provided by the switch control terminal M, K0 is turned on, the first end of the second capacitor C2 is connected to the first node N1, the second end of the second capacitor C2 is electrically connected to the reference potential terminal FX, and the second capacitor C2 participates in the potential jump voltage division of the first node N1; in the signal superposition stage, δVN1 is equal to K1×δVN2, K1 is the first voltage coefficient, K1 is equal to C1z / (C1z+C2z), the potential of the first node N1 is maintained by the first capacitor C1 based on the potential of the second node N2, and by the second capacitor C2 based on the reference potential Vfx, maintaining the total capacitance of C1z+C2z. In low brightness mode, after the potential of the second node N2 jumps, the second node N2 can also float. In this case, the potential of N1 is only maintained by the second capacitor C2 based on the reference potential Vfx, and the capacitance is maintained at C2z.

[0175] In at least one embodiment of the present invention, the first voltage terminal may be a reference potential terminal, but is not limited thereto.

[0176] like Figure 6 As shown, in Figure 2Based on at least one embodiment of the pixel circuit shown,

[0177] The driving circuit 10 includes a driving transistor T0, the data writing circuit 14 includes a first transistor T1; the switch control circuit 13 includes a switch element K0; the first energy storage circuit 11 includes a first capacitor C1, and the second energy storage circuit 12 includes a second capacitor C2;

[0178] The gate of the driving transistor T0 is electrically connected to the first node N1, the source of the driving transistor T0 is electrically connected to the power supply voltage terminal Vdd, and the drain of the driving transistor T0 is electrically connected to the light emitting element EL;

[0179] The control end of the switch element K0 is electrically connected to the switch control end M, the first end of the switch element K0 is electrically connected to the second end of the second capacitor C2, and the second end of the switch element K0 is electrically connected to the reference potential end FX; the switch element K0 is used to control the connection or disconnection between the first end of the switch element K0 and the second end of the switch element K0 under the control of the switch control signal;

[0180] A first end of the first capacitor C1 is electrically connected to the second node N2, and a second end of the first capacitor C1 is electrically connected to the first node N1;

[0181] A first end of the second capacitor C2 is electrically connected to the first node N1;

[0182] A gate of the first transistor T1 is electrically connected to the write control terminal S1 , a source of the first transistor T1 is electrically connected to the data line DT, and a drain of the first transistor T1 is electrically connected to the second node N2 .

[0183] exist Figure 6 In at least one embodiment of the pixel circuit shown, T1 may be a p-type transistor.

[0184] The present invention Figure 6 At least one embodiment of the pixel circuit shown is in operation.

[0185] In high brightness mode, by controlling the switch control signal provided by the switch control terminal M, K0 is turned off, and C2 is single-ended and floating due to the disconnection of the loop and does not participate in the operation process of the pixel circuit. In the signal superposition stage, the voltage change δVN2 of the second node N2 is coupled to the first node N1 through C1, δVN1 is equal to δVN2, and the coupling voltage division ratio is N1. Then, the first node N1 is maintained by the first capacitor C1 based on the potential of N2, and the capacitance is maintained at C1z. After the potential of the second node N2 jumps, the potential of the second node N2 needs to be maintained;

[0186] In low brightness mode, by controlling the switch control signal provided by the switch control terminal M, K0 is turned on, the first end of the second capacitor C2 is connected to the first node N1, and the second end of the second capacitor C2 is connected to the reference potential terminal FX, and the second capacitor C2 participates in the potential jump voltage division of the first node N1; in the signal superposition stage, δVN1 is equal to K1×δVN2, K1 is the first voltage coefficient, K1 is equal to C1z / (C1z+C2z), the potential of the first node N1 is jointly maintained by the first capacitor C1 based on the potential of the second node N2, and by the second capacitor C2 based on the reference potential Vfx, maintaining the total capacitance of C1z+C2z. In low brightness mode, after the potential of the second node N2 jumps, the second node N2 can also float. In this case, the potential of N1 is only maintained by the second capacitor C2 based on the reference potential Vfx, and the capacitance is maintained at C2z.

[0187] Optionally, the switch control circuit further includes a third terminal;

[0188] The third terminal of the switch control circuit is electrically connected to the second node. The switch control circuit is further configured to control the connection or disconnection between the second node and the second terminal of the second energy storage circuit under the control of the switch control signal.

[0189] like Figure 7 As shown, in Figure 2 Based on at least one embodiment of the pixel circuit shown, the switch control circuit 13 further includes a third terminal;

[0190] The third terminal of the switch control circuit 13 is electrically connected to the second node N2;

[0191] The switch control circuit 13 is further configured to control the connection or disconnection between the second node N2 and the second end of the second energy storage circuit 12 under the control of the switch control signal.

[0192] In at least one embodiment of the present invention, the switch control circuit includes a double-throw switch element; the first energy storage circuit includes a first capacitor, and the second energy storage circuit includes a second capacitor; a first end of the first capacitor is electrically connected to the second node, and a second end of the first capacitor is electrically connected to the first node;

[0193] The first end of the second capacitor is electrically connected to the first node;

[0194] The control end of the double-throw switch element is electrically connected to the switch control end, the first end of the double-throw switch element is electrically connected to the second end of the second capacitor, the second end of the double-throw switch element is electrically connected to the first voltage end, and the third end of the double-throw switch element is electrically connected to the second node;

[0195] The double-throw switch element is used to control the communication between the first end of the double-throw switch element and the second end of the double-throw switch element or the third end of the double-throw switch element under the control of the switch control signal.

[0196] like Figure 8 As shown, in Figure 7 Based on at least one embodiment of the pixel circuit shown, the driving circuit 10 includes a driving transistor T0, the data writing circuit 14 includes a first transistor T1; the switch control circuit 13 includes a double-throw switch element Z1; the first energy storage circuit 11 includes a first capacitor C1, and the second energy storage circuit 12 includes a second capacitor C2;

[0197] The gate of the driving transistor T0 is electrically connected to the first node N1, the source of the driving transistor T0 is electrically connected to the power supply voltage terminal Vdd, and the drain of the driving transistor T0 is electrically connected to the light emitting element EL;

[0198] The control terminal of the double-throw switch element Z1 is electrically connected to the switch control terminal M, the first terminal of the double-throw switch element Z1 is electrically connected to the second terminal of the second capacitor C2, the second terminal of the double-throw switch element Z1 is electrically connected to the reference potential terminal FX, and the third terminal of the double-throw switch element Z1 is electrically connected to the second node N2; the reference potential terminal FX is used to provide a reference potential Vfx;

[0199] The double-throw switch element Z1 is used to control the communication between the first end of the double-throw switch element Z1 and the second end of the double-throw switch element Z1 or the third end of the double-throw switch element Z1 under the control of the switch control signal;

[0200] A first end of the first capacitor C1 is electrically connected to the second node N2, and a second end of the first capacitor C1 is electrically connected to the first node N1;

[0201] A first end of the second capacitor C2 is electrically connected to the first node N1;

[0202] A gate of the first transistor T1 is electrically connected to the write control terminal S1 , a source of the first transistor T1 is electrically connected to the data line DT, and a drain of the first transistor T1 is electrically connected to the second node N2 .

[0203] exist Figure 8 In at least one embodiment of the pixel circuit shown, T1 may be a p-type transistor.

[0204] The present invention Figure 8 At least one embodiment of the pixel circuit shown is in operation.

[0205] In high-brightness mode, by controlling the switch control signal provided by the switch control terminal M, Z1 controls the second end of C2 to be connected to N2, and C1 and C2 are connected in parallel to form a capacitor, which plays a role in signal coupling and maintenance. In the signal superposition stage, the voltage change δVN2 of the second node N2 is coupled to the first node N1 through C1, δVN1 is equal to δVN2, and the coupling voltage divider ratio is N1. Then, the first node N1 is maintained by the parallel capacitors C1 and C2 based on the reference potential Vfx, and the maintenance capacitance is C1z+C2z. After the potential of the second node N2 jumps, the potential of the second node N2 needs to be maintained.

[0206] In low brightness mode, by controlling the switch control signal provided by the switch control terminal M, Z1 controls the second end of C2 to be connected to FX, and the second capacitor C2 participates in the potential jump voltage division of the first node N1; in the signal superposition stage, δVN1 is equal to K1×δVN2, K1 is the first voltage coefficient, K1 is equal to C1z / (C1z+C2z), the potential of the first node N1 is maintained by the first capacitor C1 based on the potential of the second node N2, and by the second capacitor C2 based on the reference potential Vfx, maintaining the total capacitance of C1z+C2z. In low brightness mode, after the potential of the second node N2 jumps, the second node N2 can also float. In this case, the potential of N1 is only maintained by the second capacitor C2 based on the reference potential Vfx, and the capacitance is maintained at C2z.

[0207] The present invention Figure 8 When at least one embodiment of the pixel circuit shown is in operation, in high brightness mode and low brightness mode, the holding capacitors are C1z+C2z and C2z respectively; or, the holding capacitors are C1z+C2z and C1z+C2z respectively; under the condition of C2z>>C1z, the difference between the holding capacitors in high and low brightness modes is not much, which facilitates the signal stability design of the pixel circuit.

[0208] like Figure 9 As shown, at least one embodiment of the double-throw switch element may include a first switch transistor T91 and a second switch transistor T92;

[0209] The gate of T91 is electrically connected to the switch control terminal M, the source of T91 is electrically connected to the second end of the second capacitor C2, and the drain of T91 is electrically connected to the reference potential terminal FX;

[0210] The gate of T92 is electrically connected to the switch control terminal M, the source of T92 is electrically connected to the second end of the second capacitor C2, and the drain of T92 is electrically connected to the second node N2.

[0211] exist Figure 9 In at least one embodiment of the double-throw switch element shown, T91 is an n-type transistor and T92 is a p-type transistor.

[0212] Figure 9 At least one embodiment of the double-throw switch element shown in FIG.

[0213] When the switch control terminal M provides a high voltage signal, T91 is turned on, T92 is turned off, and the second end of the second capacitor C2 is connected to the reference potential terminal FX;

[0214] When the switch control terminal M provides a low voltage signal, T92 is turned on, T91 is turned off, and the second end of the second capacitor C2 is connected to the second node N2.

[0215] In at least one embodiment of the present invention, T91 may also be a p-type transistor, and T92 may also be an n-type transistor.

[0216] like Figure 10 As shown, in Figure 7 Based on at least one embodiment of the pixel circuit shown, the driving circuit 10 includes a driving transistor T0, the data writing circuit 14 includes a first transistor T1; the switch control circuit 13 includes a double-throw switch element Z1; the first energy storage circuit 11 includes a first capacitor C1, and the second energy storage circuit 12 includes a second capacitor C2;

[0217] The gate of the driving transistor T0 is electrically connected to the first node N1, the source of the driving transistor T0 is electrically connected to the power supply voltage terminal Vdd, and the drain of the driving transistor T0 is electrically connected to the light emitting element EL;

[0218] A first control terminal of the double-throw switch element Z1 is electrically connected to the first switch control terminal M1, a second terminal of the double-throw switch element Z1 is electrically connected to the second switch control terminal M2, a first terminal of the double-throw switch element Z1 is electrically connected to the second terminal of the second capacitor C2, a second terminal of the double-throw switch element Z1 is electrically connected to the reference potential terminal FX, and a third terminal of the double-throw switch element Z1 is electrically connected to the second node N2; the reference potential terminal FX is used to provide a reference potential Vfx;

[0219] The double-throw switch element Z1 is used to control the communication between the first end of the double-throw switch element Z1 and the second end of the double-throw switch element Z1 or the third end of the double-throw switch element Z1 under the control of the first switch control signal provided by the first switch control terminal M1 and the second switch control signal provided by the second switch control terminal M2;

[0220] A first end of the first capacitor C1 is electrically connected to the second node N2, and a second end of the first capacitor C1 is electrically connected to the first node N1;

[0221] A first end of the second capacitor C2 is electrically connected to the first node N1;

[0222] A gate of the first transistor T1 is electrically connected to the write control terminal S1 , a source of the first transistor T1 is electrically connected to the data line DT, and a drain of the first transistor T1 is electrically connected to the second node N2 .

[0223] exist Figure 10 In at least one embodiment of the pixel circuit shown, T1 may be a p-type transistor.

[0224] The present invention Figure 10 In at least one embodiment of the illustrated pixel circuit, when operating in a high-brightness mode, the first switch control signal provided by the first switch control terminal M1 and the second switch control signal provided by the second switch control terminal M2 are controlled so that Z1 controls the second terminal of C2 to be connected to N2. C1 and C2 are connected in parallel to form a capacitor, which performs signal coupling and retention functions. During the signal superposition stage, the voltage change δVN2 at the second node N2 is coupled to the first node N1 through C1, δVN1 is equal to δVN2, and the coupling voltage divider ratio is N1. Then, the first node N1 is maintained by the parallel capacitor C1 and C2 based on the reference potential Vfx, and the capacitance is maintained at C1z+C2z. After the potential of the second node N2 jumps, the potential of the second node N2 needs to be maintained.

[0225] In low brightness mode, by controlling the first switch control signal provided by the first switch control terminal M1 and the second switch control signal provided by the second switch control terminal M2, Z1 controls the second end of C2 to be connected to FX, and the second capacitor C2 participates in the potential jump voltage division of the first node N1; in the signal superposition stage, δVN1 is equal to K1×δVN2, K1 is the first voltage coefficient, K1 is equal to C1z / (C1z+C2z), the potential of the first node N1 is jointly maintained by the first capacitor C1 based on the potential of the second node N2 and by the second capacitor C2 based on the reference potential Vfx, and the total capacitance is maintained at C1z+C2z. In low brightness mode, after the potential of the second node N2 jumps, the second node N2 can also float. In this case, the potential of N1 is only maintained by the second capacitor C2 based on the reference potential Vfx, and the capacitance is maintained at C2z.

[0226] The present invention Figure 10 When at least one embodiment of the pixel circuit shown is in operation, in high brightness mode and low brightness mode, the holding capacitors are C1z+C2z and C2z respectively; or, the holding capacitors are C1z+C2z and C1z+C2z respectively; under the condition of C2z>>C1z, the difference between the holding capacitors in high and low brightness modes is not much, which facilitates the signal stability design of the pixel circuit.

[0227] like Figure 11As shown, at least one embodiment of the double-throw switch element may include a first switch transistor T91 and a second switch transistor T92;

[0228] The gate of T91 is electrically connected to the first switch control terminal M1, the source of T91 is electrically connected to the second end of the second capacitor C2, and the drain of T91 is electrically connected to the reference potential terminal FX;

[0229] The gate of T92 is electrically connected to the second switch control terminal M2 , the source of T92 is electrically connected to the second end of the second capacitor C2 , and the drain of T92 is electrically connected to the second node N2 .

[0230] exist Figure 11 In at least one embodiment of the double-throw switch element shown, both T91 and T92 are p-type transistors.

[0231] Figure 11 At least one embodiment of the double-throw switch element shown in FIG.

[0232] When the first switch control terminal M1 provides a low voltage signal and the second switch control terminal M2 provides a high voltage signal, T91 is turned on and T92 is turned off, and the second end of the second capacitor C2 is connected to the reference potential terminal FX;

[0233] When the first switch control terminal M1 provides a high voltage signal and the second switch control terminal M2 provides a low voltage signal, T92 is turned on and T91 is turned off, and the second end of the second capacitor C2 is connected to the second node N2.

[0234] In at least one embodiment of the present invention, T91 and T92 may both be n-type transistors.

[0235] The pixel circuit according to at least one embodiment of the present invention may further include a third energy storage circuit;

[0236] A first end of the third energy storage circuit is electrically connected to the first node, a second end of the third energy storage circuit is electrically connected to the first voltage end, and the third energy storage circuit is used to store electrical energy.

[0237] like Figure 12 As shown, in Figure 1 Based on at least one embodiment of the pixel circuit shown, the pixel circuit according to at least one embodiment of the present invention may further include a third energy storage circuit 130;

[0238] A first end of the third energy storage circuit 130 is electrically connected to the first node N1 , a second end of the third energy storage circuit 130 is electrically connected to the reference potential terminal FX, and the third energy storage circuit 130 is used to store electrical energy.

[0239] Figure 12At least one embodiment of the pixel circuit shown has independent coupling capacitors and holding capacitors in both high brightness mode and low brightness mode, but the holding capacitors are adjustable under the control of the mode signal, thereby generating different voltage division ratios in different modes.

[0240] The present invention Figure 12 At least one embodiment of the pixel circuit shown is in operation.

[0241] In the high brightness mode, the switch control circuit 13 controls the first node N1 to be disconnected from the first end of the second energy storage circuit 12 under the control of the switch control signal provided by the switch control terminal M, so that the second energy storage circuit 12 is single-ended and floats without participating in the pixel circuit-related working process;

[0242] In low brightness mode, the switch control circuit 13 controls the connection between the first node N1 and the first end of the second energy storage circuit 12, one end of the second energy storage circuit 12 and the first node N1, and the other end of the second energy storage circuit 12 is electrically connected to the first voltage end V1 under the control of the switch control signal provided by the switch control end M.

[0243] like Figure 13 As shown, in Figure 2 Based on at least one embodiment of the pixel circuit shown, the pixel circuit according to at least one embodiment of the present invention may further include a third energy storage circuit 130;

[0244] A first end of the third energy storage circuit 130 is electrically connected to the first node N1 , a second end of the third energy storage circuit 130 is electrically connected to the reference potential terminal FX, and the third energy storage circuit 130 is used to store electrical energy.

[0245] Figure 13 At least one embodiment of the pixel circuit shown has independent coupling capacitors and holding capacitors in both high brightness mode and low brightness mode, but the holding capacitors are adjustable under the control of the mode signal, thereby generating different voltage division ratios in different modes.

[0246] The present invention Figure 13 At least one embodiment of the pixel circuit shown is in operation.

[0247] In the high brightness mode, the switch control circuit 13 controls the second end of the second energy storage circuit 12 to be disconnected from the first voltage end V1 under the control of the switch control signal provided by the switch control end M, and the second energy storage circuit 12 is single-ended and floats without participating in the pixel circuit-related working process;

[0248] In the low brightness mode, the switch control circuit 13 controls the second end of the second energy storage circuit 12 to be connected to the first voltage end V1 under the control of the switch control signal provided by the switch control end M, one end of the second energy storage circuit 12 is electrically connected to the first node N1, and the other end of the second energy storage circuit 12 is connected to the first voltage end V1.

[0249] Optionally, the third energy storage circuit includes a third capacitor;

[0250] A first end of the third capacitor is electrically connected to the first node, and a second end of the third capacitor is electrically connected to the first voltage end.

[0251] like Figure 14 As shown, in Figure 5 Based on at least one embodiment of the pixel circuit shown, the pixel circuit according to at least one embodiment of the present invention further includes a third energy storage circuit; the third energy storage circuit includes a third capacitor C3;

[0252] A first end of C3 is electrically connected to the first node N1 , and a second end of C3 is electrically connected to the reference potential terminal FX.

[0253] exist Figure 14 In at least one embodiment of the pixel circuit shown, T1 may be a p-type transistor.

[0254] The present invention Figure 14 At least one embodiment of the pixel circuit shown is in operation.

[0255] In the high brightness mode, by controlling the switch control signal provided by the switch control terminal M, K0 is turned off, C2 is single-ended and floating due to the disconnection of the loop and does not participate in the operation process of the pixel circuit. In the signal superposition stage, the voltage change δVN2 of the second node N2 is coupled to the first node N1 through C1, δVN1 is equal to K2×δVN2, K2 is the second voltage coefficient, K2 is equal to C1z / (C1z+C3z), where C1z is the capacitance value of C1, and C3z is the capacitance value of C3;

[0256] In high brightness mode, after the voltage of N1 jumps, the second node N2 can float. At this time, the potential of the first node N1 is maintained by the third capacitor C3 based on the reference potential Vfx, and the capacitance is maintained at C3z. Alternatively, in high brightness mode, after the voltage of N1 jumps, the potential of the second node N2 is maintained, and the potential of the first node N1 can be maintained by the first capacitor C1 and the third capacitor C3, and the capacitance is maintained at C1z+C3z.

[0257] In the low brightness mode, by controlling the switch control signal provided by the switch control terminal M, K0 is turned on, the first end of the second capacitor C2 is connected to the first node N1, the second end of the second capacitor C2 is electrically connected to the reference potential terminal FX, and the second capacitor C2 and the third capacitor C3 are connected in parallel to participate in the potential jump voltage division of the first node N1; in the signal superposition stage, δVN1 is equal to K3×δVN2, K3 is the third voltage coefficient, K3 is equal to C1z / (C1z+C2z+C3z), where C1z is the capacitance value of C1, C2z is the capacitance value of C2, and C3z is the capacitance value of C3;

[0258] In low brightness mode, after the voltage of N1 jumps, the second node N2 can be floating, and the potential of the first node N1 is maintained by the parallel capacitors C2 and C3 based on the reference potential Vfx, with the capacitance maintained at C2z + C3z; alternatively, in low brightness mode, after the voltage of N1 jumps, the potential of the second node N2 is maintained, and the potential of the first node N1 can be maintained by the first capacitor C1, the second capacitor C2, and the third capacitor C3, with the capacitance maintained at C1z + C2z + C3z;

[0259] By properly setting C1z, C2z and C3z, different K2 and K3 can be obtained, which are respectively suitable for high-brightness display mode and low-brightness display mode.

[0260] like Figure 15 As shown, in Figure 6 Based on at least one embodiment of the pixel circuit shown, the pixel circuit according to at least one embodiment of the present invention further includes a third energy storage circuit; the third energy storage circuit includes a third capacitor C3;

[0261] A first end of C3 is electrically connected to the first node N1 , and a second end of C3 is electrically connected to the reference potential terminal FX.

[0262] exist Figure 15 In at least one embodiment of the pixel circuit shown, T1 may be a p-type transistor.

[0263] The present invention Figure 15 At least one embodiment of the pixel circuit shown is in operation.

[0264] In the high brightness mode, by controlling the switch control signal provided by the switch control terminal M, K0 is turned off, C2 is single-ended and floating due to the disconnection of the loop and does not participate in the operation process of the pixel circuit. In the signal superposition stage, the voltage change δVN2 of the second node N2 is coupled to the first node N1 through C1, δVN1 is equal to K2×δVN2, K2 is the second voltage coefficient, K2 is equal to C1z / (C1z+C3z), where C1z is the capacitance value of C1, and C3z is the capacitance value of C3;

[0265] In high brightness mode, after the voltage of N1 jumps, the second node N2 can float. At this time, the potential of the first node N1 is maintained by the third capacitor C3 based on the reference potential Vfx, and the capacitance is maintained at C3z. Alternatively, in high brightness mode, after the voltage of N1 jumps, the potential of the second node N2 is maintained, and the potential of the first node N1 can be maintained by the first capacitor C1 and the third capacitor C3, and the capacitance is maintained at C1z+C3z.

[0266] In the low brightness mode, by controlling the switch control signal provided by the switch control terminal M, K0 is turned on, the first end of the second capacitor C2 is electrically connected to the first node N1, the second end of the second capacitor C2 is connected to the reference potential terminal FX, and the second capacitor C2 and the third capacitor C3 are connected in parallel to participate in the potential jump voltage division of the first node N1; in the signal superposition stage, δVN1 is equal to K3×δVN2, K3 is the third voltage coefficient, K3 is equal to C1z / (C1z+C2z+C3z), where C1z is the capacitance value of C1, C2z is the capacitance value of C2, and C3z is the capacitance value of C3;

[0267] In low brightness mode, after the voltage of N1 jumps, the second node N2 can be floating, and the potential of the first node N1 is maintained by the parallel capacitors C2 and C3 based on the reference potential Vfx, with the capacitance maintained at C2z + C3z; alternatively, in low brightness mode, after the voltage of N1 jumps, the potential of the second node N2 is maintained, and the potential of the first node N1 can be maintained by the first capacitor C1, the second capacitor C2, and the third capacitor C3, with the capacitance maintained at C1z + C2z + C3z;

[0268] By properly setting C1z, C2z and C3z, different K2 and K3 can be obtained, which are respectively suitable for high-brightness display mode and low-brightness display mode.

[0269] Figure 14 At least one embodiment of the pixel circuit shown and Figure 15 At least one embodiment of the pixel circuit shown is equivalent in terms of coupling, voltage division, and holding functions, but has different characteristics in terms of parasitic effects and other aspects under specific pixel circuit layout conditions.

[0270] The pixel circuit according to at least one embodiment of the present invention further includes a first initialization circuit, a second initialization circuit, a compensation control circuit, and a light emitting control circuit;

[0271] The first initialization circuit is electrically connected to the first initial control terminal, the reference voltage terminal and the second node respectively, and is used to control the reference voltage terminal to provide a reference voltage to the second node under the control of a first initial control signal provided by the first initial control terminal;

[0272] The second initialization circuit is electrically connected to the second initial control terminal, the initial voltage terminal and the first node respectively, and is configured to control the initial voltage terminal to provide an initial voltage to the first node under the control of a second initial control signal provided by the second initial control terminal;

[0273] The compensation control circuit is electrically connected to the compensation control terminal, the first node and the second terminal of the driving circuit respectively, and is used to control the connection or disconnection of the first node and the second terminal of the driving circuit under the control of the compensation control signal provided by the compensation control terminal;

[0274] The light emitting control circuit is electrically connected to the light emitting control terminal, the second terminal of the driving circuit and the first electrode of the light emitting element respectively, and is used to control the connection or disconnection between the second terminal of the driving circuit and the first electrode of the light emitting element under the control of the light emitting control signal;

[0275] The second electrode of the light emitting element is electrically connected to the second voltage end.

[0276] like Figure 16 As shown, in Figure 14 Based on at least one embodiment of the pixel circuit shown, the pixel circuit according to at least one embodiment of the present invention further includes a first initialization circuit 21, a second initialization circuit 22, a compensation control circuit 23 and a light emitting control circuit 24;

[0277] The first initialization circuit 21 is electrically connected to the first initial control terminal S4, the reference voltage terminal VR and the second node N2, respectively, and is configured to control the reference voltage terminal VR to provide a reference voltage Vref to the second node N2 under the control of a first initial control signal provided by the first initial control terminal S4;

[0278] The second initialization circuit 22 is electrically connected to the second initial control terminal S5, the initial voltage terminal I1 and the first node N1 respectively, and is configured to control the initial voltage terminal I1 to provide the initial voltage Vint to the first node N1 under the control of the second initial control signal provided by the second initial control terminal S5;

[0279] The compensation control circuit 23 is electrically connected to the compensation control terminal S0, the first node N1 and the second terminal of the driving circuit 10, respectively, and is used to control the connection or disconnection between the first node N1 and the second terminal of the driving circuit 10 under the control of the compensation control signal provided by the compensation control terminal S0;

[0280] The light emitting control circuit 24 is electrically connected to the light emitting control terminal EM, the second terminal of the driving circuit 10, and the first electrode of the light emitting element EL, respectively, and is used to control the connection or disconnection between the second terminal of the driving circuit 10 and the first electrode of the light emitting element EL under the control of the light emitting control signal;

[0281] The second electrode of the light emitting element EL is electrically connected to the second voltage terminal V2.

[0282] like Figure 17 As shown, in Figure 15 Based on at least one embodiment of the pixel circuit shown, the pixel circuit according to at least one embodiment of the present invention further includes a first initialization circuit 21, a second initialization circuit 22, a compensation control circuit 23 and a light emitting control circuit 24;

[0283] The first initialization circuit 21 is electrically connected to the first initial control terminal S4, the reference voltage terminal VR and the second node N2, respectively, and is configured to control the reference voltage terminal VR to provide a reference voltage Vref to the second node N2 under the control of a first initial control signal provided by the first initial control terminal S4;

[0284] The second initialization circuit 22 is electrically connected to the second initial control terminal S5, the initial voltage terminal I1 and the first node N1 respectively, and is configured to control the initial voltage terminal I1 to provide the initial voltage Vint to the first node N1 under the control of the second initial control signal provided by the second initial control terminal S5;

[0285] The compensation control circuit 23 is electrically connected to the compensation control terminal S0, the first node N1 and the second terminal of the driving circuit 10, respectively, and is used to control the connection or disconnection between the first node N1 and the second terminal of the driving circuit 10 under the control of the compensation control signal provided by the compensation control terminal S0;

[0286] The light emitting control circuit 24 is electrically connected to the light emitting control terminal EM, the second terminal of the driving circuit 10, and the first electrode of the light emitting element EL, respectively, and is used to control the connection or disconnection between the second terminal of the driving circuit 10 and the first electrode of the light emitting element EL under the control of the light emitting control signal;

[0287] The second electrode of the light emitting element EL is electrically connected to the second voltage terminal V2.

[0288] Optionally, the compensation control terminal and the first initial control terminal are the same control terminal; the driving circuit includes a driving transistor, the data writing circuit includes a first transistor, the compensation control circuit includes a second transistor, the first initialization circuit includes a third transistor, the second initialization circuit includes a fourth transistor, and the light emitting control circuit includes a sixth transistor; and the light emitting element is an organic light emitting diode;

[0289] The gate of the driving transistor is electrically connected to the first node, and the first electrode of the driving transistor is electrically connected to the power supply voltage terminal;

[0290] The gate of the first transistor is electrically connected to the write control terminal, the first electrode of the first transistor is electrically connected to the data line, and the second electrode of the first transistor is electrically connected to the second node;

[0291] The gate of the second transistor is electrically connected to the first initial control terminal, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the second electrode of the driving transistor;

[0292] The gate of the third transistor is electrically connected to the first initial control terminal, the first electrode of the third transistor is electrically connected to the second node, and the second electrode of the third transistor is electrically connected to the reference voltage terminal;

[0293] The gate of the fourth transistor is electrically connected to the second initial control terminal, the first electrode of the fourth transistor is electrically connected to the first node, and the second electrode of the fourth transistor is electrically connected to the initial voltage terminal;

[0294] The gate of the sixth transistor is electrically connected to the light emitting control terminal, the first electrode of the sixth transistor is electrically connected to the second electrode of the driving transistor, and the second electrode of the sixth transistor is electrically connected to the anode of the organic light emitting diode;

[0295] The cathode of the organic light emitting diode is electrically connected to the second voltage terminal.

[0296] like Figure 18 As shown, in Figure 16 Based on at least one embodiment of the pixel circuit shown, the switching element is a switching transistor T9;

[0297] The gate of the switch transistor T9 is electrically connected to the switch control terminal M, the source of the switch transistor T9 is electrically connected to the first node N1, and the drain of the switch transistor T9 is electrically connected to the first end of the second capacitor C2;

[0298] The compensation control circuit includes a second transistor T2, the first initialization circuit includes a third transistor T3, the second initialization circuit includes a fourth transistor T4, and the light emitting control circuit includes a sixth transistor T6; the light emitting element is an organic light emitting diode O1;

[0299] The gate of the second transistor T2 is electrically connected to the first initial control terminal S4, the source of the second transistor T2 is electrically connected to the first node N1, and the drain of the second transistor T2 is electrically connected to the drain of the driving transistor T0;

[0300] The gate of the third transistor T3 is electrically connected to the first initial control terminal S4, the source of the third transistor T3 is electrically connected to the second node N2, and the drain of the third transistor T3 is electrically connected to the reference voltage terminal VR; the reference voltage terminal VR is used to provide a reference voltage Vref;

[0301] The gate of the fourth transistor T4 is electrically connected to the second initial control terminal S5, the source of the fourth transistor T4 is electrically connected to the first node N1, and the second electrode of the fourth transistor T4 is electrically connected to the initial voltage terminal I1; the initial voltage terminal I1 is used to provide an initial voltage Vint;

[0302] The gate of the sixth transistor T6 is electrically connected to the light emitting control terminal EM, the source of the sixth transistor T6 is electrically connected to the drain of the driving transistor T0, and the drain of the sixth transistor T6 is electrically connected to the anode of the organic light emitting diode O1;

[0303] The cathode of the organic light emitting diode O1 is electrically connected to the low voltage terminal Vss.

[0304] exist Figure 18 In at least one embodiment of the pixel circuit shown, all transistors are p-type transistors, but the present invention is not limited thereto.

[0305] like Figure 19 As shown, Figure 18 When at least one embodiment of the pixel circuit shown is in operation, a display cycle may include a reset phase t1, a threshold voltage detection phase t2, a signal superposition phase t3, and a light emitting phase t4, which are arranged in sequence;

[0306] In the reset phase t1, EM provides a high voltage signal, S5 provides a low voltage signal, S1 and S4 both provide high voltage signals, and T4 is turned on to write Vint into the first node N1;

[0307] In the threshold voltage detection phase t2, EM provides a high voltage signal, S4 provides a low voltage signal, S1 and S5 both provide high voltage signals, T2 and T3 are both turned on to write Vref into the second node N2 and control the connection between the first node N1 and the drain of T3. The potential of N1 is Vd+Vth, where Vd is the voltage value of the power supply voltage provided by the power supply voltage Vdd, and Vth is the threshold voltage of T0.

[0308] In the signal superposition phase t3, EM provides a high voltage signal, S1 provides a low voltage signal, S4 and S5 both provide high voltage signals, T1 is turned on, DT provides a data voltage Vdata to the second node N2, and the potential of N1 changes accordingly;

[0309] In the signal superposition stage t3,

[0310] In high brightness mode, by controlling the switch control terminal M to provide a high voltage signal, T9 is turned off, C2 is single-ended and floating due to the disconnection of the loop and does not participate in the operation process of the pixel circuit. In the signal superposition stage, the voltage change δVN2 of the second node N2 is coupled to the first node N1 through C1, δVN1 is equal to K2×δVN2, K2 is the second voltage coefficient, K2 is equal to C1z / (C1z+C3z), where C1z is the capacitance value of C1, and C3z is the capacitance value of C3;

[0311] In the low brightness mode, the switch control terminal M is controlled to provide a low voltage signal, so that T9 is turned on, the first end of the second capacitor C2 is connected to the first node N1, the second end of the second capacitor C2 is electrically connected to the reference potential terminal FX, and the second capacitor C2 and the third capacitor C3 are connected in parallel to participate in the potential jump voltage division of the first node N1; δVN1 is equal to K3×δVN2, K3 is the third voltage coefficient, K3 is equal to C1z / (C1z+C2z+C3z), where C1z is the capacitance value of C1, C2z is the capacitance value of C2, and C3z is the capacitance value of C3;

[0312] In the light-emitting stage t4, EM provides a low voltage signal, S1 provides a high voltage signal, S4 and S5 both provide high voltage signals, and T0 drives O1 to emit light.

[0313] like Figure 20 As shown, in Figure 17 Based on at least one embodiment of the pixel circuit shown, the switching element is a switching transistor T9;

[0314] The gate of the switch transistor T9 is electrically connected to the switch control terminal M, the source of the switch transistor T9 is electrically connected to the first end of the second capacitor C2, and the drain of the switch transistor T9 is electrically connected to the reference potential terminal FX;

[0315] The compensation control circuit includes a second transistor T2, the first initialization circuit includes a third transistor T3, the second initialization circuit includes a fourth transistor T4, and the light emitting control circuit includes a sixth transistor T6; the light emitting element is an organic light emitting diode O1;

[0316] The gate of the second transistor T2 is electrically connected to the first initial control terminal S4, the source of the second transistor T2 is electrically connected to the first node N1, and the drain of the second transistor T2 is electrically connected to the drain of the driving transistor T0;

[0317] The gate of the third transistor T3 is electrically connected to the first initial control terminal S4, the source of the third transistor T3 is electrically connected to the second node N2, and the drain of the third transistor T3 is electrically connected to the reference voltage terminal VR; the reference voltage terminal VR is used to provide a reference voltage Vref;

[0318] The gate of the fourth transistor T4 is electrically connected to the second initial control terminal S5, the source of the fourth transistor T4 is electrically connected to the first node N1, and the second electrode of the fourth transistor T4 is electrically connected to the initial voltage terminal I1; the initial voltage terminal I1 is used to provide an initial voltage Vint;

[0319] The gate of the sixth transistor T6 is electrically connected to the light emitting control terminal EM, the source of the sixth transistor T6 is electrically connected to the drain of the driving transistor T0, and the drain of the sixth transistor T6 is electrically connected to the anode of the organic light emitting diode O1;

[0320] The cathode of the organic light emitting diode O1 is electrically connected to the low voltage terminal Vss.

[0321] exist Figure 20 In at least one embodiment of the pixel circuit shown, all transistors are p-type transistors, but the present invention is not limited thereto.

[0322] like Figure 19 As shown, Figure 20 When at least one embodiment of the pixel circuit shown is in operation, a display cycle may include a reset phase t1, a threshold voltage detection phase t2, a signal superposition phase t3, and a light emitting phase t4, which are arranged in sequence;

[0323] In the reset phase t1, EM provides a high voltage signal, S5 provides a low voltage signal, S1 and S4 both provide high voltage signals, and T4 is turned on to write Vint into the first node N1;

[0324] In the threshold voltage detection phase t2, EM provides a high voltage signal, S4 provides a low voltage signal, S1 and S5 both provide high voltage signals, T2 and T3 are both turned on to write Vref into the second node N2 and control the connection between the first node N1 and the drain of T3. The potential of N1 is Vd+Vth, where Vd is the voltage value of the power supply voltage provided by the power supply voltage Vdd, and Vth is the threshold voltage of T0.

[0325] In the signal superposition phase t3, EM provides a high voltage signal, S1 provides a low voltage signal, S4 and S5 both provide high voltage signals, T1 is turned on, DT provides a data voltage Vdata to the second node N2, and the potential of N1 changes accordingly;

[0326] In the signal superposition stage t3,

[0327] In the high brightness mode, by controlling the switch control signal provided by the switch control terminal M, K0 is turned off, C2 is single-ended and floating due to the disconnection of the loop and does not participate in the operation process of the pixel circuit. In the signal superposition stage, the voltage change δVN2 of the second node N2 is coupled to the first node N1 through C1, δVN1 is equal to K2×δVN2, K2 is the second voltage coefficient, K2 is equal to C1z / (C1z+C3z), where C1z is the capacitance value of C1, and C3z is the capacitance value of C3;

[0328] In the low brightness mode, by controlling the switch control signal provided by the switch control terminal M, K0 is turned on, the first end of the second capacitor C2 is electrically connected to the first node N1, the second end of the second capacitor C2 is connected to the reference potential terminal FX, and the second capacitor C2 and the third capacitor C3 are connected in parallel to participate in the potential jump voltage division of the first node N1; δVN1 is equal to K3×δVN2, K3 is the third voltage coefficient, K3 is equal to C1z / (C1z+C2z+C3z), where C1z is the capacitance value of C1, C2z is the capacitance value of C2, and C3z is the capacitance value of C3;

[0329] In the light-emitting stage t4, EM provides a low voltage signal, S1 provides a high voltage signal, S4 and S5 both provide high voltage signals, and T0 drives O1 to emit light.

[0330] The pixel circuit according to at least one embodiment of the present invention is characterized by further comprising a first initialization circuit, a second initialization circuit, a voltage control circuit, a compensation control circuit, and a light emitting control circuit;

[0331] The first initialization circuit is electrically connected to the initial control terminal, the reference voltage terminal and the second node respectively, and is used to control the reference voltage terminal to provide a reference voltage to the second node under the control of an initial control signal provided by the initial control terminal;

[0332] The second initialization circuit is electrically connected to the initial control terminal, the initial voltage terminal and the first node respectively, and is configured to control the initial voltage terminal to provide an initial voltage to the first node under the control of the initial control signal;

[0333] The voltage control circuit is electrically connected to the light-emitting control terminal, the reference voltage terminal and the second node respectively, and is used to control the reference voltage terminal to provide a reference voltage to the second node under the control of the light-emitting control signal provided by the light-emitting control terminal;

[0334] The compensation control circuit is electrically connected to the compensation control terminal, the first node and the second terminal of the driving circuit respectively, and is used to control the connection or disconnection of the first node and the second terminal of the driving circuit under the control of the compensation control signal provided by the compensation control terminal;

[0335] The light emitting control circuit is electrically connected to the light emitting control terminal, the second terminal of the driving circuit and the first electrode of the light emitting element respectively, and is used to control the connection or disconnection between the second terminal of the driving circuit and the first electrode of the light emitting element under the control of the light emitting control signal;

[0336] The second electrode of the light emitting element is electrically connected to the second voltage end.

[0337] like Figure 21 As shown, in Figure 7 Based on at least one embodiment of the pixel circuit shown, the pixel circuit according to at least one embodiment of the present invention further includes a first initialization circuit 21, a second initialization circuit 22, a voltage control circuit 20, a compensation control circuit 23 and a light emitting control circuit 24; the light emitting element is an organic light emitting diode O1;

[0338] The first initialization circuit 21 is electrically connected to the initial control terminal S3, the reference voltage terminal VR and the second node N2 respectively, and is used to control the reference voltage terminal VR to provide the reference voltage Vref to the second node N2 under the control of the initial control signal provided by the initial control terminal S3;

[0339] The second initialization circuit 22 is electrically connected to the initial control terminal S3, the initial voltage terminal I1 and the first node N1 respectively, and is used to control the initial voltage terminal I1 to provide an initial voltage to the first node N1 under the control of the initial control signal;

[0340] The voltage control circuit 20 is electrically connected to the light emitting control terminal EM, the reference voltage terminal VR and the second node N2, respectively, and is used to control the reference voltage terminal VR to provide a reference voltage Vref to the second node N2 under the control of the light emitting control signal provided by the light emitting control terminal EM;

[0341] The compensation control circuit 23 is electrically connected to the compensation control terminal S2, the first node N1, and the second terminal of the driving circuit 10, respectively, and is used to control the connection or disconnection between the first node N1 and the second terminal of the driving circuit 10 under the control of the compensation control signal provided by the compensation control terminal S2;

[0342] The light emitting control circuit 24 is electrically connected to the light emitting control terminal EM, the second terminal of the driving circuit 10, and the first electrode of the light emitting element EL, respectively, and is used to control the connection or disconnection between the second terminal of the driving circuit 10 and the first electrode of the light emitting element EL under the control of the light emitting control signal;

[0343] The second electrode of the light emitting element EL is electrically connected to the second voltage terminal V2.

[0344] Optionally, the compensation control terminal and the write control terminal are the same control terminal; the drive circuit includes a drive transistor, the data write circuit includes a first transistor, the compensation control circuit includes a second transistor, the first initialization circuit includes a third transistor, the second initialization circuit includes a fourth transistor, the voltage control circuit includes a fifth transistor, and the light emitting control circuit includes a sixth transistor; the light emitting element is an organic light emitting diode;

[0345] The gate of the driving transistor is electrically connected to the first node, and the first electrode of the driving transistor is electrically connected to the power supply voltage terminal;

[0346] The gate of the first transistor is electrically connected to the write control terminal, the first electrode of the first transistor is electrically connected to the data line, and the second electrode of the first transistor is electrically connected to the second node;

[0347] The gate of the second transistor is electrically connected to the write control terminal, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the second electrode of the drive transistor;

[0348] The gate of the third transistor is electrically connected to the initial control terminal, the first electrode of the third transistor is electrically connected to the second node, and the second electrode of the third transistor is electrically connected to the reference voltage terminal;

[0349] The gate of the fourth transistor is electrically connected to the initial control terminal, the first electrode of the fourth transistor is electrically connected to the first node, and the second electrode of the fourth transistor is electrically connected to the initial voltage terminal;

[0350] The gate of the fifth transistor is electrically connected to the light emitting control terminal, the first electrode of the fifth transistor is electrically connected to the second node, and the second electrode of the fifth transistor is electrically connected to the reference voltage terminal;

[0351] The gate of the sixth transistor is electrically connected to the light emitting control terminal, the first electrode of the sixth transistor is electrically connected to the second electrode of the driving transistor, and the second electrode of the sixth transistor is electrically connected to the anode of the organic light emitting diode;

[0352] The cathode of the organic light emitting diode is electrically connected to the second voltage terminal.

[0353] like Figure 22 As shown, in Figure 21 Based on at least one embodiment of the pixel circuit shown, the switch control circuit 13 includes a double-throw switch element; the driving circuit includes a driving transistor T0; the data writing circuit includes a first transistor T1, the first energy storage circuit includes a first capacitor C1, and the second energy storage circuit includes a second capacitor C2;

[0354] The gate of the driving transistor T0 is electrically connected to the first node N1, and the source of the driving transistor T0 is electrically connected to the power supply voltage terminal Vdd;

[0355] The gate of the first transistor T1 is electrically connected to the write control terminal S1, the source of the first transistor T1 is electrically connected to the data line DT, and the drain of the first transistor T1 is electrically connected to the second node N2;

[0356] A first end of the first capacitor C1 is electrically connected to the second node N2, and a second end of the first capacitor C1 is electrically connected to the first node N1;

[0357] A first end of the second capacitor C2 is electrically connected to the first node N1;

[0358] The double-throw switch element includes a first switch transistor T91 and a second switch transistor T92;

[0359] The gate of T91 is electrically connected to the switch control terminal M, the source of T91 is electrically connected to the second end of the second capacitor C2, and the drain of T91 is electrically connected to the reference potential terminal FX;

[0360] The gate of T92 is electrically connected to the switch control terminal M, the source of T92 is electrically connected to the second end of the second capacitor C2, and the drain of T92 is electrically connected to the second node N2;

[0361] The compensation control circuit 23 includes a second transistor T2, the first initialization circuit includes a third transistor T3, the second initialization circuit includes a fourth transistor T4, the voltage control circuit includes a fifth transistor T5, and the light emitting control circuit includes a sixth transistor T6; the light emitting element is an organic light emitting diode O1;

[0362] The gate of the driving transistor T0 is electrically connected to the first node N1, and the source of the driving transistor T0 is electrically connected to the power supply voltage terminal Vdd;

[0363] The gate of the first transistor T1 is electrically connected to the write control terminal S1, the source of the first transistor T1 is electrically connected to the data line DT, and the drain of the first transistor T1 is electrically connected to the second node N2;

[0364] The gate of the second transistor T2 is electrically connected to the write control terminal S1, the source of the second transistor T2 is electrically connected to the first node N1, and the drain of the second transistor T2 is electrically connected to the drain of the driving transistor T0;

[0365] The gate of the third transistor T3 is electrically connected to the initial control terminal S3, the source of the third transistor T3 is electrically connected to the second node N2, and the drain of the third transistor T3 is electrically connected to the reference voltage terminal VR; the reference voltage terminal VR is used to provide a reference voltage Vref;

[0366] The gate of the fourth transistor T4 is electrically connected to the initial control terminal S3, the source of the fourth transistor T4 is electrically connected to the first node N1, and the drain of the fourth transistor T4 is electrically connected to the initial voltage terminal I1; the initial voltage terminal I1 is used to provide an initial voltage Vint;

[0367] The gate of the fifth transistor T5 is electrically connected to the light emitting control terminal EM, the source of the fifth transistor T5 is electrically connected to the second node N2, and the drain of the fifth transistor T5 is electrically connected to the reference voltage terminal VR;

[0368] The gate of the sixth transistor T6 is electrically connected to the light emitting control terminal EM, the source of the sixth transistor T6 is electrically connected to the drain of the driving transistor T0, and the drain of the sixth transistor T6 is electrically connected to the anode of the organic light emitting diode O1;

[0369] The cathode of the organic light emitting diode O1 is electrically connected to the low voltage terminal Vss.

[0370] exist Figure 22 In at least one embodiment of the pixel circuit shown, the writing control terminal and the compensation control terminal are the same control terminal.

[0371] exist Figure 22 In at least one embodiment of the pixel circuit shown, T91 is an n-type transistor, T92 is a p-type transistor; and T0, T1, T2, T3, T4, T5, and T6 are all p-type transistors.

[0372] Figure 22 At least one embodiment of the pixel circuit shown is in operation.

[0373] In high-brightness mode, the switch control terminal M provides a low-voltage signal, T92 is turned on, T91 is turned off, and C1 and C2 are connected in parallel to form a capacitor, which plays a role in signal coupling and holding. In the signal superposition stage, the voltage change δVN2 of the second node N2 is coupled to the first node N1 through C1, δVN1 is equal to δVN2, and the coupling voltage divider ratio is N1. Then, the first node N1 is maintained by the parallel capacitors C1 and C2 based on the reference potential Vfx, and the holding capacitance is C1z+C2z. After the potential of the second node N2 jumps, the potential of the second node N2 needs to be maintained.

[0374] In low brightness mode, the switch control terminal M provides a high voltage signal, T91 is turned on, T92 is turned off, the second end of C2 is connected to FX, and the second capacitor C2 participates in the potential jump voltage division of the first node N1; in the signal superposition stage, δVN1 is equal to K1×δVN2, K1 is the first voltage coefficient, K1 is equal to C1z / (C1z+C2z), the potential of the first node N1 is maintained by the first capacitor C1 based on the potential of the second node N2, and by the second capacitor C2 based on the reference potential Vfx, maintaining the total capacitance of C1z+C2z. In low brightness mode, after the potential of the second node N2 jumps, the second node N2 can also float. In this case, the potential of N1 is only maintained by the second capacitor C2 based on the reference potential Vfx, and the capacitance is maintained at C2z.

[0375] In at least one embodiment of the present invention, driving with different brightness levels can also be achieved by changing the characteristics of the driving transistor included in the driving circuit. For example, a source or drain can be optionally connected at different positions in the channel of a driving transistor with a longer channel, or a gate with an optional insulating layer of different thickness can be optionally connected. Driving transistors with different gain levels and corresponding controlled and transformed driving outputs can be formed through circuit selection.

[0376] The pixel driving method according to an embodiment of the present invention is applied to the above-mentioned pixel circuit, and the pixel driving method includes:

[0377] The driving circuit drives the light emitting element under the control of the potential of the control terminal;

[0378] The data writing circuit writes the data voltage provided by the data line into the second node under the control of the write control signal;

[0379] The first energy storage circuit stores electrical energy; the second energy storage circuit stores electrical energy

[0380] Under the control of the switch control signal, the switch control circuit controls whether the first node is electrically connected to the first voltage terminal through the second energy storage circuit.

[0381] Optionally, the step of the switch control circuit controlling, under the control of the switch control signal, whether the first node is electrically connected to the first voltage terminal through the second energy storage circuit includes:

[0382] In the first display mode, the switch control circuit controls the first node to not be electrically connected to the first voltage terminal through the second energy storage circuit under the control of the switch control signal;

[0383] In the second display mode, the switch control circuit controls the first node to be electrically connected to the first voltage terminal through the second energy storage circuit under the control of the switch control signal.

[0384] In at least one embodiment of the present invention, the first display mode may be a highlight display mode, and the second display mode may be a low-brightness display mode.

[0385] The display device according to the embodiment of the present invention includes the above-mentioned pixel circuit.

[0386] The present invention is applicable to the field of digital flat panel displays. The display device may be, for example, an AMOLED (active matrix organic light emitting diode) display device, but is not limited thereto.

[0387] The display device provided in the embodiment of the present invention can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or the like.

[0388] The above is a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A pixel circuit, characterized in that: It includes a light-emitting element, a driving circuit, a first energy storage circuit, a second energy storage circuit, a switch control circuit and a data writing circuit; The control terminal of the driving circuit is electrically connected to the first node, the first terminal of the driving circuit is electrically connected to the power supply voltage terminal, and the second terminal of the driving circuit is electrically connected to the light-emitting element. The driving circuit is used to drive the light-emitting element under the control of the potential of the control terminal; The data writing circuit is electrically connected to the write control terminal, the data line and the second node respectively, and is used to write the data voltage provided by the data line into the second node under the control of the write control signal provided by the write control terminal; A first end of the first energy storage circuit is electrically connected to the second node, a second end of the first energy storage circuit is electrically connected to the first node, and the first energy storage circuit is used to store electrical energy; The switch control circuit is electrically connected to the switch control terminal, the second energy tank circuit and the first voltage terminal respectively, and is used to control whether the first node is electrically connected to the first voltage terminal through the second energy tank circuit under the control of the switch control signal provided by the switch control terminal; The second energy storage circuit is used to store electrical energy; The control end of the switch control circuit is electrically connected to the switch control end, the first end of the switch control circuit is electrically connected to the first node, the second end of the switch control circuit is electrically connected to the first end of the second energy storage circuit, and the switch control circuit is used to control the connection or disconnection between the first node and the first end of the second energy storage circuit under the control of the switch control signal; the second end of the second energy storage circuit is electrically connected to the first voltage end; or The first end of the second energy storage circuit is electrically connected to the first node; the control end of the switch control circuit is electrically connected to the switch control end, the first end of the switch control circuit is electrically connected to the second end of the second energy storage circuit, and the second end of the switch control circuit is electrically connected to the first voltage end. The switch control circuit is used to control the connection or disconnection between the second end of the second energy storage circuit and the first voltage end under the control of the switch control signal.

2. The pixel circuit according to claim 1, wherein: When the first terminal of the second energy storage circuit is electrically connected to the first node, The switch control circuit further includes a third terminal; The third terminal of the switch control circuit is electrically connected to the second node. The switch control circuit is further configured to control the connection or disconnection between the second node and the second terminal of the second energy storage circuit under the control of the switch control signal.

3. The pixel circuit according to claim 1, wherein: Also included is a third tank circuit; A first end of the third energy storage circuit is electrically connected to the first node, a second end of the third energy storage circuit is electrically connected to the first voltage end, and the third energy storage circuit is used to store electrical energy.

4. The pixel circuit according to claim 1, wherein: When the second terminal of the second energy storage circuit is electrically connected to the first voltage terminal, The switch control circuit includes a switch element; the first energy storage circuit includes a first capacitor, and the second energy storage circuit includes a second capacitor; The control end of the switch element is electrically connected to the switch control end, the first end of the switch element is electrically connected to the first node, and the second end of the switch element is electrically connected to the first end of the second capacitor; the switch element is used to control the connection or disconnection between the first end of the switch element and the second end of the switch element under the control of the switch control signal; A first end of the first capacitor is electrically connected to the second node, and a second end of the first capacitor is electrically connected to the first node; The second terminal of the second capacitor is electrically connected to the first voltage terminal.

5. The pixel circuit according to claim 1, wherein: When the first terminal of the second energy storage circuit is electrically connected to the first node, The switch control circuit includes a switch element; the first energy storage circuit includes a first capacitor, and the second energy storage circuit includes a second capacitor; The control end of the switch element is electrically connected to the switch control end, the first end of the switch element is electrically connected to the second end of the second capacitor, and the second end of the switch element is electrically connected to the first voltage end; the switch element is used to control the connection or disconnection between the first end of the switch element and the second end of the switch element under the control of the switch control signal; A first end of the first capacitor is electrically connected to the second node, and a second end of the first capacitor is electrically connected to the first node; A first terminal of the second capacitor is electrically connected to the first node.

6. The pixel circuit according to claim 2, wherein: The switch control circuit includes a double-throw switch element; the first energy storage circuit includes a first capacitor, and the second energy storage circuit includes a second capacitor; a first end of the first capacitor is electrically connected to the second node, and a second end of the first capacitor is electrically connected to the first node; The first end of the second capacitor is electrically connected to the first node; The control end of the double-throw switch element is electrically connected to the switch control end, the first end of the double-throw switch element is electrically connected to the second end of the second capacitor, the second end of the double-throw switch element is electrically connected to the first voltage end, and the third end of the double-throw switch element is electrically connected to the second node; The double-throw switch element is used to control the communication between the first end of the double-throw switch element and the second end of the double-throw switch element or the third end of the double-throw switch element under the control of the switch control signal.

7. The pixel circuit according to claim 3, wherein: The third energy storage circuit includes a third capacitor; A first end of the third capacitor is electrically connected to the first node, and a second end of the third capacitor is electrically connected to the first voltage end.

8. The pixel circuit according to any one of claims 1 to 6, wherein: It also includes a first initialization circuit, a second initialization circuit, a voltage control circuit, a compensation control circuit and a light emitting control circuit; The first initialization circuit is electrically connected to the initial control terminal, the reference voltage terminal and the second node respectively, and is used to control the reference voltage terminal to provide a reference voltage to the second node under the control of an initial control signal provided by the initial control terminal; The second initialization circuit is electrically connected to the initial control terminal, the initial voltage terminal and the first node respectively, and is configured to control the initial voltage terminal to provide an initial voltage to the first node under the control of the initial control signal; The voltage control circuit is electrically connected to the light-emitting control terminal, the reference voltage terminal and the second node respectively, and is used to control the reference voltage terminal to provide a reference voltage to the second node under the control of the light-emitting control signal provided by the light-emitting control terminal; The compensation control circuit is electrically connected to the compensation control terminal, the first node and the second terminal of the driving circuit respectively, and is used to control the connection or disconnection of the first node and the second terminal of the driving circuit under the control of the compensation control signal provided by the compensation control terminal; The light emitting control circuit is electrically connected to the light emitting control terminal, the second terminal of the driving circuit and the first electrode of the light emitting element respectively, and is used to control the connection or disconnection between the second terminal of the driving circuit and the first electrode of the light emitting element under the control of the light emitting control signal; The second electrode of the light emitting element is electrically connected to the second voltage end.

9. The pixel circuit according to claim 8, wherein: The compensation control terminal and the write control terminal are the same control terminal; the driving circuit includes a driving transistor, the data writing circuit includes a first transistor, the compensation control circuit includes a second transistor, the first initialization circuit includes a third transistor, the second initialization circuit includes a fourth transistor, the voltage control circuit includes a fifth transistor, and the light emitting control circuit includes a sixth transistor; the light emitting element is an organic light emitting diode; The gate of the driving transistor is electrically connected to the first node, and the first electrode of the driving transistor is electrically connected to the power supply voltage terminal; The gate of the first transistor is electrically connected to the write control terminal, the first electrode of the first transistor is electrically connected to the data line, and the second electrode of the first transistor is electrically connected to the second node; The gate of the second transistor is electrically connected to the write control terminal, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the second electrode of the drive transistor; The gate of the third transistor is electrically connected to the initial control terminal, the first electrode of the third transistor is electrically connected to the second node, and the second electrode of the third transistor is electrically connected to the reference voltage terminal; The gate of the fourth transistor is electrically connected to the initial control terminal, the first electrode of the fourth transistor is electrically connected to the first node, and the second electrode of the fourth transistor is electrically connected to the initial voltage terminal; The gate of the fifth transistor is electrically connected to the light emitting control terminal, the first electrode of the fifth transistor is electrically connected to the second node, and the second electrode of the fifth transistor is electrically connected to the reference voltage terminal; The gate of the sixth transistor is electrically connected to the light emitting control terminal, the first electrode of the sixth transistor is electrically connected to the second electrode of the driving transistor, and the second electrode of the sixth transistor is electrically connected to the anode of the organic light emitting diode; The cathode of the organic light emitting diode is electrically connected to the second voltage terminal.

10. The pixel circuit according to claim 3, wherein: It also includes a first initialization circuit, a second initialization circuit, a compensation control circuit and a light emitting control circuit; The first initialization circuit is electrically connected to the first initial control terminal, the reference voltage terminal and the second node respectively, and is used to control the reference voltage terminal to provide a reference voltage to the second node under the control of a first initial control signal provided by the first initial control terminal; The second initialization circuit is electrically connected to the second initial control terminal, the initial voltage terminal and the first node respectively, and is configured to control the initial voltage terminal to provide an initial voltage to the first node under the control of a second initial control signal provided by the second initial control terminal; The compensation control circuit is electrically connected to the compensation control terminal, the first node and the second terminal of the driving circuit respectively, and is used to control the connection or disconnection of the first node and the second terminal of the driving circuit under the control of the compensation control signal provided by the compensation control terminal; The light emitting control circuit is electrically connected to the light emitting control terminal, the second terminal of the driving circuit and the first electrode of the light emitting element respectively, and is used to control the connection or disconnection between the second terminal of the driving circuit and the first electrode of the light emitting element under the control of the light emitting control signal provided by the light emitting control terminal; The second electrode of the light emitting element is electrically connected to the second voltage end.

11. The pixel circuit according to claim 10, wherein: The compensation control terminal and the first initial control terminal are the same control terminal; the driving circuit includes a driving transistor, the data writing circuit includes a first transistor, the compensation control circuit includes a second transistor, the first initialization circuit includes a third transistor, the second initialization circuit includes a fourth transistor, and the light emitting control circuit includes a sixth transistor; the light emitting element is an organic light emitting diode; The gate of the driving transistor is electrically connected to the first node, and the first electrode of the driving transistor is electrically connected to the power supply voltage terminal; The gate of the first transistor is electrically connected to the write control terminal, the first electrode of the first transistor is electrically connected to the data line, and the second electrode of the first transistor is electrically connected to the second node; The gate of the second transistor is electrically connected to the first initial control terminal, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the second electrode of the driving transistor; The gate of the third transistor is electrically connected to the first initial control terminal, the first electrode of the third transistor is electrically connected to the second node, and the second electrode of the third transistor is electrically connected to the reference voltage terminal; The gate of the fourth transistor is electrically connected to the second initial control terminal, the first electrode of the fourth transistor is electrically connected to the first node, and the second electrode of the fourth transistor is electrically connected to the initial voltage terminal; The gate of the sixth transistor is electrically connected to the light emitting control terminal, the first electrode of the sixth transistor is electrically connected to the second electrode of the driving transistor, and the second electrode of the sixth transistor is electrically connected to the anode of the organic light emitting diode; The cathode of the organic light emitting diode is electrically connected to the second voltage terminal.

12. A pixel driving method, applied to the pixel circuit according to any one of claims 1 to 11, characterized in that: The pixel driving method includes: The driving circuit drives the light emitting element under the control of the potential of the control terminal; The data writing circuit writes the data voltage provided by the data line into the second node under the control of the write control signal; The first energy storage circuit stores electrical energy; the second energy storage circuit stores electrical energy; The switch control circuit controls, under the control of the switch control signal, whether the first node is electrically connected to the first voltage terminal through the second energy storage circuit; The step of the switch control circuit controlling whether the first node is electrically connected to the first voltage terminal through the second energy storage circuit under the control of the switch control signal includes: In the first display mode, the switch control circuit controls the first node to not be electrically connected to the first voltage terminal through the second energy storage circuit under the control of the switch control signal; In the second display mode, the switch control circuit controls the first node to be electrically connected to the first voltage terminal through the second energy storage circuit under the control of the switch control signal.

13. A display device, characterized in that: The method comprises the pixel circuit according to any one of claims 1 to 11.

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