Method for multi-bit quantization of memory

Abstract

Embodiments of the present application disclose a multi-bit quantization method of a memory, comprising: receiving target data and writing the target data into a memory to obtain an analog output value; performing a first read quantization operation on the analog output value by a decision circuit to obtain a first quantization read result; performing a second read quantization operation based on the first quantization read result to obtain a second quantization read result, wherein the first quantization read result and the second quantization read result are used for quantization decision of the memory unit; the decision circuit is a sensitive amplifier, wherein at least one sensitive amplifier with full margin decision function is contained; in the read quantization operation, the decision circuit compares the analog output value with a resistance threshold set to output a group of discrete values and generate a multi-bit quantization result.

Description

Technical Field

[0001] This application relates to the field of data processing technology, and more specifically, to a multi-bit quantization method for memory. Background Technology

[0002] Memory is an electronic device that uses semiconductors. Currently, new types of memory include MRAM based on magnetic tunnel junction devices, RRAM based on resistive switching materials, FRAM based on ferroelectric capacitors, or capacitor-free DRAM based on amorphous oxide thin film transistors, etc., which have the characteristics of high read / write bandwidth, high integration, or non-volatility, and are expected to replace traditional memory in the future.

[0003] However, newer types of memory are currently more prone to errors during operation than traditional memory, such as latch-based static RAM and capacitor-based dynamic RAM (DRAM), leading to changes in stored data values. Furthermore, regardless of whether it's traditional or new memory, as memory device manufacturing processes improve, memory capacity and integration levels increase, potentially causing errors from previously unknown sources to appear, further compromising the reliability of storage devices. Therefore, additional overhead is needed to mitigate these errors. Summary of the Invention

[0004] Embodiments of this application provide a multi-bit quantization method for a memory, which aims to solve or partially solve the above-mentioned problems.

[0005] Other features and advantages of this application will become apparent from the following detailed description, or may be learned in part from practice of this application.

[0006] According to one aspect of the embodiments of this application, a multi-bit quantization method for a memory is provided, the multi-bit quantization method for the memory comprising:

[0007] Receive target data and write the target data into memory to obtain a simulated output value;

[0008] The analog output value is quantized for the first time by a decision circuit to obtain the first quantization result.

[0009] A second quantization operation is performed based on the first quantization read result to obtain the second quantization read result. The first quantization read result and the second quantization read result are used to make a quantization decision on the storage unit.

[0010] The decision circuit is equipped with a sensitive amplifier, including at least one sensitive amplifier with full margin decision function;

[0011] When the decision circuit performs the read quantization operation, it compares the analog output value with a set of resistance decision thresholds and outputs a set of discrete values ​​to generate the corresponding quantization result.

[0012] In some examples, receiving target data and writing the target data into a storage unit includes:

[0013] The target data is received by the control logic circuit and written into the storage unit.

[0014] In some examples, a first quantization operation is performed on the simulated output value to obtain the first quantization read result, including:

[0015] The analog output value is compared with a first decision threshold value in the resistance value decision threshold set to determine the first discrete value corresponding to the decision threshold value, and the first discrete value is used as the first quantization reading result.

[0016] The decision circuit is a sensitive amplifier.

[0017] In some examples, a second quantization operation is performed based on the first quantization read result to obtain a second quantization read result, including:

[0018] Based on the first quantization reading result, the second decision threshold value is determined from the resistance decision threshold set;

[0019] The second discrete value is determined based on the second decision threshold value, and the second discrete value is used as the result of the second quantization reading.

[0020] In some examples, before performing a first read quantization operation on the simulated output value to obtain the first quantization read result, the method further includes:

[0021] Based on one or more reference storage devices that are the same as the storage devices of the storage cell, obtain a set of reference cells with different resistance values.

[0022] When the reference unit contains more than one reference storage device, the reference storage devices have the same or different resistance values ​​and are connected in series, parallel or series-parallel configurations.

[0023] Based on the resistance value of one or more reference cells in the set of reference cells, a decision threshold value is obtained.

[0024] Based on the obtained decision threshold values, a set of resistance decision thresholds is determined.

[0025] In some examples, the decision circuit is a sensitive amplifier, wherein at least one sensitive amplifier with full margin decision capability is included, comprising:

[0026] The decision circuit includes at least one sensitive amplifier with full margin decision function;

[0027] The decision circuit performs the multiple read quantization operations.

[0028] The decision circuit performs a second quantization operation based on the first quantization result to obtain the second quantization result.

[0029] Based on the two quantization readings, a set of discrete values ​​is output and a multi-bit quantization result is generated.

[0030] In some examples, at least one sensitive amplifier with full margin decision capability is included, including:

[0031] The sensitive amplifier with full margin decision function is connected to the storage device of the storage unit and two reference units with different resistance values ​​in the resistance decision threshold set.

[0032] The sensitive amplifier with full margin decision function makes a decision based on the two reference units with different resistance values.

[0033] The sensitive amplifier with full margin decision function makes a decision based on the two reference cells with different resistance values. In the technical solution provided by the embodiments of this application, a multi-bit quantization method for a memory includes: receiving target data and writing the target data into a memory to obtain an analog output value; performing a first read quantization operation on the analog output value through a decision circuit to obtain a first quantization read result; performing a second read quantization operation based on the first quantization read result to obtain a second quantization read result, wherein the first quantization read result and the second quantization read result are used to make a quantization decision on the memory cell; the decision circuit is a sensitive amplifier, including at least one sensitive amplifier with full margin decision function; in the read quantization operation, the decision circuit compares the analog output value with a resistance decision threshold set, outputs a set of discrete values, and generates a multi-bit quantization result. This read method can improve the accuracy of multi-bit quantization decision operations.

[0034] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0035] Figure 1This is a schematic diagram illustrating a multi-bit quantization method for a memory, as shown in an exemplary embodiment of this application;

[0036] Figure 2 This is a schematic diagram illustrating a multi-bit quantization method for a memory, where the decision circuit used for the first read is a comparator-type sensitive amplifier, as shown in an exemplary embodiment of this application.

[0037] Figure 3a This is a schematic diagram illustrating one end of a decision circuit and a selected memory cell, as shown in an exemplary embodiment of this application.

[0038] Figure 3b This application illustrates an exemplary embodiment of a decision circuit and a selected memory cell R. data A schematic diagram showing the connection to two different reference units;

[0039] Figure 4 This is a schematic diagram illustrating an exemplary embodiment of the present application, showing that the decision circuit used for the first read in a multi-bit quantization method of a memory is a sensitive amplifier with full margin decision function;

[0040] Figure 5a This is a schematic diagram illustrating another decision circuit and selected memory cell in an exemplary embodiment of this application;

[0041] Figure 5b This is another example of a decision circuit and selected memory cell R shown in an exemplary embodiment of this application. data Connected and reference unit R REF Connection diagram. Detailed Implementation

[0042] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0043] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities can be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0044] The flowcharts shown in the accompanying drawings are merely illustrative and do not necessarily include all content and operations / steps, nor do they necessarily have to be performed in the described order. For example, some operations / steps can be broken down, while others can be combined or partially combined; therefore, the actual execution order may change depending on the specific circumstances.

[0045] It should also be noted that "multiple" as mentioned in this application refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0046] like Figure 1 As shown, Figure 1 This application illustrates a multi-bit quantization method for a memory, comprising:

[0047] S101. Receive target data and write the target data into a memory to obtain a simulated output value;

[0048] S102. The decision circuit includes at least one sensitive amplifier with full margin decision function, and compares the analog output with a set of resistance decision thresholds to realize multi-bit quantization operation.

[0049] S103. The analog output value is quantized for the first time through the decision circuit to obtain the first quantization result.

[0050] S104. Based on the first quantization reading result, a second quantization reading operation is performed to obtain the second quantization reading result. The two quantization reading operations output a set of discrete values ​​and generate a multi-bit quantization result.

[0051] The decision circuit is a sensitive amplifier, including at least one sensitive amplifier with full margin decision function. When the decision circuit performs a read quantization operation, it compares the analog output value with a set of resistance decision thresholds and outputs a set of discrete values ​​to generate the corresponding quantization result.

[0052] The multi-bit quantization method for memory is used to reduce the area and power consumption overhead of multi-bit quantization operations in circuit implementation, while improving the accuracy of multi-bit quantization decision operations. Further, it is applied to memory cell arrays. The memory cell array includes multiple memory blocks, each of which includes multiple memory cells. Each memory cell contains at least one memory device, and each memory device has two or more resistance states that can be switched between. Optionally, the different resistance states have different resistance values; optionally, the resistance states have non-volatile characteristics. By focusing on an example where the memory cell is MRAM, some exemplary embodiments of the inventive concept will now be described in detail. The MRAM can be programmed as R... P Or R AP The two resistive states represent the stored data as 0 and 1, respectively.

[0053] In some examples, receiving target data and writing the target data into a storage unit includes:

[0054] The target data is received by the control logic circuit and written into the storage unit.

[0055] In some examples, a first quantization operation is performed on the simulated output value to obtain the first quantization read result, including:

[0056] The analog output value is compared with a first decision threshold value in the resistance value decision threshold set to determine the first discrete value corresponding to the decision threshold value, and the first discrete value is used as the first quantization reading result.

[0057] The decision circuit is a sensitive amplifier.

[0058] In some examples, a second quantization operation is performed based on the first quantization read result to obtain a second quantization read result, including:

[0059] Based on the first quantization reading result, the second decision threshold value is determined from the resistance decision threshold set;

[0060] The second discrete value is determined based on the second decision threshold value, and the second discrete value is used as the result of the second quantization reading.

[0061] In some examples, before performing a first read quantization operation on the simulated output value to obtain the first quantization read result, the method further includes:

[0062] Based on one or more reference storage devices that are the same as the storage devices of the storage cell, obtain a set of reference cells with different resistance values.

[0063] When the reference unit contains more than one reference storage device, the reference storage devices have the same or different resistance values ​​and are connected in series, parallel or series-parallel configurations.

[0064] Based on the resistance value of one or more reference cells in the set of reference cells, a decision threshold value is obtained.

[0065] Based on the obtained decision threshold values, a set of resistance decision thresholds is determined.

[0066] In some examples, the decision circuit is a sensitive amplifier, wherein at least one sensitive amplifier with full margin decision capability is included, comprising:

[0067] The decision circuit includes at least one sensitive amplifier with full margin decision function;

[0068] The decision circuit performs the multiple read quantization operations.

[0069] The decision circuit performs a second quantization operation based on the first quantization result to obtain the second quantization result.

[0070] Based on the two quantization readings, a set of discrete values ​​is output and a multi-bit quantization result is generated.

[0071] In some examples, at least one sensitive amplifier with full margin decision capability is included, including:

[0072] The sensitive amplifier with full margin decision function is connected to the storage device of the storage unit and two reference units with different resistance values ​​in the resistance decision threshold set.

[0073] The sensitive amplifier with full margin decision function makes a decision based on the two reference units with different resistance values.

[0074] In some examples, both the memory device and the reference memory device are resistive memory devices, that is, the resistive memory devices have different resistance values ​​under different states, and may include MRAM based on magnetic tunnel junction devices, RRAM based on memristor devices, FRAM based on ferroelectric capacitor devices, and capacitor-free DRAM based on amorphous oxide thin film transistors, etc.

[0075] In some examples, receiving target data and writing the target data into a storage unit includes: receiving target data through a control logic circuit and writing the target data into the storage unit; wherein the control logic circuit is used to receive the target data and write the received data into the memory. And it can...

[0076] The system controls the memory cell array and the multi-bit quantizer; further, the logic control circuit determines the decision threshold selected by each stage of the sub-decision circuit of the multi-bit quantizer, and inputs the decision threshold into the sub-decision circuit; specifically, the decision threshold is selected according to the input data or the output result of the previous stage sub-decision circuit; specifically, the reference cell combination corresponding to the decision threshold is selected according to the mapping relationship, and an analog value is output to the sub-decision circuit.

[0077] Steps S102, S103, and S104 are executed by a multi-bit quantizer, which includes a set of resistance decision thresholds and a set of decision circuits.

[0078] In some examples, before performing the first quantization operation on the simulated output value to obtain the first quantization result, the method further includes: the reference cell set contains one or more reference cells; the reference cell is composed of one or more reference storage devices identical to the storage cell; when the number of reference storage devices contained in the reference cell is greater than one, the reference storage devices have the same or different resistance values ​​and are connected in series, parallel, or series-parallel configurations; the resistance value output by the reference cell has a mapping relationship with the resistance value decision threshold.

[0079] The mapping relationship is as follows: according to the mapping relationship, the simulated value of a decision threshold in the resistance decision threshold set is derived from the simulated output values ​​of several reference cells in the set of reference cells. Further, the number of decision thresholds in the decision threshold set is equal to or less than the number of reference cells in the set of reference cells.

[0080] In some examples, the resistance decision threshold set consists of one or more decision thresholds, and the method further includes: obtaining a decision threshold value based on the resistance value of one or more reference cells in the reference cell set; the resistance decision threshold set divides all resistance value ranges of the analog memory cell into multiple decision threshold regions.

[0081] This reading method requires multiple readings of the data unit when performing multi-bit quantization. That is, the analog output value stored in the storage unit is compared and quantized step by step with the decision threshold value in the resistance decision threshold set. When the analog output value is determined to be in a certain decision threshold region, a discrete value corresponding to the region is output as the result of this quantization reading.

[0082] In some examples, the decision circuit performs a first read quantization operation on the analog output value to obtain a first quantization read result, including: comparing the analog output value with decision threshold values ​​in the resistance decision threshold set, outputting a set of discrete values; determining a first discrete value based on the decision threshold values, and using the first discrete value as the first quantization read result.

[0083] In some examples, a second quantization operation is performed based on the first quantization read result to obtain a second quantization read result. This includes: determining a secondary decision threshold based on the first quantization read result; determining a second discrete value based on the secondary decision threshold; and using the second discrete value as the second quantization read result. Specifically, the decision threshold used for the second and subsequent reads is determined by the quantization read result of the previous stage decision circuit, thereby implementing a second or more read quantization operations.

[0084] The decision circuit has one or more sub-decision circuits and a sensitive amplifier; furthermore, it is necessary to perform at least two levels of decision quantization operations, each of which requires calling at least one of the sub-decision circuits and selecting at least one of the decision thresholds from the set of resistance decision thresholds; when performing the decision quantization operation, the decision circuit is connected to the memory cell and to the set of resistance decision thresholds.

[0085] In some examples, the analog output value in the storage unit and the analog value of the resistance decision threshold set can be either a current or a voltage.

[0086] In some examples, multiple sub-decision circuits can perform serial decision quantization or pipelined decision quantization operations on the analog output values ​​in the memory cells in a certain order.

[0087] In some examples, in a single-stage decision quantization operation, multiple sub-decision circuits can simultaneously perform parallel decision quantization operations on the analog output values ​​in the memory cell.

[0088] In some examples, the decision circuit invokes a sensitive amplifier for each read quantization operation, including at least one sub-decision circuit with full margin decision functionality;

[0089] As shown in Figure 3(b), in some examples, a sensitive amplifier with full margin decision function includes: the sensitive amplifier with full margin decision function is connected to the storage device of the storage cell and two reference cells with different resistance values ​​in the resistance decision threshold set.

[0090] The sensitive amplifier with full margin decision function makes decisions based on the two reference cells with different resistance values. Specifically, the analog output value in the storage cell is compared with the analog value of each reference cell in a certain order, and multiple differences are output. Further, the output result is determined to be greater than or less than the decision threshold based on the analog value of the reference cell with the smallest difference. Further, the decision threshold region where the analog output value is located is determined, and the discrete value corresponding to the region is output, that is, the full margin decision quantization operation is completed.

[0091] Optionally, the plurality of reference units may include a reference unit in the set of reference units whose output voltage value is greater than the decision threshold output voltage value and whose resistance value is the smallest, and a reference unit in the set of reference units whose output voltage value is less than the decision threshold output voltage value and whose resistance value is the largest.

[0092] Optionally, the plurality of reference units may include a reference unit in the set of reference units whose output current value is greater than the decision threshold output current value and whose resistance value is the largest, and a reference unit in the set of reference units whose output current value is less than the decision threshold output current value and whose resistance value is the smallest.

[0093] In some examples, the analog output value is first read-quantized using the comparator-type sensitive amplifier to obtain a first quantization read result; the decision threshold value used by the second decision circuit is determined by the first quantization read result, and at least one of the two read-quantization operations uses a sensitive amplifier with full margin decision function as the decision circuit. A set of discrete values ​​is output, and a multi-bit quantization result is generated.

[0094] In some examples, the analog output value is first quantized using a sensitive amplifier with full margin decision capability to obtain a first quantization result. The decision threshold value used by the second decision circuit is determined by the first quantization result, and at least one of the two quantization operations uses a sensitive amplifier with full margin decision capability as the decision circuit. Based on the two quantization results, a set of discrete values ​​is output, generating a multi-bit quantization result.

[0095] The output discrete value is characterized in that the number of output discrete values ​​is equal to or greater than the maximum number of impedance states of the storage device, including that the output discrete value can be encoded according to a certain rule; the number of output discrete values ​​determines the number of decision thresholds included in the impedance decision threshold set; and the output discrete value is equal to or greater than the power of the number of bits of the radix of the set of output quantization values.

[0096] In some examples, for an N-bit binary quantizer, the maximum number of states is 2. NThe number of judgment thresholds is equal to 2. N -1 .

[0097] In some examples, for the read method and the case where a two-bit quantizer is applied to the quantizer in the error correction code (ECC) decoder of the memory array cell, a set of analog input values ​​is encoded according to ECC before being written to the memory cell; further, before performing ECC decoding, a set of resistance decision thresholds corresponding to the ECC decoding algorithm is selected; the decision circuit of the multi-bit quantizer performs the decision quantization operation on the analog output values ​​of a set of memory cells in the memory cell array and obtains a set of discrete output values; finally, the ECC decoding algorithm is executed on the set of discrete output values ​​to obtain a set of decoded output values.

[0098] This example provides a multi-bit quantization method for a memory, comprising: receiving target data and writing the target data into the memory to obtain an analog output value; performing a first read quantization operation on the analog output value through a decision circuit to obtain a first quantization read result; performing a second read quantization operation based on the first quantization read result to obtain a second quantization read result, wherein the first quantization read result and the second quantization read result are used to make a quantization decision for the memory cell; the decision circuit is a sensitive amplifier, including at least one sensitive amplifier with full margin decision function; in the read quantization operation, the decision circuit compares the analog output value with a set of resistance decision thresholds, outputs a set of discrete values, and generates a multi-bit quantization result. Multi-bit quantization typically uses an analog-to-digital converter (ADC) as the multi-bit quantizer, which requires a large number of quantization bits and a large circuit area, resulting in higher power consumption for the operating circuit. Compared to ADC circuits, the multi-bit quantization method provided in this example uses a simpler, smaller decision circuit, fewer quantization bits, and lower power consumption, which improves the accuracy of multi-bit quantization operations and maintains higher accuracy of multi-bit quantization operations over a wide temperature range, a wide range of resistive memory device process variations, and low read margin conditions.

[0099] To better understand the present invention, this embodiment provides a more specific example;

[0100] Taking MRAM as an example, the MTJ device in an MRAM memory cell is a resistive memory device. In the high-resistivity state, the resistance of the MTJ is R. AP In the low-resistance state, the resistance of MTJ is R. PAccording to the method provided in this example, the reference cell of the MRAM uses a single MTJ device or a series-parallel combination of MTJ devices with parameters and dimensions identical to the memory cell MTJ, so that the resistance value of the resistor or resistor network combination approximates the resistance value obtained from the ideal decision threshold. When configuring the resistor or resistor network combination, the minimum number of MTJ devices should be selected to save area and ensure that the reference cell resistance value of the scheme has good tracking performance across temperature ranges and process fluctuation ranges.

[0101] When considering binary two-bit quantization, three resistor network combinations that best approximate the ideal decision threshold are selected as reference units. For the case where only a comparator-type sensitive amplifier is used as the decision circuit, this example selects the optimal three resistor network combinations as R. REF_L =R P +(R P / / R AP / / R AP ), R REF_M =2(R) P / / R AP ), and R REF_H =(R P / / R AP )+(R P / / R AP / / R AP For cases where a comparator-type sensitive amplifier and a sensitive amplifier with full margin decision function are used as the decision circuit, this example selects the optimal combination of three sets of resistor networks as R. REF_L =R P R REF_M =2(R) P / / R AP ), and R REF_H =R AP .

[0102] The selected reference cell value and the two-bit quantizer resistor decision threshold have a mapping relationship. Based on one aspect of the example, such as... Figure 2 As shown, the decision circuit used for the first read is a comparator-type sensitive amplifier (SA), such as... Figure 3a As shown. One end of the decision circuit is connected to the selected memory cell R. data One end is connected to the reference element; the other end is connected to the reference element, and the resistor network used by the reference element is R. REF_M The decision circuit converts resistance values ​​into voltage or current values ​​for comparison, thereby enabling the storage cell R to... data With reference unit R REF_M The resistance values ​​are compared, and the result is read from the OUT terminal. The second reading uses a decision circuit with a sensitive amplifier having full margin decision function, such as... Figure 3b As shown. The decision circuit and the selected memory cell Rdata It is connected to two different reference elements, one of which is R REF The selection of the reference cell is determined by the first read result, and the other reference cell uses the same reference cell as the first read, which is R. REF_M =R REF_M The reading result is obtained from the OUT terminal.

[0103] Taking the example of storing 0 data and reading 0 data. As shown in Figure 3(a), the storage unit R data =R P The first reading result was 0. As shown in Figure 3(b), the reference cell for the second reading was selected as R. REF =R REF_L 'With R REF_M '; The opposite is true if data 1 is read, R data =R AP The first reading returned 1, and the reference cell for the second reading was selected as R. REF =R REF_H 'With R REF_M The selection of the reference cell is achieved by the access transistor that selects the reference cell. The results of two readings constitute the result of two-bit quantization.

[0104] On the other hand, based on the example, such as Figure 4 As shown in Figure 5(a), the decision circuit used in the first instance is a sensitive amplifier with full margin decision function. The decision circuit and the selected memory cell R... data It is connected to two different reference elements, one of which is R. REF_L ', another reference unit is R REF_H The reading result is output from the OUT terminal. The decision circuit used for the second reading is a comparator-type sensitive amplifier, as shown in Figure 5(b). The decision circuit and the selected memory cell R... data Connected and reference unit R REF The reference cell is selected based on the first read result. The read result is output from the OUT terminal.

[0105] Taking the example of storing 0 data and reading 0 data. As shown in Figure 5(a), the storage unit R data =R P The first reading result was 0. As shown in Figure 5(b), the reference cell for the second reading was selected as R. REF =R REF_H And this serves as the decision threshold. Conversely, if data 1 is read, R... data =R AP The reference cell for the second read operation is selected as R. REF =R REF_LThis serves as the decision threshold. The results from the two readings approximate the results from two-dimensional quantization.

[0106] Based on another aspect of the example, the two-bit binary quantizer can serve as a quantizer applied in the ECC decoder of the memory array cell. Specifically, a set of analog input values ​​is binary encoded according to a selected ECC scheme before being written to the memory cell;

[0107] Furthermore, before implementing ECC decoding, a set of three resistance value decision thresholds corresponding to the ECC decoding algorithm is selected;

[0108] Furthermore, the decision circuit of the multi-bit quantizer performs the decision quantization operation on the analog output values ​​of a group of memory cells in the memory cell array, and outputs the obtained two discrete values.

[0109] Furthermore, the ECC decoding algorithm is executed on the set of output discrete values ​​to obtain a set of decoded output values.

[0110] The two-bit binary quantization method provided in this example employs a simpler, smaller decision circuit, fewer quantization bits, and lower power consumption, thereby improving the accuracy of multi-bit quantization operations. Within a wide temperature range of 233K to 400K and a TMR variation range of 70% to 120%, the resistive quantization decision threshold exhibits good tracking performance. Under conditions of TMR ≤ 90%, resistive memory device resistance fluctuation ≥ 10%, and comparator-type sensitive amplifier read margin < 3σ, the provided two-bit quantization decision circuit with full margin decision function can provide a better read accuracy than the BCH encoding / decoding scheme based on a one-bit quantization circuit under the Polar code SC decoding algorithm and SCL decoding algorithm, while the former, based on the SC decoding algorithm, has a much lower computational complexity than the latter.

[0111] Other embodiments of this application will readily conceive of by considering the specification and practicing the embodiments disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein.

[0112] The above content is merely a preferred exemplary embodiment of this application and is not intended to limit the implementation of this application. Those skilled in the art can easily make corresponding modifications or alterations based on the main concept and spirit of this application. Therefore, the scope of protection of this application should be determined by the scope of protection claimed in the claims.

Claims

1. A multi-bit quantization method for a memory, characterized in that, The multi-bit quantization method for the memory includes: Receive target data and write the target data into a memory to obtain a simulated output value; The analog output value is quantized for the first time by a decision circuit to obtain the first quantization result. A second quantization operation is performed based on the first quantization read result to obtain the second quantization read result. The first quantization read result and the second quantization read result are used to make quantization decisions on the storage unit. The decision circuit is equipped with a sensitive amplifier, which includes at least one sensitive amplifier with full margin decision function; When the decision circuit performs the read quantization operation, the decision circuit compares the analog output value with a set of resistance decision thresholds and outputs a set of discrete values ​​to generate the corresponding quantization result; The simulated output value is subjected to a first quantization operation to obtain the first quantization read result, including: The analog output value is compared with a first decision threshold value in the resistance decision threshold set to determine the first discrete value corresponding to the decision threshold value, and the first discrete value is used as the first quantization reading result. The decision circuit is a sensitive amplifier; A second quantization operation is performed based on the first quantization result to obtain the second quantization result, including: Based on the first quantization reading result, the second decision threshold value is determined from the resistance decision threshold set; A second discrete value is determined based on the second decision threshold value, and the second discrete value is used as the result of the second quantization reading. Before performing the first quantization operation on the simulated output value to obtain the first quantization result, the method further includes: Based on one or more reference storage devices that are the same as the storage devices of the storage cell, obtain a set of reference cells with different resistance values. When the reference unit contains more than one reference storage device, the reference storage devices have the same or different resistance values ​​and are connected in series, parallel or series-parallel configurations. Based on the resistance value of one or more reference cells in the set of reference cells, a decision threshold value is obtained. Based on the obtained decision threshold values, a set of resistance decision thresholds is determined.

2. The multi-bit quantization method for memory according to claim 1, characterized in that, Receiving target data and writing the target data into the storage unit includes: The target data is received by the control logic circuit and written into the storage unit.

3. The multi-bit quantization method for memory according to claim 2, characterized in that, The decision circuit is a sensitive amplifier, which includes at least one sensitive amplifier with full margin decision function, including: The decision circuit includes at least one sensitive amplifier with full margin decision function; The decision circuit performs multiple read-quantization operations; The decision circuit performs a second quantization operation based on the first quantization reading result to obtain the second quantization reading result; Based on the two quantization readings, a set of discrete values ​​is output and a multi-bit quantization result is generated.

4. The multi-bit quantization method for memory according to claim 3, characterized in that, It includes at least one sensitive amplifier with full margin decision capability, including: The sensitive amplifier with full margin decision function is connected to the storage device of the storage unit and two reference units with different resistance values ​​in the resistance decision threshold set; The sensitive amplifier with full margin decision function makes a decision based on the two reference units with different resistance values.

Images