Layout structure of data buffer circuit

Abstract

The present disclosure provides a layout structure of a data buffer circuit, which comprises a first amplification circuit module, a second amplification circuit module and an equalization decision circuit module; an output end of the first amplification circuit module is connected with an input end of the second amplification circuit module through a first group of signal lines; an adjusting output end of the equalization decision circuit module is connected with the first group of signal lines, and is used for adjusting a voltage on the first group of signal lines; the output end of the first amplification circuit module, the input end of the second amplification circuit module, the adjusting output end of the equalization decision circuit module and the first group of signal lines are arranged on the same layer. The embodiment of the present disclosure can reduce the signal line load of the small signal line.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit design technology, and more specifically, to a layout structure of a data buffer circuit. Background Technology

[0002] In high-speed circuit layout design, signal line load is a crucial consideration. Signal lines with lower loads have wider eye diagrams and better signal transmission quality, which is essential for high-speed circuits. In DRAM layout design, the data buffer circuit is the channel for data input and output, serving as a vital interface for receiving external data and reading internal data. Therefore, the load of its signal lines, i.e., the signal quality, affects the overall data read and write performance of the DRAM.

[0003] In DDR4 circuits, the data buffer circuit includes a connected first amplifier module, a second amplifier module, and an equalization decision circuit module for adjusting the input signal of the second amplifier module. Based on module partitioning, components of the same module are typically grouped together, and the signals from each circuit module are routed to the metal layer via contacts and vias. Because the contact structure has high resistance, this results in high resistance-capacitance (RC) parameters for small signal lines used for transmission. While this layout may meet signal eye diagram requirements at relatively low signal transmission speeds, it is less than ideal for high-speed transmission circuits such as LPDDR5, where the small signal propagation quality is compromised.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] The purpose of this disclosure is to provide a layout structure for a data buffer circuit that can at least partially overcome the problem of excessive load on small signal lines in high-speed circuits, which fails to meet signal quality requirements.

[0006] According to one aspect of this disclosure, a layout structure for a data buffer circuit is provided, the data buffer circuit including a first amplifier circuit module, a second amplifier circuit module, and an equalization decision circuit module; the output terminal of the first amplifier circuit module and the input terminal of the second amplifier circuit module are connected through a first set of signal lines; the adjustment output terminal of the equalization decision circuit module is connected to the first set of signal lines for adjusting the voltage on the first set of signal lines; the output terminal of the first amplifier circuit module, the input terminal of the second amplifier circuit module, the adjustment output terminal of the equalization decision circuit module, and the first set of signal lines are arranged on the same layer.

[0007] In one exemplary embodiment of this disclosure, the first amplifier circuit module includes a comparison unit and a first reset unit, wherein the comparison unit is connected to the first reset unit via a second set of signal lines; the second set of signal lines is arranged on the same layer as the first set of signal lines.

[0008] In an exemplary embodiment of this disclosure, the second set of signal lines includes a first conductor and a second conductor; the comparison unit includes a first P-type transistor and a second P-type transistor; the first reset unit includes a first N-type transistor and a second N-type transistor; the drain terminal of the first P-type transistor is electrically connected to the drain terminal of the first N-type transistor via the first conductor; the drain terminal of the second P-type transistor is electrically connected to the drain terminal of the second N-type transistor via the second conductor; the drain terminals of the first P-type transistor, the second P-type transistor, the first N-type transistor, the second N-type transistor, the first conductor, and the second conductor are arranged in the same layer.

[0009] In an exemplary embodiment of this disclosure, the equalization decision circuit module includes a first decision feedback unit and a second decision feedback unit; the adjustment output terminal includes a first adjustment output terminal connected to the output of the first decision feedback unit and a second adjustment output terminal connected to the output of the second decision feedback unit; the first group of signal lines includes a first sub-signal line and a second sub-signal line, the first sub-signal line being connected to the first conductor and the second sub-signal line being connected to the second conductor; the first adjustment output terminal is electrically connected to the first sub-signal line via a third conductor, and the second adjustment output terminal is electrically connected to the second sub-signal line via a fourth conductor; the first adjustment output terminal, the second adjustment output terminal, the third conductor, the fourth conductor, and the first group of signal lines are arranged on the same layer.

[0010] In one exemplary embodiment of this disclosure, the second amplifier circuit module includes an input unit, a latch unit, and a second reset unit; the input unit is connected to the first set of signal lines.

[0011] In one exemplary embodiment of this disclosure, the input unit includes a third N-type transistor and a fourth N-type transistor; the latch unit includes a third P-type transistor, a fourth P-type transistor, a fifth N-type transistor, and a sixth N-type transistor.

[0012] In an exemplary embodiment of this disclosure, the latching unit is internally connected by a first lead and a second lead, wherein the drain terminal of the third P-type transistor, the drain terminal of the fifth N-type transistor, the gate terminal of the fourth P-type transistor, and the gate terminal of the sixth N-type transistor are connected by the first lead; the gate terminal of the third P-type transistor, the gate terminal of the fifth N-type transistor, the drain terminal of the fourth P-type transistor, and the drain terminal of the sixth N-type transistor are connected by the second lead.

[0013] In an exemplary embodiment of this disclosure, the first lead and the second lead are located on different layers from the first group of signal lines. The first lead and the second lead each include a first conductive portion and a second conductive portion. The first conductive portion is located in a metal layer, and the second conductive portion is located in a via. The second conductive portion is used to connect the gate terminal, the drain terminal, and the first conductive portion.

[0014] In one exemplary embodiment of this disclosure, the first amplifier circuit module, the second amplifier circuit module, and the equalization decision circuit module are arranged along a first axis; the first P-type transistor and the second P-type transistor are arranged symmetrically along a second axis; the first N-type transistor and the second N-type transistor are arranged symmetrically along the second axis; the first decision feedback unit and the second decision feedback unit are arranged symmetrically along the second axis; the third N-type transistor and the fourth N-type transistor are arranged symmetrically along the second axis; the third P-type transistor and the fourth P-type transistor are arranged symmetrically along the second axis; the fifth N-type transistor and the sixth N-type transistor are arranged symmetrically along the second axis; and the second axis is perpendicular to the first axis.

[0015] In one exemplary embodiment of this disclosure, the third P-type transistor and the fifth N-type transistor are arranged symmetrically along the second axis, the first P-type transistor and the third N-type transistor are arranged symmetrically along the second axis, the first decision feedback unit and the first N-type transistor are arranged symmetrically along the second axis, the fourth P-type transistor and the sixth N-type transistor are arranged symmetrically along the second axis, the second P-type transistor and the fourth N-type transistor are arranged symmetrically along the second axis, and the second decision feedback unit and the second N-type transistor are arranged symmetrically along the second axis.

[0016] In one exemplary embodiment of this disclosure, the second reset unit includes a reset transistor, a first terminal of which is connected to the drain of the third N-type transistor and the source of the fifth N-type transistor, a second terminal of which is connected to the drain of the fourth N-type transistor and the source of the sixth N-type transistor, and a control terminal of which is used to receive a reset signal.

[0017] In one exemplary embodiment of this disclosure, the second amplifier circuit module further includes a first output transistor and a second output transistor, wherein the first output transistor is connected to the first lead and the second output transistor is connected to the second lead.

[0018] In one exemplary embodiment of this disclosure, the first amplifier circuit module, the second amplifier circuit module, and the equalization decision circuit module are arranged along a first axis, and the first output transistor and the second output transistor are arranged symmetrically along a second axis, which is perpendicular to the first axis.

[0019] In one exemplary embodiment of this disclosure, the first amplifier circuit module, the second amplifier circuit module, and the equalization decision circuit module are all connected to the power supply module, and the power supply module, the first amplifier circuit module, the second amplifier circuit module, and the equalization decision circuit module are arranged along the first axis.

[0020] In one exemplary embodiment of this disclosure, the power module includes a power supply unit and a clock unit, the power supply unit and the clock unit being arranged along the first axis, and the clock unit being connected to the equalization decision circuit module.

[0021] This embodiment of the disclosure reduces the length of the signal lines by arranging the output terminals of each module in the data buffer circuit and the signal lines connecting the output terminals of each module on the same layer, thereby reducing the load on the signal lines and optimizing the signal eye diagram. Simultaneously, since the signal lines are arranged on the same layer as the output terminals of each module, there is no need for wiring on the metal layer, reducing the wiring area of ​​the metal layer and thus reducing the overall chip area.

[0022] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0023] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0024] Figure 1 This is a schematic diagram of the layout structure of the data buffer circuit in an exemplary embodiment of this disclosure.

[0025] Figure 2 This is a schematic diagram of a first amplifier circuit module in one embodiment of the present disclosure.

[0026] Figure 3 This is a schematic diagram of the second group of signal lines in one embodiment of this disclosure.

[0027] Figure 4 This is a schematic diagram of an equalization decision circuit module in one embodiment of this disclosure.

[0028] Figure 5 This is a schematic diagram of the second amplifier circuit module in one embodiment of this disclosure.

[0029] Figure 6 This is a schematic diagram of a second amplifier circuit module in another embodiment of this disclosure.

[0030] Figure 7 This is a schematic diagram of the component layout in one embodiment of the present disclosure.

[0031] Figure 8 This is one embodiment of the present disclosure. Figure 7 The diagram shows a top view of the signal traces corresponding to the component layout.

[0032] Figure 9 This is one embodiment of the present disclosure. Figure 7 A perspective 3D schematic diagram of the signal line routing corresponding to the component layout shown.

[0033] Figure 10 This is a schematic diagram of the component layout in another embodiment of this disclosure.

[0034] Figure 11 This is a comparative schematic diagram of the layout structure of this application and the layout structure of related technologies. Detailed Implementation

[0035] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this disclosure more comprehensive and complete, and to fully convey the concept of the example embodiments to those skilled in the art. The described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a full understanding of embodiments of this disclosure. However, those skilled in the art will recognize that the technical solutions of this disclosure can be practiced with one or more of the specific details omitted, or other methods, components, apparatus, steps, etc., can be employed. In other instances, well-known technical solutions are not shown or described in detail to avoid obscuring various aspects of this disclosure.

[0036] Furthermore, the accompanying drawings are merely illustrative of this disclosure, and the same reference numerals in the drawings denote the same or similar parts, thus repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0037] The exemplary embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0038] Figure 1 This is a schematic diagram of the layout structure of the data buffer circuit in an exemplary embodiment of this disclosure.

[0039] refer to Figure 1 The layout structure 100 of the data buffer circuit may include:

[0040] The first amplifier circuit module 1, the second amplifier circuit module 2, and the equalization decision circuit module 3 are connected. The output terminal of the first amplifier circuit module 1 and the input terminal of the second amplifier circuit module 2 are connected through a first set of signal lines S1. The adjustment output terminal of the equalization decision circuit module 3 is connected to the first set of signal lines S1 and is used to adjust the voltage on the first set of signal lines S1. The output terminal of the first amplifier circuit module 1, the input terminal of the second amplifier circuit module 2, the adjustment output terminal of the equalization decision circuit module 3, and the first set of signal lines S1 are arranged on the same layer.

[0041] This embodiment of the disclosure reduces the length of the signal lines by arranging the output terminals of each module in the data buffer circuit and the signal lines connecting the output terminals of each module on the same layer, thereby reducing the load on the signal lines and optimizing the signal eye diagram. Simultaneously, since the signal lines are arranged on the same layer as the output terminals of each module, there is no need for routing on the metal wiring layer (Metel1), reducing the wiring area of ​​the metal wiring layer and thus reducing the overall chip area.

[0042] Figure 2 This is a schematic diagram of a first amplifier circuit module in one embodiment of the present disclosure.

[0043] refer to Figure 2 In one embodiment, the first amplifier circuit module 1 includes a comparison unit 11 and a first reset unit 12. The comparison unit 11 is connected to the first reset unit 12 through a second set of signal lines S2. The second set of signal lines S2 is arranged on the same layer as the first set of signal lines S1.

[0044] By arranging the comparison unit 11, the first reset unit 12, and the second set of signal lines S2 connecting them on the same layer inside the first amplifier circuit module 1, the internal trace length of the first amplifier circuit module 1 can be reduced, the signal line load inside the module can be reduced, the wiring of the first amplifier circuit module 1 on the metal layer can be reduced, and thus the layout area of ​​the first amplifier circuit module 1 can be reduced, and the overall area of ​​the chip can be reduced.

[0045] Meanwhile, by arranging the internal signal lines of the first amplifier circuit module 1 and the first group of signal lines S1 on the same layer, the internal signal line load of the first amplifier circuit 1 can be reduced, while the connection line length between the first amplifier circuit 1 and the first group of signal lines S1 can be reduced, thereby reducing the signal line load of the first group of signal lines S1.

[0046] Figure 3 This is a schematic diagram of the second group of signal lines in one embodiment of this disclosure.

[0047] refer to Figure 3 In one embodiment, the second set of signal lines S2 includes a first conductor S21 and a second conductor S22.

[0048] The comparison unit 11 includes a first P-type transistor P1 and a second P-type transistor P2. The first reset unit 12 includes a first N-type transistor N1 and a second N-type transistor N2. The drain terminal of the first P-type transistor P1 is electrically connected to the drain terminal of the first N-type transistor N1 through a first wire S21. The drain terminal of the second P-type transistor P2 is electrically connected to the drain terminal of the second N-type transistor N2 through a second wire S22. The drain terminals of the first P-type transistor P1, the second P-type transistor P2, the first N-type transistor N1, the second N-type transistor N2, the first wire S21, and the second wire S22 are arranged on the same layer.

[0049] exist Figure 3 In the illustrated embodiment, the sources of both the first P-type transistor P1 and the second P-type transistor P2 are connected to the power supply module 4, and the drains of both the first N-type transistor N1 and the second N-type transistor N2 are connected to zero potential VSS. In other embodiments of this disclosure, the internal circuitry of the first amplifier circuit module 1 and the specific connections of the second signal line S2 may also have other forms, and this disclosure is not limited thereto.

[0050] Figure 4 This is a schematic diagram of an equalization decision circuit module in one embodiment of this disclosure.

[0051] refer to Figure 4 ,exist Figure 3 Based on the embodiment shown, the first amplifier circuit module 1 has two output terminals. At this time, the equalization decision circuit module 3 may include a first decision feedback unit 31, a second decision feedback unit 32, and an adjustment output terminal 33. The adjustment output terminal 33 includes a first adjustment output terminal 331 connected to the output of the first decision feedback unit 31 and a second adjustment output terminal 332 connected to the output of the second decision feedback unit 32.

[0052] The first group of signal lines S2 includes a first sub-signal line S11 and a second sub-signal line S12. The first sub-signal line S11 is connected to the first conductor S21, and the second sub-signal line S12 is connected to the second conductor S22. The first sub-signal line S11 and the second sub-signal line S12, as well as the first conductor S21 and the second conductor S22, are all disposed on the same layer as the drain terminals of the first P-type transistor P1, the second P-type transistor P2, the first N-type transistor N1, and the second N-type transistor N2.

[0053] The first adjustment output terminal 331 is electrically connected to the first sub-signal line S11 through the third wire S31, and the second adjustment output terminal 332 is electrically connected to the second sub-signal line S12 through the fourth wire S32. The first adjustment output terminal 331, the second adjustment output terminal 332, the third wire S31, the fourth wire S32 and the first group of signal lines S1 are arranged on the same layer.

[0054] By arranging the connection between the equalization decision circuit module 3 and the first group of signal lines S1 on the same layer as the first group of signal lines S2 and the second group of signal lines S2, the connection load between modules can be reduced, and the connection between modules can be shortened, further reducing the chip area.

[0055] Figure 5 This is a schematic diagram of the second amplifier circuit module in one embodiment of this disclosure.

[0056] refer to Figure 5 In one embodiment, the second amplifier circuit module 2 includes an input unit 21, a latch unit 22, and a second reset unit 23. The input unit 21 is connected to the first group of signal lines S1.

[0057] The input unit 21 includes a third N-type transistor N3 and a fourth N-type transistor N4, and the latch unit 22 includes a third P-type transistor P3, a fourth P-type transistor P4, a fifth N-type transistor N5, and a sixth N-type transistor N6.

[0058] The latch unit 22 is internally connected by a first lead A1 and a second lead A2. The drain terminals of the third P-type transistor P3, the fifth N-type transistor N5, the gate terminals of the fourth P-type transistor P4, and the sixth N-type transistor N6 are connected by the first lead A1. The gate terminals of the third P-type transistor P3, the fifth N-type transistor N5, the fourth P-type transistor P4, and the sixth N-type transistor N6 are connected by the second lead A2.

[0059] The first lead A1 and the second lead A2 are also known as high-signal lines, used to transmit high-power data output signals.

[0060] Figure 6 This is a schematic diagram of a second amplifier circuit module in another embodiment of this disclosure.

[0061] refer to Figure 6 In one embodiment, the second amplifier circuit module 2 further includes a first output transistor OUT and a second output transistor OUTN. The first output transistor OUT is connected to the first lead A1, and the second output transistor OUTN is connected to the second lead A2. The first output transistor OUT serves as the first output terminal of the data buffer circuit, used to output a data signal; the first output transistor OUT also serves as the second output terminal of the data buffer circuit, used to output an inverted signal of the data signal.

[0062] The gate of the third N-type transistor N3 is connected to the first sub-signal line S11, and the gate of the fourth N-type transistor N4 is connected to the second sub-signal line S12.

[0063] The second reset unit 23 may include a reset transistor M. The first terminal of the reset transistor M is connected to the drain of the third N-type transistor N3 and the source of the fifth N-type transistor N5. The second terminal of the reset transistor M is connected to the drain of the fourth N-type transistor N4 and the source of the sixth N-type transistor N6. The control terminal of the reset transistor M is used to receive the reset signal Reset.

[0064] Figure 7 This is a schematic diagram of the component layout in one embodiment of the present disclosure.

[0065] Figure 7 The component layout shown can correspond to Figure 6 The illustrated embodiment.

[0066] refer to Figure 7 In this embodiment of the present disclosure, the first P-type transistor P1 and the second P-type transistor P2 in the comparison unit 11 are arranged symmetrically along the second axis (Y-axis), the first N-type transistor N1 and the second N-type transistor N2 in the first reset unit 12 are arranged symmetrically along the second axis, the first decision feedback unit 331 and the second decision feedback unit 332 in the equalization decision circuit module 3 are arranged symmetrically along the second axis, the third N-type transistor N3 and the fourth N-type transistor N4 in the input unit 21 are arranged symmetrically along the second axis, the third P-type transistor P3 and the fourth P-type transistor P4 in the latch unit 22 are arranged symmetrically along the second axis, the fifth N-type transistor N5 and the sixth N-type transistor N6 are arranged symmetrically along the second axis, and the second axis (Y-axis) is perpendicular to the first axis (X-axis).

[0067] Furthermore, in Figure 7 In the illustrated embodiment, the components of the first amplifier circuit module 1, the second amplifier circuit module 2, and the equalization decision circuit module 3 are arranged in two parallel rows along the first axis (X-axis). Specifically, in the direction of the first axis, the third P-type transistor P3 and the fifth N-type transistor N5 can be arranged symmetrically along the first axis, the first P-type transistor P1 and the third N-type transistor N3 can be arranged symmetrically along the first axis, the first decision feedback unit 331 and the first N-type transistor N1 can be arranged symmetrically along the first axis, the fourth P-type transistor P4 and the sixth N-type transistor N6 can be arranged symmetrically along the first axis, the second P-type transistor P2 and the fourth N-type transistor N4 can be arranged symmetrically along the first axis, and the second decision feedback unit 332 and the second N-type transistor N2 can be arranged symmetrically along the first axis.

[0068] The first output transistor OUT and the second output transistor OUTN are arranged symmetrically along the first axis (X-axis). By placing the first output transistor OUT and the second output transistor OUTN on the axis of symmetry, and by placing the four transistors corresponding to the latch module 23 (the third P-type transistor P3, the fourth P-type transistor P4, the fifth N-type transistor N5, and the sixth N-type transistor N6) close to the axis of symmetry (Y-axis), the length of the first lead A1 and the second lead A2 can be shortened, reducing the load on the large signal lines.

[0069] exist Figure 7 In the illustrated embodiment, the components are arranged in a centralized and symmetrical layout according to their connection relationships, rather than according to the functional modules to which they belong. This allows components / functional sub-units with direct connections to be placed close together, thereby providing conditions for the implementation of same-layer wiring.

[0070] Figure 7 The symmetry shown in the embodiments is merely an example. In practical applications, those skilled in the art can adjust the symmetry and relative positions of the components according to the actual types and quantities of components used, and the layout area occupied by the components, as long as it is compatible with... Figure 7 As in the illustrated embodiment, components / functional units with direct connections can be arranged in a centralized manner.

[0071] Figure 8 This is one embodiment of the present disclosure. Figure 7 The diagram shows a top view of the signal traces corresponding to the component layout.

[0072] refer to Figure 8 When the components in the data buffer circuit follow the instructions... Figure 7 When arranged symmetrically along the Y-axis as shown, the first N-type transistor N1, the first P-type transistor P1, the first decision feedback unit 331, the third N-type transistor N3, the fifth N-type transistor N5, and the third P-type transistor P3, which are connected to the first sub-signal line S11, are arranged in a concentrated manner. The first sub-signal line S11 can be set between them, so as to realize the connection of multiple components / functional units with a shorter distance.

[0073] Similarly, the second N-type transistor N2, the second P-type transistor P2, the second decision feedback unit 332, the fourth N-type transistor N4, the sixth N-type transistor N6, and the fourth P-type transistor P4, which are connected together to the second sub-signal line S12, are arranged in a concentrated manner, and the second sub-signal line S12 can be set between them to achieve the connection of multiple components / functional units with a shorter distance.

[0074] The distances between signal lines of each component, such as the distances between the first and third conductors and the first sub-signal line S11, and the distances between the second and fourth conductors and the second sub-signal line S12, can also be reduced.

[0075] The third P-type transistor P3, the fourth P-type transistor P4, the fifth N-type transistor N5, the sixth N-type transistor N6, the first output transistor OUT, and the second output transistor OUTN are arranged in a concentrated manner, which can make the first lead A1 and the second lead A2 short and straight, so that even if they are arranged through layers, they will not have a large load.

[0076] Figure 9 This is one embodiment of the present disclosure. Figure 7 A perspective 3D schematic diagram of the signal line routing corresponding to the component layout shown. Figure 9 Used to demonstrate the extension and connection relationship of the first sub-signal line S11 and the second sub-signal line S12 in the direction perpendicular to the paper.

[0077] refer to Figure 9 Comparison Figure 7 and Figure 8 In one embodiment, the terminals of the first sub-signal line S11, the second sub-signal line S12, the first N-type transistor N1, the first P-type transistor P1, the first decision feedback unit 331, the third N-type transistor N3, the fifth N-type transistor N5, the third P-type transistor P3, the second N-type transistor N2, the second P-type transistor P2, the second decision feedback unit 332, the fourth N-type transistor N4, the sixth N-type transistor N6, and the fourth P-type transistor P4 are all located on the same layer, namely the first metal layer 91 (Metal 0 layer), eliminating the need for layer crossings, thus greatly reducing the signal line length and lowering the signal line load. A first insulating layer 92 is formed on the first metal layer 91, which is used to isolate different metal layers.

[0078] The first lead A1 and the second lead A2 are located on different layers from the first group of signal lines S1. Both the first lead A1 and the second lead A2 include first conductive portions A11 and A21, and second conductive portions A12 and A22. The first conductive portions A11 and A21 are located in the second metal layer 94, and the second conductive portions A12 and A22 are located in vias formed in the first insulating layer 92. The second conductive portions A12 and A22 are used to connect the gate terminals and drain terminals of each transistor to the first conductive portions A11 and A21. A second insulating layer 93 is formed on the second metal layer 94 to provide an isolation structure for the second metal layer 94.

[0079] exist Figure 9 In the illustrated embodiment, each transistor is represented by a MOS structure. Each MOS structure includes three terminals: a source terminal, a gate terminal, and a drain terminal, with the gate terminal located in the middle. All three terminals are located on the first metal layer 91 (Metal0). Figure 9This is only a three-dimensional perspective diagram and is not intended to limit the actual spatial relationship between the layers. For example, the first sub-signal line S11 and the second sub-signal line S12 are not higher than the terminals of each transistor, but are located on the same horizontal plane as the terminals in the first metal layer 91. The same applies to other layers.

[0080] The first sub-signal line S11 and the second sub-signal line S12 are located in the first metal layer 91 (Metal0 layer), and have relatively small resistance and capacitance parameters (RC), which can still meet the signal quality requirements at the 6400M transmission rate of LPDDR5. To clearly illustrate the technical effects of this application, Figure 9 The first sub-signal line S11 and the second sub-signal line S12 are not shown in a straight-line cross-section. You can imagine that the cross-section is cut along a broken line in the top view and then viewed from the side.

[0081] Furthermore, in order to clearly illustrate the structure of the first sub-signal line S11 and the second sub-signal line S12 on the same diagram, Figure 9 The location of the MOS transistors in the diagram is for illustrative purposes only. Figure 9 The MOS in it is not with Figure 7 Each transistor in the array corresponds one-to-one, and the correspondence is only based on their centrally located positions, such as... Figure 9 The range of MOS transistors enclosed in curly braces.

[0082] Depend on Figure 9 As can be seen, the first lead A1 and the second lead A2 are located on the Metal1 layer, which is the metal layer where routing is normally performed. Due to the interleaved connection of the first lead A1 and the second lead A2, routing on the same layer is not possible.

[0083] Figure 10 This is a schematic diagram of the component layout in another embodiment of this disclosure.

[0084] refer to Figure 10 In one embodiment of this disclosure, the first amplifier circuit module 1, the second amplifier circuit module 2, and the equalization decision circuit module 3 are all connected to the power supply module 4, and the power supply module 4, the first amplifier circuit module 1, the second amplifier circuit module 2, and the equalization decision circuit module 3 are arranged along the first axis (X-axis).

[0085] The power module 4 includes a power supply unit 41 and a clock unit 42, which are arranged along the first axis. The clock unit is connected to the equalization decision circuit module 3.

[0086] Figure 11 This is a comparative schematic diagram of the layout structure of this application and the layout structure of related technologies.

[0087] refer to Figure 11 In DDR4, with Figure 6The layout structure 1100 corresponding to the same circuit is shown in the figure. The two transistors P1 and P2 of the comparison unit 11 are arranged together symmetrically along the X-axis. The two functional units 331 and 332 of the equalization decision circuit module 3 are arranged together symmetrically along the X-axis. The two transistors N1 and N2 of the reset unit 12 are arranged together symmetrically along the X-axis. The two transistors N3 and N4 of the input unit 21 are arranged together symmetrically along the X-axis. The four transistors N5, N6, P3, and P4 of the latch unit 22 are arranged together symmetrically along the X-axis. The first output transistor OUT, the second output transistor OUTN, and the clock unit 42 are arranged separately.

[0088] from Figure 11 As can be seen from the comparison diagram, from a top-down perspective, the layout structure 1000 shown in this embodiment occupies a smaller overall area. Moreover, the transistors connected to the same sub-signal lines are arranged in a concentrated manner, so that the sub-signal lines S11 and S12 can be arranged in the same layer with multiple transistors that have a direct connection relationship with them, which greatly shortens the signal line length and improves the signal quality.

[0089] After eye diagram verification testing, the eye diagram width of the output signal in layout structure 1000 is significantly greater than that of the output signal in layout structure 1100.

[0090] This embodiment of the disclosure reduces the length of the signal lines by arranging the output terminals of each module in the data buffer circuit and the signal lines connecting the output terminals of each module on the same layer, thereby reducing the load on the signal lines and optimizing the signal eye diagram. Simultaneously, since the signal lines are arranged on the same layer as the output terminals of each module, there is no need for wiring on the metal layer, reducing the wiring area of ​​the metal layer and thus reducing the overall chip area.

[0091] It should be noted that although several modules or units for the device used to perform actions have been mentioned in the detailed description above, this division is not mandatory. In fact, according to embodiments of this disclosure, the features and functions of two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided and embodied by multiple modules or units.

[0092] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and concept of this disclosure are indicated by the claims.

Claims

1. A layout structure of a data buffer circuit, the data buffer circuit comprising a first amplification circuit module, a second amplification circuit module, and an equalization decision circuit module; the output terminal of the first amplification circuit module and the input terminal of the second amplification circuit module are connected via a first set of signal lines; the adjustment output terminal of the equalization decision circuit module is connected to the first set of signal lines for adjusting the voltage on the first set of signal lines; characterized in that, The output terminal of the first amplifier circuit module, the input terminal of the second amplifier circuit module, the adjustment output terminal of the equalization decision circuit module, and the first group of signal lines are arranged on the same layer. The second amplifier circuit module includes an input unit, a latch unit, and a second reset unit; the input unit is connected to the first group of signal lines. The input unit includes a third N-type transistor and a fourth N-type transistor; the latch unit includes a third P-type transistor, a fourth P-type transistor, a fifth N-type transistor, and a sixth N-type transistor; The latching unit is internally connected by a first lead and a second lead. The drain terminal of the third P-type transistor, the drain terminal of the fifth N-type transistor, the gate terminal of the fourth P-type transistor, and the gate terminal of the sixth N-type transistor are connected by the first lead. The gate terminals of the third P-type transistor, the gate terminals of the fifth N-type transistor, the drain terminals of the fourth P-type transistor, and the drain terminals of the sixth N-type transistor are connected by the second lead.

2. The layout structure of the data buffer circuit as described in claim 1, characterized in that, The first amplifier circuit module includes a comparison unit and a first reset unit. The comparison unit is connected to the first reset unit through a second set of signal lines. The second set of signal lines is arranged on the same layer as the first set of signal lines.

3. The layout structure of the data buffer circuit as described in claim 2, characterized in that, The second group of signal lines includes a first conductor and a second conductor; The comparison unit includes a first P-type transistor and a second P-type transistor; The first reset unit includes a first N-type transistor and a second N-type transistor; The drain terminal of the first P-type transistor is electrically connected to the drain terminal of the first N-type transistor via a first wire; the drain terminal of the second P-type transistor is electrically connected to the drain terminal of the second N-type transistor via a second wire. The drain terminals of the first P-type transistor, the second P-type transistor, the first N-type transistor, the second N-type transistor, the first wire, and the second wire are arranged in the same layer.

4. The layout structure of the data buffer circuit as described in claim 3, characterized in that, The equalization decision circuit module includes a first decision feedback unit and a second decision feedback unit. The adjustment output terminal includes a first adjustment output terminal connected to the output of the first decision feedback unit and a second adjustment output terminal connected to the output of the second decision feedback unit; The first group of signal lines includes a first sub-signal line and a second sub-signal line, wherein the first sub-signal line is connected to the first conductor and the second sub-signal line is connected to the second conductor; The first adjustment output terminal is electrically connected to the first sub-signal line via a third wire, and the second adjustment output terminal is electrically connected to the second sub-signal line via a fourth wire; The first adjustment output terminal, the second adjustment output terminal, the third wire, and the fourth wire are arranged in the same layer as the first group of signal lines.

5. The layout structure of the data buffer circuit as described in claim 1, characterized in that, The first lead and the second lead are located on different layers from the first group of signal lines. Both the first lead and the second lead include a first conductive part and a second conductive part. The first conductive part is located in a metal layer, and the second conductive part is located in a via. The second conductive part is used to connect the gate terminal, the drain terminal, and the first conductive part.

6. The layout structure of the data buffer circuit as described in claim 4, characterized in that, The first amplifier circuit module, the second amplifier circuit module, and the equalization decision circuit module are arranged along a first axis. The first P-type transistor and the second P-type transistor are arranged symmetrically along a second axis. The first N-type transistor and the second N-type transistor are arranged symmetrically along the second axis. The first decision feedback unit and the second decision feedback unit are arranged symmetrically along the second axis. The third N-type transistor and the fourth N-type transistor are arranged symmetrically along the second axis. The third P-type transistor and the fourth P-type transistor are arranged symmetrically along the second axis. The fifth N-type transistor and the sixth N-type transistor are arranged symmetrically along the second axis. The second axis is perpendicular to the first axis.

7. The layout structure of the data buffer circuit as described in claim 6, characterized in that, The third P-type transistor and the fifth N-type transistor are arranged symmetrically along the second axis, the first P-type transistor and the third N-type transistor are arranged symmetrically along the second axis, the first decision feedback unit and the first N-type transistor are arranged symmetrically along the second axis, the fourth P-type transistor and the sixth N-type transistor are arranged symmetrically along the second axis, the second P-type transistor and the fourth N-type transistor are arranged symmetrically along the second axis, and the second decision feedback unit and the second N-type transistor are arranged symmetrically along the second axis.

8. The layout structure of the data buffer circuit as described in claim 1, characterized in that, The second reset unit includes a reset transistor. The first terminal of the reset transistor is connected to the drain of the third N-type transistor and the source of the fifth N-type transistor. The second terminal of the reset transistor is connected to the drain of the fourth N-type transistor and the source of the sixth N-type transistor. The control terminal of the reset transistor is used to receive a reset signal.

9. The layout structure of the data buffer circuit as described in claim 1, characterized in that, The second amplifier circuit module further includes a first output transistor and a second output transistor, wherein the first output transistor is connected to the first lead and the second output transistor is connected to the second lead.

10. The layout structure of the data buffer circuit as described in claim 9, characterized in that, The first amplifier circuit module, the second amplifier circuit module, and the equalization decision circuit module are arranged along a first axis, and the first output transistor and the second output transistor are arranged symmetrically along a second axis, which is perpendicular to the first axis.

11. The layout structure of the data buffer circuit as described in claim 6, characterized in that, The first amplifier circuit module, the second amplifier circuit module, and the equalization decision circuit module are all connected to the power supply module, and the power supply module, the first amplifier circuit module, the second amplifier circuit module, and the equalization decision circuit module are arranged along the first axis.

12. The layout structure of the data buffer circuit as described in claim 11, characterized in that, The power module includes a power supply unit and a clock unit, which are arranged along the first axis. The clock unit is connected to the equalization decision circuit module.

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