A chip clock calibration method, apparatus and circuit

Abstract

This invention relates to the field of chip design technology and discloses a chip clock calibration method, apparatus, and circuit, aiming to solve the problems of reliance on external equipment and long calibration times in existing chip clock calibration technologies. The method includes: receiving a calibration start command; generating an on-chip clock based on an initial calibration codeword; determining the relationship between the on-chip clock frequency and a standard frequency based on a reference clock to obtain a decision result; updating the calibration codeword using a binary search method according to the decision result; repeating the above steps until a preset condition is met, and storing the final calibration codeword in a non-volatile storage medium. This application achieves autonomous frequency determination and rapid calibration of the chip through an on-chip integrated frequency decision circuit and calibration codeword search circuit. The binary search method reduces the number of calibrations to logarithmic levels, significantly shortening the calibration time, reducing dependence on external testing equipment, facilitating mass production testing of the chip, and reducing production costs.

Description

Technical Field

[0001] This invention relates to the field of chip design technology, and in particular to a chip clock calibration method, apparatus and circuit. Background Technology

[0002] In modern electronic devices, the clock signal is the "heart" of the system, and its stability and accuracy directly determine the performance and reliability of the entire electronic system. With the booming development of the Internet of Things, smart homes, wearable devices, automotive electronics, and industrial control, chips, as the core control units of these devices, have widely adopted integrated clock generation circuits (such as RC oscillators). For example, in low-cost consumer electronics, to reduce material costs and simplify peripheral circuit design, manufacturers commonly use chip-embedded RC oscillators instead of external crystal oscillators to provide clock sources for functional modules such as MCUs, communication interfaces (such as UART, I2C, SPI), and timers. In automotive electronics, the vehicle's ECU (Electronic Control Unit) has stringent requirements for clock stability; any frequency deviation can lead to communication failures or control timing errors, thereby causing safety issues. Furthermore, in industrial automation control, precise clock synchronization is crucial for data acquisition, motor control, and other processes. Therefore, ensuring the accuracy of the chip's internal clock frequency is a prerequisite for the normal operation of various electronic terminal products and an indispensable part of the entire chip process, from design and production to final application.

[0003] However, in actual production and application, precise control of the internal clock frequency of a chip faces many technical challenges:

[0004] First, due to inherent deviations in semiconductor manufacturing processes, even chips from the same batch and at different locations on the same wafer will have significant differences in the actual frequency of their internal oscillators. This process deviation causes the nominal frequency of the chip at the time of manufacture to be inconsistent with the actual frequency. If no calibration is performed, it will directly lead to a series of problems such as incorrect communication baud rate, inaccurate timing, and increased power consumption.

[0005] Secondly, existing clock calibration technologies generally rely on external equipment. In traditional chip production testing, calibration is typically performed using a traversal method: testers use an external test machine or host computer to sequentially write different calibration (TRIM) values ​​to the chip, then use a high-precision frequency meter to measure the clock output frequency after each write, compare the measured value with the target frequency, and finally select the TRIM value that minimizes the frequency error and solidify it into the chip's non-volatile memory. This calibration method places extremely high demands on the accuracy and speed of the test equipment, and during the calibration process, the external equipment needs to conduct multiple serial communications with the chip (such as through I2C or SPI interfaces), resulting in excessively long calibration time for a single chip. In large-scale mass production scenarios, this inefficient calibration method becomes a bottleneck in production capacity and significantly increases testing costs. Furthermore, this method's strong dependence on external equipment means that the chip cannot be recalibrated autonomously in subsequent application scenarios (such as system online upgrades or frequency drift after aging), lacking flexibility.

[0006] Finally, in existing technologies, codeword search strategies are mostly linear search or full range traversal, which are inefficient. When the calibration codeword bit width is large (such as 8 bits or 10 bits), it is necessary to try hundreds or even thousands of times to find the optimal value, which further exacerbates the problem of long calibration time.

[0007] Therefore, those skilled in the art urgently need a circuit that can be integrated inside a chip and automatically complete frequency determination without relying on complex external testing equipment, as well as an intelligent search mechanism that can quickly lock in the optimal calibration value. Summary of the Invention

[0008] The core technical problems solved by this invention are: first, the calibration process heavily relies on external testing equipment, making it impossible to achieve independent chip calibration, resulting in high testing costs and poor flexibility; second, the search strategies (such as traversal methods) used in the calibration process are inefficient, resulting in excessively long calibration time for a single chip, making it difficult to meet the testing efficiency requirements of large-scale mass production.

[0009] For those skilled in the art, solving the aforementioned core problems is not only a technological improvement in chip testing engineering, but also a significant leap from "manufacturing and testing-oriented" to "autonomous and intelligent-oriented." It directly relates to the chip's mass production cost, production efficiency, environmental adaptability, and system reliability. Those skilled in the art urgently need a technical solution capable of on-chip autonomous frequency decision-making and rapid convergence of calibration codewords to break free from the constraints of expensive external equipment, overcome testing capacity bottlenecks, and endow the chip with adaptive capabilities throughout its entire lifecycle. This invention is based on this urgent need, providing a complete and efficient solution through the deep integration of an on-chip closed-loop self-calibration architecture, a bidirectional frequency error determination mechanism, and a binary hardware search method; its importance is self-evident. This invention, while reducing or eliminating dependence on external equipment, enables the chip to autonomously complete clock frequency calibration and significantly shortens calibration time, thereby reducing production costs, improving production efficiency, and endowing the chip with adaptive capabilities in complex application environments.

[0010] In order to solve the above-mentioned core technical problems, this invention designs a chip clock calibration method, device and circuit. Its purpose is to realize automatic frequency comparison and rapid convergence of calibration codewords through hardware logic or simple state machine, thereby transforming the calibration process from the traditional "external intervention type" to "chip autonomous type".

[0011] The main contents of this invention include: integrating a frequency decision circuit inside the chip, using a single external reference clock source as a benchmark to autonomously determine the error direction between the current on-chip clock frequency and the standard frequency; simultaneously, combining efficient search algorithms such as the binary search method, the codeword search circuit inside the chip automatically adjusts the calibration codeword to approach the target frequency with the fewest iterations, and finally solidifies the optimal calibration codeword in the on-chip non-volatile storage medium, thereby realizing an efficient and autonomous clock calibration method and device.

[0012] To achieve the above objectives, the specific technical solution of the present invention is a chip clock calibration method, comprising:

[0013] Step 1: Receive the calibration start command;

[0014] Step 2: Generate an on-chip clock based on the initial calibration codeword;

[0015] Step 3: Determine the relationship between the frequency of the on-chip clock and the standard clock frequency based on the reference clock to obtain the decision result;

[0016] Step 4: Update the calibration codeword using a binary search method based on the judgment result;

[0017] Step 5: Repeat steps 2 to 4 until the preset conditions are met, and store the calibration codeword when the preset conditions are met into a non-volatile storage medium.

[0018] In some embodiments, the process of determining the relationship between the frequency of the on-chip clock and the standard clock frequency based on the reference clock in step three includes:

[0019] According to the first selection strategy, a frequency division clock and a counting clock are determined; wherein the frequency division clock and the counting clock are respectively one of the reference clock and the on-chip clock;

[0020] Perform frequency division on the clock The frequency is divided to obtain a frequency-divided clock, and the counting window is determined based on the rising edge of the frequency-divided clock.

[0021] The period of the counting clock is counted within the counting window to obtain a count value;

[0022] The count value is compared with the target count value to obtain the decision result.

[0023] In some embodiments, the first selection strategy includes:

[0024] If the frequency of the on-chip clock is higher than the frequency of the reference clock, then the reference clock is selected as the frequency divider clock, and the on-chip clock is selected as the counting clock;

[0025] If the frequency of the on-chip clock is lower than the frequency of the reference clock, then the on-chip clock is selected as the frequency divider clock, and the reference clock is selected as the counting clock.

[0026] In some embodiments, the process of determining the relationship between the frequency of the on-chip clock and the standard clock frequency based on the reference clock in step three further includes:

[0027] Based on the target frequency, the divided clock frequency, and the division factor The target count value is determined by the length of the counting window.

[0028] Wherein, the length of the counting window is equal to The half-cycle length of the clock after frequency division.

[0029] In some embodiments, the process of updating the calibration codeword using a binary search method in step four according to the decision result includes:

[0030] If the decision result indicates that the current on-chip clock frequency is lower than the standard clock frequency, the current calibration codeword is updated to the median of the remaining codeword space so that the updated on-chip clock frequency increases.

[0031] If the decision indicates that the current on-chip clock frequency is higher than the standard clock frequency, the current calibration codeword is updated to the median of the remaining codeword space, so that the updated on-chip clock frequency is reduced.

[0032] A chip clock calibration device, comprising:

[0033] Clock generation circuit, used to generate on-chip clock based on calibration codeword;

[0034] A frequency decision circuit is used to determine the relationship between the frequency of the on-chip clock and the standard clock frequency based on a reference clock, and to obtain a decision result.

[0035] A calibration codeword search circuit is used to update the calibration codeword using a binary search method based on the decision result.

[0036] A non-volatile storage medium used to store the final calibration codeword when preset conditions are met.

[0037] In some embodiments, the frequency decision circuit includes:

[0038] A frequency divider is used to divide the input clock frequency. Frequency division yields the divided clock.

[0039] A counter is used to count the input clock within a counting window determined based on the transition edge of the divided clock, and obtain a count value.

[0040] A comparator is used to compare the count value with the target count value and output the decision result;

[0041] The frequency division clock and the counting clock are respectively one of the reference clock and the on-chip clock.

[0042] In some embodiments, the frequency decision circuit further includes:

[0043] The selection control unit is used to determine, based on the frequency relationship between the reference clock and the on-chip clock, whether to use one of the reference clock and the on-chip clock as the frequency division clock, or to use one of the reference clock and the on-chip clock as the counting clock.

[0044] A chip clock calibration circuit, comprising:

[0045] The chip clock calibration device;

[0046] The clock generation circuit, frequency decision circuit, calibration codeword search circuit, and non-volatile storage medium are integrated into the same chip.

[0047] The chip is externally connected to a reference clock source to provide the reference clock.

[0048] In some embodiments, the calibration codeword search circuit is implemented using a state machine, which is used to successively approximate the optimal calibration codeword according to the binary search rule under the drive of the decision result output by the frequency decision circuit.

[0049] Compared with the prior art, the technical solution disclosed in this application has the following non-obvious technical features:

[0050] First, this application adopts an on-chip integrated closed-loop self-calibration architecture. In existing technologies, frequency measurement and codeword adjustment are completed by external devices and internal chip registers, respectively, with measurement and adjustment actions separated and relying on an external host computer for logical judgment and loop control. This application constructs an on-chip closed-loop feedback system by integrating a frequency decision circuit and a calibration codeword search circuit inside the chip. After receiving a simple start command, the chip can autonomously complete the entire process of "measurement-decision-adjustment" without the need for external devices to participate in intermediate decision-making. This architecture, which transfers the calibration logic from the outside to the inside of the chip and is executed autonomously by the hardware, is not something that those skilled in the art would easily conceive of when solving the problem of mass production testing efficiency.

[0051] Secondly, this application adopts a bidirectional frequency error determination mechanism based on a reference clock. In the prior art, external devices usually directly measure the absolute value of the clock frequency output by the chip to determine whether it is high or low. This application creatively adopts a bidirectional counting method based on a single reference clock through a frequency decision circuit. It flexibly selects the frequency division clock and the counting clock according to the comparison situation. It can determine whether the current on-chip clock is faster or slower than the standard clock through a single counting window, without needing to know the precise absolute value of the frequency. This method of determining the direction of relative error, combined with hardware logic implementation, avoids complex floating-point operations or division operations, and reduces hardware implementation costs. This asymmetric comparison logic design has significant creativity.

[0052] Third, this application achieves a deep integration of binary search and on-chip frequency decision. Although binary search is a well-known classic search algorithm in the software field, its combination with on-chip frequency decision circuits, driven by hardware state machines, and used for codeword search in chip clock calibration is the originality of this application. In existing technologies, codeword search typically employs traversal methods or linear approximation methods. This application utilizes the binary result of "too high" or "too low" output by the frequency decision circuit as the decision basis for binary search, making the number of calibrations logarithmically related to the calibration codeword width (e.g., an N-bit codeword requires only N iterations), rather than a linear relationship. This technical solution, which solidifies software algorithm ideas through hardware logic and deeply optimizes for clock calibration scenarios, not only solves the problem of long calibration time but also reflects innovative thinking in collaborative design at the system level.

[0053] Compared with the prior art, the present invention has the following beneficial effects:

[0054] 1. This invention reduces reliance on external devices and enables autonomous calibration. By setting a frequency decision circuit and a calibration codeword search circuit inside the chip, the chip can automatically complete the closed-loop process of frequency measurement, error judgment, and codeword adjustment without external device intervention after receiving a simple start command. This significantly reduces reliance on expensive external testing equipment (such as high-precision frequency meters and automated testing equipment), simplifies the testing process, and allows the chip to be calibrated using simpler test fixtures during mass production. It also gives the chip the ability to self-correct according to environmental changes (such as temperature and voltage drift) in system applications.

[0055] 2. This invention can significantly shorten calibration time and improve production efficiency by employing a binary search method as the core search strategy for calibration codewords. Compared to the common full-range traversal method or linear search method in existing technologies, the binary search method can reduce the number of calibration attempts from... The frequency (N is the calibration codeword width) is reduced to... For example, taking an 8-bit calibration codeword, the traversal method requires a maximum of 256 attempts, while this application only requires 8 attempts to complete the search, reducing calibration time by tens of times. In large-scale chip production testing, this advantage will directly translate into a leap in testing efficiency, significantly reducing the testing cost per chip and effectively breaking through production capacity bottlenecks.

[0056] 3. This invention improves calibration accuracy and flexibility by flexibly configuring the frequency division factor. and counting window The calibration accuracy can be dynamically adjusted according to actual system requirements. Users can balance calibration time and accuracy by increasing the frequency division factor or extending the counting window to improve the target counting value. The degree of integerization reduces frequency decision error. This configurable calibration accuracy mechanism makes this technical solution flexible and applicable to a variety of application scenarios, from cost-sensitive consumer electronics to precision-critical industrial control and automotive electronics. Attached Figure Description

[0057] Figure 1 This is a flowchart of the method according to at least one exemplary embodiment of the present invention;

[0058] Figure 2 This is a schematic diagram of the circuit according to at least one exemplary embodiment of the present invention;

[0059] Figure 3 This is a flowchart illustrating the frequency decision-making process according to at least one exemplary embodiment of the present invention;

[0060] Figure 4This is a schematic diagram of the codeword search process according to at least one exemplary embodiment of the present invention;

[0061] Figure 5 This is a schematic diagram of the binary update strategy according to at least one example embodiment of the present invention. Detailed Implementation

[0062] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings. Those skilled in the art should be able to understand the invention through reference to the drawings. Figures 1 to 5 To understand the embodiments of the present invention and its potential advantages.

[0063] Some embodiments will now be described more fully below with reference to the accompanying drawings, which illustrate some, but not all, of the embodiments. Various embodiments of the invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will satisfy applicable legal requirements. The same reference numerals throughout refer to the same elements. As used herein, the terms “data,” “content,” “information,” and similar terms are used interchangeably to refer to data that can be transmitted, received, and / or stored according to embodiments of the invention. Therefore, the use of any such terms should not be construed as limiting the spirit and scope of the embodiments of the invention.

[0064] Figure 1 A flowchart of a chip clock calibration method provided by at least one example embodiment is shown, which can be performed by... Figure 2 The chip's internal circuitry is shown. In at least one example embodiment, the method includes receiving a calibration start command, generating an on-chip clock based on an initial calibration codeword, determining the relationship between the on-chip clock frequency and a standard clock frequency based on a reference clock, updating the calibration codeword using a binary search method according to the determination result, repeating the above steps until a preset condition is met, and storing the final calibration codeword in a non-volatile storage medium.

[0065] exist Figure 1 In the process, the chip receives a calibration start command. In at least one example embodiment, the calibration start command is sent by an external host computer via a serial port. In another example embodiment, the calibration start command can be generated autonomously by the chip's internal state machine or test controller. Upon receiving the calibration start command, the chip enters calibration mode.

[0066] exist Figure 1 In this implementation, the clock generation circuit generates an on-chip clock based on an N-bit initial calibration codeword. In at least one example embodiment, the initial calibration codeword is set to have the most significant bit as 1 and the least N-1 bits as 0; this setting is suitable for scenarios employing a binary search strategy. In another example embodiment, the initial calibration codeword may be set to the median or other predetermined values.

[0067] Figure 3 A flowchart illustrating frequency decision-making provided in at least one example embodiment is shown, whereby the frequency decision-making is based on a chip ( Figure 2 The off-chip reference clock of the chip (shown) determines the relationship between the current on-chip clock frequency and the standard clock frequency. In at least one example embodiment, this determination process includes the following sub-steps:

[0068] exist Figure 3 In the process, determine the frequency division clock. and counting clock Specifically, there are two situations: Select the frequency divider clock as the reference clock. Select the current on-chip clock as the counting clock. ; Select the current on-chip clock as a frequency-divided clock. Select the reference clock as the counting clock. The selection strategy can be determined based on the estimated relationship between the reference clock frequency and the on-chip clock frequency, or it can be specified in advance by the host computer.

[0069] exist Figure 3 In the process of dividing the clock frequency... conduct Frequency division yields the divided clock. In at least one example embodiment, The value is determined based on the calibration accuracy requirements. The larger the value, the longer the clock period after frequency division, the longer the subsequent counting window, and the higher the calibration accuracy.

[0070] exist Figure 3 In China, with The transition edge (e.g., rising or falling edge) determines the boundary of the counting window. In at least one example embodiment, the counting window length is equal to... The half-cycle length of the divided clock, assuming a duty cycle of 50%. The longer the counting window time, the higher the calibration accuracy.

[0071] exist Figure 3 In the counting window Internal counting clock Counting is performed periodically to obtain the count value. .

[0072] exist Figure 3 In the middle, the count value Compared with the target count value The comparison is performed to obtain a judgment result. Among them, the target count value... satisfy: , The standard clock frequency is used. In at least one example embodiment, to improve frequency decision accuracy, the target frequency is used... Select the reference clock frequency and division factor. and counting window , making It is an integer, meaning the length of the counting window is exactly 1. The length of a standard clock cycle. If equal This indicates that the clock frequency corresponding to the current codeword meets the calibration accuracy requirements; if Greater than Then in This indicates that the current clock frequency is higher than the standard frequency. This indicates that the current clock frequency is lower than the standard frequency; if Less than Then in This indicates that the current clock frequency is lower than the standard frequency. This indicates that the current clock frequency is higher than the standard frequency.

[0073] Figure 4 A schematic diagram of a codeword search process provided in at least one example embodiment is shown, used to determine whether preset conditions are met. In at least one example embodiment, the preset conditions include a count value. equal Alternatively, the codeword space may have been searched. If the preset conditions are met, the calibration ends and the current calibration codeword is stored in a non-volatile storage medium; otherwise, the codeword update process begins.

[0074] The code word update process uses a binary search update strategy. Figure 5 A schematic diagram of the binary search update strategy provided in at least one example embodiment is shown: if the current on-chip clock frequency is lower than the standard frequency, the current calibration codeword is updated to the median of the remaining codeword space, thereby increasing the updated on-chip clock frequency; if the current on-chip clock frequency is higher than the standard frequency, the current calibration codeword is updated to the median of the remaining codeword space, thereby decreasing the updated on-chip clock frequency. In at least one example embodiment, for an N-bit calibration codeword, the binary search method converges in at most N iterations.

[0075] In at least one example embodiment, the process of generating an on-chip clock and updating the calibration codeword using a binary search method is repeated until the calibration is complete.

[0076] In at least one example embodiment, the final calibration codeword is stored in a non-volatile storage medium (e.g., EEPROM or flash memory). Thereafter, each time the chip is powered on, the calibration codeword is read from the non-volatile storage medium and configured to the clock generation circuitry to obtain an accurate on-chip clock.

[0077] Figure 2 A schematic diagram of a chip clock calibration circuit provided in at least one example embodiment is shown. The components of the circuit are integrated inside the same chip, which is externally connected to a reference clock source to provide a stable reference clock signal.

[0078] In at least one example embodiment, the chip can also be connected to a host computer for sending calibration start commands and / or monitoring calibration status.

[0079] Specifically, such as Figure 2 As shown, the chip clock calibration circuit includes internal and external components. The internal components include: a clock generation circuit, a frequency decision circuit, a calibration codeword search circuit, and a non-volatile storage medium. The external components include: a host computer and a reference clock source. The host computer connects to the chip via a serial port (e.g., UART, I2C, or SPI) to send calibration start commands. The reference clock source provides an accurate and stable reference clock signal, such as from an external crystal oscillator or a high-precision clock generator.

[0080] In at least one example embodiment, the output of the clock generation circuit is connected to the first input of the frequency decision circuit, and the output of the reference clock source is connected to the second input of the frequency decision circuit. The output of the frequency decision circuit is connected to the input of the calibration codeword search circuit, and the output of the calibration codeword search circuit is connected to the calibration codeword input of the clock generation circuit and the data input of the non-volatile storage medium. The output of the non-volatile storage medium is connected to the calibration codeword holding input of the clock generation circuit (for power-on loading).

[0081] In at least one example embodiment, the calibration codeword search circuit is implemented using a state machine. This state machine is activated upon receiving a calibration start command and, driven by the decision result output by the frequency decision circuit, successively approximates the optimal calibration codeword according to a binary search rule. The state machine internally maintains a finite set of states, including: an initial state, a waiting-for-decision state, an updated codeword state, a verification state, and a completion state. In the initial state, the state machine sets the initial calibration codeword (e.g., the highest bit is 1, and the remaining bits are 0). In the waiting-for-decision state, the state machine enables the frequency decision circuit and waits for its output result. In the updated codeword state, the state machine updates the upper and lower bounds of the binary search and the current codeword according to the decision result. In the verification state, the state machine determines whether the termination condition is met (e.g., the frequency error corresponding to the current codeword is within the allowable range, or the search space has been exhausted). In the completion state, the state machine writes the final codeword to a non-volatile storage medium and generates a calibration completion indication signal.

[0082] In at least one example embodiment, the frequency decision circuit internally includes: a selection switch, a programmable frequency divider, a gated counter, and a digital comparator. The selection switch, controlled by a selection control unit, routes the reference clock and the on-chip clock to the input of the frequency divider or the input of the counter, respectively. The programmable frequency divider divides the clock frequency... Frequency division, its frequency division factor This can be configured via the configuration register. The gated counter uses the transition edge of the divided clock as the open and close signal for the counting window to count the clock. The digital comparator compares the counting result with a preset target count value. The comparison is performed, and a high / low frequency indication signal is output.

[0083] In at least one example embodiment, the circuit may also include a bypass mode: when calibration is not required, the calibration codeword search circuit is disabled, the calibration codeword stored in the non-volatile storage medium is directly output to the clock generation circuit, and the on-chip clock is directly used as the system clock.

[0084] With the circuit described above, the chip can complete clock frequency calibration completely autonomously after receiving a simple start command, without the need for external devices to participate in the intermediate decision-making process, thereby significantly reducing testing costs and improving calibration efficiency.

[0085] In at least one example embodiment, a chip clock calibration device is provided, which includes the chip clock calibration circuit described above, for autonomously performing clock frequency calibration.

[0086] In at least one example embodiment, the device includes: a clock generation circuit, a frequency decision circuit, a calibration codeword search circuit, and a non-volatile storage medium.

[0087] In at least one example embodiment, the clock generation circuit is used to generate an on-chip clock based on a calibration codeword.

[0088] In at least one example embodiment, the clock generation circuit includes an RC oscillator or a ring oscillator whose output frequency is controlled by a calibration codeword. The calibration codeword can be... The different values ​​of the codewords in the 1-bit digital signal correspond to different oscillator bias currents or capacitor array configurations, thereby changing the output frequency.

[0089] In at least one example embodiment, the frequency decision circuit is used to determine the relationship between the current on-chip clock frequency and the standard clock frequency based on an off-chip reference clock, and outputs the decision result.

[0090] In at least one example embodiment, the frequency decision circuit includes: a frequency divider, a counter, a comparator, and a selection control unit.

[0091] A frequency divider is used to divide the input clock frequency. conduct Frequency division yields the divided clock. In at least one example embodiment, the division multiple of the frequency divider. It is configurable. The higher the value, the higher the calibration accuracy.

[0092] A counter is used to measure the clock frequency after division. The transition edge is determined by the counting window Internally, the counting clock for the input. Perform periodic counting to obtain the count value. .

[0093] A comparator is used to convert the count value Compared with the target count value The system compares the frequencies and outputs the result. The result can be one of three states: frequency too high, frequency too low, or frequency acceptable.

[0094] The selection control unit is used to determine, based on the frequency relationship between the reference clock and the on-chip clock, which path of the reference clock or the on-chip clock should be used as the frequency divider clock. Which channel serves as the counting clock? .

[0095] In at least one example embodiment, the selection control unit can be implemented by a simple comparator or state machine, or it can be preset by a host computer through configuration registers.

[0096] In at least one example embodiment, the calibration codeword search circuit is used to update the calibration codeword by binary search based on the decision result output by the frequency decision circuit.

[0097] In at least one example embodiment, the calibration codeword search circuit includes a state machine that maintains an upper bound, a lower bound, and the current codeword. After each decision, the state machine updates the upper or lower bound based on the result of "frequency too high" or "frequency too low," and calculates a new current codeword (e.g., taking the median of the upper and lower bounds). The state machine also controls the number of iterations and the termination condition of the calibration process.

[0098] In at least one example embodiment, a non-volatile storage medium is used to store the final calibration codeword when preset conditions are met.

[0099] In at least one example embodiment, the non-volatile storage medium is an EEPROM, flash memory, or one-time programmable memory (OTP). The calibration codeword is read out and configured to the clock generation circuitry during subsequent normal operation of the chip.

[0100] In at least one example embodiment, the device further includes interface circuitry for receiving a calibration start command from an external host computer. In another example embodiment, the device further includes an on-chip timer or self-test circuitry for autonomously triggering the calibration process.

[0101] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, the phrase "comprising an element defined as..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0102] The above technical solutions only embody the preferred technical solutions of the present invention. Any modifications that may be made by those skilled in the art to certain parts thereof embody the principles of the present invention and fall within the protection scope of the present invention.

Claims

1. A chip clock calibration method, characterized in that, include: Step 1: Receive the calibration start command; Step 2: Generate an on-chip clock based on the initial calibration codeword; Step 3: Determine the relationship between the frequency of the on-chip clock and the standard clock frequency based on the reference clock to obtain the decision result; Step 4: Update the calibration codeword using a binary search method based on the judgment result; Step 5: Repeat steps 2 to 4 until the preset conditions are met, and store the calibration codeword when the preset conditions are met into a non-volatile storage medium.

2. The method according to claim 1, characterized in that, Step three, which involves determining the relationship between the on-chip clock frequency and the standard clock frequency based on the reference clock, includes: The frequency division clock and the counting clock are determined according to the first selection strategy; Perform frequency division on the clock The frequency is divided to obtain a frequency-divided clock, and the counting window is determined based on the rising edge of the frequency-divided clock. The period of the counting clock is counted within the counting window to obtain a count value; The count value is compared with the target count value to obtain the decision result.

3. The method according to claim 2, characterized in that, The first selection strategy includes: If the frequency of the on-chip clock is higher than the frequency of the reference clock, then the reference clock is selected as the frequency divider clock, and the on-chip clock is selected as the counting clock; If the frequency of the on-chip clock is lower than the frequency of the reference clock, then the on-chip clock is selected as the frequency divider clock, and the reference clock is selected as the counting clock.

4. The method according to claim 2, characterized in that, Also includes: Based on the target frequency, the divided clock frequency, and the division factor The target count value is determined by the length of the counting window. Wherein, the length of the counting window is equal to The half-cycle length of the clock after frequency division.

5. The method according to claim 1, characterized in that, The process of updating the calibration codeword using the binary search method based on the judgment result in step four includes: If the decision result indicates that the current on-chip clock frequency is lower than the standard clock frequency, the current calibration codeword is updated to the median of the remaining codeword space so that the updated on-chip clock frequency increases. If the decision indicates that the current on-chip clock frequency is higher than the standard clock frequency, the current calibration codeword is updated to the median of the remaining codeword space, so that the updated on-chip clock frequency is reduced.

6. A chip clock calibration device, characterized in that, include: Clock generation circuit, used to generate on-chip clock based on calibration codeword; A frequency decision circuit is used to determine the relationship between the frequency of the on-chip clock and the standard clock frequency based on a reference clock, and to obtain a decision result. A calibration codeword search circuit is used to update the calibration codeword using a binary search method based on the decision result. A non-volatile storage medium used to store the final calibration codeword when preset conditions are met.

7. The apparatus according to claim 6, characterized in that, The frequency decision circuit includes: A frequency divider is used to divide the input clock frequency. Frequency division yields the divided clock. A counter is used to count the input clock within a counting window determined based on the transition edge of the divided clock, and obtain a count value. A comparator is used to compare the count value with the target count value and output the decision result; The frequency division clock and the counting clock are respectively one of the reference clock and the on-chip clock.

8. The apparatus according to claim 7, characterized in that, The frequency decision circuit also includes: The selection control unit is used to determine, based on the frequency relationship between the reference clock and the on-chip clock, whether to use one of the reference clock and the on-chip clock as the frequency division clock, or to use one of the reference clock and the on-chip clock as the counting clock.

9. A chip clock calibration circuit, characterized in that, include: The chip clock calibration apparatus as described in any one of claims 6 to 8; The clock generation circuit, frequency decision circuit, calibration codeword search circuit, and non-volatile storage medium are integrated into the same chip. The chip is externally connected to a reference clock source to provide the reference clock.

10. The circuit according to claim 9, characterized in that, The calibration codeword search circuit is implemented using a state machine, which, driven by the decision result output by the frequency decision circuit, successively approximates the optimal calibration codeword according to the binary search rule.

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