Sensitive amplifiers and memory

Abstract

This application relates to the field of data storage technology, and discloses a sensitive amplifier and a memory. The first clamping circuit and the second clamping circuit of the sensitive amplifier are respectively connected to a high-voltage generation circuit. During the reading process of the memory cell, the high-voltage signal is used as the power supply voltage for the first clamping circuit and the second clamping circuit. The high-voltage signal maintains the bit line voltage and the reference bit line voltage within a preset voltage range. Because the ripple of the high-voltage signal is small, the voltage coefficients of the bit line voltage and the reference bit line voltage are small, thereby improving the reading speed of the sensitive amplifier.

Description

Technical Field

[0001] This application relates to the field of data storage technology, such as a sensitive amplifier and a memory. Background Technology

[0002] The sensitive amplifier circuit is a crucial component of memory, directly impacting its read speed. The sensitive amplifier senses signal changes on the bit lines and amplifies these small signal changes to obtain the data stored in the memory cell. Before sensing a small signal change on the bit lines, the clamping unit of the sensitive amplifier adjusts the bit line voltage to a fixed value to stabilize it as quickly as possible, thus enabling the sensing of a stable bit line current during read operations. As a vital component of memory, the sensitive amplifier circuit directly influences the memory's read speed.

[0003] In the process of implementing the embodiments of this disclosure, at least the following problems were found in the related art:

[0004] When the power supply voltage range is large, the bit line voltage output by the clamping circuit fluctuates significantly, which can affect the read speed of the memory cell.

[0005] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this application, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0006] To provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. This summary is not intended as a general commentary, nor is it intended to identify key / important components or describe the scope of protection of these embodiments, but rather as a prelude to the detailed description that follows.

[0007] This disclosure provides a sensitive amplifier and a memory to improve the data read speed of the sensitive amplifier.

[0008] In some embodiments, the sensitive amplifier includes: a precharge circuit configured to provide a precharge current during a precharge phase; a high-voltage generation circuit configured to provide a high-voltage signal; a reference current generation circuit including a second clamping circuit, a first terminal of the second clamping circuit being connected to a reference memory cell, a second terminal of the second clamping circuit being connected to the high-voltage generation circuit, the reference current generation circuit being configured to generate a reference current after the precharge phase ends; and a first clamping circuit, a first input terminal of the first clamping circuit being connected to the precharge circuit and the reference current generation circuit, a second input terminal of the first clamping circuit being connected to the high-voltage generation circuit, and a bit line voltage output terminal of the first clamping circuit being connected to the memory cell. The first clamping circuit is configured to charge the bit line voltage at the bit line voltage output terminal to a preset voltage according to the pre-charge current received at the first input terminal during the pre-charge phase, receive the high voltage signal through the second input terminal of the first clamping circuit during the pre-charge phase, maintain the bit line voltage within the preset voltage range according to the high voltage signal, and generate a comparison voltage based on the reference current and the bit line current after the pre-charge phase ends; the comparison circuit has its inverting input terminal connected to the second output terminal of the clamping circuit, and is configured to receive the comparison voltage generated by the first clamping circuit, and output a data reading result according to the comparison result between the comparison voltage and the reference voltage.

[0009] Optionally, the bit line voltage output terminal of the first clamping circuit is connected to the memory cell via a column decoding circuit.

[0010] Optionally, the first terminal of the second clamping circuit is connected to the reference storage cell via a column decoding circuit.

[0011] Optionally, the first clamping circuit includes: a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, and a second PMOS transistor; the source of the first NMOS transistor is grounded; the drains of the first NMOS transistor and the first PMOS transistor are connected to the gate of the second NMOS transistor, and the gate of the first PMOS transistor, the gate of the first NMOS transistor, and the source of the second NMOS transistor together serve as the bit line voltage output terminal of the first clamping circuit; the source of the second PMOS transistor is connected to the output terminal of the high voltage generation circuit, the gate of the second PMOS transistor is used to receive a first control signal input from an external circuit, and the drain of the second PMOS transistor is connected to the source of the first PMOS transistor; the drain of the second NMOS transistor is connected to the output terminal of the reference current generation circuit, the output terminal of the precharge circuit, and the inverting input terminal of the comparator circuit, respectively.

[0012] Optionally, the first clamping circuit further includes a first level conversion circuit, which is connected between the gate of the second PMOS transistor and the first control signal, and the first clamping circuit is configured to convert the first control signal to a preset high voltage range.

[0013] Optionally, the reference current generating circuit further includes a mirror circuit, the input terminal of which is connected to the output terminal of the second clamping circuit, and the mirror circuit is configured to generate a reference current based on the reference cell current.

[0014] Optionally, the second clamping circuit includes: a third NMOS transistor, a fourth NMOS transistor, a third PMOS transistor, and a fourth PMOS transistor; the source of the third NMOS transistor is grounded; the source of the third PMOS transistor is connected to the drain of the fourth PMOS transistor, and the drain of the third PMOS transistor and the drain of the third NMOS transistor are connected together to the gate of the fourth NMOS transistor; the gate of the third PMOS transistor, the gate of the third NMOS transistor, and the source of the fourth NMOS transistor together serve as the reference bit line voltage output terminal; the source of the fourth PMOS transistor is connected to the high voltage generation circuit, and the gate of the fourth PMOS transistor is connected to a second control signal input from an external circuit; the drain of the fourth NMOS transistor is connected to the mirror circuit.

[0015] Optionally, the second clamping circuit further includes a second level conversion circuit, which is connected between the gate of the fourth PMOS transistor and the second control signal, for converting the second control signal to a preset high voltage range.

[0016] Optionally, the mirror circuit includes: a fifth PMOS transistor, the source of which is connected to a power supply, and the drain of which is connected to the gate of which is connected to the second clamping circuit; and a sixth PMOS transistor, the source of which is connected to the power supply, the gate of which is connected to the gate of which is connected to the gate of which is connected to the fifth PMOS transistor, and the drain of which is connected to the pre-charge circuit and the first clamping circuit.

[0017] Optionally, the pre-charge circuit includes: a seventh PMOS transistor, the source of which is connected to a power supply, the gate of which is used to receive a third control signal input from an external circuit, and the drain of which serves as the output terminal of the pre-charge circuit to output a pre-charge current.

[0018] Optionally, the comparison circuit includes: a comparator, the inverting input of the comparator being connected to the second output of the first clamping circuit, the non-inverting input of the comparator receiving a reference voltage, the comparator comparing the comparison voltage output by the first clamping circuit with the reference voltage, and outputting a data reading result based on the comparison result.

[0019] In some embodiments, the memory includes: a memory array; and the aforementioned sensitive amplifier, the sensitive amplifier being connected to the memory array.

[0020] Optionally, the sensitive amplifier is connected to the storage array via a column decoding circuit.

[0021] The sensitive amplifier and memory provided in this disclosure can achieve the following technical effects:

[0022] The sensitive amplifier provided in this embodiment of the present disclosure has a first clamping circuit and a second clamping circuit connected to a high voltage generating circuit. During the reading process of the memory cell, the high voltage signal is used as the power supply voltage for the first clamping circuit and the second clamping circuit. The high voltage signal maintains the bit line voltage and the reference bit line voltage within a preset voltage range. Since the ripple of the high voltage signal is small, the voltage coefficients of the bit line voltage and the reference bit line voltage are small, thereby improving the reading speed of the sensitive amplifier.

[0023] The above general description and the description below are exemplary and illustrative only and are not intended to limit this application. Attached Figure Description

[0024] One or more embodiments are illustrated by way of example with reference to the accompanying drawings. These illustrations and drawings do not constitute a limitation on the embodiments. Elements having the same reference numerals in the drawings are shown as similar elements. The drawings are not to be scaled. And wherein:

[0025] Figure 1 This is a circuit block diagram of a sensitive amplifier provided in an embodiment of this disclosure;

[0026] Figure 2 This is a timing diagram of the read operation of a sensitive amplifier provided in an embodiment of this disclosure;

[0027] Figure 3 This is a circuit block diagram of another sensitive amplifier provided in an embodiment of this disclosure;

[0028] Figure 4 This is a circuit diagram of a sensitive amplifier provided in an embodiment of this disclosure;

[0029] Figure 5 This is a schematic diagram of the structure of a memory provided in an embodiment of this disclosure. Detailed Implementation

[0030] To provide a more detailed understanding of the features and technical content of the embodiments of this disclosure, the implementation of the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for illustrative purposes only and are not intended to limit the embodiments of this disclosure. In the following technical description, for ease of explanation, several details are used to provide a full understanding of the disclosed embodiments. However, one or more embodiments may still be implemented without these details. In other cases, well-known structures and devices may be simplified in their depiction to simplify the drawings.

[0031] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this disclosure described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0032] In this disclosure, the terms "upper," "lower," "inner," "middle," "outer," "front," and "rear," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. These terms are primarily for better description of the embodiments of this disclosure and their implementations, and are not intended to limit the indicated devices, elements, or components to having a specific orientation, or to require them to be constructed and operated in a specific orientation. Furthermore, some of the aforementioned terms may be used to indicate other meanings besides orientation or positional relationship; for example, the term "upper" may in some cases indicate a dependency or connection relationship. Those skilled in the art can understand the specific meaning of these terms in the embodiments of this disclosure according to the specific circumstances.

[0033] Furthermore, the terms "set up," "connect," and "fix" should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral structure; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, or it can be an internal connection between two devices, components, or parts. Those skilled in the art can understand the specific meaning of the above terms in the embodiments of this disclosure according to the specific circumstances.

[0034] Unless otherwise stated, the term "multiple" means two or more.

[0035] In this embodiment of the disclosure, the character " / " indicates that the objects before and after it are in an "or" relationship. For example, A / B means: A or B.

[0036] The term "and / or" describes an association between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or A and B.

[0037] It should be noted that, unless otherwise specified, the embodiments and features described in the present disclosure can be combined with each other.

[0038] Combination Figure 1 The diagram shown is a circuit block diagram of a sensitive amplifier provided in an embodiment of this disclosure. The sensitive amplifier includes a precharge circuit 11, a high-voltage generation circuit 12 (HV generator), a reference current generation circuit 13, a first clamp circuit 14, and a comparator circuit 15.

[0039] The pre-charging circuit 11 is configured to provide a pre-charging current during the pre-charging phase.

[0040] The high voltage generating circuit 12 is configured to provide a high voltage signal HV.

[0041] The reference current generating circuit 13 includes a second clamping circuit 131. The first terminal of the second clamping circuit 131 is connected to the reference storage cell, and the second terminal of the second clamping circuit 131 is connected to the high voltage generating circuit 12. The reference current generating circuit 13 is configured to generate a reference current Iref after the pre-charge phase is completed.

[0042] A first clamping circuit 14 is configured to connect a first input terminal to the pre-charge circuit 11 and the reference current generation circuit 13, a second input terminal to the high voltage generation circuit 12, and a bit line voltage output terminal to the storage unit. The first clamping circuit 14 is configured to charge the bit line voltage D at the bit line voltage output terminal to a preset voltage based on the pre-charge current received at the first input terminal during the pre-charge phase. During the pre-charge phase, it receives the high voltage signal through the second input terminal and maintains the bit line voltage D within the preset voltage range based on the high voltage signal. After the pre-charge phase ends, it generates a comparison voltage E based on the reference current Iref and the bit line current Isense.

[0043] Comparator circuit 15, the inverting input of which is connected to the second output of the first clamping circuit 14, is configured to receive a comparison voltage E generated by the first clamping circuit 14 and compare the comparison voltage E with a reference voltage V. REF_E The comparison results are output as data reading results.

[0044] In actual operation, the timing diagram of the sensitive amplifier is as follows: Figure 2 As shown, the RE pulse signal generates a detection signal ATD, which in turn generates a series of read control signals (PREb, SEN, and SEN2). During the pre-charge phase, the pre-charge circuit 11 is turned on, charging the bit line voltage output terminal of the first clamping circuit 14 and raising the bit line voltage to a preset voltage. This preset voltage can be any voltage value between 0.4V and 0.8V, also known as the target voltage, which is the operating voltage required when reading the memory cell. During this phase, the first clamping circuit 14 continuously receives a high-voltage signal from the high-voltage generation circuit 12, stabilizing the bit line voltage within the preset voltage range. For example, stabilizing the bit line voltage within the range of 0.4V to 0.8V.

[0045] Optionally, the bit line voltage output terminal of the first clamping circuit 14 is connected to the memory cell via a column decoding circuit.

[0046] Optionally, the first terminal of the second clamping circuit 131 is connected to the reference storage cell via a column decoding circuit.

[0047] Compared to sensitive amplifiers in related technologies, the clamping circuit's supply voltage is always provided by the power supply, meaning the clamping circuit has a certain voltage coefficient. When the power supply voltage VCC range is wide, the bit line voltage generated by the clamping circuit fluctuates significantly. Since the current fluctuations of the reference memory cell and the selected memory cell (read 0 and read 1 cells) are different, this affects the size of the current window for reading 0 and 1. When the power supply voltage decreases, the current of the reference memory cell decreases more, while the current of the read 0 cell decreases less, thus reducing the read 0 window. A smaller window leads to a slower read speed for the sensitive amplifier, directly affecting the memory's read speed. However, the first and second clamping circuits in the sensitive amplifier provided in this embodiment are powered by the high-voltage generation circuit 12, resulting in smaller voltage coefficients for the bit line voltage and the reference bit line voltage. The current of the reference memory cell and the selected memory cell (Icell0 & Icell1) fluctuate less with the power supply voltage. Therefore, the current windows for read 0 and read 1 cells fluctuate less with the power supply voltage, meaning the current window margins for read 0 and read 1 cells are stable. This improves the read speed of the sensitive amplifier. When the pre-charge phase ends, the pre-charge circuit 11 is turned off, and the data reading phase begins.

[0048] In summary, the sensitive amplifier provided in this embodiment has a first clamping circuit 14 connected to a high-voltage generation circuit 12. During the reading process of the storage unit, the high-voltage signal is used as the power supply voltage for the first clamping circuit 14 and the second clamping circuit 131. The high-voltage signal maintains the bit line voltage within a preset voltage range. Since the ripple of the high-voltage signal is small, the voltage coefficient of the bit line voltage is small, thereby improving the reading speed of the sensitive amplifier.

[0049] Combination Figure 3 The diagram shown is a circuit block diagram of another sensitive amplifier provided in an embodiment of this disclosure. Figure 3 As shown, the reference current generation circuit 13 further includes a mirror circuit 132. The input terminal of the mirror circuit 132 is connected to the output terminal of the second clamping circuit 131, and the mirror circuit 132 is configured to generate a reference current Iref based on the reference cell current.

[0050] Combination Figure 4 As shown, to further optimize the above embodiments, this disclosure also provides specific implementation methods for the various components of the sensitive amplifier. Figure 3 A circuit diagram of a sensitive amplifier provided for an embodiment of this disclosure.

[0051] Optionally, the pre-charge circuit 11 includes a seventh PMOS transistor P7, the source of which is connected to a power supply, the gate of which is used to receive a third control signal input from an external circuit, and the drain of which serves as the output terminal of the pre-charge circuit 11 to output a pre-charge current.

[0052] The third control signal is the read control signal (e.g.) Figure 2 The PREb shown is shown.

[0053] In specific work, during the pre-charging stage, such as Figure 2 As shown, when the read control signal PREb is a negative pulse, the seventh PMOS transistor P7 is turned on, causing the pre-charge circuit 11 to output a pre-charge current, which in turn charges the first clamping circuit 14 connected to the pre-charge circuit 11. When the pre-charge phase ends, the read control signal PREb turns into a positive pulse, and the seventh PMOS transistor P7 is turned off.

[0054] Optionally, the second clamping circuit includes: a third NMOS transistor N3, a fourth NMOS transistor N4, a third PMOS transistor P3, and a fourth PMOS transistor P4. The source of the third NMOS transistor N3 is grounded. The source of the third PMOS transistor P3 is connected to the drain of the fourth PMOS transistor P4. The drains of the third PMOS transistor P3 and the third NMOS transistor N3 are connected to the gate of the fourth NMOS transistor N4. The gates of the third PMOS transistor P3, N3, and N4, together with the source of the fourth NMOS transistor N4, serve as the reference bit line voltage output terminal. The source of the fourth PMOS transistor P4 is connected to the high-voltage generation circuit 12, and its gate is connected to a second control signal input from an external circuit. The drain of the fourth NMOS transistor N4 is connected to the mirror circuit 132.

[0055] It should be noted that the second control signal mentioned above is the read control signal SENb.

[0056] Optionally, the second clamping circuit 131 further includes a second level conversion circuit 1311, which is connected between the gate of the fourth PMOS transistor P4 and the second control signal, for converting the second control signal into a preset high voltage range.

[0057] It should be noted that since the high-voltage signal HV and the power supply voltage VCC are not equal, the main purpose of the second level conversion circuit 1311 is to convert the second control signal SENb from the VCC domain to the HV domain. The level conversion circuit can adopt a latch structure, and the specific structure of the second level conversion circuit 1311 is not limited in this embodiment.

[0058] Optionally, the mirror circuit 132 includes a fifth PMOS transistor P5 and a sixth PMOS transistor P6. The source of the fifth PMOS transistor P5 is connected to a power supply, and the drain of the fifth PMOS transistor P5 is connected to the gate of the fifth PMOS transistor and the second clamping circuit 131, respectively. The source of the sixth PMOS transistor P6 is connected to the power supply, the gate of the sixth PMOS transistor P6 is connected to the gate of the fifth PMOS transistor P5, and the drain of the sixth PMOS transistor P6 is connected to the pre-charge circuit 11 and the first clamping circuit 14, respectively.

[0059] In specific operation, the reference current generation circuit 13 operates as follows: During the pre-charge phase, the reference bit line voltage REFD is charged to a preset voltage by the pre-charge circuit 11. This preset voltage is a voltage value within a preset range of the threshold voltage of the third NMOS transistor N3, thereby forming the reference cell current Irefcell. This reference cell current is then converted into the reference current Iref after passing through the mirror circuit 132 composed of the fifth PMOS transistor P5 and the sixth PMOS transistor P6.

[0060] Optionally, the high voltage generating circuit 12 includes: a charge pump circuit 121, a voltage sampling circuit 122, and a comparator 123.

[0061] In practice, during the high-voltage establishment process, the voltage sampling circuit samples the output of the charge pump circuit to determine the sampling voltage Vdet. The comparator then compares the sampling voltage Vdet with the reference voltage Vref. If Vdet is less than Vref, the comparator outputs a high level. At this time, the charge pump circuit operates, continuously increasing its output voltage, causing the sampling voltage Vdet to rise accordingly. This continues until Vdet exceeds Vref, at which point the comparator outputs a low level, and the charge pump circuit stops operating. At this point, the output voltage of the charge pump circuit reaches the preset target value. After the charge pump circuit stops operating, its output voltage gradually decreases until Vdet is again less than Vref, at which point the comparator outputs a high level again, and the charge pump circuit restarts. This cycle repeats to continuously output a high-voltage signal.

[0062] Optionally, the first clamping circuit 14 includes: a first NMOS transistor N1, a second NMOS transistor N2, a first PMOS transistor P1, and a second PMOS transistor P2. The source of the first NMOS transistor N1 is grounded, and the drains of the first NMOS transistor N1 and the first PMOS transistor P1 are connected to the gate of the second NMOS transistor N2. The gates of the first PMOS transistor P1, the first NMOS transistor N1, and the source of the second NMOS transistor N2 together serve as the bit line voltage output terminal D of the first clamping circuit 14. The source of the second PMOS transistor P2 is connected to the output terminal of the high-voltage generation circuit 12, and the gate of the second PMOS transistor P2 is used to receive a first control signal input from an external circuit. The drain of the second PMOS transistor P2 is connected to the source of the first PMOS transistor P1. The drain of the second NMOS transistor N2 is connected to the output terminal of the reference current generation circuit 13, the output terminal of the pre-charge circuit 11, and the inverting input terminal of the comparator circuit 15.

[0063] Wherein, the first control signal is a read control signal SENb, and the read control signal SENb is Figure 2 The inverted signal of the read control signal SEN.

[0064] Optionally, the first clamping circuit 14 further includes: a first level conversion circuit 141, which is connected between the gate of the second PMOS transistor P2 and the first control signal, and is configured to convert the first control signal into a preset high-voltage range.

[0065] It should be noted that since the high-voltage signal HV and the power supply voltage VCC are not equal, the main purpose of the first level conversion circuit 141 is to convert the first control signal SENb signal from the VCC domain to the HV domain. The first level conversion circuit 141 may adopt a latch structure, and the specific structure of the first level conversion circuit 141 is not limited in the embodiments of the present disclosure. The structure of the first level conversion circuit 141 and the above-mentioned second level conversion circuit 1311 may be the same or different, as long as it can convert the control signal in the VCC domain into a signal in the HV domain, it can solve the technical problems in the embodiments of the present disclosure.

[0066] During specific operation, the working principle of the above-mentioned first clamping circuit 14 is as follows: In the pre-charge stage, when the first control signal PREb is a negative pulse, that is, at a low level, the read control signal SENb is also at a low level. At this time, both the second PMOS transistor P2 and the seventh PMOS transistor P7 are turned on, and at this time, the bit line voltage D is at a low level, for example, 0V. Therefore, the first PMOS transistor P1 is turned on, the first NMOS transistor N1 is turned off, and the gate C point of the second NMOS transistor is charged to a high level. Since the C point is charged high, the second NMOS transistor N2 is turned on, and the bit line voltage D is raised by the branch after the seventh PMOS transistor and the second NMOS transistor are turned on. As the bit line voltage D is gradually raised, the first NMOS transistor is turned on, and finally the voltage at the gate C point of the second NMOS transistor will slowly decrease, and the second NMOS transistor N2 gradually enters the sub-threshold region, making the bit line voltage D point stable within a preset voltage range.

[0067] Similarly, REFD is also clamped at the target voltage and forms a reference cell current Irefcell, and then a reference current Iref is generated through the fifth PMOS transistor P5 current mirror and the sixth PMOS transistor P6.

[0068] After the pre-charge stage ends, the read control signal PREb is converted to a high level, and the seventh PMOS transistor P7 is turned off. The voltage at point E (comparison voltage VE) is completely determined by the current Isense of the storage unit and the reference current Iref. When Iref > Isense, that is, the data stored in the read storage unit is 0, the voltage at point E remains unchanged. When Iref < Isense, that is, the data stored in the read storage unit is 1, at this time, the voltage at point E is pulled down to a low potential.

[0069] Optionally, the comparison circuit 15 includes: a comparator, the inverting input of which is connected to the second output of the first clamping circuit 14, the non-inverting input of which receives a reference voltage, and the comparator being configured to compare the voltage V output by the first clamping circuit 14. E and the reference voltage V REF_E Compare the data and output the reading results based on the comparison results.

[0070] The specific working principle is as follows: After the first clamping circuit 14 outputs the comparison voltage VE, the comparison stage begins. SEN2 is pulled high, the comparator is enabled, and the comparison voltage VE is compared with the reference voltage V. REF_E The comparison is performed, and the data reading results are output based on the comparison results.

[0071] It should be noted that the precharge time in the above precharge stage is Tpre, the establishment time of the comparison voltage is T1, and the output delay time of the comparator is T2. Therefore, the read time Taa to complete the reading of one memory cell is calculated as follows: Taa = Tpre + T1 + T2.

[0072] Table 1 shows the simulation results of the sensitive amplifier provided in this embodiment. For an application scenario with VCC = 2.3V~3.63V, the simulation results of the reference bit line voltage (REFD) of the reference clamping circuit are shown in Table 1 below, where REFD_Old represents the simulation results of the prior art, and REFD_New represents the simulation results using the sensitive amplifier provided in this embodiment. As can be seen from Table 1, after using the sensitive amplifier provided in this embodiment, even with large fluctuations in the power supply voltage VCC, the reference bit line voltage remains between 0.66V and 0.68V, showing minimal fluctuation with the power supply voltage.

[0073] Table 1

[0074]

[0075] Combination Figure 5 As shown, this disclosure also provides a memory 50, which includes a memory array 51 and a sensitive amplifier 52 connected to the memory array 51. The sensitive amplifier 52 in this disclosure can be any of the sensitive amplifiers described in the above embodiments of this disclosure.

[0076] Optionally, the sensitive amplifier 52 is connected to the storage array 51 via a column decoding circuit.

[0077] The foregoing description and accompanying drawings fully illustrate embodiments of the present disclosure to enable those skilled in the art to practice them. Other embodiments may include structural and other changes. The embodiments represent only possible variations. Individual components and functions are optional unless explicitly required, and the order of operation may vary. Parts and features of some embodiments may be included or substituted for parts and features of other embodiments. Embodiments of the present disclosure are not limited to the structures described above and shown in the accompanying drawings, and various modifications and changes may be made without departing from its scope. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A sensitive amplifier, characterized in that, include: The pre-charging circuit is configured to provide a pre-charging current during the pre-charging phase; The high-voltage generating circuit is configured to provide a high-voltage signal; The reference current generating circuit includes a second clamping circuit, a first terminal of which is connected to a reference storage cell, and a second terminal of which is connected to the high voltage generating circuit. The reference current generating circuit is configured to generate a reference current after the pre-charge phase is completed. A first clamping circuit is configured to connect a first input terminal to the pre-charge circuit and the reference current generation circuit, a second input terminal to the high voltage generation circuit, and a bit line voltage output terminal to the storage unit. The first clamping circuit is configured to charge the bit line voltage at the bit line voltage output terminal to a preset voltage according to the pre-charge current received at the first input terminal during the pre-charge phase, receive the high voltage signal through the second input terminal of the first clamping circuit during the pre-charge phase, maintain the bit line voltage within the preset voltage range according to the high voltage signal, and generate a comparison voltage based on the reference current and the bit line current after the pre-charge phase ends. A comparator circuit is provided, wherein the inverting input terminal of the comparator circuit is connected to the second output terminal of the clamping circuit, and the comparator circuit is configured to receive a comparison voltage generated by the first clamping circuit and output a data reading result based on the comparison result between the comparison voltage and the reference voltage.

2. The sensitive amplifier according to claim 1, characterized in that, The first clamping circuit includes: a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, and a second PMOS transistor; The source of the first NMOS transistor is grounded; The drain of the first NMOS transistor and the drain of the first PMOS transistor are connected to the gate of the second NMOS transistor. The gate of the first PMOS transistor, the gate of the first NMOS transistor, and the source of the second NMOS transistor are used together as the bit line voltage output terminal of the first clamping circuit. The source of the second PMOS transistor is connected to the output terminal of the high voltage generating circuit, the gate of the second PMOS transistor is used to receive the first control signal input from the external circuit, and the drain of the second PMOS transistor is connected to the source of the first PMOS transistor. The drain of the second NMOS transistor is connected to the output terminal of the reference current generation circuit, the output terminal of the precharge circuit, and the inverting input terminal of the comparator circuit, respectively.

3. The sensitive amplifier according to claim 2, characterized in that, The first clamping circuit further includes a first level conversion circuit, which is connected between the gate of the second PMOS transistor and the first control signal. The first clamping circuit is configured to convert the first control signal to a preset high voltage range.

4. The sensitive amplifier according to any one of claims 1-3, characterized in that, The reference current generating circuit further includes: A mirror circuit, the input of which is connected to the output of the second clamping circuit, is configured to generate a reference current based on the reference cell current.

5. The sensitive amplifier according to claim 4, characterized in that, The second clamping circuit includes: a third NMOS transistor, a fourth NMOS transistor, a third PMOS transistor, and a fourth PMOS transistor; The source of the third NMOS transistor is grounded; The source of the third PMOS transistor is connected to the drain of the fourth PMOS transistor, and the drain of the third PMOS transistor and the drain of the third NMOS transistor are connected together to the gate of the fourth NMOS transistor. The gate of the third PMOS transistor, the gate of the third NMOS transistor, and the source of the fourth NMOS transistor together serve as the reference bit line voltage output terminal. The source of the fourth PMOS transistor is connected to the high voltage generating circuit, and the gate of the fourth PMOS transistor is connected to the second control signal input from the external circuit. The drain of the fourth NMOS transistor is connected to the mirror circuit.

6. The sensitive amplifier according to claim 5, characterized in that, The second clamping circuit further includes a second level conversion circuit, which is connected between the gate of the fourth PMOS transistor and the second control signal, and is used to convert the second control signal to a preset high voltage range.

7. The sensitive amplifier according to claim 4, characterized in that, The mirror circuit includes: The fifth PMOS transistor has its source connected to the power supply and its drain connected to both the gate and the second clamping circuit. The sixth PMOS transistor has its source connected to the power supply, its gate connected to the gate of the fifth PMOS transistor, and its drain connected to the pre-charge circuit and the first clamping circuit.

8. The sensitive amplifier according to claim 1, characterized in that, The pre-charging circuit includes: The seventh PMOS transistor has its source connected to the power supply, its gate used to receive the third control signal input from the external circuit, and its drain used as the output terminal of the pre-charge circuit to output the pre-charge current.

9. The sensitive amplifier according to claim 1, characterized in that, The comparison circuit includes: The comparator has its inverting input connected to the second output of the first clamping circuit, and its non-inverting input receiving a reference voltage. The comparator compares the comparison voltage output by the first clamping circuit with the reference voltage and outputs a data reading result based on the comparison result.

10. A memory, characterized in that, The memory includes: Storage array; The sensitive amplifier as described in any one of claims 1-9, wherein the sensitive amplifier is connected to the storage array.

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