Silicon-based substrate and method of manufacturing the same, chip
By designing vias with different cross-sectional areas and staggering metal lines in a silicon substrate, the loss problem in long-distance signal transmission during chip packaging was solved, achieving both high-density short-distance and low-loss long-distance signal transmission.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- HYGON INFORMATION TECH CO LTD
- Filing Date
- 2022-03-17
- Publication Date
- 2026-06-05
AI Technical Summary
Existing interconnect structures implemented in chip packaging using silicon wafers result in signal integrity loss during long-distance, high-speed signal transmission, failing to effectively balance short-distance high-density and long-distance low-loss signal transmission.
Design a silicon-based substrate that uses vias and metal lines with different cross-sectional areas. Large cross-sectional area vias and metal lines enable long-distance, low-loss signal transmission, while small cross-sectional area vias and metal lines enable short-distance, high-density signal transmission. The vias and metal lines are arranged in an alternating pattern within the substrate to optimize electrical performance.
This achieves both short-distance high-density and long-distance low-loss signal transmission on the same silicon substrate, improving signal quality and transmission efficiency.
Smart Images
Figure CN116053230B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor packaging technology, and in particular to a silicon-based substrate, its manufacturing method, and a chip. Background Technology
[0002] With the miniaturization, integration, and intelligence of electronic products, the complexity and number of chips used have increased significantly, leading to increasingly complex chip packaging. In chip packaging, interconnections between different pins of a single chip or between multiple chips are typically achieved using silicon wafers and organic substrates.
[0003] For the interconnects implemented via silicon wafers, dense metal wires (typically with a linewidth less than 1 μm and a line height less than 1 μm) are typically used as interconnects, and fine vias are placed in the silicon wafer to connect the metal wires in different layers of the silicon wafer. These vias are generally small in size and uniformly distributed, which facilitates high-density, high-bandwidth inter-wafer short-distance signal transmission and also facilitates control of the manufacturing process.
[0004] However, while this via and interconnect structure can effectively support short-distance signal transmission, it can lead to loss of signal integrity in long-distance, high-speed signal transmission, causing the received signal to be inconsistent with the original transmitting signal, thus resulting in chip malfunction. Summary of the Invention
[0005] In view of this, embodiments of the present invention provide a silicon-based substrate and its manufacturing method, as well as a chip, which facilitate the effective integration of short-distance high-density signal transmission and long-distance low-loss signal transmission using the same silicon-based substrate in chip packaging.
[0006] In a first aspect, embodiments of the present invention provide a silicon-based substrate, comprising: a substrate body, wherein at least two vias are disposed therein, the at least two vias including at least one first via and at least one second via, wherein the cross-sectional area of the first via is larger than the cross-sectional area of the second via; wherein the first via is used for electrically connecting a first metal line disposed in the substrate body, and the second via is used for electrically connecting a second metal line disposed in the substrate body, wherein the cross-sectional area of the first metal line is larger than the cross-sectional area of the second metal line; wherein at least one of the at least two vias has any of the following positions: one end is located on a first surface of the substrate body and the other end is located inside the substrate body; one end is located on a second surface of the substrate body and the other end is located inside the substrate body; one end is located on a first surface of the substrate body and the other end is located on a second surface of the substrate body; both ends are located inside the substrate body; wherein the first surface of the substrate body is used for disposing of dies, and the second surface is opposite to the first surface.
[0007] Optionally, the cross-sectional area of the first via is greater than a first area threshold, and the cross-sectional area of the second via is less than a second area threshold, wherein the first area threshold is greater than or equal to the second area threshold.
[0008] Optionally, the ratio of the cross-sectional area of the first via to the cross-sectional area of the second via is greater than or equal to a first ratio threshold.
[0009] Optionally, the first ratio threshold is 2:1, 4:1, 5:1, 9:1, or 16:1.
[0010] Optionally, in at least a partial spatial region within the substrate body, the first via and the second via are arranged alternately in a direction parallel to the first surface of the substrate body and / or in a direction perpendicular to the first surface of the substrate body.
[0011] Optionally, the first surface of the substrate body is used to lay out the grains; the second via is used for the second metal line for electrical connection and the first via is used for the first metal line for electrical connection, and the layer where the second metal line is located is closer to the first surface of the substrate body than the layer where the first metal line is located.
[0012] Optionally, the length of the first metal wire is greater than a first length threshold, and the length of the second metal wire is less than or equal to the first length threshold.
[0013] Optionally, the first length threshold can be in the range of 4 mm to 6 mm.
[0014] Secondly, embodiments of the present invention also provide a method for manufacturing a silicon-based substrate, comprising: providing a silicon-based substrate substrate; providing at least one third via and at least one fourth via on the substrate substrate, wherein the cross-sectional area of the third via is larger than the cross-sectional area of the fourth via, and both the third via and the fourth via penetrate the substrate substrate; providing at least one insulating dielectric layer on the substrate substrate having the third via and the fourth via, the at least one insulating dielectric layer including a first insulating dielectric layer; the substrate substrate and the at least one insulating dielectric layer forming a substrate body of the silicon-based substrate; providing a first etch barrier layer on the first insulating dielectric layer, wherein the first etch barrier layer has at least one first via pattern and at least one second via pattern, the area of the first via pattern being larger than the area of the second via pattern; and, under the protection of the first etch barrier layer, the substrate substrate... At least one first via corresponding to the at least one first via pattern and at least one second via corresponding to the at least one second via pattern are etched on the first insulating dielectric layer, wherein the cross-sectional area of the first via is larger than the cross-sectional area of the second via; wherein each of the first via, each of the second via, each of the third via, and each of the fourth via forms a substrate via by staggering or aligning the upper and lower layers, wherein the position of the substrate via has any of the following positions: one end is located on the first surface of the substrate body, and the other end is located inside the substrate body; one end is located on the second surface of the substrate body, and the other end is located inside the substrate body; one end is located on the first surface of the substrate body, and the other end is located on the second surface of the substrate body; both ends are located inside the substrate body; wherein the first surface of the substrate body is used for laying out the grains, and the second surface is opposite to the first surface.
[0015] Optionally, after etching at least one first via corresponding to the at least one first via pattern and at least one second via corresponding to the at least one second via pattern on the first insulating dielectric layer, the method further includes: laying a first metal line and a second metal line on the first insulating dielectric layer; wherein the first metal line is electrically connected to the first via, the second metal line is electrically connected to the second via, and the cross-sectional area of the first metal line is larger than the cross-sectional area of the second metal line.
[0016] Optionally, after laying the first metal wire and the second metal wire on the first insulating dielectric layer, the method further includes: setting a second insulating dielectric layer on the first insulating dielectric layer on which the first metal wire and the second metal wire are laid; etching at least one fifth via and at least one sixth via on the second insulating dielectric layer, wherein the absolute value of the difference between the cross-sectional area of the fifth via and the cross-sectional area of the first via is less than a preset threshold, the absolute value of the difference between the cross-sectional area of the sixth via and the cross-sectional area of the second via is less than the preset threshold, and the fifth via and the first via are aligned vertically or staggered vertically.
[0017] Optionally, the first via and the second via on the first insulating dielectric layer are arranged alternately in the width direction and / or length direction of the first insulating dielectric layer.
[0018] Thirdly, embodiments of the present invention also provide a chip, including a substrate and at least one die disposed on the substrate, wherein the substrate is any silicon-based substrate provided in the embodiments of the present invention, a first metal contact on the die is electrically connected to a first metal line in the substrate, and a second metal contact on the die is electrically connected to a second metal line in the substrate; wherein the first metal line is electrically connected to a first via, and the second metal line is electrically connected to a second via.
[0019] Fourthly, embodiments of the present invention also provide a chip, comprising: a first substrate, a second substrate, and a die, wherein the first substrate is any silicon-based substrate provided in the embodiments of the present invention; at least a portion of the pins of the die are electrically connected to metal contacts on a first surface of the first substrate; metal lines are arranged in the first substrate, the metal lines including at least one first metal line and at least one second metal line; a portion of the metal contacts on the first surface of the first substrate are interconnected through the metal lines in the first substrate, and another portion of the metal contacts are electrically connected to metal contacts on a second surface of the first substrate through vias and metal lines in the first substrate; metal contacts on the second surface of the first substrate are electrically connected to metal contacts on the first surface of the second substrate, and metal contacts on the first surface of the second substrate are electrically connected to metal contacts on the second surface of the second substrate through vias and metal lines in the second substrate.
[0020] Optionally, the first metal contact and the second metal contact on the first surface of the first substrate are interconnected via the first metal line; and / or, the third metal contact and the fourth metal contact on the first surface of the first substrate are interconnected via the second metal line.
[0021] Optionally, the minimum spacing between metal contacts on the first surface of the first substrate is less than a first spacing threshold; the minimum spacing between metal contacts on the second surface of the second substrate is greater than a second spacing threshold, and the first spacing threshold is less than the second spacing threshold.
[0022] Optionally, the minimum spacing between metal contacts on the second surface of the first substrate is greater than the first spacing threshold and less than the second spacing threshold.
[0023] Optionally, the second substrate is a high-density interconnect printed circuit board.
[0024] Optionally, the second metal line and the first metal line are arranged in layers in the first substrate, the first metal line and the second metal line are in different layers, and the thickness of the first metal line is greater than the thickness of the second metal line.
[0025] Optionally, the width of the second metal wire is less than 10 micrometers.
[0026] Optionally, the number of grains may include one or more.
[0027] Optionally, the number of the first substrates may include one or more, and each of the first substrates may have at least one grain disposed thereon.
[0028] The silicon-based substrate and its manufacturing method and chip provided in the embodiments of the present invention have at least two vias in the substrate body. At least one of the at least two vias has any of the following positions: one end is located on the first surface of the substrate body and the other end is located inside the substrate body; one end is located on the second surface of the substrate body and the other end is located inside the substrate body; one end is located on the first surface of the substrate body and the other end is located on the second surface of the substrate body; or both ends are located inside the substrate body. This facilitates the electrical connection of the first and second surfaces of the substrate body, as well as the metal lines or metal contacts inside the substrate body, providing abundant available resources for the interconnection of die pins. Furthermore, since the cross-sectional area of the first via is larger than that of the second via, and the cross-sectional area of the first metal line is larger than that of the second metal line, the first via is easily connected to the first metal line, and the second via is easily connected to the second metal line. This allows for the interconnection of distant die pins using the larger cross-sectional area of the first metal line, reducing signal attenuation due to metal line impedance and ensuring signal quality. Simultaneously, it facilitates the interconnection of closer die pins using the smaller cross-sectional area of the second metal line, enabling high-density signal transmission. Thus, it is possible to achieve both short-distance, high-density signal transmission and long-distance, low-loss signal transmission using the same silicon substrate. Attached Figure Description
[0029] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0030] Figure 1 A schematic diagram of a silicon-based substrate provided for an embodiment of the present invention;
[0031] Figure 2 This is a schematic diagram of a via structure in an embodiment of the present invention;
[0032] Figure 3 This is a schematic diagram of another via structure in an embodiment of the present invention;
[0033] Figure 4 This is a schematic diagram of another via structure in an embodiment of the present invention;
[0034] Figure 5 This is a schematic diagram of yet another structure of the via in an embodiment of the present invention;
[0035] Figure 6 Another schematic diagram of a silicon-based substrate provided for an embodiment of the present invention;
[0036] Figure 7 A schematic diagram of yet another structure of a silicon-based substrate provided for an embodiment of the present invention;
[0037] Figure 8 A schematic diagram of another structure of a silicon-based substrate provided for an embodiment of the present invention;
[0038] Figure 9 A flowchart illustrating a method for manufacturing a silicon-based substrate according to an embodiment of the present invention;
[0039] Figure 10 for Figure 9 The illustrated embodiment corresponds to a process flow diagram;
[0040] Figure 11 This is a schematic diagram of a chip structure provided for an embodiment of the present invention. Detailed Implementation
[0041] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.
[0042] It should be understood that the described embodiments are merely some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.
[0043] In a first aspect, embodiments of the present invention provide a silicon-based substrate that facilitates both short-distance, high-density signal transmission and long-distance, low-loss signal transmission using the same silicon-based substrate.
[0044] Figure 1 A side view of a silicon-based substrate provided for an embodiment of the present invention. (See figure) Figure 1 As shown, the silicon-based substrate provided in the embodiments of the present invention may include:
[0045] A substrate body 1 has at least two vias 2, each via 2 including at least one first via 21 and at least one second via 22. The cross-sectional area of the first via 21 is larger than that of the second via 22. The first via 21 is used to electrically connect a first metal line 31 disposed in the substrate body 1, and the second via 22 is used to electrically connect a second metal line 32 disposed in the substrate body 1. The cross-sectional area of the first metal line 31 is larger than that of the second metal line 32. At least one of the at least two vias 2 has any of the following positions: one end is located on the first surface 11 of the substrate body 1, and the other end is located inside the substrate body 1; one end is located on the second surface 12 of the substrate body 1, and the other end is located inside the substrate body 1; one end is located on the first surface 11 of the substrate body 1, and the other end is located on the second surface 12 of the substrate body 1; both ends are located inside the substrate body 1. The first surface 11 of the substrate body 1 is used to dispose of grains, and the second surface 12 is opposite to the first surface 11.
[0046] The silicon substrate provided in the embodiments of the present invention has at least two vias 2 in the substrate body 1. At least one of the at least two vias 2 has any of the following positions: one end is located on the first surface 11 of the substrate body 1 and the other end is located inside the substrate body 1; one end is located on the second surface 12 of the substrate body 1 and the other end is located inside the substrate body 1; one end is located on the first surface 11 of the substrate body 1 and the other end is located on the second surface 12 of the substrate body 1; or both ends are located inside the substrate body 1. This facilitates the electrical connection of the first surface, the second surface, and the metal lines or metal contacts inside the substrate body, providing abundant resources for the interconnection of die pins. Furthermore, since the cross-sectional area of the first via 21 is larger than that of the second via 22, and the cross-sectional area of the first metal line 31 is larger than that of the second metal line 32, the first via 21 is easily connected to the first metal line 31, and the second via 22 is easily connected to the second metal line 32. This allows for the interconnection of distant die pins via the larger cross-sectional area of the first metal line 31, reducing signal attenuation due to metal line impedance and ensuring signal quality. Simultaneously, it facilitates the interconnection of closer die pins via the smaller cross-sectional area of the second metal line 32, enabling high-density signal transmission. Thus, it is possible to achieve both short-distance high-density signal transmission and long-distance low-loss signal transmission using the same silicon substrate.
[0047] In embodiments of the present invention, via 2 can refer to any hole in a silicon substrate used for electrically connecting metal lines of different layers. Depending on whether the openings at both ends of the via 2 are located on the surface of the substrate body 1, the via 2 can be further classified into the following types. It should be noted that the via 2 here can include either a first via 21 with a larger cross-sectional area or a second via 22 with a smaller cross-sectional area.
[0048] like Figure 2 As shown, in one embodiment of the present invention, at least one of the at least two vias 2 may have one end located on the first surface 11 of the substrate body 1, and the other end located inside the substrate body 1. Such vias 2 can be used to electrically connect metal contacts on the first surface 11 of the substrate body 1 to metal lines inside the substrate body 1. Alternatively, as... Figure 3 As shown, in another embodiment of the present invention, at least one of the at least two vias 2 may have one end located on the second surface 12 of the substrate body 1, and the other end located inside the substrate body 1. Such vias 2 can be used to electrically connect metal lines inside the substrate body 1 to metal contacts on the second surface 12 of the substrate body 1. Alternatively, as... Figure 4As shown, in another embodiment of the present invention, at least one of the at least two vias 2 may have one end located on the first surface 11 of the substrate body 1, and the other end located on the second surface 12 of the substrate body 1. Such vias 2 can be used to electrically connect metal contacts on the first surface 11 of the substrate body 1 to metal contacts on the second surface 12 of the substrate body 1. Alternatively, as... Figure 5 As shown, in another embodiment of the present invention, at least one of the at least two vias 2 can have both ends located inside the substrate body 1; such vias 2 can be used to electrically connect two metal lines of different layers inside the substrate body 1. Various interconnections of metal lines of different layers can be effectively achieved through these vias 2.
[0049] In specific implementations, the interconnection between die pins can be determined as needed, using either a first via 21 and a first metal line 31, or a second via 22 and a second metal line 32. Since the first via 21 and the first metal line 31 have large cross-sectional areas, they can support signal transmission over longer distances. Therefore, in one embodiment of the invention, the length of the first metal line 31 can be greater than a first length threshold, so that when the signal transmission distance is greater than the first length threshold, the first metal line 31 and the first via 21 are used for interconnection. Conversely, the length of the second metal line 32 can be less than or equal to the first length threshold, so that when the signal transmission distance is less than or equal to the first length threshold, the second metal line 32 and the second via 22 are used for interconnection. Optionally, the first length threshold can vary depending on the conductivity of the metal line; the better the conductivity, the larger the first length threshold, and the worse the conductivity, the smaller the first length threshold. For example, in one embodiment of the invention, for a metal line made of copper, the first length threshold can range from 4 mm to 6 mm, typically 5 mm.
[0050] In an embodiment of the present invention, the size of the via 2 can be represented by its cross-sectional area; a larger via has a larger cross-sectional area, and a smaller via has a smaller cross-sectional area. Since the first via 21 and the first metal line 31 are suitable for long-distance, low-loss signal transmission, and the second via 22 and the second metal line 32 are suitable for short-distance, high-density signal transmission, i.e., they have different task assignments, in order to more effectively complete both long-distance, low-loss signal transmission and short-distance, high-density signal transmission tasks, in one embodiment of the present invention, the cross-sectional areas of the first via 21 and the second via 22 can be manufactured to have a significant difference. For example, in one embodiment of the present invention, the cross-sectional area of the first via 21 can be greater than a first area threshold, and the cross-sectional area of the second via 22 can be less than a second area threshold, wherein the first area threshold is greater than or equal to the second area threshold. The specific values of the first and second area thresholds can be set or adjusted according to specific process parameters. Optionally, to ensure a significant difference between the cross-sectional area of the first via 21 and the cross-sectional area of the second via 22, in another embodiment of the invention, the difference between the cross-sectional areas of the first via 21 and the second via 22 can be defined by the ratio of their cross-sectional areas. For example, the ratio of the cross-sectional area of the first via 21 to the cross-sectional area of the second via 22 can be greater than or equal to a first ratio threshold. Optionally, the first ratio threshold can be, for example, 2:1, 4:1, 5:1, 9:1, 16:1, etc.
[0051] In the embodiments of the present invention, the first via 21 and the second via 22 are used to electrically connect metal lines in different layers of the substrate body. Therefore, as long as the above-mentioned effective electrical connection can be achieved, the specific shape of each via 2 is not limited. For example, each via 2 can be circular, elliptical, rectangular, polygonal, etc. The specific shape can be set and changed according to the layout. Moreover, the shapes of each via 2 can be the same or different.
[0052] Furthermore, since the interconnection of die pins is often complex and diverse, the distribution of metal lines and vias used for interconnection can vary to achieve such interconnection. For example, multiple layers of metal lines can be laid on the substrate, and an insulating dielectric layer can be provided between adjacent metal lines. Any two metal lines from different layers can be electrically connected through vias 2. Specifically, the first metal line 31 with a larger cross-sectional area can be electrically connected through the first via 21, and the second metal line 32 with a smaller cross-sectional area can be electrically connected through the second via 22.
[0053] Optionally, to facilitate electrical connections between different layers of metal lines, the vias 2 can be positioned or arranged arbitrarily as needed, and the embodiments of the present invention do not limit this. For example, in one embodiment of the present invention, a certain distribution area can be planned for the first via 21 and a certain distribution area can be planned for the second via 22, so that the distribution of the two vias in the substrate has a clear boundary. Alternatively, the first via 21 and the second via 22 can be staggered or randomly distributed, thereby making the distribution of vias in the substrate more uniform and optimizing stress and electrical performance.
[0054] For example, such as Figures 6 to 8 As shown, in one embodiment of the present invention, within at least a partial spatial region within the substrate body 1, the first via 21 and the second via 22 may be arranged alternately in a direction parallel to the first surface 11 of the substrate body 1 and / or in a direction perpendicular to the first surface 11 of the substrate body 1. Here, the first surface 11 of the substrate body 1 can be any surface of the substrate body 1, for example, a surface used for laying out grains. Figure 6 The first via 21 and the second via 22 are arranged alternately in a direction parallel to the first surface 11 of the substrate body 1. Figure 7 The first via 21 and the second via 22 are arranged alternately in a direction perpendicular to the first surface 11 of the substrate body 1. Figure 8 The first via 21 and the second via 22 are arranged alternately in both the direction parallel to the first surface 11 of the substrate body 1 and the direction perpendicular to the first surface 11 of the substrate body 1.
[0055] As mentioned earlier, the first via 21 and the first metal line 31, due to their larger cross-sectional areas, are more suitable for long-distance, low-loss signal transmission, while the second via 22 and the second metal line 32, due to their smaller cross-sectional areas, are more suitable for short-distance, high-density signal transmission. In one embodiment of the present invention, since the first surface 11 of the substrate body 1 is used to lay out the die, in order to minimize the length of the second metal line 32 and avoid causing more signal loss, the second metal line 32 for electrical connection in the second via 22 and the first metal line 31 for electrical connection in the first via 21 can be laid out in layers in the substrate body 1. The layer containing the second metal line 32 can be closer to the first surface 11 of the substrate body 1, that is, closer to the die, compared to the layer containing the first metal line 31. Since the first metal lines 31 of different layers are electrically connected through the first via 21, and the second metal lines 32 of different layers are electrically connected through the second via 22, the second via 22 can also be distributed relatively close to the first surface 11 of the substrate body 1. For example, in one embodiment of the present invention, one end of the second via 22 may be located on the first surface 11 of the substrate body 1, and the other end may be located inside the substrate body 1.
[0056] Optionally, in one embodiment of the present invention, the layer containing the first metal line 31 can be closer to either the first surface 11 or the second surface 12 of the substrate body 1. Correspondingly, the distribution of the first via 21 used for electrically connecting the first metal line 31 is not particularly limited. For example, in one embodiment of the present invention, one end of the first via 21 can be located on the first surface 11 of the substrate body 1, and the other end can be located inside the substrate body 1; or, one end of the first via 21 can be located on the second surface 12 of the substrate body 1, and the other end can be located inside the substrate body 1; or, one end of the first via 21 can be located on the first surface 11 of the substrate body 1, and the other end can be located on the second surface 12 of the substrate body 1; or, both ends of the first via 21 can be located inside the substrate body 1.
[0057] Accordingly, embodiments of the present invention also provide a method for manufacturing a substrate, which facilitates the effective balancing of short-distance, high-density signal transmission and long-distance, low-loss signal transmission in chip packaging.
[0058] Figure 9 A flowchart of a silicon-based substrate manufacturing method provided for embodiments of the present invention. Figure 10 for Figure 9 The corresponding process flow diagram, combined with Figure 9 and Figure 10 The method for manufacturing a silicon-based substrate provided in the embodiments of the present invention may include:
[0059] S31, Providing a silicon-based substrate;
[0060] In embodiments of the present invention, the substrate material can refer to the load-bearing plate in the substrate. Various circuits in the substrate can be implemented based on the substrate material through further processing techniques.
[0061] S32. At least one third via and at least one fourth via are provided on the substrate, wherein the cross-sectional area of the third via is larger than the cross-sectional area of the fourth via, and both the third via and the fourth via penetrate the substrate.
[0062] S33. On the substrate material having the third via and the fourth via, at least one insulating dielectric layer is provided, the at least one insulating dielectric layer including a first insulating dielectric layer; the substrate material and the at least one insulating dielectric layer form the substrate body of the silicon-based substrate;
[0063] Optionally, after forming the third and fourth vias on the substrate, one or more insulating dielectric layers can be further formed. The first insulating dielectric layer mentioned in this step can be any one of these insulating dielectric layers. Figure 10The first insulating dielectric layer shown can also be any of the insulating dielectric layers.
[0064] S34. A first etching barrier layer is provided on the first insulating dielectric layer, wherein at least one first via pattern and at least one second via pattern are provided in the first etching barrier layer, and the area of the first via pattern is greater than the area of the second via pattern.
[0065] An etch stop layer, in semiconductor etching processes, refers to a masking layer used to partially expose and partially block the surface to be etched, based on a pattern therein. Under the protection of the etch stop layer, after etching, the pattern in the etch stop layer can be transferred to the etched object. In one embodiment of the present invention, the etch stop layer can be a patterned photoresist after exposure and development, or other masking materials forming corresponding patterns based on the photoresist, such as silicon dioxide. Specifically, in this embodiment, the first etch stop layer is an etch masking material for the first insulating dielectric layer, and the first via pattern and the second via pattern in the first etch stop layer are the patterns to be transferred to the first insulating dielectric layer.
[0066] S35. Under the protection of the first etching barrier layer, at least one first via corresponding to the at least one first via pattern and at least one second via corresponding to the at least one second via pattern are etched on the first insulating dielectric layer, wherein the cross-sectional area of the first via is larger than the cross-sectional area of the second via; wherein each of the first via, each of the second via, each of the third via, and each of the fourth via forms a substrate via by staggering or aligning the upper and lower layers.
[0067] The vias on the substrate are located in any of the following positions: one end is located on the first surface of the substrate body and the other end is located inside the substrate body; one end is located on the second surface of the substrate body and the other end is located inside the substrate body; one end is located on the first surface of the substrate body and the other end is located on the second surface of the substrate body; both ends are located inside the substrate body; wherein the first surface of the substrate body is used to lay out the grains, and the second surface is opposite to the first surface.
[0068] In this step, a patterned first etch barrier layer is covered on the first insulating dielectric layer. Under the protection of the first etch barrier layer, the first insulating dielectric layer exposed outside the first etch barrier layer can be etched by etching liquid or etching gas. The etching depth can be controlled by the etching time until the first insulating dielectric layer is etched through. That is, at least one first via and at least one second via are formed on the first insulating dielectric layer, wherein the cross-sectional area of the first via is larger than the cross-sectional area of the second via.
[0069] In embodiments of the present invention, each of the first vias, the second vias, the third vias, and the fourth vias can be interconnected by staggering or aligning their upper and lower layers. Since the cross-sectional area of the first via is larger than that of the second via, and the cross-sectional area of the third via is larger than that of the fourth via, the first and third vias are more suitable for connecting thicker metal wires, while the second and fourth vias are more suitable for connecting thinner metal wires. Based on this, in one embodiment of the present invention, when the first and third vias are aligned vertically, the substrate vias formed by the first and third vias allow metal wires passing through the substrate vias to penetrate the substrate material for interconnection. When the first and third vias are staggered vertically, the first and third vias can each form two independent substrate vias, achieving interconnection of different metal wires. Similarly, when the second and fourth vias are aligned vertically, the substrate vias formed by the second and fourth vias allow metal lines passing through the substrate vias to penetrate the substrate material and achieve interconnection. When the second and fourth vias are staggered vertically, the second and fourth vias can each form two independent substrate vias, achieving different metal line interconnections respectively.
[0070] The silicon substrate manufacturing method provided in the embodiments of the present invention includes a third via and a fourth via on a substrate substrate, a first via and a second via on a first insulating dielectric layer of the substrate substrate, and substrate vias formed by staggering or aligning the first, second, third, and fourth vias between upper and lower layers. The substrate vias are located in any of the following positions: one end is located on the first surface of the substrate body, and the other end is located inside the substrate body; one end is located on the second surface of the substrate body, and the other end is located inside the substrate body; one end is located on the first surface of the substrate body, and the other end is located on the second surface of the substrate body; or both ends are located inside the substrate body. This facilitates the electrical connection of the first and second surfaces of the substrate body, as well as the metal lines or metal contacts inside the substrate body, providing abundant available resources for the interconnection of die pins. Since the cross-sectional area of the first via is larger than that of the second via, the first via is easy to connect to thicker metal lines, and the second via is easy to connect to thinner metal lines. This facilitates the interconnection of die pins that are far apart using thicker metal lines, reducing the signal attenuation caused by metal line impedance and ensuring the quality of transmitted signals. At the same time, it facilitates the interconnection of die pins that are close together using thinner metal lines, enabling high-density signal transmission. This allows for both short-distance high-density signal transmission and long-distance low-loss signal transmission on the same silicon substrate.
[0071] Optionally, in step S32, when fabricating the third and fourth vias on the substrate, in order to ensure a significant difference between the cross-sectional areas of the third and fourth vias, in one embodiment of the present invention, the difference between the cross-sectional areas of the third and fourth vias can be limited by the ratio of their cross-sectional areas. For example, the ratio of the cross-sectional areas of the third and fourth vias can be greater than or equal to a first ratio threshold. Optionally, the first ratio threshold can be, for example, 2:1, 4:1, 5:1, 9:1, 16:1, etc.
[0072] In specific implementation, at least one third via and at least one fourth via can be formed on the substrate using etching or laser processes. Specifically, forming at least one third via and at least one fourth via on the substrate using etching can include: fabricating a second etch barrier layer on a first surface of the substrate, the second etch barrier layer containing third and fourth via patterns; and etching the third via corresponding to the third via pattern and the fourth via corresponding to the fourth via pattern on the substrate under the protection of the second etch barrier layer. Optionally, after etching the third and fourth vias, the second etch barrier layer can be removed.
[0073] Furthermore, under the protection of the second etching barrier layer, after etching the third via corresponding to the third via pattern and the fourth via corresponding to the fourth via pattern on the substrate, the silicon substrate manufacturing method provided in the embodiments of the present invention may further include: thinning the substrate from the second surface of the substrate so that the third via and the fourth via are exposed from the thinned surface, wherein the second surface of the substrate is opposite to the first surface of the substrate.
[0074] In step S35, when fabricating the first via and the second via on the first insulating dielectric layer, the positions of the first via and the second via on the first insulating dielectric layer can be set at any position or arranged arbitrarily as needed, and the embodiments of the present invention do not limit this. For example, in one embodiment of the present invention, a certain distribution area can be planned for the first via and a certain distribution area can be planned for the second via, so that the distribution of the two vias in the substrate has a clear boundary, or the first via and the second via can be staggered or randomly distributed. For example, the first via and the second via on the first insulating dielectric layer can be staggered in the width direction and / or length direction of the first insulating dielectric layer, so that the distribution of vias in the substrate is more uniform and the stress and electrical performance are optimized.
[0075] Furthermore, to enable the first and second vias on the first insulating layer to effectively assist in the signal interconnection of the die, in one embodiment of the present invention, after etching at least one first via corresponding to the at least one first via pattern and at least one second via corresponding to the at least one second via pattern on the first insulating dielectric layer in step S35, the silicon substrate manufacturing method provided by the embodiment of the present invention may further include: laying a first metal line and a second metal line on the first insulating dielectric layer; wherein, the first metal line is electrically connected to the first via, the second metal line is electrically connected to the second via, and the cross-sectional area of the first metal line is larger than the cross-sectional area of the second metal line. Optionally, the first metal line and the second metal line can be disposed on the first insulating dielectric layer by a combination of damascene process and chemical vapor deposition, sputtering, etc.
[0076] To protect the first and second metal lines laid on the first insulating dielectric layer and thus enable effective signal interconnection, in one embodiment of the present invention, after laying the first and second metal lines on the first insulating dielectric layer, the silicon substrate manufacturing method provided by the embodiment of the present invention may further include: setting a second insulating dielectric layer on the first insulating dielectric layer on which the first and second metal lines are laid; etching at least one fifth via and at least one sixth via on the second insulating dielectric layer, wherein the absolute value of the difference between the cross-sectional area of the fifth via and the cross-sectional area of the first via is less than a preset threshold, and the absolute value of the difference between the cross-sectional area of the sixth via and the cross-sectional area of the second via is less than the preset threshold. The preset threshold may be a value relatively small compared to the cross-sectional area of the via, for example, a value at least one order of magnitude smaller than the cross-sectional area of the via, thereby ensuring that the cross-sectional areas of the first via and the fifth via are approximately equal, and the cross-sectional areas of the second via and the sixth via are approximately equal. In embodiments of the present invention, a fifth via can be used to electrically connect a first metal wire laid on a first insulating dielectric layer, and a sixth via can be used to electrically connect a second metal wire laid on the first insulating dielectric layer. Optionally, the fifth via and the first via can be aligned vertically or staggered vertically, and the sixth via and the second via can be aligned vertically or staggered vertically. When the fifth via and the first via are aligned vertically, the second insulating dielectric layer and the first insulating dielectric layer can be connected to form a cross-layer metal wire connection. When the fifth via and the first via are staggered vertically, the vias can be more evenly distributed in the substrate, and the stress and electrical performance can be optimized. Similarly, when the sixth via and the second via are aligned vertically, the second insulating dielectric layer and the first insulating dielectric layer can be connected to form a cross-layer metal wire connection. When the sixth via and the second via are staggered vertically, the vias can be more evenly distributed in the substrate, and the stress and electrical performance can be optimized.
[0077] Accordingly, embodiments of the present invention also provide a chip that facilitates both short-distance, high-density signal transmission and long-distance, low-loss signal transmission on the same silicon substrate.
[0078] The chip provided in the embodiments of the present invention may include a substrate and at least one die disposed on the substrate, wherein the substrate is any of the silicon-based substrates provided in the foregoing embodiments, a first metal contact on the die is electrically connected to a first metal line in the substrate, and a second metal contact on the die is electrically connected to a second metal line in the substrate; wherein the first metal line is electrically connected to a first via, and the second metal line is electrically connected to a second via.
[0079] The chip provided in the embodiments of the present invention utilizes any of the silicon-based substrates provided in the foregoing embodiments for die interconnection, thus achieving the corresponding beneficial technical effects, which have been described in detail above and will not be repeated here.
[0080] Accordingly, embodiments of the present invention also provide a chip that facilitates both short-distance, high-density signal transmission and long-distance, low-loss signal transmission on the same silicon substrate.
[0081] like Figure 11 As shown, the chip provided in the embodiments of the present invention may include: a first substrate 10, a second substrate 20, and a die 30; wherein, the first substrate 10 is any of the silicon-based substrates provided in the foregoing embodiments; at least a portion of the pins of the die 30 are electrically connected to metal contacts 110 on the first surface 101 of the first substrate 10; metal lines 102 are arranged in the first substrate 10, and the metal lines 102 may include at least one first metal line 1021 and at least one second metal line 1022, wherein the cross-sectional area of the first metal line 1021 is larger than the cross-sectional area of the second metal line 1022;
[0082] A portion of the metal contacts on the first surface 101 of the first substrate 10 can be interconnected by the metal wire 102 in the first substrate 10, and another portion of the metal contacts can be electrically connected to the metal contacts 140 on the second surface 104 of the first substrate 10 through the via 103 and the metal wire 102 in the first substrate 10.
[0083] The metal contacts 140 on the second surface 104 of the first substrate 10 are electrically connected to the metal contacts on the first surface 201 of the second substrate 20. The metal contacts on the first surface 201 of the second substrate 20 are electrically connected to the metal contacts on the second surface 204 of the second substrate 20 through the via 203 and the metal line 202 in the second substrate 20.
[0084] The chip provided in the embodiments of the present invention has at least a portion of the pins of the die 30 electrically connected to metal contacts 110 on the first surface 101 of the first substrate 10. Metal lines 102 are arranged in the first substrate 10. A portion of the metal contacts on the first surface 101 of the first substrate 10 can be interconnected through the metal lines 102 in the first substrate 10. Another portion of the metal contacts can be electrically connected to metal contacts 140 on the second surface 104 of the first substrate 10 through vias 103 and the metal lines 102 in the first substrate 10, and further electrically connected to the second substrate 20. Since the first substrate... The metal lines 102 in board 10 include both a first metal line 1021 with a larger cross-sectional area and a second metal line 1022 with a smaller cross-sectional area. In this way, the first metal line 1021 with a larger cross-sectional area can be used to interconnect die pins that are far apart, so as to reduce the signal attenuation caused by the metal line impedance and ensure the quality of the transmitted signal. At the same time, the second metal line 1022 with a smaller cross-sectional area can be used to interconnect die pins that are close together, so as to realize high-density signal transmission, thereby facilitating short-distance high-density signal transmission and long-distance low-loss signal transmission.
[0085] It should be noted that the various metal contacts described in the embodiments of the present invention can refer to metal contact points with electrical connection functions in general, without limiting the specific form and shape of the metal contact point. For example, the metal contact point can be a planar metal point, or a metal bump or metal ball protruding from the surface.
[0086] Optionally, in embodiments of the present invention, the packaged chip may include one or more dies 30, which may be disposed on one or more first substrates 10. That is, the number of dies 30 may include one or more, and the number of first substrates 10 may also include one or more. Each first substrate 10 may be disposed on a second substrate 20, wherein each first substrate 10 may be provided with one or more dies 30.
[0087] Optionally, the second substrate 20 can be a variety of substrates suitable for chip packaging. For example, in one embodiment of the present invention, the second substrate 20 can be a high-density interconnect printed circuit board.
[0088] In specific implementations, when interconnecting the pin signals of the die, in order to more effectively achieve the effect of reducing signal loss with the first metal line 1021 and increasing signal interconnection density with the second metal line 1022, in one embodiment of the present invention, the cross-sectional areas of the first metal line 1021 and the second metal line 1022 can have a large difference. For example, the cross-sectional area of the first metal line 1021 can be greater than a first area threshold, and the cross-sectional area of the second metal line 1022 can be less than a second area threshold. The first area threshold can be greater than or equal to the second area threshold. For example, the first area threshold can be one of the following area thresholds: 4 square micrometers, 10 square micrometers, or 100 square micrometers. Furthermore, the width of the second metal line 1022 can also be limited. For example, the width of the second metal line 1022 can be limited to less than 10 micrometers, so that more second metal lines 1022 can be arranged per unit area of the first substrate 10, effectively increasing the signal interconnection density of the second metal lines 1022.
[0089] The chip provided in the embodiments of the present invention can refer to a chip product obtained by packaging the die 30. To achieve signal interconnection between different pins of the same die 30, or between pins of different dies 30, in the embodiments of the present invention, the die 30 can be disposed on a first substrate 10, so that the above-mentioned signal interconnection is achieved through metal lines 102 arranged in the first substrate 10. Optionally, when multiple layers of metal lines 102 are arranged in the first substrate 10, the metal lines 102 of different layers can be further electrically connected through vias 103 in the first substrate 10.
[0090] Furthermore, in order to facilitate the application of the chip, such as to facilitate the placement of the packaged chip on the device motherboard or to connect it with other external circuits, in the embodiments of the present invention, in addition to interconnecting the pins of the die 30 with the metal line 102, the first substrate 10 can also lead the pin signals of the die 30 to the second substrate 20 through the metal line 102 and the via 13, so as to electrically connect the second substrate 20 to the device motherboard or other external circuits.
[0091] Optionally, both the metal line 102 used for interconnecting die pin signals and the metal line 102 used for leading die pin signals to the second substrate 20 can be implemented using a first metal line 1021 with a larger cross-sectional area or a second metal line 1022 with a smaller cross-sectional area, depending on the length of the path between the signal transmission endpoints. For example, in one embodiment of the present invention, the first metal contact and the second metal contact on the first surface 101 of the first substrate 10 can be interconnected using the first metal line 1021; and / or, the third metal contact and the fourth metal contact on the first surface 101 of the first substrate 10 can be interconnected using the second metal line 1022. That is to say, in this embodiment, the metal line 102 used to realize the interconnection of die pin signals can include the first metal line 1021, the second metal line 1022, or both. Similarly, in another embodiment of the present invention, the metal line 102 for leading the die pin signal to the second substrate 20 may include a first metal line 1021, a second metal line 1022, or both.
[0092] To facilitate the selection of either the first metal wire 1021 or the second metal wire 1022 for signal interconnection based on the path length between signal transmission endpoints, in one embodiment of the present invention, the lengths of the first metal wire 1021 and the second metal wire 1022 can be set within a certain range. For example, the length of the first metal wire 1021 can be greater than a preset length threshold, and the length of the second metal wire 1022 can be less than or equal to the preset length threshold. Optionally, the preset length threshold can range from 4 mm to 6 mm, for example, 5 mm. Thus, if the path between the signal transmission endpoints is greater than the preset length threshold, signal interconnection can be performed using the first metal wire 1021; if the path between the signal transmission endpoints is less than or equal to the preset length threshold, signal interconnection can be performed using the second metal wire 1022.
[0093] To enable the transmission of more signals in the first substrate 10, a larger number of metal lines 102 can be arranged in the first substrate 10. When the metal lines 102 cannot be arranged on a single plane, they can be arranged in layers, and the metal lines 102 in different layers can be isolated by an insulating dielectric layer. For example, in one embodiment of the present invention, the metal lines 102 can be arranged in one or more layers in the first substrate 10, and an insulating dielectric layer is provided between the metal lines 102 in different layers. The metal lines 102 in different layers can be electrically connected through vias in the insulating dielectric layer. Optionally, in an embodiment of the present invention, the vias 103 in the first substrate 10 may include at least one first via and at least one second via, wherein the first via can be electrically connected to the first metal line 1021, the second via can be electrically connected to the second metal line 1022, and the cross-sectional area of the first via is larger than that of the second via.
[0094] Optionally, the first metal line 1021 and the second metal line 1022 can be located in the same layer or in different layers. For example, in one embodiment of the present invention, the second metal line 1022 and the first metal line 1021 are arranged in layers in the first substrate 10, and the layer containing the second metal line 1022 is closer to the first surface 101 of the first substrate 10 than the layer containing the first metal line 1021. In this way, since the die 30 is disposed on the first surface 101 of the first substrate 10, the second metal line 1022 will be closer to the die 30 than the first metal line 1021, thereby effectively reducing the length of the second metal line 1022 and reducing the signal transmission loss of the second metal line 1022.
[0095] Furthermore, when the first metal line 1021 and the second metal line 1022 are on the same layer, the difference in cross-sectional area between the first metal line 1021 and the second metal line 1022 can be achieved by using different widths of the metal lines. When the first metal line 1021 and the second metal line 1022 are on different layers, the difference in cross-sectional area between the first metal line 1021 and the second metal line 1022 can be achieved by using different widths and / or different thicknesses of the metal lines. For example, in one embodiment of the present invention, the second metal line 1022 and the first metal line 1021 are arranged in layers on the first substrate 10, with the first metal line 1021 and the second metal line 1022 on different layers, and the thickness of the first metal line 1021 can be greater than the thickness of the second metal line 1022.
[0096] Generally, compared to packaged chip products, the area and volume of the die 30 are relatively small, therefore the pin spacing of the same die 30 is also small. For example, in one embodiment of the present invention, the minimum distance between the pins of the same die 30 can be 40 micrometers to 150 micrometers. However, the minimum spacing between pads in external circuits such as motherboards is generally larger, for example, 800 micrometers to 1000 micrometers. In view of this, in order to facilitate the connection of the die 30 to external circuits such as motherboards, in embodiments of the present invention, a transition can be made using the first substrate 1 and the second substrate 2 to gradually transition the pin spacing of 40 micrometers to 150 micrometers to the pad spacing of 800 micrometers to 1000 micrometers.
[0097] Specifically, in one embodiment of the present invention, in chip packaging, the die 30 can be disposed on the first surface 101 of the first substrate 10, for example, by a process such as flip-chip bonding. The first substrate 10 can also be disposed on the first surface 201 of the second substrate 20 by a process such as flip-chip bonding. The second surface 204 of the second substrate 20 can be used for electrical connection with external circuits such as a motherboard. The minimum spacing between the metal contacts 110 on the first surface 101 of the first substrate 10 can be less than a first spacing threshold, and the minimum spacing between the metal contacts on the second surface 204 of the second substrate 20 can be greater than a second spacing threshold, wherein the first spacing threshold can be less than the second spacing threshold. For example, in one example, the first spacing threshold can be 100 micrometers, and the second spacing threshold can be 800 micrometers.
[0098] To smoothly transition from the minimum spacing between metal contacts 110 on the first surface 101 of the first substrate 10 to the minimum spacing between metal contacts on the second surface 204 of the second substrate 20, in one embodiment of the present invention, the minimum spacing between metal contacts 140 on the second surface 104 of the first substrate 10 can be further defined. For example, the minimum spacing between metal contacts 140 on the second surface 104 of the first substrate 10 can be greater than the aforementioned first spacing threshold and less than the aforementioned second spacing threshold. For example, in one example, the minimum spacing between metal contacts 140 can be between 350 micrometers and 600 micrometers.
[0099] Understandably, since the first substrate 10 is disposed on the first surface 201 of the second substrate 20 by flip-chip bonding, the metal contacts 140 on the second surface 104 of the first substrate 10 can correspond to the metal contacts on the first surface 201 of the second substrate 20, that is, the minimum spacing between the metal contacts is equal to the minimum spacing between the metal contacts 140.
[0100] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0101] The various embodiments in this specification are described in a related manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.
[0102] In particular, the device embodiment is basically similar to the method embodiment, so the description is relatively simple. For relevant details, please refer to the description of the method embodiment.
[0103] For ease of description, the above apparatus is described by dividing it into various functional units / modules. Of course, in implementing this invention, the functions of each unit / module can be implemented in one or more software and / or hardware.
[0104] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.
Claims
1. A silicon-based substrate, characterized in that, include: A substrate body having at least two vias, the at least two vias including at least one first via and at least one second via, the cross-sectional area of the first via being larger than the cross-sectional area of the second via; wherein, the first via is used for electrically connecting a first metal line disposed in the substrate body, and the second via is used for electrically connecting a second metal line disposed in the substrate body, the cross-sectional area of the first metal line being larger than the cross-sectional area of the second metal line. Wherein, at least one of the at least two vias has any of the following positions: One end is located on the first surface of the substrate body, and the other end is located inside the substrate body; One end is located on the second surface of the substrate body, and the other end is located inside the substrate body; One end is located on the first surface of the substrate body, and the other end is located on the second surface of the substrate body; Both ends are located inside the substrate body; The first surface of the substrate body is used to lay the grains, and the second surface is opposite to the first surface; The substrate body includes a substrate material and at least one insulating dielectric layer disposed on the substrate material, wherein the at least one insulating dielectric layer includes a first insulating dielectric layer. The substrate includes a third substrate via and a fourth substrate via. The cross-sectional area of the third substrate via is larger than that of the fourth substrate via, and both the third substrate via and the fourth substrate via penetrate the substrate. The first insulating dielectric layer includes at least one first dielectric via and at least one second dielectric via, wherein the cross-sectional area of the first dielectric via is larger than the cross-sectional area of the second dielectric via; Each of the first dielectric via, each of the second dielectric via, each of the third substrate via, and each of the fourth substrate via are connected by staggered or aligned upper and lower layers to form a substrate via, wherein the substrate via includes at least two vias; The second metal wire for electrical connection of the second via and the first metal wire for electrical connection of the first via are arranged in layers in the substrate body, and the layer where the second metal wire is located is closer to the first surface of the substrate body than the layer where the first metal wire is located. The length of the first metal wire is greater than a first length threshold, and the length of the second metal wire is less than or equal to the first length threshold.
2. The silicon-based substrate according to claim 1, characterized in that, The cross-sectional area of the first via is greater than a first area threshold, and the cross-sectional area of the second via is less than a second area threshold, wherein the first area threshold is greater than or equal to the second area threshold.
3. The silicon-based substrate according to claim 1, characterized in that, The ratio of the cross-sectional area of the first via to the cross-sectional area of the second via is greater than or equal to a first ratio threshold.
4. The silicon-based substrate according to claim 3, characterized in that, The first ratio threshold is 2:1, 4:1, 5:1, 9:1, or 16:
1.
5. The silicon-based substrate according to claim 1, characterized in that, In at least a partial spatial region within the substrate body, first vias and second vias are arranged alternately in a direction parallel to the first surface of the substrate body and / or in a direction perpendicular to the first surface of the substrate body.
6. The silicon-based substrate according to claim 1, characterized in that, The first length threshold ranges from 4 mm to 6 mm.
7. A method for manufacturing a silicon-based substrate, characterized in that, include: Provide silicon-based substrate materials; At least one third substrate via and at least one fourth substrate via are provided on the substrate, wherein the cross-sectional area of the third substrate via is larger than the cross-sectional area of the fourth substrate via, and both the third substrate via and the fourth substrate via penetrate the substrate. On the substrate substrate having the third substrate via and the fourth substrate via, at least one insulating dielectric layer is provided, the at least one insulating dielectric layer including a first insulating dielectric layer; the substrate substrate and the at least one insulating dielectric layer form the substrate body of the silicon-based substrate; A first etching barrier layer is provided on the first insulating dielectric layer. The first etching barrier layer is provided with at least one first via pattern and at least one second via pattern. The area of the first via pattern is larger than the area of the second via pattern. Under the protection of the first etching barrier layer, at least one first dielectric via corresponding to the at least one first via pattern and at least one second dielectric via corresponding to the at least one second via pattern are etched on the first insulating dielectric layer, wherein the cross-sectional area of the first dielectric via is greater than the cross-sectional area of the second dielectric via. Wherein, each of the first dielectric via, each of the second dielectric via, each of the third substrate via, and each of the fourth substrate via are interconnected by staggered or aligned upper and lower layers to form substrate vias, wherein the substrate vias are located in any of the following positions: One end is located on the first surface of the substrate body, and the other end is located inside the substrate body; One end is located on the second surface of the substrate body, and the other end is located inside the substrate body; One end is located on the first surface of the substrate body, and the other end is located on the second surface of the substrate body; Both ends are located inside the substrate body; The first surface of the substrate body is used to lay the grains, and the second surface is opposite to the first surface; After etching at least one first dielectric via corresponding to the at least one first via pattern and at least one second dielectric via corresponding to the at least one second via pattern on the first insulating dielectric layer, the method further includes: A first metal wire and a second metal wire are laid on the first insulating dielectric layer; wherein the first metal wire is electrically connected to the first dielectric via, the second metal wire is electrically connected to the second dielectric via, and the cross-sectional area of the first metal wire is larger than the cross-sectional area of the second metal wire. The second metal line and the first metal line are arranged in layers in the substrate body, and the layer containing the second metal line is closer to the first surface of the substrate body than the layer containing the first metal line. The length of the first metal wire is greater than a first length threshold, and the length of the second metal wire is less than or equal to the first length threshold.
8. The method according to claim 7, characterized in that, After laying the first metal wire and the second metal wire on the first insulating dielectric layer, the method further includes: A second insulating dielectric layer is provided on a first insulating dielectric layer on which a first metal wire and a second metal wire are laid; At least one fifth dielectric via and at least one sixth dielectric via are etched on the second insulating dielectric layer, wherein the absolute value of the difference between the cross-sectional area of the fifth dielectric via and the cross-sectional area of the first dielectric via is less than a preset threshold, the absolute value of the difference between the cross-sectional area of the sixth dielectric via and the cross-sectional area of the second dielectric via is less than the preset threshold, and the fifth dielectric via and the first dielectric via are aligned vertically or staggered vertically.
9. The method according to claim 7, characterized in that, The first dielectric via and the second dielectric via on the first insulating dielectric layer are arranged alternately in the width direction and / or length direction of the first insulating dielectric layer.
10. A chip, characterized in that, The invention includes a substrate and at least one die disposed on the substrate, wherein the substrate is a silicon-based substrate according to any one of claims 1 to 6, a first metal contact on the die is electrically connected to a first metal line in the substrate, and a second metal contact on the die is electrically connected to a second metal line in the substrate; wherein the first metal line is electrically connected to a first via, and the second metal line is electrically connected to a second via.
11. A chip, characterized in that, include: A first substrate, a second substrate, and a die, wherein the first substrate is a silicon-based substrate according to any one of claims 1 to 6; at least a portion of the pins of the die are electrically connected to metal contacts on a first surface of the first substrate; and metal lines are arranged in the first substrate, the metal lines including at least one first metal line and at least one second metal line. A portion of the metal contacts on the first surface of the first substrate are interconnected through metal lines in the first substrate, and another portion of the metal contacts are electrically connected to metal contacts on the second surface of the first substrate through vias and metal lines in the first substrate. The metal contacts on the second surface of the first substrate are electrically connected to the metal contacts on the first surface of the second substrate. The metal contacts on the first surface of the second substrate are electrically connected to the metal contacts on the second surface of the second substrate through vias and metal lines in the second substrate.
12. The chip according to claim 11, characterized in that, The first metal contact and the second metal contact on the first surface of the first substrate are interconnected via the first metal wire; and / or, The third and fourth metal contacts on the first surface of the first substrate are interconnected by the second metal line.
13. The chip according to claim 11, characterized in that, The minimum spacing between metal contacts on the first surface of the first substrate is less than a first spacing threshold; the minimum spacing between metal contacts on the second surface of the second substrate is greater than a second spacing threshold, and the first spacing threshold is less than the second spacing threshold.
14. The chip according to claim 13, characterized in that, The minimum spacing between metal contacts on the second surface of the first substrate is greater than the first spacing threshold and less than the second spacing threshold.
15. The chip according to claim 11, characterized in that, The second substrate is a high-density interconnect printed circuit board.
16. The chip according to claim 11, characterized in that, The second metal line and the first metal line are arranged in layers in the first substrate, and the first metal line and the second metal line are in different layers, and the thickness of the first metal line is greater than the thickness of the second metal line.
17. The chip according to claim 11, characterized in that, The width of the second metal wire is less than 10 micrometers.
18. The chip according to claim 11, characterized in that, The number of grains may include one or more.
19. The chip according to claim 11, characterized in that, The number of the first substrates includes one or more, and each first substrate has at least one grain disposed thereon.