Semiconductor Structure and Method of Forming the Same

Abstract

A semiconductor structure and a method for forming the same, wherein the method includes: providing a substrate having two discrete fin portions thereon, the two fin portions extending in a first direction and arranged in a second direction, the fin portions including a plurality of sacrificial layers overlapping on the substrate and horizontal fins between adjacent two sacrificial layers, there being an isolation opening between the two fin portions; forming an initial dielectric wall in the isolation opening; forming a gate across the two fin portions and the initial dielectric wall on the substrate; etching the two fin portions to form source-drain openings in each of the fin portions on both sides of the gate; thinning the initial dielectric wall exposed between adjacent source-drain openings to form a dielectric wall; and forming source-drain structures in the source-drain openings after forming the dielectric wall. Thus, while ensuring the reliability of the semiconductor structure, the performance of the semiconductor structure is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and particularly to a semiconductor structure and a method for forming the same. Background Art

[0002] In the existing semiconductor field, gate-all-around (GAA) devices have become a new direction of research and development in the industry. The feature of this technology is that the gate wraps around the channel on all four sides. The source and drain no longer contact the substrate. Instead, after multiple source and drain electrodes in the form of lines, plates or sheets are distributed horizontally perpendicular to the gate, the basic structure and function of a metal-oxide-semiconductor field-effect transistor (MOSFET) are realized. GAA devices largely solve various problems brought about by the reduction of the gate pitch size, including capacitance effects. At the same time, since the channel is wrapped by the gate on all four sides, the channel current is also smoother than that of the fin field-effect transistor (FinFET) which is wrapped on three sides.

[0003] With the further development of semiconductor technology, it is required that the spacing between PMOS devices and NMOS devices in a standard cell be smaller. However, for FinFET and GAA devices, the process limits the spacing between PMOS devices and NMOS devices. To expand the scalability of devices, Forksheet devices are considered a natural extension of GAA devices. Compared with GAA devices, the channel of Forksheet devices is controlled by a fork-shaped gate structure, which is achieved by introducing a "dielectric wall" between PMOS devices and NMOS devices before gate patterning. The dielectric wall physically isolates the gate trenches of PMOS devices from those of NMOS devices, thereby allowing a smaller spacing between PMOS devices and NMOS devices and having better scalability in terms of area and performance.

[0004] However, the technology of Forksheet devices is not yet perfect, and the performance of semiconductor devices still needs to be improved. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of the semiconductor structure while ensuring the reliability of the semiconductor structure.

[0006] To solve the above technical problems, the technical solution of the present invention provides a semiconductor structure, including: a substrate; a dielectric wall located on the substrate, the dielectric wall extending in a first direction; in a second direction, a plurality of horizontal fins on the side wall surfaces respectively located on both sides of the dielectric wall, the horizontal fins being parallel to the surface of the substrate, the plurality of horizontal fins being separated from each other, and, on each side wall surface of the dielectric wall, the plurality of horizontal fins being stacked in the direction of the normal of the substrate surface, the first direction and the second direction being perpendicular to each other; a gate structure spanning the dielectric wall and the plurality of horizontal fins in the second direction, and, the gate structure spanning the plurality of horizontal fins in the direction of the normal of the substrate surface; a source-drain structure located within the plurality of horizontal fins, and, the source-drain structure being located on both sides of the gate structure in the first direction, the source-drain structure being located on both sides of the dielectric wall in the second direction; in the second direction, the dielectric wall between adjacent horizontal fins has a first thickness, the dielectric wall between adjacent source-drain structures has a second thickness, and, the second thickness is less than the first thickness.

[0007] Optionally, the dielectric wall is a single-layer structure.

[0008] Optionally, the dielectric wall includes: an inner dielectric wall, and a surface dielectric wall located on the surface of the inner dielectric wall, the inner dielectric wall having a second thickness, the material of the inner dielectric wall being different from the material of the surface dielectric wall, and, the dielectric wall between the source-drain structures exposes the inner dielectric wall.

[0009] Optionally, the dielectric wall includes: a bottom dielectric wall, and a top dielectric wall located on the top surface of the bottom dielectric wall, the top surface of the bottom dielectric wall being higher than the surface of the horizontal fins, the material of the bottom dielectric wall being different from the material of the top dielectric wall, the bottom dielectric wall between the source-drain structures having the second thickness, and, the thickness of the top dielectric wall being greater than the second thickness.

[0010] Optionally, the height ratio of the top dielectric wall to the bottom dielectric wall is 1:3 to 2:3.

[0011] Optionally, it further includes: an isolation layer located on the surface of the substrate, and the gate structure is located on the isolation layer.

[0012] Optionally, the material of the dielectric wall includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxide, silicon carbonitride, and silicon carbon oxynitride.

[0013] Optionally, the ratio of the second thickness to the first thickness is 1 / 2 to 4 / 5.

[0014] Optionally, it further includes: a gate sidewall located on the sidewall surface of the gate structure, and, the gate sidewall is also located between the gate structure and the source-drain structure.

[0015] Optionally, the dielectric wall also extends into the substrate, and the dielectric wall within the substrate also has the first thickness.

[0016] Optionally, further comprising: bottom channel layers respectively located on two sides of the dielectric wall in a second direction, the bottom channel layers also being located on the substrate, a plurality of horizontal fins being located above the bottom channel layers, and the dielectric wall between adjacent bottom channel layers also having the first thickness.

[0017] Correspondingly, the technical solution of the present invention further provides a method for forming a semiconductor structure, including: providing a substrate, on which there are two discrete fin portions, the two fin portions extending along a first direction and arranged along a second direction, the first direction being perpendicular to the second direction, the fin portions including a plurality of sacrificial layers overlapping on the substrate, and horizontal fins between adjacent two sacrificial layers, there being an isolation opening between the two fin portions, the isolation opening exposing the adjacent side wall surfaces of the two fin portions, and the bottom surface of the isolation opening being lower than the bottom surface of any sacrificial layer; forming an initial dielectric wall in the isolation opening, the top surface of the initial dielectric wall being higher than the top surface of the horizontal fins; forming a gate across the two fin portions and the initial dielectric wall on the substrate; etching the two fin portions to form source-drain openings in each of the fin portions on both sides of the gate, the inner wall surface of the source-drain openings exposing the side wall of the initial dielectric wall; thinning the initial dielectric wall exposed between adjacent source-drain openings to form a dielectric wall, and, in the second direction, the dielectric wall between adjacent horizontal fins has a first thickness, and the dielectric wall between adjacent source-drain openings has a second thickness, the second thickness being smaller than the first thickness; after forming the dielectric wall, forming a source-drain structure in the source-drain openings.

[0018] Optionally, the initial dielectric wall is a single-layer structure.

[0019] Optionally, the method for thinning the initial dielectric wall exposed between adjacent source-drain openings includes: etching the side wall of the initial dielectric wall exposed by the inner wall surface of the source-drain openings.

[0020] Optionally, the method for etching the side wall of the initial dielectric wall exposed by the inner wall surface of the source-drain openings includes: etching the exposed side wall of the initial dielectric wall by using a wet etching process to thin the initial dielectric wall between the source-drain openings to a third thickness, the third thickness being greater than the second thickness; after the wet etching process, using an anisotropic dry etching process to etch the exposed side wall of the initial dielectric wall in a direction perpendicular to the surface of the substrate to form the dielectric wall.

[0021] Optionally, the initial dielectric wall includes: an inner dielectric wall and a surface dielectric wall located on the surface of the inner dielectric wall. The material of the inner dielectric wall is different from that of the surface dielectric wall, and the inner dielectric wall has the second thickness.

[0022] Optionally, the method for thinning the initial dielectric wall exposed between adjacent source-drain openings includes: etching the sidewalls of the exposed surface dielectric wall until the sidewall surfaces of the inner dielectric wall are exposed.

[0023] Optionally, the initial dielectric wall includes: a bottom dielectric wall and a top dielectric wall located on the top surface of the bottom dielectric wall. The top surface of the bottom dielectric wall is higher than the surface of the horizontal fin, and the material of the bottom dielectric wall is different from that of the top dielectric wall.

[0024] Optionally, the method for thinning the initial dielectric wall exposed between adjacent source-drain openings includes: etching the sidewalls of the bottom dielectric wall and the top dielectric wall exposed by the inner wall surfaces of the source-drain openings, and during the etching process, the etching rate of the material of the bottom dielectric wall is greater than that of the material of the top dielectric wall.

[0025] Optionally, it further includes: forming a dielectric film on the surface of the fin before forming the initial dielectric wall.

[0026] Optionally, it further includes: forming an isolation layer on the surface of the substrate after forming the initial dielectric wall and before forming the gate.

[0027] Optionally, it further includes: forming an initial interlayer dielectric layer on the surface of the substrate, the surface of the source-drain structure, the surface of the dielectric wall, the surface of the fin, and the sidewall surfaces of the gate after forming the source-drain structure. The initial interlayer dielectric layer exposes the top surface of the gate; etching the exposed gate until the surface of the isolation layer is exposed, forming a gate opening in the initial interlayer dielectric layer; etching a plurality of sacrificial layers exposed in the gate opening until the sacrificial layers are removed, forming gate grooves between adjacent two layers of horizontal fins and between the horizontal fins and the substrate; forming an initial gate structure in the gate opening and the gate grooves, the top surface of the initial gate structure being higher than the top surface of the dielectric wall; planarizing the initial gate structure and the initial interlayer dielectric layer until the top surface of the dielectric wall is exposed, forming a gate structure and an interlayer dielectric layer, the top surface of the gate structure being flush with the top surface of the dielectric wall.

[0028] Optionally, the fin further includes a bottom channel layer located on the substrate, a plurality of sacrificial layers and a plurality of horizontal fins are located above the bottom channel layer, and the bottom of the isolation opening exposes the surface of the substrate, and the source-drain opening exposes the surface of the bottom channel layer.

[0029] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0030] In the method for forming a semiconductor structure provided by the technical solution of the present invention, since an initial dielectric wall with a top surface higher than the top surface of the horizontal fin is formed in the isolation opening, and before forming the source / drain structure in the source / drain opening, the initial dielectric wall exposed between adjacent source / drain openings is thinned to form a dielectric wall, therefore, the thickness (second thickness) of the dielectric wall between the source / drain openings adjacent in the second direction is smaller than the thickness (first thickness) of the initial dielectric wall. Thus, on the one hand, the dielectric wall under the gate is higher and has a larger thickness (first thickness). Consequently, the subsequently formed gate structure can be better spaced apart by the higher and thicker part of the dielectric wall. Furthermore, not only is the insulation between adjacent gate structures good, ensuring the reliability of the semiconductor structure, but also the parasitic capacitance between adjacent gate structures is smaller, improving the performance of the semiconductor structure. On the other hand, the thickness (second thickness) of the dielectric wall between adjacent source / drain openings is smaller, increasing the space provided for forming the source / drain structure. Thus, a source / drain structure with a larger size can be formed to improve the performance of the semiconductor structure. In summary, while ensuring the reliability of the semiconductor structure, the performance of the semiconductor structure is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figures 1 to 4 is a schematic structural diagram of a semiconductor structure formation process;

[0032] Figures 5 to 19 is a schematic structural diagram corresponding to each step in the method for forming a semiconductor structure according to an embodiment of the present invention;

[0033] Figures 20 to 32 is a schematic structural diagram corresponding to each step in the method for forming a semiconductor structure according to another embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0034] As described in the background art, the performance of semiconductor devices in the prior art still needs to be improved. Now, a semiconductor structure is combined for illustration and analysis.

[0035] Figures 1 to 4 is a schematic cross-sectional view of a semiconductor structure formation process.

[0036] Please refer to Figure 1 , a substrate 100 is provided, and there are 2 mutually discrete fin portions 110 on the substrate 100.

[0037] The fin portion 110 includes: a first channel layer 111; several overlapping sacrificial layers 112 on the first channel layer 111; and a channel layer 113 between adjacent sacrificial layers 112.

[0038] There is an opening 120 between adjacent fin portions 110.

[0039] Please refer to Figure 2 and Figure 3 , Figure 3 is Figure 2 a schematic cross-sectional structure diagram along the direction M1-M2 in Figure 2 is Figure 3 a top view along the direction M3 in , a dielectric wall 121 is formed within the opening 120, and the top surface of the dielectric wall 121 is flush with the top surface of the fin portion 110.

[0040] Please continue to refer to Figure 2 and Figure 3 , after forming the dielectric wall 121, an isolation layer 130 is formed on the surface of the substrate 100; a dummy gate 140 spanning 2 fin portions 110 and the dielectric wall 121 is formed on the isolation layer 130.

[0041] Please refer to Figure 4 , after forming the dummy gate 140, the 2 fin portions 110 are etched, and source / drain openings (not shown) located on both sides of the dummy gate 110 along the direction Y (as shown in Figure 2 ) are formed within each fin portion 110. The shown source / drain openings expose the sidewalls of the dielectric wall 121; source / drain structures (not shown) are formed within the source / drain openings; after forming the source / drain structures, an interlayer dielectric layer (not shown) is formed on the substrate 100, and the interlayer dielectric layer exposes the dummy gate 140; after forming the interlayer dielectric layer, the dummy gate 140 and the sacrificial layer 112 below the dummy gate 140 are removed to form a gate opening (not shown); a metal gate 150 is formed within the gate opening, and the top surface of the metal gate 150 is flush with the top surface of the dielectric wall 121.

[0042] In the above solution, it is necessary to form a dielectric wall 121 with a relatively large height H (as shown in Figure 4 ) and a relatively large thickness W (as shown in Figure 4 ) to enhance the insulation between adjacent metal gates 150 along the direction Y to ensure the reliability of the semiconductor structure. However, the relatively thick dielectric wall 121 limits the size of the source / drain openings, resulting in a relatively small size of the source / drain structures grown within the source / drain openings and causing poor performance of the semiconductor structure.

[0043] To solve the above technical problems, the technical solution of the present invention provides a semiconductor structure and a method for forming the same. Since a thicker and higher dielectric wall is formed below the gate, and at the same time, a thinner dielectric wall is formed between the source / drain openings, the performance of the semiconductor structure is improved while ensuring the reliability of the semiconductor structure.

[0044] To make the above objects, features, and beneficial effects of the present invention more obvious and understandable, the following detailed description of the specific embodiments of the present invention will be given with reference to the accompanying drawings.

[0045] Figures 5 to 19 These are schematic structural diagrams corresponding to the steps in the method for forming a semiconductor structure according to an embodiment of the present invention.

[0046] Please refer to Figure 5 and Figure 6 , Figure 5 is Figure 6 a top-down structural schematic diagram of Figure 6 is Figure 5 a cross-sectional structural schematic diagram along the direction T1 - T2 in . A substrate 200 is provided. There are 2 discrete fin portions 210 on the substrate 200. There is an isolation opening 201 between the 2 fin portions 210. The isolation opening 201 exposes the adjacent side wall surfaces of the 2 fin portions 210.

[0047] The material of the substrate 200 includes semiconductor materials.

[0048] Specifically, the material of the substrate 200 includes silicon.

[0049] In other embodiments, the material of the substrate includes silicon carbide, silicon germanium, a multi-semiconductor material composed of group III - V elements, silicon on insulator (SOI), or germanium on insulator (GOI), etc. Among them, the multi-semiconductor material composed of group III - V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP, etc.

[0050] The fin portion 210 includes: a plurality of sacrificial layers 212 located on and overlapping the substrate 200, and horizontal fins 213 between adjacent two sacrificial layers 212. The bottom surface of the isolation opening 201 is lower than the bottom surface of any sacrificial layer 212.

[0051] Specifically, the adjacent side wall surfaces of the 2 fin portions 210 exposed by the isolation opening 201 include: the side wall surfaces of a plurality of sacrificial layers 212 and horizontal fins 213.

[0052] In this embodiment, the fin portion 210 further includes: a bottom channel layer 211 located on the substrate 200. And a plurality of sacrificial layers 212 and a plurality of horizontal fins 213 are located above the bottom channel layer 211.

[0053] At the same time, the adjacent side wall surfaces of the 2 fin portions 210 exposed by the isolation opening 201 further include: the side wall surfaces of the bottom channel layer 211. And the bottom of the isolation opening 201 also exposes the surface of the substrate 200.

[0054] In other embodiments, there is no bottom channel layer, and the isolation opening extends into the interior of the substrate.

[0055] In this embodiment, the method for forming the fin portion 210 and the isolation opening 201 includes: providing an initial substrate (not shown); forming a composite layer (not shown) on the initial substrate, the composite layer including a plurality of overlapping sacrificial material layers (not shown) and a horizontal fin material layer (not shown) between two adjacent sacrificial material layers; forming a patterned fin mask layer (not shown) on the composite layer; etching the composite layer and the initial substrate using the fin mask layer as a mask to form the two fin portions 210 and the isolation opening 201 between the two fin portions 210.

[0056] In this embodiment, the materials of the sacrificial layer 212 and the horizontal fin 213 are different from each other.

[0057] In this embodiment, the materials of the sacrificial layer 212 and the bottom channel layer 211 are different from each other.

[0058] The purpose of making the material of the sacrificial layer 212 different from that of the horizontal fin 213 and the material of the sacrificial layer 212 different from that of the bottom channel layer 211 is that in the subsequent etching process for removing the sacrificial layer 212, there is a large etching selectivity for both the sacrificial layer 212 and the horizontal fin 213, and the sacrificial layer 212 and the bottom channel layer 211, so as to reduce the etching damage to the horizontal fin 213 and the bottom channel layer 211 during the etching process.

[0059] In this embodiment, the material of the sacrificial layer 212 is silicon germanium, the material of the horizontal fin 213 is silicon, and the material of the bottom channel layer 211 is silicon.

[0060] In other embodiments, the material of the bottom channel layer is germanium or silicon germanium, the material of the horizontal fin is germanium or silicon germanium, and the material of the sacrificial layer can be ZnS, ZnSe, BeS, GaP, etc.

[0061] In this embodiment, the fin portion 210 extends along the first direction X, and the two fin portions 210 are arranged along the second direction Y, and the first direction X and the second direction Y are perpendicular to each other.

[0062] In this embodiment, the isolation opening 201 has a width L in the second direction Y. It should be understood that the spacing between adjacent horizontal fins 213 in the second direction Y is equal to the width L.

[0063] In this embodiment, before forming the initial dielectric wall subsequently, a dielectric film 202 is formed on the surface of the fin portion 210 and the surface of the substrate 200.

[0064] Specifically, the material of the dielectric film 202 includes silicon oxide.

[0065] In this embodiment, the two fin portions 210 are respectively used to form an NMOS device and a PMOS device.

[0066] It should be understood that for the sake of convenience of description, Figure 5 the dielectric film 202 is not shown.

[0067] Please refer to Figure 7 and Figure 8 , Figure 7 which Figure 8 is a top view structural schematic diagram of Figure 8 and Figure 7 is a cross-sectional structural schematic diagram along the direction T1 - T2 in . An initial dielectric wall 220 is formed within the isolation opening 201, and the top surface of the initial dielectric wall 220 is higher than the top surface of the horizontal fin 213.

[0068] The initial dielectric wall 220 has a first thickness L1 in the second direction Y. It should be understood that since the initial dielectric wall 220 is formed within the isolation opening 201, the first thickness L1 is equal to the width L.

[0069] The initial dielectric wall 220 is used to form the dielectric wall.

[0070] The purpose that the top surface of the initial dielectric wall 220 is higher than the horizontal fin 213 is to enable the dielectric wall formed subsequently to separate the horizontal fin 213 in the two fin portions 210 and the gate structures formed subsequently on the two fin portions 210.

[0071] In this embodiment, the top surface of the initial dielectric wall 220 is flush with the top surface of the fin portion 210.

[0072] In this embodiment, the initial dielectric wall 220 is a single-layer structure.

[0073] In this embodiment, the method for forming the initial dielectric wall 220 includes: forming a dielectric wall material layer (not shown) on the surface of the substrate 200 and the surface of the fin portion 210, and the dielectric wall material layer fills the isolation opening 201 (as Figure 6 shown); forming an initial dielectric wall mask layer (not shown) on the surface of the dielectric wall material layer on the isolation opening 201; using the initial dielectric wall mask layer as a mask to etch the dielectric wall material layer until the surface of the fin portion 210 and the surface of the substrate 200 are exposed.

[0074] In this embodiment, the material of the initial dielectric wall 220 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, carbon oxysilicon, carbon nitride silicon, and carbon oxynitride silicon.

[0075] In another embodiment, the initial dielectric wall includes a bottom dielectric wall and a top dielectric wall located on the top surface of the bottom dielectric wall. The top surface of the bottom dielectric wall is higher than the horizontal fin surface, and the material of the bottom dielectric wall is different from that of the top dielectric wall. Since the bottom dielectric wall and the top dielectric wall with different materials are formed, in the subsequent etching process of thinning the initial dielectric wall, different etching rates can be achieved for the materials of the bottom dielectric wall and the top dielectric wall. Thus, by making the etching process have a smaller etching rate for the material of the top dielectric wall and a larger etching rate for the material of the bottom dielectric wall, while providing a larger formation space for the source-drain structure, on the one hand, in the direction perpendicular to the substrate surface, the overall height reduction of the exposed dielectric wall can be effectively reduced, and on the other hand, the risk of the dielectric wall under the subsequently formed gate being etched can be reduced. Thereby, the performance and reliability of the semiconductor structure are further improved. Preferably, the height ratio of the top dielectric wall to the bottom dielectric wall is 1:3 to 2:3.

[0076] In addition, in another embodiment, the method for forming the initial dielectric wall includes: forming an initial bottom dielectric wall flush with or higher than the top surface of the fin in the isolation opening; back-etching the initial bottom dielectric wall until a part of the sidewall surface of the uppermost sacrificial layer is exposed to form the bottom dielectric wall; and forming the top dielectric wall in the isolation opening after forming the bottom dielectric wall.

[0077] In this embodiment, after forming the initial dielectric wall 220 and before forming the gate subsequently, an isolation layer 230 is formed on the surface of the substrate 200.

[0078] In this embodiment, the isolation layer 230 also covers the sidewall surfaces of the bottom channel layer 211, and the surface of the isolation layer 230 is flush with the top surface of the bottom channel layer 211.

[0079] In other embodiments, the surface of the isolation layer is slightly lower than the top surface of the bottom channel layer.

[0080] In this embodiment, the isolation layer 230 is made of a dielectric material, and the dielectric material includes one or more of silicon oxide, silicon nitride, silicon oxynitride, carbon oxide silicon, carbon nitride silicon, and carbon oxynitride silicon. Preferably, the material of the isolation layer 230 includes silicon oxide.

[0081] It should be understood that for the sake of convenience of description, Figure 7 the dielectric film 202 is not shown.

[0082] Please refer to Figure 9 and Figure 10 , Figure 9 is Figure 10 a top view structural schematic diagram of Figure 10 is Figure 9Schematic cross-sectional structure diagram along direction T3 - T4, a gate 240 is formed on the substrate 200 across the two fin portions 210 and the initial dielectric wall 220.

[0083] It should be noted that, for ease of understanding, Figure 9 the dielectric film 202 is not shown in [].

[0084] In this embodiment, the method of forming the gate 240 includes: forming a gate material layer (not shown) on the isolation layer 230, on the fin portions 210, and on the initial dielectric wall 220, the surface of the gate material layer being higher than the top surfaces of the fin portions 210 and the initial dielectric wall 220; forming a patterned gate mask layer on the surface of the gate material layer; using the gate mask layer as a mask to etch the gate material layer until the surface of the isolation layer 230, the surface of the fin portions 210, and the surface of the initial dielectric wall 220 are exposed, thereby forming the gate 240.

[0085] In this embodiment, the sidewalls of the gate 240 further have gate spacers (not shown).

[0086] In this embodiment, the gate mask layer is retained after the gate 240 is formed. Through the gate spacers and the retained gate mask layer, not only can they serve as a mask during the subsequent formation of the source-drain openings to define the position and shape of the source-drain openings, but also they can protect the morphology of the gate 240 during subsequent etching processes, so that a gate structure with a better morphology can be formed after the gate 240 is removed subsequently.

[0087] In this embodiment, the material of the gate 240 includes polysilicon.

[0088] Please refer to Figure 11 and Figure 12 , Figure 11 is Figure 12 the top-down structure schematic diagram of [], Figure 12 is Figure 11 the cross-sectional structure schematic diagram along direction T1 - T2 in [], etching the two fin portions 210 (as shown in Figure 10 ), source-drain openings 251 are formed in the fin portions 210 on both sides of the gate 240, and the inner wall surfaces of the source-drain openings 251 expose the sidewalls of the initial dielectric wall 220.

[0089] It should be understood that, for ease of description, Figure 11 the dielectric film 202 is not shown in [].

[0090] In this embodiment, the source-drain openings 251 also expose the surface of the bottom channel layer 211.

[0091] In other embodiments, when there is no bottom channel layer, the source-drain openings also expose the surface of the substrate under the fin portions.

[0092] Specifically, in the first direction X, source-drain openings 251 are formed in each fin 210 on both sides of the gate 240, and the initial dielectric wall 220 penetrates the source-drain openings 251 in each fin 210 in the second direction Y.

[0093] In this embodiment, the method for forming the source-drain openings 251 includes: using the gate mask layer and the gate sidewall as masks to etch the two exposed fins 210 until the top surface of the bottom channel layer 211 and the sidewall surface of the initial dielectric wall 220 are exposed.

[0094] In other embodiments, when there is no bottom channel layer, the method for forming the source-drain openings includes: using the gate mask layer and the gate sidewall as masks to etch the two exposed fins until the substrate surface is exposed.

[0095] In this embodiment, the process of etching the two exposed fins 210 using the gate mask layer and the gate sidewall as masks includes at least one of a dry etching process and a wet etching process.

[0096] Please refer to Figure 13 , Figure 13 which is Figure 12 in the same view direction as. The initial dielectric wall 220 exposed between adjacent source-drain openings 251 is used to form the dielectric wall 221. In the second direction, the dielectric wall 221 between adjacent horizontal fins 213 has a first thickness L1, and the dielectric wall between adjacent source-drain openings 251 has a second thickness W1, and the second thickness W1 is less than the first thickness L1.

[0097] Since the initial dielectric wall 220 with a top surface higher than the top surface of the horizontal fin 213 is formed in the isolation opening 201, and the initial dielectric wall 220 exposed between adjacent source-drain openings 251 is thinned to form the dielectric wall 221 before forming the source-drain structure in the source-drain openings 251 subsequently, the thickness (second thickness W1) of the dielectric wall 221 between adjacent source-drain openings 251 in the second direction Y is less than the thickness (first thickness L1) of the initial dielectric wall 220. Thus, on the one hand, the gate 240 (such as Figure 11The dielectric wall 221 below (as shown) is higher and has a greater thickness (the first thickness L1). As a result, the subsequently formed gate structure can be better separated by the higher and thicker portion of the dielectric wall 221. Furthermore, not only is the insulation between adjacent gate structures good, ensuring the reliability of the semiconductor structure, but also the parasitic capacitance between adjacent gate structures is smaller, improving the performance of the semiconductor structure. On the other hand, the thickness (the second thickness W1) of the dielectric wall 221 between adjacent source-drain openings 251 is smaller, increasing the space provided for forming the source-drain structure subsequently. Thus, a source-drain structure with a larger size can be formed to improve the performance of the semiconductor structure. In summary, while ensuring the reliability of the semiconductor structure, the performance of the semiconductor structure is improved.

[0098] In this embodiment, the method for thinning the initial dielectric wall 220 between adjacent source-drain openings 251 in the two fin portions includes: etching the sidewalls of the initial dielectric wall 220 exposed by the inner wall surfaces of the source-drain openings 251.

[0099] It should be understood that in this embodiment, during the process of etching the sidewalls of the initial dielectric wall 220 exposed by the inner wall surfaces of the source-drain openings 251 to form the dielectric wall 221, in the direction perpendicular to the surface of the substrate 200, the height of the exposed dielectric wall 221 will be reduced compared to the initial dielectric wall 220 due to etching loss.

[0100] In this embodiment, the process of etching the sidewalls of the initial dielectric wall 220 exposed by the inner wall surfaces of the source-drain openings 251 includes at least one of a wet etching process and a dry etching process.

[0101] Preferably, the method for etching the sidewalls of the initial dielectric wall 220 exposed by the inner wall surfaces of the source-drain openings 251 includes: etching the sidewalls of the exposed initial dielectric wall 220 using a wet etching process to thin the initial dielectric wall 220 between the source-drain openings 251 to a third thickness (not shown), the third thickness being greater than the second thickness W1; after the wet etching process, using an anisotropic dry etching process to etch the sidewalls of the exposed initial dielectric wall 220 in the direction perpendicular to the surface of the substrate 200 to form the dielectric wall 221.

[0102] Compared with the dry etching process, the wet etching process can usually achieve a greater etching selectivity for different materials. In this embodiment, by first using the wet etching process to etch the initial dielectric wall 220, not only can a certain thickness of the initial dielectric wall 220 be better removed, but also, during this etching process, the surface of the bottom channel layer 211 exposed by the source-drain opening 251 is less damaged. On this basis, since after the wet etching process, an anisotropic dry etching process is used to etch the sidewalls of the exposed initial dielectric wall 220 in the direction perpendicular to the surface of the substrate 200, therefore, not only can the initial dielectric wall 220 with the third thickness be thinned to the second thickness W1 to form the dielectric wall 221, but also the etching direction perpendicular to the surface of the substrate 200 reduces the risk of partial etching of the initial dielectric wall 220 under the gate 240. Thus, the performance and reliability of the semiconductor structure are further improved.

[0103] Specifically, the dry etching process includes a plasma etching process.

[0104] In this embodiment, the ratio of the second thickness W1 to the first thickness L1 is 1 / 2 to 4 / 5. That is, the second thickness W1 is 50% to 80% of the first thickness L1.

[0105] If the second thickness W1 is too thick, the increased size of the source-drain opening 251 is small, which is not conducive to forming a larger source-drain structure subsequently. If the second thickness W1 is too thin, on the one hand, when forming the dielectric wall 221 with the too-thin second thickness W1, the process window is small, and at the same time, the adjacent source-drain structures formed subsequently are too close to each other, then there is an easy risk of leakage. Therefore, when selecting a suitable second thickness W1, that is, when the second thickness W1 is 50% to 80% of the first thickness L1, not only is the process window larger, but also the reliability of the semiconductor structure can be ensured while improving the performance of the semiconductor structure.

[0106] In this embodiment, the material of the dielectric wall 221 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, carbon silicon oxide, carbon silicon nitride, and carbon oxynitride silicon.

[0107] In another embodiment, the method for thinning the initial dielectric wall between the source-drain openings includes: etching the sidewalls of the bottom dielectric wall and the top dielectric wall exposed by the inner wall surface of the source-drain opening, and during the etching process, the etching rate of the material of the bottom dielectric wall is greater than the etching rate of the material of the top dielectric wall.

[0108] Please refer to Figure 14 , Figure 14 And Figure 13 in the same view direction, after forming the dielectric wall 221, a source-drain structure 250 is formed in the source-drain opening 251.

[0109] In this embodiment, the process of forming the source-drain structure 250 includes an epitaxial growth process.

[0110] Please refer to Figure 15 and Figure 16 , Figure 15 is Figure 16 a top view structural schematic diagram of Figure 16 is Figure 15 a cross-sectional structural schematic diagram along the direction T3 - T4 in Figure 14 shown. After forming the source-drain structure 250, an initial interlayer dielectric layer 260 is formed on the surface of the substrate 200, the surface of the source-drain structure 250 (as shown in Figure 10 ), the surface of the dielectric wall 221, the surface of the fin 210 (as shown in Figure 10 ), and the sidewall surface of the gate 240. The initial interlayer dielectric layer 260 exposes the top surface of the gate 240; the exposed gate 240 is etched until the surface of the isolation layer 230 is exposed, and a gate opening 261 is formed in the initial interlayer dielectric layer 260; several sacrificial layers 212 (as shown in

[0111] In this embodiment, several horizontal fins 213 on the sidewall surface of each side of the dielectric wall 221 form one horizontal fin structure 215, and two horizontal fin structures 215 on both sides of the dielectric wall 221 form a fork-shaped fin structure (Forksheet).

[0112] It should be noted that in this embodiment, since the fin 210 further includes a bottom channel layer 211, forming the gate groove 262 between the horizontal fin 213 and the substrate 200 means: forming the gate groove 262 between the lowermost horizontal fin 213 and the bottom channel layer 211.

[0113] In other embodiments, when there is no bottom channel layer, forming the gate groove between the horizontal fin and the substrate means: forming a gate groove that exposes the bottom surface of the horizontal fin and the surface of the substrate between the lowermost horizontal fin and the substrate.

[0114] In this embodiment, the process of etching the gate 240 includes at least one of a dry etching process and a wet etching process.

[0115] In this embodiment, the process of etching the sacrificial layer 212 includes at least one of a dry etching process and a wet etching process.

[0116] In this embodiment, the fin mask layer is removed before forming the gate opening 261.

[0117] Please refer to Figures 17 to 19 , Figure 17 which Figure 18 is Figure 19 a top - view structural schematic diagram of Figure 18 and Figure 17 ; Figure 19 is Figure 17 a cross - sectional structural schematic diagram along the direction T1 - T2 in Figure 16 ; Figure 16 is Figure 15 a cross - sectional structural schematic diagram along the direction T3 - T4 in

[0118] Specifically, the gate structure 270 surrounds the horizontal fin 213.

[0119] The gate structure 270 includes: a gate dielectric layer (not labeled in the figure) located on the exposed surfaces of the horizontal fin 213 and the bottom channel layer 211, a work function layer (not labeled in the figure) located on the surface of the gate dielectric layer, and a gate electrode layer (not labeled in the figure) located on the surface of the work function layer.

[0120] It should be noted that since the two horizontal fin structures 215 are respectively used to form NMOS devices and PMOS devices, the work function layers on both sides of the dielectric wall 221 along the Y direction can be different to adjust the work functions of the NMOS devices and PMOS devices respectively.

[0121] In this embodiment, the method of forming the initial gate structure in the gate opening 261 and the gate groove 262 includes: forming a gate structure material layer (not shown) in the gate opening 261, in the gate groove 262, and on the surface of the initial inter - layer dielectric layer 260, the surface of the gate structure material layer being higher than the surface of the initial inter - layer dielectric layer 260; planarizing the gate structure material layer until the surface of the initial inter - layer dielectric layer 260 is exposed to form the initial gate structure.

[0122] In this embodiment, the process of planarizing the gate structure material layer includes a chemical mechanical polishing process.

[0123] In this embodiment, the process of planarizing the initial gate structure and the initial inter - layer dielectric layer 260 includes a chemical mechanical polishing process.

[0124] Correspondingly, an embodiment of the present invention further provides a semiconductor structure formed by the above forming method. Please continue to refer to Figures 17 to 19 , including: a substrate 200; a dielectric wall 221 located on the substrate 200, the dielectric wall 221 extending along a first direction X; a plurality of horizontal fins 213 on side wall surfaces respectively located on both sides of the dielectric wall 221 in a second direction Y, the horizontal fins 213 being parallel to the surface of the substrate 200, the plurality of horizontal fins 213 being separated from each other, and the plurality of horizontal fins 213 on the side wall surface on each side of the dielectric wall 221 being stacked along the normal direction of the surface of the substrate 200, the first direction X and the second direction Y being perpendicular to each other; a gate structure 270 spanning the dielectric wall 221 and the plurality of horizontal fins 213 along the second direction Y, and the gate structure 270 spanning the plurality of horizontal fins 213 along the normal direction of the surface of the substrate 200; a source-drain structure 250 located within the plurality of horizontal fins 213, and the source-drain structure 250 being located on both sides of the gate structure 270 in the first direction X, the source-drain structure 250 being located on both sides of the dielectric wall 221 in the second direction Y; in the second direction Y, the dielectric wall 221 between adjacent horizontal fins 213 has a first thickness L1, the dielectric wall 221 between adjacent source-drain structures 250 has a second thickness W1, and the second thickness W1 is less than the first thickness L1.

[0125] It should be understood that since the semiconductor structure is used to form an integrated circuit, the semiconductor structure may include a plurality of the dielectric walls 221 arranged along the second direction Y.

[0126] The material of the substrate 200 includes a semiconductor material.

[0127] Specifically, the material of the substrate 200 includes silicon.

[0128] In other embodiments, the material of the substrate includes silicon carbide, silicon germanium, a multi-semiconductor material composed of group III-V elements, silicon on insulator (SOI), or germanium on insulator (GOI), etc. Among them, the multi-semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP, etc. In this embodiment, the material of the horizontal fins 213 is silicon.

[0129] In this embodiment, the material of the horizontal fins 213 is silicon.

[0130] In this embodiment, the plurality of horizontal fins 213 on the side wall surface on each side of the dielectric wall 221 form 1 horizontal fin structure 215, and the 2 horizontal fin structures 215 on both sides of the dielectric wall 221 form a fork-shaped fin structure.

[0131] In this embodiment, the semiconductor structure further includes: a bottom channel layer 211 on the sidewall bottom surfaces respectively located on both sides of the dielectric wall 221 in the second direction Y. The bottom channel layer 211 is also located on the substrate 200. A plurality of horizontal fins 213 are located above the bottom channel layer 211. Moreover, the dielectric wall 221 between adjacent bottom channel layers 211 also has the first thickness L1.

[0132] In other embodiments, there is no bottom channel layer. Moreover, the dielectric wall extends into the substrate, and the dielectric wall in the substrate has the first thickness.

[0133] In this embodiment, the material of the bottom channel layer 211 is silicon.

[0134] In other embodiments, the material of the horizontal fins is germanium or germanium silicon, and the material of the bottom channel layer is germanium or germanium silicon.

[0135] In this embodiment, the dielectric wall 221 is a single-layer structure.

[0136] In this embodiment, the material of the dielectric wall 221 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, carbon oxide silicon, carbon nitride silicon, and carbon oxynitride silicon.

[0137] In this embodiment, the ratio of the second thickness W1 to the first thickness L1 is 1 / 2 to 4 / 5.

[0138] In yet another embodiment, the dielectric wall includes: a bottom dielectric wall and a top dielectric wall located on the top surface of the bottom dielectric wall. The top surface of the bottom dielectric wall is higher than the surface of the horizontal fins. The material of the bottom dielectric wall is different from the material of the top dielectric wall. The bottom dielectric wall between the source-drain structures has the second thickness. Moreover, the thickness of the top dielectric wall is greater than the second thickness.

[0139] Preferably, the height ratio of the top dielectric wall to the bottom dielectric wall is 1:3 to 2:3.

[0140] In this embodiment, the gate structure 270 has gate sidewalls (not shown) on the sidewalls on both sides in the first direction X. Specifically, the gate sidewalls are also located between the gate structure 270 and the source-drain structure 250.

[0141] In this embodiment, the gate structure 270 surrounds each horizontal fin 213 and the exposed surface of the bottom channel layer 211.

[0142] In this embodiment, the top surface of the gate structure 270 is flush with the top surface of the dielectric wall 221.

[0143] In this embodiment, the gate structure 270 includes: a gate dielectric layer (not labeled in the figure) located on the exposed surfaces of the horizontal fin 213 and the bottom channel layer 211, a work function layer (not labeled in the figure) located on the surface of the gate dielectric layer, and a gate electrode layer (not labeled in the figure) located on the surface of the work function layer.

[0144] It should be noted that since the two horizontal fin structures 215 are respectively used to form NMOS devices and PMOS devices, the work function layers on both sides of the dielectric wall 221 along the second direction Y can be different to adjust the work functions of the NMOS device and the PMOS device respectively.

[0145] In this embodiment, the semiconductor structure further includes: an isolation layer 230 located on the surface of the substrate 200, and the gate structure 270 is located on the isolation layer 230.

[0146] In this embodiment, the top surface of the isolation layer 230 is lower than or flush with the top surface of the bottom channel layer 211.

[0147] In this embodiment, the isolation layer 230 is a dielectric material, and the dielectric material includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxide, silicon carbon nitride, and silicon carbon oxynitride. Preferably, the material of the isolation layer 230 includes silicon oxide.

[0148] Figures 20 to 32 For the semiconductor structure forming method according to another embodiment of the present invention, the schematic diagrams corresponding to the steps are shown in Figure 5 and Figure 6 On the basis of, refer to Figure 20 and Figure 21 , an initial dielectric wall 320 is formed in the isolation opening 201, and the top surface of the initial dielectric wall 320 is higher than the top surface of the horizontal fin 213.

[0149] The initial dielectric wall 320 has a first thickness L2 in the second direction Y. It should be understood that since the initial dielectric wall 320 is formed in the isolation opening 201, the first thickness L2 is equal to the width L.

[0150] The initial dielectric wall 320 is used to form the dielectric wall.

[0151] The purpose of the top surface of the initial dielectric wall 320 being higher than the horizontal fin 213 is to enable the dielectric wall formed subsequently to separate the horizontal fin 213 in the two fin portions 210 and the gate structures formed subsequently on the two fin portions 210.

[0152] In this embodiment, the top surface of the initial dielectric wall 320 is flush with the top surface of the fin portion 210.

[0153] In this embodiment, the initial dielectric wall 320 includes an inner dielectric wall 321 and a surface dielectric wall 322 located on the surface of the inner dielectric wall 321. Moreover, the material of the inner dielectric wall 321 is different from that of the surface dielectric wall 322, and the inner dielectric wall 321 has a second thickness M1.

[0154] With the inner dielectric wall 321 and the surface dielectric wall 322 having different materials, a relatively high etching selectivity for the surface dielectric wall 322 and the inner dielectric wall 321 can be achieved during the subsequent etching process of thinning the initial dielectric wall 320. Meanwhile, since the inner dielectric wall 321 also has a second thickness M1, subsequently, the etching process can be easily controlled to thin the initial dielectric wall 320 between the source-drain openings formed subsequently to the second thickness M1. Thus, the process window of the etching process is reduced, and risks such as over-etching during the etching process are reduced.

[0155] In this embodiment, the method for forming the initial dielectric wall 320 includes: forming a dielectric wall material layer (not shown) on the surface of the substrate 200, the surface of the fin 210, and the inner wall surface of the isolation opening 201, the dielectric wall material layer filling the isolation opening 201, the inner dielectric wall material layer including at least an inner material layer (not shown) located on the inner wall surface of the isolation opening 201, and an outer material layer (not shown) located on the surface of the inner material layer; forming an initial dielectric wall mask layer (not shown) on the surface of the dielectric wall material layer on the isolation opening 201; using the initial dielectric wall mask layer as a mask to etch the dielectric wall material layer until the surface of the fin 210 and the surface of the substrate 200 are exposed.

[0156] In this embodiment, the material of the inner dielectric wall 321 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxide, silicon carbonitride, and silicon carbon oxynitride.

[0157] In this embodiment, the material of the surface dielectric wall 322 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxide, silicon carbonitride, and silicon carbon oxynitride.

[0158] In this embodiment, after forming the initial dielectric wall 320 and before forming the gate subsequently, an isolation layer 230 is formed on the surface of the substrate 200.

[0159] In this embodiment, the isolation layer 230 also lies on the sidewall surface of the bottom channel layer 211, and the surface of the isolation layer 230 is lower than or flush with the top surface of the bottom channel layer 211.

[0160] In this embodiment, the isolation layer 230 is a dielectric material, and the dielectric material includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbonitride, and silicon carbon oxynitride. Preferably, the material of the isolation layer 230 includes silicon oxide.

[0161] It should be noted that for the sake of easy understanding, Figure 20 the dielectric film 202 is not shown in

[0162] Please refer to Figure 22 and Figure 23 , Figure 22 which Figure 23 is a top view structural schematic diagram of Figure 23 which Figure 22 is a cross-sectional structural schematic diagram of

[0163] It should be understood that for the sake of easy explanation, Figure 22 the dielectric film 202 is not shown in

[0164] In this embodiment, the method for forming the gate 340 includes: forming a gate material layer (not shown) on the isolation layer 230, on the fin 210, and on the initial dielectric wall 320, the surface of the gate material layer being higher than the top surfaces of the fin 210 and the initial dielectric wall 320; forming a patterned gate mask layer on the surface of the gate material layer; using the gate mask layer as a mask to etch the gate material layer until the surfaces of the isolation layer 230, the fin 210, and the initial dielectric wall 320 are exposed, thereby forming the gate 340.

[0165] In this embodiment, the sidewalls of the gate 340 further have gate spacers (not shown).

[0166] In this embodiment, the gate mask layer is retained after the gate 340 is formed. Through the gate spacers and the retained gate mask layer, not only can they be used as a mask during the subsequent formation of the source-drain openings to define the positions and shapes of the source-drain openings, but also they can protect the morphology of the gate 240 during subsequent etching processes so that a gate structure with a better morphology can be formed after the gate 340 is removed later.

[0167] In this embodiment, the material of the gate 340 includes polysilicon.

[0168] Please refer to Figure 24 and Figure 25 , Figure 24 which Figure 25 is a top view structural schematic diagram of Figure 25 which Figure 24Schematic cross-sectional structure diagram along the direction T1 - T2. Etch the two fin portions 210 to form source / drain openings 351 in the fin portions 210 on both sides of the gate 340, and the inner wall surface of the source / drain openings 351 exposes the side walls of the initial dielectric wall 320.

[0169] In this embodiment, the source / drain openings 351 also expose the surface of the bottom channel layer 211.

[0170] Specifically, in the first direction X, source / drain openings 351 are formed in the fin portions 210 on both sides of the gate 340, and the initial dielectric wall 320 penetrates the source / drain openings 351 in each fin portion 210 in the second direction Y.

[0171] In this embodiment, the method for forming the source / drain openings 351 includes: using the gate mask layer and the gate sidewall as masks to etch the exposed two fin portions 210 (as Figure 23 shown) until the top surface of the bottom channel layer 211 and the sidewall surface of the initial dielectric wall 320 are exposed.

[0172] In this embodiment, the process of etching the exposed two fin portions 210 using the gate mask layer and the gate sidewall as masks includes at least one of a dry etching process and a wet etching process.

[0173] Please refer to Figure 26 , Figure 26 and Figure 25 with the same view direction as

[0174] Thin the exposed initial dielectric wall 320 between the source / drain openings 351 to form the dielectric wall 323. The dielectric wall 323 includes: an inner dielectric wall 321 and a surface dielectric wall 322 located on the surface of the inner dielectric wall 321. The material of the inner dielectric wall is different from that of the surface dielectric wall, and the dielectric wall 323 between the source / drain structures 351 exposes the surface of the inner dielectric wall 321.

[0175] In the second direction Y, the dielectric wall 323 between adjacent horizontal fins 213 has a first thickness L2, and the dielectric wall 323 between adjacent source / drain openings 351 has a second thickness M1, and the second thickness M1 is less than the first thickness L2.

[0176] Since an initial dielectric wall 320 with a top surface higher than the top surface of the horizontal fin 213 is formed within the isolation opening 201, and before forming the source-drain structure within the source-drain opening 351 subsequently, the initial dielectric wall 320 exposed between the source-drain openings 351 is thinned to form the dielectric wall 323, the thickness (second thickness M1) of the dielectric wall 323 between the source-drain openings 351 adjacent in the second direction Y is less than the thickness (first thickness L2) of the initial dielectric wall 320. Thus, on the one hand, the dielectric wall 323 under the gate 340 is higher and has a larger thickness (first thickness L2). Consequently, the subsequently formed gate structure can be better spaced by the higher and thicker part of the dielectric wall 323. Furthermore, not only is the insulation between adjacent gate structures good, ensuring the reliability of the semiconductor structure, but also the parasitic capacitance between adjacent gate structures is smaller, improving the performance of the semiconductor structure. On the other hand, the thickness (second thickness M1) of the dielectric wall 321 between adjacent source-drain openings 351 is smaller, increasing the space provided for forming the source-drain structure subsequently. Thus, a source-drain structure with a larger size can be formed to improve the performance of the semiconductor structure. In summary, while ensuring the reliability of the semiconductor structure, the performance of the semiconductor structure is improved.

[0177] In addition, through the inner dielectric wall 321 and the surface dielectric wall 322 with different materials, a higher etching selectivity ratio for the surface dielectric wall 322 and the inner dielectric wall 321 can be achieved during the etching process of thinning the initial dielectric wall 320. Meanwhile, since the inner dielectric wall 321 also has the second thickness M1, not only can the etching process be easily controlled to thin the initial dielectric wall 320 between the source-drain openings 351 to the second thickness M1 to form the dielectric wall 323, but also the height of the dielectric wall 323 is not easily reduced. Thus, the process window of the etching process is reduced, and risks such as over-etching during the etching process are reduced.

[0178] In this embodiment, the method for thinning the initial dielectric wall 320 between the source-drain openings 351 includes: etching the sidewall of the exposed surface dielectric wall 322 until the sidewall surface of the inner dielectric wall 321 is exposed.

[0179] The process of etching the sidewall of the exposed surface dielectric wall 322 includes at least one of a dry etching process and a wet etching process.

[0180] Preferably, the ratio of the second thickness M1 to the thickness L2 is 1 / 2 to 4 / 5. That is, the second thickness M1 is 50% to 80% of the first thickness L2.

[0181] If the second thickness M1 is too thick, the increased size of the source-drain opening 351 is small, which is not conducive to forming a larger source-drain structure subsequently. If the second thickness M1 is too thin, the adjacent source-drain structures formed subsequently are too close to each other, and thus there is an easy risk of leakage. Therefore, when a suitable second thickness M1 is selected, that is, when the second thickness M1 is 50% to 80% of the first thickness L2, the performance of the semiconductor structure can be improved while ensuring the reliability of the semiconductor structure.

[0182] Please refer to Figure 27 , Figure 27 and Figure 26 in the same view direction. After forming the dielectric wall 323, a source-drain structure 350 is formed in the source-drain opening 351.

[0183] In this embodiment, the process of forming the source-drain structure 350 includes an epitaxial growth process.

[0184] Please refer to Figure 28 and Figure 29 , Figure 28 is Figure 29 a top view structural schematic diagram of Figure 29 is Figure 28 a cross-sectional structural schematic diagram along the direction T3 - T4 in . After forming the source-drain structure 350, an initial interlayer dielectric layer 360 is formed on the surface of the substrate 200, the surface of the source-drain structure 350, the surface of the dielectric wall 323, the surface of the fin 210, and the side wall surface of the gate 340. The initial interlayer dielectric layer 360 exposes the top surface of the gate 340. The exposed gate 340 is etched until the surface of the isolation layer 230 is exposed, and a gate opening 361 is formed in the initial interlayer dielectric layer 360. The exposed sacrificial layers 212 in the gate opening 361 are etched until the sacrificial layers 212 are removed, and gate grooves 362 are formed between adjacent two layers of horizontal fins 213 and between the horizontal fin 213 and the substrate 200.

[0185] In this embodiment, several horizontal fins 213 on the side wall surface of each side of the dielectric wall 323 form one horizontal fin structure 215, and two horizontal fin structures 215 on both sides of the dielectric wall 323 form a fork-shaped fin structure.

[0186] It should be noted that in this embodiment, since the fin 210 further includes a bottom channel layer 211, forming the gate groove 362 between the horizontal fin 213 and the substrate 200 means forming the gate groove 362 between the lowermost horizontal fin 213 and the bottom channel layer 211.

[0187] In this embodiment, the process of etching the gate 340 includes at least one of a dry etching process and a wet etching process.

[0188] In this embodiment, the process of etching the sacrificial layer 212 includes at least one of a dry etching process and a wet etching process.

[0189] In this embodiment, the fin mask layer is removed before forming the gate opening 361.

[0190] Please refer to Figures 30 to 32 , Figure 30 is Figure 31 and Figure 32 a top view structural schematic diagram of Figure 31 is Figure 30 a cross-sectional structural schematic diagram of Figure 32 is Figure 30 a cross-sectional structural schematic diagram of Figure 29 along the direction T3-T4 in Figure 29 As shown), an initial gate structure (not shown) is formed in the gate opening 361 (as shown in

[0191] Specifically, the gate structure 370 surrounds the horizontal fin 213.

[0192] The gate structure 370 includes: a gate dielectric layer (not marked in the figure) located on the exposed surfaces of the horizontal fin 213 and the bottom channel layer 211, a work function layer (not marked in the figure) located on the surface of the gate dielectric layer, and a gate electrode layer (not marked in the figure) located on the surface of the work function layer.

[0193] It should be noted that since the two horizontal fin structures 215 are respectively used to form NMOS devices and PMOS devices, the work function layers on both sides of the dielectric wall 323 along the direction Y can be different to adjust the work functions of the NMOS devices and PMOS devices respectively.

[0194] In this embodiment, the method of forming the initial gate structure in the gate opening 361 and the gate groove 362 includes: forming a gate structure material layer (not shown) in the gate opening 361, in the gate groove 362, and on the surface of the initial interlayer dielectric layer 360, and the surface of the gate structure material layer is higher than the surface of the initial interlayer dielectric layer 360; planarizing the gate structure material layer until the surface of the initial interlayer dielectric layer 360 is exposed to form the initial gate structure.

[0195] In this embodiment, the process of planarizing the gate structure material layer includes a chemical mechanical polishing process.

[0196] In this embodiment, the process of planarizing the initial gate structure and the initial interlayer dielectric layer 360 includes a chemical mechanical polishing process.

[0197] Correspondingly, another embodiment of the present invention further provides a semiconductor structure formed by the above method. Please continue to refer to Figures 30 to 32 , including: a substrate 200; a dielectric wall 323 located on the substrate 200, the dielectric wall 323 extending along a first direction X; a plurality of horizontal fins 213 on the side wall surfaces on both sides of the dielectric wall 323 in a second direction Y, the horizontal fins 213 being parallel to the surface of the substrate 200, the plurality of horizontal fins 213 being discrete from each other, and, on each side wall surface of the dielectric wall 323, the plurality of horizontal fins 213 being stacked along the normal direction of the surface of the substrate 200, the first direction X and the second direction Y being perpendicular to each other; a gate structure 370 spanning the dielectric wall 323 and the plurality of horizontal fins 213 in the second direction Y, and, the gate structure 370 spanning the plurality of horizontal fins 213 along the normal direction of the surface of the substrate 200; a source-drain structure 350 located within the plurality of horizontal fins 213, and, the source-drain structure 350 being located on both sides of the gate structure 370 in the first direction X, the source-drain structure 350 being located on both sides of the dielectric wall 323 in the second direction Y; in the second direction Y, the dielectric wall 323 between adjacent horizontal fins 213 has a first thickness L2, the dielectric wall 221 between adjacent source-drain structures 350 has a second thickness M1, and, the second thickness M1 is less than the first thickness L2.

[0198] It should be understood that since the semiconductor structure is used to form an integrated circuit, therefore, the semiconductor structure may include a plurality of the dielectric walls 323 arranged in the second direction Y.

[0199] The material of the substrate 200 includes a semiconductor material.

[0200] Specifically, the material of the substrate 200 includes silicon.

[0201] In other embodiments, the material of the substrate includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon on insulator (SOI) or germanium on insulator (GOI), etc. Among them, the multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP, etc.

[0202] In this embodiment, the material of the horizontal fins 213 is silicon.

[0203] In this embodiment, a plurality of horizontal fins 213 on each side wall surface of the dielectric wall 323 form 1 horizontal fin structure 215, and 2 horizontal fin structures 215 on both sides of the dielectric wall 323 form a fork-shaped fin structure.

[0204] In this embodiment, the semiconductor structure further includes: in the second direction Y, bottom channel layers 211 on the bottom sidewalls respectively located on both sides of the dielectric wall 323, the bottom channel layers 211 are also located on the substrate 200, a plurality of horizontal fins 213 are located above the bottom channel layers 211, and the dielectric wall 323 between adjacent bottom channel layers 211 also has the first thickness L2.

[0205] In this embodiment, the material of the bottom channel layer 211 is silicon.

[0206] In other embodiments, the material of the bottom channel layer is germanium or germanium silicon, and the material of the horizontal fins is germanium or germanium silicon.

[0207] In this embodiment, the dielectric wall 323 includes: an inner dielectric wall 321 and a surface dielectric wall 322 located on the surface of the inner dielectric wall 321. The material of the inner dielectric wall 321 is different from that of the surface dielectric wall 322, and the dielectric wall 323 between the source-drain structures 351 exposes the surface of the inner dielectric wall 321.

[0208] Preferably, the ratio of the second thickness M1 to the first thickness L2 is 1 / 2 to 4 / 5.

[0209] In this embodiment, the material of the inner dielectric wall 321 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxide, silicon carbon nitride, and silicon carbon oxynitride.

[0210] In this embodiment, the material of the surface dielectric wall 322 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxide, silicon carbon nitride, and silicon carbon oxynitride.

[0211] In this embodiment, the gate structure 370 has gate sidewalls (not shown) on the sidewalls on both sides in the first direction X. Specifically, the gate sidewalls are also located between the gate structure 370 and the source-drain structure 350.

[0212] In this embodiment, the gate structure 370 surrounds each horizontal fin 213 and the exposed surface of the bottom channel layer 211.

[0213] Specifically, the gate structure 370 surrounds the horizontal fins 213.

[0214] In this embodiment, the gate structure 370 includes: a gate dielectric layer (not identified in the figure) located on the exposed surfaces of the horizontal fins 213 and the bottom channel layer 211, a work function layer (not identified in the figure) located on the surface of the gate dielectric layer, and a gate electrode layer (not identified in the figure) located on the surface of the work function layer.

[0215] It should be noted that since the two horizontal fin structures 215 are respectively used to form NMOS devices and PMOS devices, the work function layers on both sides of the dielectric wall 323 along the Y direction can be different to adjust the work functions of the NMOS devices and PMOS devices respectively.

[0216] In this embodiment, the semiconductor structure further includes: an isolation layer 230 located on the surface of the substrate 200, and the gate structure 370 is located on the isolation layer 230.

[0217] In this embodiment, the top surface of the isolation layer 230 is lower than or flush with the top surface of the bottom channel layer 211.

[0218] In this embodiment, the isolation layer 230 is a dielectric material, and the dielectric material includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxide, silicon carbon nitride, and silicon carbon oxynitride. Preferably, the material of the isolation layer 230 includes silicon oxide.

[0219] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that, Comprising: A substrate; A dielectric wall located on the substrate, the dielectric wall extending in a first direction; In a second direction, a plurality of horizontal fins on side wall surfaces respectively located on both sides of the dielectric wall, the horizontal fins being parallel to the substrate surface, the plurality of horizontal fins being discrete from each other, and the plurality of horizontal fins on the side wall surface on each side of the dielectric wall being stacked along the normal direction of the substrate surface, the first direction and the second direction being perpendicular to each other; A gate structure spanning the dielectric wall and the plurality of horizontal fins in the second direction, and the gate structure spanning the plurality of horizontal fins along the normal direction of the substrate surface; A source-drain structure located within the plurality of horizontal fins, and the source-drain structure being located on both sides of the gate structure in the first direction, the source-drain structure being located on both sides of the dielectric wall in the second direction; In the second direction, the dielectric wall between adjacent horizontal fins has a first thickness, the dielectric wall between adjacent source-drain structures has a second thickness, and the second thickness is less than the first thickness; Wherein, the dielectric wall includes: a bottom dielectric wall, and a top dielectric wall located on the top surface of the bottom dielectric wall, the top surface of the bottom dielectric wall being higher than the surface of the horizontal fins, the material of the bottom dielectric wall being different from the material of the top dielectric wall, the bottom dielectric wall between the source-drain structures having the second thickness, and the thickness of the top dielectric wall being greater than the second thickness.

2. The semiconductor structure according to claim 1, wherein, The height ratio of the top dielectric wall to the bottom dielectric wall is 1:3 to 2:

3.

3. The semiconductor structure according to claim 1, wherein Further comprising: An isolation layer located on the surface of the substrate, the gate structure being located on the isolation layer.

4. The semiconductor structure according to claim 1, wherein, The material of the dielectric wall includes one or more of silicon oxide, silicon nitride, silicon oxynitride, carbon oxysilicon, carbon nitride silicon, and carbon oxynitride silicon.

5. The semiconductor structure according to claim 1, wherein The ratio of the second thickness to the first thickness is 1 / 2 to 4 / 5.

6. The semiconductor structure according to claim 1, wherein, Further comprising: A gate sidewall located on the sidewall surface of the gate structure, and the gate sidewall is also located between the gate structure and the source-drain structure.

7. The semiconductor structure according to claim 1, wherein The dielectric wall also extends into the substrate, and the dielectric wall in the substrate also has the first thickness.

8. The semiconductor structure according to claim 1, wherein Further comprising: In the second direction, bottom channel layers respectively located on both sides of the dielectric wall, the bottom channel layers being also located on the substrate, the plurality of horizontal fins being located above the bottom channel layers, and the dielectric wall between adjacent bottom channel layers also has the first thickness.

9. A method for forming a semiconductor structure, characterized in that, Comprising: Providing a substrate, having 2 discrete fin portions on the substrate, the 2 fin portions extending in a first direction and arranged in a second direction, the first direction and the second direction being perpendicular to each other, the fin portions including a plurality of sacrificial layers overlapping on the substrate, and horizontal fins between adjacent two sacrificial layers, there being an isolation opening between the 2 fin portions, the isolation opening exposing the adjacent sidewall surfaces of the 2 fin portions, and the bottom surface of the isolation opening being lower than the bottom surface of any sacrificial layer; Forming an initial dielectric wall in the isolation opening, the top surface of the initial dielectric wall being higher than the top surface of the horizontal fins; Forming a gate on the substrate spanning the 2 fin portions and the initial dielectric wall; Etching the 2 fin portions to form source-drain openings in each of the fin portions on both sides of the gate, the inner wall surface of the source-drain openings exposing the sidewall of the initial dielectric wall; Thin the initial dielectric wall exposed between adjacent source / drain openings to form a dielectric wall, and in the second direction, the dielectric wall between adjacent horizontal fins has a first thickness, and the dielectric wall between adjacent source / drain openings has a second thickness, where the second thickness is less than the first thickness; After forming the dielectric wall, form a source / drain structure within the source / drain openings.

10. The method for forming a semiconductor structure as described in claim 9, characterized in that, The initial dielectric wall is a single-layer structure.

11. The method for forming a semiconductor structure according to claim 10, wherein The method for thinning the initial dielectric wall exposed between adjacent source / drain openings includes: etching the sidewalls of the initial dielectric wall exposed by the inner wall surfaces of the source / drain openings.

12. The method for forming a semiconductor structure according to claim 10, wherein, The method for etching the sidewalls of the initial dielectric wall exposed by the inner wall surfaces of the source / drain openings includes: etching the sidewalls of the exposed initial dielectric wall using a wet etching process to thin the initial dielectric wall between the source / drain openings to a third thickness, where the third thickness is greater than the second thickness; after the wet etching process, use an anisotropic dry etching process to etch the sidewalls of the exposed initial dielectric wall in a direction perpendicular to the substrate surface to form the dielectric wall.

13. The method for forming a semiconductor structure as described in claim 9, characterized in that, The initial dielectric wall includes: an inner dielectric wall and a surface dielectric wall located on the surface of the inner dielectric wall, where the material of the inner dielectric wall is different from that of the surface dielectric wall, and the inner dielectric wall has the second thickness.

14. The method for forming a semiconductor structure as claimed in claim 13, wherein, The method for thinning the initial dielectric wall exposed between adjacent source / drain openings includes: etching the sidewalls of the exposed surface dielectric wall until the sidewall surfaces of the inner dielectric wall are exposed.

15. The method for forming a semiconductor structure according to claim 9, wherein, The initial dielectric wall includes: a bottom dielectric wall and a top dielectric wall located on the top surface of the bottom dielectric wall, where the top surface of the bottom dielectric wall is higher than the surface of the horizontal fin, and the material of the bottom dielectric wall is different from that of the top dielectric wall.

16. The method for forming a semiconductor structure according to claim 15, wherein, The method for thinning the initial dielectric wall exposed between adjacent source / drain openings includes: etching the sidewalls of the bottom dielectric wall and the top dielectric wall exposed by the inner wall surfaces of the source / drain openings, and during the etching process, the etching rate of the material of the bottom dielectric wall is greater than the etching rate of the material of the top dielectric wall.

17. The method for forming a semiconductor structure according to claim 9, wherein, Further includes: Before forming the initial dielectric wall, form a dielectric film on the surface of the fin.

18. The method for forming a semiconductor structure as claimed in claim 9, wherein, Further includes: After forming the initial dielectric wall and before forming the gate, form an isolation layer on the substrate surface.

19. The method for forming a semiconductor structure according to claim 18, wherein, Further includes: After forming the source / drain structure, form an initial interlayer dielectric layer on the substrate surface, the source / drain structure surface, the dielectric wall surface, the fin surface, and the sidewall surfaces of the gate, where the initial interlayer dielectric layer exposes the top surface of the gate; etch the exposed gate until the surface of the isolation layer is exposed, and form a gate opening within the initial interlayer dielectric layer; Etch a plurality of sacrificial layers exposed in the gate opening until the sacrificial layers are removed, and form gate grooves between adjacent two layers of horizontal fins and between the horizontal fins and the substrate; form an initial gate structure in the gate opening and the gate grooves, and the top surface of the initial gate structure is higher than the top surface of the dielectric wall; planarize the initial gate structure and the initial interlayer dielectric layer until the top surface of the dielectric wall is exposed, and form a gate structure and an interlayer dielectric layer, and the top surface of the gate structure is flush with the top surface of the dielectric wall.

20. The method for forming a semiconductor structure according to claim 9, wherein The fin further includes a bottom channel layer on the substrate, a plurality of sacrificial layers and a plurality of horizontal fins are located above the bottom channel layer, and the bottom of the isolation opening exposes the surface of the substrate, and the source-drain opening exposes the surface of the bottom channel layer.

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