SGT MOSFET device and manufacturing method thereof, electronic device and manufacturing method thereof

Abstract

The present invention provides a method for fabricating an SGT MOSFET device, comprising: forming a substrate, a first epitaxial layer, a first field oxide layer, and a first gate trench; forming a shield gate and a cavity; filling a portion of the first gate trench with the shield gate; forming a cavity in the unfilled first gate trench at the top of the shield gate; wherein the top of the shield gate is a flat surface; forming an intergate oxide layer, a second epitaxial layer, a second field oxide layer, and a gate; forming an interlayer dielectric layer, a body ion implantation region, a source ion implantation region, and a contact hole; wherein the body ion implantation region and the source ion implantation region are sequentially formed in the second epitaxial layer around the gate in a direction away from the first epitaxial layer; forming an interlayer dielectric layer on the surface of the gate and source ion implantation region; and forming a contact hole penetrating the interlayer dielectric layer, the body ion implantation region, and a portion of the source ion implantation region. This technical solution solves the problem of how to reduce the characteristic dimensions of SGT MOSFET devices.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular to an SGT MOSFET device and a preparation method thereof, an electronic device and a preparation method thereof. Background Art

[0002] In current SGT products, lateral depletion of the two-dimensional electric field plays a crucial role in the device's electrical parameters. This is primarily achieved through lateral depletion of the bottom shield gate, Sourcepoly. To ensure two-dimensional depletion of the device, the width of the Sourcepoly must be specified. This leads to further scaling issues due to channel concentration requirements for the mesa width. Furthermore, maintaining an extremely small mesa width and maintaining a certain Sourcepoly width makes device scaling a challenge. Furthermore, filling the IPO during device fabrication is a major process challenge. Furthermore, issues with polysilicon filling can create gaps, preventing the device from achieving 90-degree trenches, further complicating device scaling.

[0003] Therefore, developing a process for preparing small-sized SGT devices has become a technical focus that needs to be urgently addressed by those skilled in the art. Summary of the Invention

[0004] The present invention provides an SGT MOSFET device and a manufacturing method thereof, an electronic device and a manufacturing method thereof, so as to solve the problem of how to reduce the characteristic size of the SGT MOSFET device.

[0005] According to a first aspect of the present invention, a method for preparing an SGT MOSFET device is provided, comprising:

[0006] forming a substrate, a first epitaxial layer, a first field oxide layer, and a first gate trench; wherein the first epitaxial layer is formed on the substrate; the first gate trench is formed in the first epitaxial layer; and the first field oxide layer is formed on the inner wall of the first gate trench and on the surface of the first epitaxial layer;

[0007] A shielding gate and a cavity are formed; the shielding gate is filled in a portion of the first gate trench; the first gate trench not filled with the top of the shielding gate forms the cavity; wherein the top of the shielding gate is a flat surface;

[0008] forming an intergate oxide layer, a second epitaxial layer, a second field oxide layer, and a gate; wherein the second epitaxial layer is formed on top of the first epitaxial layer; the intergate oxide layer is formed in the cavity; the gate is formed on top of the intergate oxide layer; and the second field oxide layer is formed between the gate and the second epitaxial layer;

[0009] An interlayer dielectric layer, a body ion implantation region, a source ion implantation region, and a contact hole are formed; wherein the body ion implantation region and the source ion implantation region are sequentially formed in the second epitaxial layer around the gate in a direction away from the first epitaxial layer; the interlayer dielectric layer is formed on the surface of the gate and the source ion implantation region; the contact hole penetrates the interlayer dielectric layer, the body ion implantation region, and a portion of the source ion implantation region.

[0010] Optionally, forming the shielding gate and the cavity specifically includes:

[0011] Depositing a shielding gate material in the first gate trench and on the surface of the first field oxide layer outside the first gate trench;

[0012] The shield gate material is etched to form the shield gate in a portion of the first gate trench and to form the cavity at a top of the shield gate.

[0013] Optionally, the aspect ratio of the cavity is 0.5:1 to 3:1.

[0014] Optionally, forming an inter-gate oxide layer, a second epitaxial layer, a second field oxide layer, and a gate specifically includes:

[0015] Filling the cavity with an inter-gate oxide layer material and simultaneously removing the first field oxide layer on the surface of the first epitaxial layer; wherein the height of the inter-gate oxide layer material is flush with the height of the first epitaxial layer;

[0016] Depositing a second epitaxial layer material on top of the inter-gate oxide layer material and the first epitaxial layer;

[0017] forming a patterned hard mask layer; the patterned hard mask layer is formed on the surface of the second epitaxial layer material;

[0018] Using the patterned mask layer as a mask, etching the second epitaxial layer material and exposing the inter-gate oxide layer material to form a second gate trench and the second epitaxial layer; and etching the surface layer of the middle portion of the inter-gate oxide layer material to form the inter-gate oxide layer; wherein the edge height of the inter-gate oxide layer is greater than the height of the middle portion;

[0019] removing the patterned hard mask;

[0020] A second field oxide layer and a gate are formed; the second field oxide layer is formed on the inner wall of the second gate trench and the surface of the second epitaxial layer; and the gate is formed in the second gate trench.

[0021] Optionally, filling the cavity with an intergate oxide layer material and removing the first field oxide layer on the surface of the first epitaxial layer specifically includes:

[0022] depositing an intergate oxide layer material in the cavity and on the surface of the first field oxide layer;

[0023] The inter-gate oxide layer material and the first field oxide layer on the surface of the first epitaxial layer are etched so that the height of the inter-gate oxide layer material is flush with the height of the first epitaxial layer; wherein the top of the inter-gate oxide layer material is a flat surface.

[0024] Optionally, the thickness of the edge portion of the inter-gate oxide layer is 3000Å-4000Å.

[0025] Optionally, after etching the surface layer of the middle portion of the inter-gate oxide layer material to form the inter-gate oxide layer, the method further includes:

[0026] The edge portion of the inter-gate oxide layer is rounded.

[0027] Optionally, a height difference between the gate and the second epitaxial layer is between 500A and 1000A.

[0028] Optionally, the lateral width of the second gate trench is reduced by 20%-50% relative to the lateral width of the first gate trench.

[0029] According to a second aspect of the present invention, there is provided an SGT MOSFET device, which is manufactured using the SGT MOSFET manufacturing method according to any one of the first aspects of the present invention, and the device comprises:

[0030] The substrate, the first epitaxial layer, the first field oxide layer and the first gate trench; wherein the first field oxide layer is formed on the inner wall of the first gate trench;

[0031] The shielding gate is filled in a portion of the first gate trench, wherein the top of the shielding gate is a flat surface;

[0032] The inter-gate oxide layer, the second epitaxial layer, the second field oxide layer and the gate; wherein the inter-gate oxide layer is formed in the first gate trench that is not filled at the top of the shielding gate;

[0033] The interlayer dielectric layer, the body ion implantation region, the source ion implantation region and the contact hole.

[0034] Optionally, the top of the shielding gate is a flat surface.

[0035] Optionally, the middle portion of the top of the inter-gate oxide layer is a flat surface.

[0036] Optionally, the edge portion of the inter-gate oxide layer is a rounded structure.

[0037] According to a third aspect of the present invention, there is provided a method for manufacturing an electronic device, comprising the method for manufacturing an SGT MOSFET device according to any one of the first aspects of the present invention.

[0038] According to a fourth aspect of the present invention, an electronic device is provided, comprising the SGT MOSFET device according to any one of the second aspects of the present invention.

[0039] The technical solution provided by the present invention forms an epitaxial layer in steps, specifically comprising the following steps: a first step: forming a first epitaxial layer and a first gate trench, wherein the first gate trench is used to fill a shielding gate, wherein a portion of the cavity at the top of the first gate trench not filled by the shielding gate is used to fill an intergate oxide layer; a second step: forming a second epitaxial layer and a second gate trench, wherein the second gate trench is used to fill a gate; since the gate trenches are formed in steps, it can be seen that the shielding gate, the intergate oxide layer, and the gate are all formed in relatively shallow trenches; thus, a shielding gate, an intergate oxide layer, and a gate with a flat top and no gaps can be formed. Compared with the prior art, there is no need to increase the width of the shielding gate to balance the gap at the top. Therefore, while ensuring the distance between the gate trenches, the characteristic size of the SGT MOSFET device can be further reduced, thereby achieving a reduction in the size of the SGT MOSFET device.

[0040] Furthermore, since the inter-gate oxide layer does not shield the partial cavity of the gate at the top of the first gate trench, the aspect ratio of the inter-gate oxide layer filling is greatly reduced compared with the existing technology, so the process of filling the inter-gate oxide layer becomes particularly simple. Therefore, the technical solution provided by the present invention also solves the problem of the inter-gate oxide layer filling process. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0042] Figure 1 This is a flow chart of a method for preparing an SGT MOSFET device provided by one embodiment of the present invention;

[0043] Figure 2-101 is a schematic diagram of a device structure at different process stages according to a method for preparing an SGT MOSFET device provided by one embodiment of the present invention;

[0044] Description of reference numerals:

[0045] 101-substrate;

[0046] 102-first epitaxial layer;

[0047] 103-first field oxygen layer;

[0048] 104- shielding grid;

[0049] 105-intergate oxide layer material;

[0050] 106-second epitaxial layer;

[0051] 107-intergate oxide layer;

[0052] 108- second field oxygen layer;

[0053] 109-gate;

[0054] 110-body ion implantation region;

[0055] 111-source ion implantation region;

[0056] 112-interlayer dielectric layer;

[0057] 113-passivation layer. DETAILED DESCRIPTION

[0058] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0059] The terms "first," "second," "third," "fourth," and the like (if any) in the description and claims of the present invention and in the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a particular order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. In addition, the terms "including" and "having," as well as any variations thereof, are intended to cover non-exclusive inclusions, e.g., a process, method, system, product, or apparatus comprising a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units that are not explicitly listed or that are inherent to these processes, methods, products, or apparatus.

[0060] In SGT / Trench MOS products, due to the presence of the trench, a seam will inevitably form below the top of the trench during polysilicon formation. This seam will be magnified during polysilicon etching, making it impossible to make the shield gate into a flat surface, thus affecting device performance.

[0061] In order to solve this problem, in the existing technical means, when filling polysilicon, in order to adapt to the non-flat surface of the shielding gate and ensure the filling effect of polysilicon, the trench angle of the device is usually controlled to be less than 89 degrees (that is, the angle of the top of the gate made on the top of the shielding gate is less than 89°), which results in the thickness of the bottom polysilicon shielding gate being smaller in the non-right-angle trench filling, which reduces the charge coupling ability of the device. Therefore, in the case of lateral two-dimensional charge-coupled devices, in order to avoid gaps, the width of the gate trench is usually made larger, so that the device size will be further increased while ensuring the distance between the two adjacent shielding gates. In traditional SGT / Trench MOS products, the SGT size is between 0.8-1.2um.

[0062] As can be seen, the technical problems existing in the prior art are: the shield gate surface is uneven, with a severe V-shaped morphology; and to accommodate the gap in the shield gate, the device trench angle (i.e., the angle of the gate tip after the shield gate is formed in the gate trench) is reduced from 90° to below 89°, making it impossible to form a right-angled trench. The shield gate width is increased, thus causing problems in reducing the feature size of the device. Furthermore, the conventional process method, when depositing the inter-gate oxide layer, has a large depth-to-width ratio in the cavity portion at the top of the gate trench, resulting in poor quality of the inter-gate oxide layer and greater process difficulty.

[0063] In view of this, the inventors of the present application form the epitaxial layer in steps. First, a first epitaxial layer and a shallower trench are formed to fill the shielding gate and the inter-gate oxide layer; secondly, a second epitaxial layer and a top trench are formed to fill the gate; since the gate trench is formed in steps, the shielding gate and the inter-gate oxide layer are formed in the shallower trench; not only can a shielding gate with a flat surface be formed, but also the technical effect of ensuring that the device has better electrical properties is achieved; and finally a surface flatness angle is formed at the top of the gate, so that the trench angle can be 90°, avoiding the production of a wider shielding gate. Compared with the existing technology, the feature size is reduced, so that the device size can be further reduced when the distance between the gate trenches is constant; further, because the device greatly reduces the aspect ratio of IPO filling, the IPO filling process becomes particularly simple, thereby solving the problem of IPO filling process.

[0064] The following specific embodiments are used to describe the technical solution of the present invention in detail. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0065] Please refer to Figures 1-10 According to one embodiment of the present invention, a method for preparing an SGT mosfet device is provided. The flow chart of the method for preparing an SGT mosfet device is as follows: Figure 1 As shown, the method includes:

[0066] S11: forming a substrate 101, a first epitaxial layer 102, a first field oxide layer 103 and a first gate trench; wherein the first epitaxial layer 102 is formed on the substrate 101; the first gate trench is formed in the first epitaxial layer 102; the first field oxide layer 103 is formed on the inner wall of the first gate trench and on the surface of the first epitaxial layer 102, as shown in FIG. Figure 2 As shown;

[0067] S12: forming a shielding gate 104 and a cavity; the shielding gate 104 is filled in part of the first gate trench; the top of the shielding gate 104 is not filled in the first gate trench to form the cavity; wherein the top of the shielding gate 104 is a flat surface, such as Figure 3 As shown;

[0068] S13: forming an inter-gate oxide layer, a second epitaxial layer 106, a second field oxide layer 108 and a gate 109; wherein the second epitaxial layer 106 is formed on the top of the first epitaxial layer 102; the inter-gate oxide layer is formed in the cavity; the gate 109 is formed on the top of the inter-gate oxide layer; the second field oxide layer 108 is formed between the gate 109 and the second epitaxial layer 106, as shown in FIG. Figure 8As shown;

[0069] S14: forming an interlayer dielectric layer 112, a body ion implantation region 110, a source ion implantation region 111, and a contact hole; wherein the body ion implantation region 110 and the source ion implantation region 111 are sequentially formed in the second epitaxial layer 106 around the gate 109 in a direction away from the first epitaxial layer 102; the interlayer dielectric layer 112 is formed on the surface of the gate 109 and the source ion implantation region 111; the contact hole penetrates the interlayer dielectric layer 112, the body ion implantation region 110, and a portion of the source ion implantation region 111, and the device after the interlayer dielectric layer 112 is formed is as follows: Figure 9 As shown, the device after forming the contact hole is as follows Figure 10 shown.

[0070] After step S14, the process further includes forming a passivation layer 113; the passivation layer 113 covers the interlayer dielectric layer 112 and the source ion implantation region 111. Figure 10 shown.

[0071] The technical solution provided by the present invention forms an epitaxial layer in steps, specifically including the following steps: a first step: forming a first epitaxial layer and a first gate trench, wherein the first gate trench is used to fill a shielding gate, wherein the portion of the cavity at the top of the first gate trench not filled by the shielding gate is used to fill an intergate oxide layer; a second step: forming a second epitaxial layer and a second gate trench, wherein the second gate trench is used to fill a gate; because the gate trenches are formed in steps, it can be seen that the shielding gate, the intergate oxide layer, and the gate are all formed in relatively shallow trenches; thus, a shielding gate, an intergate oxide layer, and a gate with a flat top and no gaps can be formed. Compared with the prior art, there is no need to increase the width of the shielding gate to balance the gaps at the top. Therefore, while ensuring the distance between the gate trenches, the characteristic size of the SGT MOSFET device can be further reduced, thereby achieving a reduction in the size of the SGT MOSFET device. Therefore, the technical solution provided by the present invention solves the problem of how to reduce the characteristic size of the SGT MOSFET device.

[0072] Furthermore, since the inter-gate oxide layer does not shield the partial cavity of the gate at the top of the first gate trench, the aspect ratio of the inter-gate oxide layer filling is greatly reduced compared with the existing technology, so the process of filling the inter-gate oxide layer becomes particularly simple. Therefore, the technical solution provided by the present invention also solves the problem of the inter-gate oxide layer filling process.

[0073] In one embodiment, in step S12, forming the shielding gate 104 and the cavity specifically includes steps S121-S122:

[0074] Step S121: depositing a shielding gate material in the first gate trench and on the surface of the first field oxide layer 103 outside the first gate trench;

[0075] Step S122 : etching the shielding gate material to form the shielding gate 104 in a portion of the first gate trench, and forming the cavity at the top of the shielding gate 104 .

[0076] In one embodiment, the aspect ratio of the cavity is 0.5:1 to 3:1.

[0077] In one embodiment, in step S13, forming the inter-gate oxide layer 107, the second epitaxial layer 106, the second field oxide layer 108 and the gate 109 specifically includes steps S131-S136:

[0078] Step S131: Filling the inter-gate oxide layer material 105 in the cavity and removing the first field oxide layer 103 on the surface of the first epitaxial layer 102; wherein the height of the inter-gate oxide layer material 105 is flush with the height of the first epitaxial layer 102, as shown in FIG. Figure 4 As shown;

[0079] In one embodiment, in step S131, the inter-gate oxide layer material 105 is filled in the cavity, and the first field oxide layer 103 on the surface of the first epitaxial layer 102 is removed, which specifically includes steps S1311-S1312:

[0080] Step S1311: depositing an inter-gate oxide layer material in the cavity and on the surface of the first field oxide layer 103;

[0081] Step S1312: etching the inter-gate oxide layer material 105 and the first field oxide layer 103 on the surface of the first epitaxial layer 102 so that the height of the inter-gate oxide layer material 105 is flush with the height of the first epitaxial layer 102; wherein the top of the inter-gate oxide layer material 105 is a flat surface.

[0082] In one embodiment, the thickness of the edge portion of the inter-gate oxide layer 107 is 3000 Å-4000 Å.

[0083] Step S132: depositing a second epitaxial layer 106 material on top of the inter-gate oxide layer material 105 and the first epitaxial layer 102, such as Figure 5 As shown;

[0084] Step S133: forming a patterned hard mask layer; the patterned hard mask layer is formed on the surface of the second epitaxial layer 106 material;

[0085] Step S134: using the patterned mask layer (not shown in the figure) as a mask, etching the second epitaxial layer 106 material and exposing the inter-gate oxide layer material 105 to form a second gate trench and the second epitaxial layer 106; and etching the surface of the middle portion of the inter-gate oxide layer material 105 to form the inter-gate oxide layer 107; wherein the edge height of the inter-gate oxide layer 107 is greater than the height of the middle portion, as shown in FIG. Figure 6 As shown;

[0086] In one embodiment, the lateral width of the second gate trench is reduced by 20%-50% relative to the lateral width of the first gate trench.

[0087] In one embodiment, in step S134, after etching the surface layer of the middle portion of the inter-gate oxide layer material 105 to form the inter-gate oxide layer 107, the process further includes:

[0088] The edge of the inter-gate oxide layer 107 is rounded.

[0089] Step S135: removing the patterned hard mask;

[0090] Step S136: forming a second field oxide layer 108 and a gate 109; the second field oxide layer 108 is formed on the inner wall of the second gate trench and the surface of the second epitaxial layer 106, as shown in FIG. Figure 7 As shown; the gate 109 is formed in the second gate trench, as shown Figure 8 shown.

[0091] In one embodiment, the height difference between the gate 109 and the second epitaxial layer 106 is between 500 Å and 1000 Å.

[0092] According to another embodiment of the present invention, there is further provided an SGT MOSFET device, which is manufactured using the SGT MOSFET manufacturing method described in any of the aforementioned embodiments of the present invention, and includes:

[0093] The substrate 101, the first epitaxial layer 102, the first field oxide layer 103 and the first gate trench; wherein the first field oxide layer 103 is formed on the inner wall of the first gate trench;

[0094] The shielding gate 104 is filled in a portion of the first gate trench, wherein the top of the shielding gate 104 is a flat surface;

[0095] The inter-gate oxide layer 107, the second epitaxial layer 106, the second field oxide layer 108 and the gate 109; wherein the inter-gate oxide layer 107 is formed in the unfilled first gate trench at the top of the shielding gate 104;

[0096] The interlayer dielectric layer 112 , the body ion implantation region 110 , the source ion implantation region 111 and the contact hole.

[0097] In one embodiment, the top of the shielding gate 104 is a flat surface.

[0098] In one embodiment, the middle portion of the top of the inter-gate oxide layer 107 is a flat surface.

[0099] In one embodiment, the edge portion of the inter-gate oxide layer 107 is a rounded structure.

[0100] Secondly, according to an embodiment of the present invention, a method for manufacturing an electronic device is also provided, including the method for manufacturing the SGT MOSFET device according to any one of the aforementioned embodiments of the present invention.

[0101] In addition, according to an embodiment of the present invention, an electronic device is provided, comprising the SGT MOSFET device according to any one of the aforementioned embodiments of the present invention.

[0102] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for preparing an SGT mosfet device, characterized in that: include: forming a substrate, a first epitaxial layer, a first field oxide layer, and a first gate trench; wherein the first epitaxial layer is formed on the substrate; the first gate trench is formed in the first epitaxial layer; and the first field oxide layer is formed on the inner wall of the first gate trench and on the surface of the first epitaxial layer; A shielding gate and a cavity are formed; the shielding gate is filled in a portion of the first gate trench; the first gate trench not filled with the top of the shielding gate forms the cavity; wherein the top of the shielding gate is a flat surface; forming an intergate oxide layer, a second epitaxial layer, a second field oxide layer, and a gate; wherein the second epitaxial layer is formed on top of the first epitaxial layer; the intergate oxide layer is formed in the cavity; the gate is formed on top of the intergate oxide layer; and the second field oxide layer is formed between the gate and the second epitaxial layer; An interlayer dielectric layer, a body ion implantation region, a source ion implantation region, and a contact hole are formed; wherein the body ion implantation region and the source ion implantation region are sequentially formed in the second epitaxial layer around the gate in a direction away from the first epitaxial layer; the interlayer dielectric layer is formed on the surface of the gate and the source ion implantation region; the contact hole penetrates the interlayer dielectric layer, the body ion implantation region, and a portion of the source ion implantation region; The forming of the shielding gate and the cavity specifically includes: Depositing a shielding gate material in the first gate trench and on the surface of the first field oxide layer outside the first gate trench; Etching the shield gate material to form the shield gate in a portion of the first gate trench and forming the cavity at a top of the shield gate; The process of forming an inter-gate oxide layer, a second epitaxial layer, a second field oxide layer, and a gate specifically includes: Filling the cavity with an inter-gate oxide layer material and simultaneously removing the first field oxide layer on the surface of the first epitaxial layer; wherein the height of the inter-gate oxide layer material is flush with the height of the first epitaxial layer; Depositing a second epitaxial layer material on top of the inter-gate oxide layer material and the first epitaxial layer; forming a patterned hard mask layer; the patterned hard mask layer is formed on the surface of the second epitaxial layer material; Using the patterned mask layer as a mask, etching the second epitaxial layer material and exposing the inter-gate oxide layer material to form a second gate trench and the second epitaxial layer; and etching the surface layer of the middle portion of the inter-gate oxide layer material to form the inter-gate oxide layer; wherein the edge height of the inter-gate oxide layer is greater than the height of the middle portion; removing the patterned hard mask; A second field oxide layer and a gate are formed; the second field oxide layer is formed on the inner wall of the second gate trench and the surface of the second epitaxial layer; and the gate is formed in the second gate trench.

2. The method for preparing the SGT MOSFET device according to claim 1, wherein: The aspect ratio of the cavity is 0.5:1 to 3:

1.

3. The method for preparing the SGT MOSFET device according to claim 2, wherein: Filling the cavity with an intergate oxide layer material and removing the first field oxide layer on the surface of the first epitaxial layer specifically includes: depositing an intergate oxide layer material in the cavity and on the surface of the first field oxide layer; The inter-gate oxide layer material and the first field oxide layer on the surface of the first epitaxial layer are etched so that the height of the inter-gate oxide layer material is flush with the height of the first epitaxial layer; wherein the top of the inter-gate oxide layer material is a flat surface.

4. The method for preparing the SGT MOSFET device according to claim 3, wherein: The thickness of the edge portion of the inter-gate oxide layer is 3000Å-4000Å.

5. The method for preparing the SGT MOSFET device according to claim 4, characterized in that: After etching the surface layer of the middle portion of the inter-gate oxide layer material to form the inter-gate oxide layer, the method further includes: The edge portion of the inter-gate oxide layer is rounded.

6. The method for preparing the SGT MOSFET device according to claim 5, characterized in that: A height difference between the gate and the second epitaxial layer is between 500A and 1000A.

7. The method for preparing the SGT MOSFET device according to claim 6, wherein: The lateral width of the second gate trench is reduced by 20%-50% relative to the lateral width of the first gate trench.

8. An SGT mosfet device, characterized in that: The device is manufactured using the method for preparing an SGT MOSFET according to any one of claims 1 to 7, and comprises: The substrate, the first epitaxial layer, the first field oxide layer and the first gate trench; wherein the first field oxide layer is formed on the inner wall of the first gate trench; The shielding gate is filled in a portion of the first gate trench, wherein the top of the shielding gate is a flat surface; The inter-gate oxide layer, the second epitaxial layer, the second field oxide layer and the gate; wherein the inter-gate oxide layer is formed in the first gate trench that is not filled at the top of the shielding gate; The interlayer dielectric layer, the body ion implantation region, the source ion implantation region and the contact hole.

9. The SGT MOSFET device according to claim 8, characterized in that: The top of the shielding grid is a flat surface.

10. The SGT MOSFET device according to claim 9, characterized in that: The middle portion of the top of the inter-gate oxide layer is a flat surface.

11. The SGT MOSFET device according to claim 10, wherein: The edge portion of the inter-gate oxide layer is a rounded structure.

12. A method for preparing an electronic device, comprising the method for preparing the SGT MOSFET device according to any one of claims 1 to 7.

13. An electronic device comprising the SGT MOSFET device according to any one of claims 8 to 11.

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