A low-parasitic GaN HEMT device with a cavity structure and its fabrication method

Abstract

The application discloses a low parasitic GaN HEMT device with a cavity structure and a manufacturing method thereof. The structure of the device comprises, from bottom to top, a substrate, a GaN buffer layer, a barrier layer, an active electrode, a drain electrode and a SiN passivation thin layer above the barrier layer, a recess is formed in the SiN passivation thin layer, and two micro field plates are arranged on the two sides of the recess. The micro field plates are part of an M-shaped gate, and a secondary passivation layer is wrapped on the M-shaped gate to form a cavity. The application first proposes to form an M-shaped gate with two upward protrusions by using a temporary gate control layer, and then forms a cavity by secondary passivation and stabilizes the gate, so that the parasitic capacitance effect is effectively inhibited. In addition, through the self-aligned micro field plate structure, the breakdown voltage of the device is improved, and the current collapse is inhibited. The application effectively solves the contradiction between the breakdown voltage and the frequency characteristics of the traditional T-shaped gate GaN HEMT device, and can be applied to the field of microwave and millimeter wave power devices.

Description

Technical Field

[0001] This invention relates to GaN HEMT devices, and more particularly to a low-parasitic GaN HEMT device with a cavity structure and a method for manufacturing the same. Background Technology

[0002] With the rapid rise of 5G technology, GaN HEMTs, which boast excellent performance in the microwave and millimeter-wave fields, have become a research hotspot. To achieve higher cutoff frequencies, [f...]. T At the same time, to avoid increasing the gate resistance as much as possible, GaN HEMT devices have adopted T-gate structures to further shorten the gate length and improve frequency characteristics. Although the T-gate structure can significantly improve the cutoff frequency of the device, the traditional T-gate structure still has problems such as gate instability and poor breakdown characteristics. Improving the traditional T-gate structure has become one of the key research directions of various research institutions at home and abroad in recent years.

[0003] Generally, depositing a gate protection dielectric layer on top of the T-gate can effectively stabilize the T-gate and suppress current collapse. However, traditional gate protection dielectric passivation schemes have the following problems: if the passivation dielectric is too thin, it cannot stabilize the T-gate; if the passivation dielectric is too thick, it will cause a large parasitic effect and degrade the frequency characteristics of the device.

[0004] Meanwhile, field plate structure is one of the important means to improve breakdown voltage, suppress current collapse, and thus improve power characteristics in the fabrication process of GaN HEMT devices. Its drawback is that it introduces parasitic capacitance that affects frequency characteristics, which is contrary to the design concept of T-gate. Therefore, it is rarely directly applied to the fabrication process of GaN HEMT devices based on T-gate.

[0005] To balance the excellent frequency characteristics of the T-gate structure and the excellent power characteristics of the field plate structure, the idea of ​​manipulating the gate morphology to form a micro field plate has been proposed and has attracted widespread attention. S. Bouzid-Driad manipulated the T-gate morphology using multilayer adhesives such as PMMA, and deposited SiN after gate fabrication to form a micro field plate, thereby improving the frequency and breakdown characteristics of the device (see S. Bouzid-Driad al., "AlGaN / GaN HEMTs on Silicon Substrate With 206-GHz F..."). MAX (IEEE ELECTRON DEVICE LETTERS, Vol. 34, No. 1, January 2013), f was obtained at a gate length of 90 nm. T =100GHz, f maxThe device boasts excellent performance of 206 GHz. However, this technology does not perform surface passivation. Instead, a 50 nm SiN gate protective dielectric is grown after the T-gate is fabricated. Due to the obstruction of the gate metal, it is difficult to uniformly cover the SiN under the microfield plate. In addition, because the passivation dielectric is very thin, there is also the problem of unstable T-gate structure, which is very easy to collapse.

[0006] In addition, Jeong-sun Moon reported a T-gate GaN HEMT device with a micro-field plate (see Jeong-sun Moon et al., "Power Scaling of Graded-Channel GaN HEMTs With Mini-Field-Plate T-gate and 156GHz f T (IEEE Electron Device Letters, vol.42, no.6, pp.796-799, June 2021) Research shows that the micro-field plate structure reduces the peak electric field between the gate and drain, and improves the breakdown voltage of the device. However, in addition to the problem of the instability of the T-gate structure, this technology also causes a serious degradation of the frequency characteristics of the device after passivation.

[0007] In summary, although the studies in the two aforementioned papers have achieved preliminary fabrication of microfield plate structures and improved frequency and breakdown characteristics, they still employ the traditional method of passivating SiN after T-gate fabrication. This method fails to ensure uniform SiN dielectric coverage of the surface beneath the microfield plate, and the thin dielectric layer cannot guarantee the stability of the gate structure, hindering subsequent processing. Furthermore, because the morphology of the T-gate is not controlled, cavities cannot be formed after passivation, thus exacerbating the device's capacitive parasitic effects. Summary of the Invention

[0008] Purpose of the invention: The purpose of this invention is to provide a low-parasitic GaN HEMT device with a cavity structure and its manufacturing method, which can suppress the adverse effects of passivation layer parasitic effects and improve the breakdown and frequency characteristics of GaN microwave power devices.

[0009] Technical solution: The low parasitic GaN HEMT device of the present invention comprises, from bottom to top, a substrate, a GaN buffer layer, and a barrier layer. A source and a drain are disposed above the barrier layer. A SiN passivation thin layer is disposed above the source, drain, and barrier layer, respectively. A groove is disposed in the SiN passivation thin layer above the barrier layer. Microfield plates are disposed on both sides above the groove. The microfield plates and the M-type gate are integrally structured. The lower part of the middle of the M-type gate is disposed in the groove. A secondary passivation layer is disposed above and on both sides of the M-type gate. A cavity is provided between the M-type gate and the secondary passivation layer.

[0010] Furthermore, the depth of the groove is the same as the thickness of the SiN passivation thin layer, which has a thickness of 30nm to 100nm.

[0011] Furthermore, the lengths of the microfield plates are all between 20 nm and 50 nm.

[0012] Furthermore, the M-type gate is a structure with upward protrusions on both sides formed by a temporary gate-shaped layer. The cavity is located between the secondary passivation layer and the M-type gate and is composed of air with a low dielectric constant. The metal thickness of the M-type gate is not less than 500 nm. The thickness of the secondary passivation layer is 150 nm to 300 nm.

[0013] A method for fabricating a low-parasitic GaN HEMT device with a cavity structure includes the following steps:

[0014] S1, through photolithography, evaporation, lift-off processes and high-temperature annealing, forms the source and drain on the barrier layer;

[0015] S2, depositing a thin SiN passivation layer on the surface of the barrier layer, source, and drain;

[0016] S3, a temporary gate-controlled dielectric layer is deposited over the SiN passivation thin layer;

[0017] S4, spin-coating electron beam negative adhesive, directly writing two adhesive masks between the source and drain;

[0018] S5, dry etching is used to remove the temporary gate control layer dielectric outside the two resist masks, and the resist is removed to obtain the two temporary gate control structures;

[0019] S6. Spin-coat the first layer of electron beam positive adhesive onto the substrate surface. Define the gate pin pattern by electron beam direct writing between the two temporary gate control structures.

[0020] S7, then spin-coat the second layer of electron beam positive adhesive, and define the grid cap pattern by electron beam direct writing;

[0021] S8, dry etching is used to etch the SiN passivation thin layer between the gate pins and obtain the groove;

[0022] S9, through high-temperature oxygen plasma treatment to control the gel type of electron beam adhesive on both sides above the groove, forms a self-aligned microfield plate after evaporation and peeling.

[0023] S10, through high selectivity wet etching, removes the temporary gate control structure to form an M-type gate with micro-field plate structure and upward protrusion on both sides;

[0024] S11, a secondary passivation layer is deposited to encapsulate the M-type gate and form a cavity.

[0025] Furthermore, the temporary gate-controlled layer medium is SiO2 or W, which has high selectivity corrosion characteristics.

[0026] Furthermore, in step S4, the thickness of the electron beam negative adhesive is 300–500 nm; in step S6, the thickness of the first electron beam positive adhesive is 300–500 nm; and in step S7, the thickness of the second electron beam positive adhesive is 600–900 nm.

[0027] Furthermore, in step S9, the high-temperature oxygen plasma treatment is a constant-temperature treatment with a temperature of 70–100°C, an oxygen flow rate of 200–400 sccm, a nitrogen flow rate of 50–150 sccm, and a treatment time of 3–5 min.

[0028] Furthermore, in step S10, the high selectivity wet etching solution is BOE or H2O2.

[0029] Furthermore, the source and drain materials are any one of Ti / Al / Ni / Au, Ta / Ti / Al / Ni / Au, and Si / Ti / Al / Ni / Au, respectively; the M-type gate material is any one of Ni / Au, Ni / Pt / Au, and Ni / Pt / Au / Ti; and the secondary passivation layer material is any one of SiN, SiON, and SiO2.

[0030] Compared with the prior art, the significant advantages of this invention are as follows:

[0031] 1. The present invention obtains an M-shaped gate structure with upward protrusion on both sides by using a temporary gate control layer to regulate the morphology of the gate metal, and then wraps the M-shaped gate with a secondary passivation layer to form a cavity, thereby achieving the dual effect of stabilizing the gate structure and reducing parasitic capacitance effect.

[0032] 2. This invention introduces the design concept of field plate structure into M-type gate GaN HEMT devices. The self-aligned micro field plate structure weakens the peak electric field near the gate foot, thereby improving the breakdown voltage of the device and effectively suppressing the current collapse effect. Attached Figure Description

[0033] Figure 1 This is a cross-sectional structural diagram of the present invention;

[0034] Figure 2(a) is a schematic diagram of depositing a SiN passivation thin layer on the substrate surface;

[0035] Figure 2(b) is a schematic diagram of the deposition of a temporary SiO2 gate-controlled layer over a SiN passivation thin layer;

[0036] Figure 2(c) is a schematic diagram of the two temporary SiO2 gate-controlled layers obtained;

[0037] Figure 2(d) is a schematic diagram of the gate pin pattern in the middle of the SiO2 temporary gate control layer;

[0038] Figure 2(e) is a schematic diagram of the obtained grid cap pattern;

[0039] Figure 2(f) is a schematic diagram of the grooves formed on the SiN passivation thin layer;

[0040] Figure 2(g) is a schematic diagram of the formation of a self-aligned microfield plate;

[0041] Figure 2(h) is a schematic diagram of the formation of an M-type gate;

[0042] Figure 2(i) is a schematic diagram of the cavity formation. Detailed Implementation

[0043] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.

[0044] like Figure 1 The diagram shows a low-parasitic GaN HEMT device of the present invention. Its structure, from bottom to top, includes a substrate 1, a GaN buffer layer 2, and a barrier layer 3. Above the barrier layer 3 are a source electrode 4, a drain electrode 5, and a SiN passivation thin layer 6. A groove 7 is formed in the SiN passivation thin layer 6 by etching. Microfield plates 8 are located on both sides above the groove 7. An M-type gate 9 with upward protrusions on both sides is formed by controlling a temporary gate shaping layer. Then, a secondary passivation layer 10 is deposited above the M-type gate 9 to form a low-parasitic GaN HEMT device with a cavity 11. Wherein:

[0045] Substrate 1 is any one of Si, SiC and sapphire substrates.

[0046] The third barrier layer is any one of AlGaN, InAlN, and AlN.

[0047] This invention obtains an M-shaped gate 9 with upward protrusions on both sides by controlling the temporary gate shaping layer, and deposits a secondary passivation layer 10 to encapsulate the M-shaped gate to prevent it from collapsing in subsequent processes, thereby improving the stability of the device. In addition, the M-shaped gate metal structure is used to block the gas that diffuses inward during the deposition process, thereby obtaining a cavity 11 composed of air with a low dielectric constant, which reduces the parasitic capacitance effect.

[0048] The present invention also designs a self-aligned micro field plate structure, which is composed of field plate metal extending outward from both sides above the groove. The field plate metal improves the electric field distribution near the gate foot, weakens the sharp peak electric field at the edge of the gate foot and thus improves the breakdown voltage. At the same time, the weakening of the electric field is also conducive to suppressing the formation of electron traps, improving the virtual gate charging phenomenon and suppressing the current collapse effect.

[0049] The method for fabricating a low-parasitic GaN HEMT device according to the present invention specifically includes the following steps:

[0050] 1) The source electrode 4 and drain electrode 5 are formed on the barrier layer 3 by photolithography, evaporation, stripping and high temperature annealing;

[0051] 2) SiN passivation thin layer 6 is deposited on the surface of barrier layer 3, source 4 and drain 5 using MOCVD, ALD, PECVD, LPCVD, ICP-CVD and other methods. The thickness of SiN passivation thin layer 6 is preferably 30 to 100 nm, as shown in Figure 2(a).

[0052] 3) A temporary SiO2 gate-shaped layer is deposited on top of the SiN passivation thin layer 6 using methods such as PECVD, LPCVD, and ICP-CVD. The thickness of the layer is preferably 150-350 nm, as shown in Figure 2(b).

[0053] 4) Spin-coat electron beam negative adhesive over the SiO2 temporary gate control layer, and write two first adhesive masks between the source electrode 4 and the drain electrode 5. The width of the two first adhesive masks is preferably 200-400 nm and the thickness is preferably 300-500 nm.

[0054] 5) The SiO2 outside the two resist masks is removed by dry etching methods such as ICP and RIE, and the resist is removed to obtain two SiO2 temporary gate structures 201. The width of the SiO2 temporary gate structure 201 is preferably 200-400nm and the thickness is preferably 150-350nm, as shown in Figure 2(c).

[0055] 6) Spin-coat the first layer of electron beam positive resist. The second resist mask 202 obtained by electron beam direct writing defines the gate pin located in the middle of the SiO2 temporary gate control structure 201. The distance between the gate pin and the SiO2 temporary gate control structures 201 on both sides is the same and preferably 50-200nm. The thickness of this resist layer is preferably 300-500nm, as shown in Figure 2(d).

[0056] 7) Next, spin-coat the second layer of electron beam positive resist, preferably with a resist thickness of 600-900 nm. Define the gate cap by the third resist mask 203 obtained by electron beam direct writing, as shown in Figure 2(e);

[0057] 8) The SiN passivation thin layer 6 exposed at the gate foot is etched using ICP, RIE and other methods to form a groove 7. The depth of the groove 7 is the same as the thickness of the SiN passivation thin layer 6, as shown in Figure 2(f).

[0058] 9) The adhesive pattern of the second adhesive mask 202 on both sides above the groove 7 is controlled by high temperature oxygen plasma treatment. After the second adhesive mask 202 and the third adhesive mask 203 are removed by evaporation and peeling, a self-aligned micro field plate 8 and an M-type gate 9 with upward protrusion on both sides are formed. The length of the micro field plate 8 is preferably 20-50nm and the metal thickness of the M-type gate 9 is not less than 500nm, as shown in Figure 2(g).

[0059] 10) The SiO2 temporary gate structure 201 was removed by high-selectivity etching with BOE solution for 20-40 s, as shown in Figure 2(h).

[0060] 11) A secondary passivation layer 10 is deposited using methods such as MOCVD, ALD, PECVD, LPCVD, and ICP-CVD. The area of ​​dielectric deposition is controlled by the upward protrusion structure on both sides of the M-type gate 9, and a cavity 11 is formed, as shown in Figure 2(i). The secondary passivation layer 10 is preferably SiN, SiON, or SiO2, and its thickness is preferably 150–300 nm.

[0061] Based on the structure and manufacturing method of the present invention described above, the present invention provides the following embodiment, but is not limited to these embodiments.

[0062] Example 1

[0063] The fabrication process for a low-parasitic GaNHEMT device with a Si substrate, an AlGaN barrier layer, a microfield plate length of 40 nm, and a SiN secondary passivation layer is as follows:

[0064] A1) The source and drain regions are defined on the AlGaN barrier layer using photoresist as a mask. The source and drain electrodes are obtained by evaporation, stripping, and high-temperature annealing. The evaporation and annealing conditions for the source and drain electrodes are: vacuum degree ≤ 2 × 10⁻⁶. -6 Torr, the source and drain metals are Ta / Ti / Al / Ni / Au with thicknesses of 5 / 20 / 130 / 40 / 50nm respectively, the annealing temperature is 800℃, the annealing time is 30s, and the annealing gas atmosphere is N2;

[0065] A2) A 50 nm SiN passivation thin layer was deposited on the surface using PECVD. The dielectric deposition conditions were as follows: gases were SiH4, NH3 and N2, with flow rates of 200 sccm, 2400 sccm and 10 sccm, respectively; pressure was 550 mTorr; temperature was 300 ℃; and power was 40 W.

[0066] A3) A 200 nm thick SiO2 layer was deposited on top of the SiN passivation thin layer using PECVD; the dielectric deposition conditions were: gases SiH4, He and N2O, with flow rates of 20 sccm, 100 sccm and 50 sccm, pressure of 600 mTorr, temperature of 250℃ and power of 100 W.

[0067] A4) Spin-coat electron beam negative resist AR-N 7520.17 on top of SiO2, and obtain two resist masks located between the source and drain electrodes by direct electron beam writing and development with AR300-46 negative resist developer. The width of the two resist masks is 200nm and the thickness is 500nm.

[0068] A5) The SiO2 outside the two resist masks was removed by F-based ICP dry etching, and the resist was removed to obtain two temporary SiO2 gate structures. The width and thickness of the temporary SiO2 gate structures were 200 nm. The etching conditions were: the etching gas was CHF3, the gas flow rate was 20 sccm, the upper electrode power was 150 W, the temperature was 100 °C, and the etching depth was 200 nm.

[0069] A6) Spin-coating electron beam positive adhesive AR-P 6200.09, defining the gate pin pattern by direct electron beam writing and development with butyl acetate organic developer, wherein the gate pin length is 100nm and the thickness of this adhesive layer is 350nm;

[0070] A7) Next, spin-coat electron beam positive resist UV135-0.9, define the gate cap pattern by direct electron beam writing and development with 3038 positive resist developer, and the thickness of this resist layer is 900nm;

[0071] A8) A 50nm SiN groove was formed by etching the exposed area at the gate pin using F-based ICP, and the electron beam resist on both sides above the groove was treated with high-temperature oxygen plasma to facilitate the formation of a self-aligned microfield plate structure. The etching conditions were: SF6 etching gas, gas flow rate of 15 sccm, upper electrode power of 130W, lower electrode power of 15W, temperature of 100℃, and etching depth of 50nm. The high-temperature oxygen plasma treatment conditions were: temperature of 80℃, O2 flow rate of 250 sccm, N2 flow rate of 50 sccm, and time of 4 min.

[0072] A9) After evaporation and stripping, an M-shaped gate with upward-protruding sides and a microfield plate structure is finally formed. The gate metal structure consists of four layers of metal Ni / Pt / Au / Ti with thicknesses of 20 / 40 / 600 / 20nm, respectively, and the length of the microfield plate structure on both sides is 40nm.

[0073] A10) The SiO2 temporary gate structure was removed by high-selectivity etching of BOE for 30 seconds.

[0074] A11) A 200nm SiN secondary passivation layer was deposited using PECVD to encapsulate the M-type gate and form a cavity. The dielectric deposition conditions were as follows: gases SiH4, NH3, and N2, with flow rates of 200sccm, 2400sccm, and 10sccm, respectively; pressure of 550mTorr; temperature of 300℃; and power of 40W.

[0075] The above specific implementation methods and embodiments are specific support for the technical concept of a low parasitic GaNHEMT device with a cavity structure and its manufacturing method proposed in this invention. They should not be used to limit the scope of protection of this invention. Any equivalent changes or modifications made on the basis of this technical solution in accordance with the technical concept proposed in this invention shall still fall within the scope of protection of this invention.

Claims

1. A low-parasitic GaN HEMT device with a cavity structure, characterized in that, The structure of the low parasitic GaN HEMT device, from bottom to top, includes a substrate (1), a GaN buffer layer (2), and a barrier layer (3). A source (4) and a drain (5) are provided above the barrier layer (3). A SiN passivation thin layer (6) is provided above the source (4), the drain (5), and the barrier layer (3). A groove (7) is provided in the SiN passivation thin layer (6) above the barrier layer (3). Microfield plates (8) are provided on both sides above the groove (7). The microfield plates (8) and the M-type gate (9) are an integral structure. The lower part of the middle of the M-type gate (9) is provided in the groove (7). A secondary passivation layer (10) is provided above and on both sides of the M-type gate (9). A cavity (11) is provided between the M-type gate (9) and the secondary passivation layer (10). The M-type gate (9) is a structure formed by a temporary gate control layer with upward protrusions on both sides. The cavity (11) is located between the secondary passivation layer (10) and the M-type gate (9) and is composed of air with a low dielectric constant. The metal thickness of the M-type gate (9) is not less than 500 nm. The thickness of the secondary passivation layer (10) is 150 nm to 300 nm.

2. The low-parasitic GaN HEMT device with a cavity structure according to claim 1, characterized in that, The depth of the groove (7) is the same as the thickness of the SiN passivation thin layer (6), and the thickness of the SiN passivation thin layer (6) is 30 nm to 100 nm.

3. The low-parasitic GaN HEMT device with a cavity structure according to claim 1, characterized in that, The lengths of the microfield plates (8) are all 20 nm to 50 nm.

4. The method for manufacturing a low-parasitic GaN HEMT device with a cavity structure as described in any one of claims 1-3, characterized in that, Includes the following steps: S1, through photolithography, evaporation, stripping and high temperature annealing, a source (4) and a drain (5) are formed on the barrier layer (3). S2, deposit a SiN passivation thin layer (6) on the surface of the barrier layer (3), source (4) and drain (5). S3, a temporary gate-controlled dielectric layer is deposited over the SiN passivation thin layer (6); S4, spin-coat electron beam negative adhesive, and write two adhesive masks directly between the source (4) and drain (5); S5, dry etching is used to remove the temporary gate control layer dielectric outside the two resist masks, and the resist is removed to obtain the two temporary gate control structures; S6. Spin-coat the first layer of electron beam positive adhesive onto the substrate surface. Define the gate pin pattern by electron beam direct writing between the two temporary gate control structures. S7, then spin-coat the second layer of electron beam positive adhesive, and define the grid cap pattern by electron beam direct writing; S8, the SiN passivation thin layer (6) between the gate pins is etched by dry etching to obtain the groove (7). S9, the gel type of electron beam adhesive on both sides above the groove (7) is controlled by high temperature oxygen plasma treatment, and a self-aligned micro field plate (8) is formed after evaporation and peeling. S10, through high selectivity wet etching, remove the temporary gate control structure to form an M-type gate (9) with micro-field plate structure and upward protrusion on both sides. S11, a secondary passivation layer (10) is deposited to wrap the M-type gate (9) and form a cavity (11).

5. The method for manufacturing a low-parasitic GaN HEMT device with a cavity structure according to claim 4, characterized in that, The temporary gate-controlled layer medium is SiO2 or W, which has high selectivity corrosion characteristics.

6. The method for manufacturing a low-parasitic GaN HEMT device with a cavity structure according to claim 4, characterized in that, The electron beam negative adhesive thickness in step S4 is 300–500 nm; the thickness of the first electron beam positive adhesive layer in step S6 is 300–500 nm; and the thickness of the second electron beam positive adhesive layer in step S7 is 600–900 nm.

7. The method for manufacturing a low-parasitic GaN HEMT device with a cavity structure according to claim 4, characterized in that, The high-temperature oxygen plasma treatment in step S9 is a constant-temperature treatment with a temperature of 70–100 °C, an oxygen flow rate of 200–400 sccm, a nitrogen flow rate of 50–150 sccm, and a treatment time of 3–5 min.

8. The method for manufacturing a low-parasitic GaN HEMT device with a cavity structure according to claim 4, characterized in that, The high-selectivity wet etching solution mentioned in step S10 is BOE or H2O2.

9. The method for manufacturing a low-parasitic GaN HEMT device with a cavity structure according to claim 4, characterized in that, The source (4) and drain (5) are made of any one of Ti / Al / Ni / Au, Ta / Ti / Al / Ni / Au, or Si / Ti / Al / Ni / Au; the M-type gate (9) is made of any one of Ni / Au, Ni / Pt / Au, or Ni / Pt / Au / Ti; and the secondary passivation layer (10) is made of any one of SiN, SiON, or SiO2.

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