Semiconductor element and method for manufacturing the same

Abstract

A semiconductor device and a method of fabricating the same are disclosed. The semiconductor device includes a substrate, an active region on the substrate, a recessed region in the active region, a gate dielectric layer on the recessed region, wherein an edge portion of the gate dielectric layer has a rounded profile, a gate structure on the gate dielectric layer, and a source / drain region in the active region on a side of the gate structure and directly contacting the edge portion of the gate dielectric layer.

Description

TECHNICAL FIELD

[0001] The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly, to a semiconductor device including a recessed channel and a method of fabricating the same. BACKGROUND

[0002] A Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is a semiconductor device widely used in analog and digital circuits. The MOSFET device uses a bias voltage of a gate electrode to attract carriers at the interface between a semiconductor and an oxide layer of a MOS capacitor to form a current channel between a source electrode and a drain electrode. The on and off of the current channel is controlled by controlling the bias voltage of the gate electrode.

[0003] With the advancement of semiconductor technology, the feature size of MOSFET devices is continuously reduced to increase the integration of integrated circuits. However, the Short Channel Effects (SCEs) become more and more significant. For example, the gate induced drain leakage (GIDL) and the hot carrier injection (HCI) seriously affect the performance and reliability of the device. SUMMARY

[0004] The present invention aims to provide a semiconductor device and a method of fabricating the same. The electric field intensity of the portion of the source / drain region adjacent to the gate dielectric layer is adjusted by the design of the recessed channel, which reduces the GIDL and HCI and improves the performance of the device.

[0005] According to an embodiment of the present invention, a semiconductor device includes a substrate, an active region on the substrate, a recessed region in the active region, a gate dielectric layer on the recessed region, wherein an edge portion of the gate dielectric layer has a rounded profile, a gate structure on the gate dielectric layer, and a source / drain region in the active region on a side of the gate structure and directly contacting the edge portion of the gate dielectric layer.

[0006] According to an embodiment of the present application, a method for fabricating a semiconductor device is provided. The method includes providing a substrate, forming an active region in the substrate, the active region including a recessed region, performing an oxidation fabrication process on the substrate to form a gate dielectric layer on the recessed region, wherein an edge portion of the gate dielectric layer has a rounded profile, forming a gate structure on the gate dielectric layer, and forming a source / drain region in the active region on a side of the gate structure, wherein the source / drain region directly contacts the edge portion of the gate dielectric layer. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figure 1A , Figure 1B , Figure 2A , Figure 2B , Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 5A , Figure 5B , Figure 6A , Figure 6B , Figure 7 and Figure 8 are schematic diagrams of a semiconductor device according to a first embodiment of the present application at different stages of fabrication.

[0008] Figure 1A is a plan view of the semiconductor device after a recessed region has been formed in the substrate, Figure 1B is a cross-sectional view along the AA line in Figure 1A .

[0009] Figure 2A is a plan view of the semiconductor device after a shallow trench isolation structure and an active region have been formed in the substrate, Figure 2B is a cross-sectional view along the AA line in Figure 2A .

[0010] Figure 3A is a plan view of the semiconductor device after a well region and a lightly doped region have been formed, Figure 3B is a cross-sectional view along the AA line in Figure 3A .

[0011] Figure 4A is a plan view of the semiconductor device after a gate dielectric layer has been formed, Figure 4B is a cross-sectional view along the AA line in Figure 4A .

[0012] Figure 5A is a plan view of the semiconductor device after a gate structure has been formed, Figure 5B is a cross-sectional view along the AA line in Figure 5A .

[0013] Figure 6A This is a planar schematic diagram of a semiconductor device after the spacer walls and source / drain regions have been fabricated. Figure 6B For along Figure 6A A cross-sectional diagram of the AA tangent; and

[0014] Figure 7 for Figure 6B A cross-sectional schematic diagram of a semiconductor device after the metal gate and contact plug have been fabricated;

[0015] Figure 8 for Figure 7 A partially enlarged schematic diagram of the semiconductor device shown;

[0016] Figure 9 This is a partially enlarged schematic diagram of a semiconductor element according to a second embodiment of the present invention;

[0017] Figure 10 This is a partially enlarged schematic diagram of a semiconductor element according to a third embodiment of the present invention;

[0018] Figure 11 This is a cross-sectional schematic diagram of a semiconductor element according to the fourth embodiment of the present invention;

[0019] Figure 12 and Figure 13 This is a schematic diagram of a semiconductor device according to the fifth embodiment of the present invention at different stages of the manufacturing process, wherein:

[0020] Figure 12 This is a cross-sectional view of a semiconductor device after the gate structure has been fabricated; and

[0021] Figure 13 This is a cross-sectional schematic diagram of a semiconductor device after the metal gate and contact plug have been fabricated.

[0022] Figure 14 This is a cross-sectional schematic diagram of a semiconductor element according to the sixth embodiment of the present invention;

[0023] Figure 15 This is a top view of the semiconductor device according to the seventh embodiment of the present invention after the active region, shallow trench isolation structure and recessed region have been fabricated.

[0024] Explanation of main component symbols

[0025] 100 base

[0026] 102 Active (Active) Region

[0027] 104 Shallow trench isolation structure

[0028] 106 Depressed area

[0029] 120 Tunnel

[0030] 122 lightly doped region

[0031] 124 source / drain region

[0032] 126 metal silicide

[0033] 130 gate dielectric layer

[0034] 131 base oxide layer

[0035] 132 deposited dielectric layer

[0036] 140 gate structure

[0037] 141 polysilicon layer

[0038] 142 hard mask layer

[0039] 150 spacer

[0040] 151 first spacer

[0041] 152 second spacer

[0042] 160 contact etch stop layer

[0043] 162 interlayer dielectric layer

[0044] 164 contact plug

[0045] 170 metal gate

[0046] 172 work function metal layer

[0047] 174 barrier layer

[0048] 176 low-resistance metal layer

[0049] 102a edge

[0050] 102b edge

[0051] 102c top corner

[0052] 102s surface

[0053] 106a edge

[0054] 106b edge

[0055] 106c bottom corner

[0056] 106d sidewall

[0057] 130A edge portion

[0058] 130a horizontal extension

[0059] 140a side wall

[0060] 170a side wall

[0061] AA tangent line

[0062] D1 distance

[0063] D2 distance

[0064] P1 oxidation fabrication process

[0065] P2 deposition fabrication process

[0066] TK1 depth

[0067] TK2 depth

[0068] W1 width

[0069] W1' width

[0070] W2 width

[0071] W2' width

[0072] W3 width

[0073] W4 width

[0074] X direction

[0075] Y direction

[0076] Z direction DETAILED DESCRIPTION

[0077] In order to make the above objectives, features and advantages of the present application more apparent, the following preferred embodiments will be specifically described with reference to the accompanying drawings. The accompanying drawings are schematic and not drawn to scale, and the same or similar features are generally described with the same reference numerals. The embodiments described herein and the accompanying drawings are for reference and illustration only, and are not intended to limit the present application. The scope of the present application is defined by the claims. Those having the same meaning as the claims of the present application should also be included in the scope of the present application.

[0078] Please refer to Figure 1A , Figure 1B , Figure 2A , Figure 2B , Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 5A , Figure 5B , Figure 6A , Figure 6B , Figure 7 and Figure 8, are cross-sectional views of the semiconductor device according to the first embodiment of the present application at different stages of the manufacturing process, wherein Figure 1A 、 Figure 2A 、 Figure 3A 、 Figure 4A 、 Figure 5A and Figure 6B are plan views of the semiconductor device on a plane defined along the X and Y directions, Figure 1B 、 Figure 2B 、 Figure 3B 、 Figure 4B 、 Figure 5B 、 Figure 6B are cross-sectional views of the semiconductor device along the A-A cut line in Figure 1A 、 Figure 2A 、 Figure 3A 、 Figure 4A 、 Figure 5A and Figure 6B on a plane defined along the X and Z directions. Figure 7 is a cross-sectional view of the semiconductor device on a plane defined along the X and Z directions. Figure 8 are enlarged views of the semiconductor device shown in Figure 7 .

[0079] As shown in Figure 1A and Figure 1B , a substrate 100, such as a silicon substrate, an epitaxial silicon substrate, a silicon germanium semiconductor substrate, a silicon carbide substrate, a silicon-on-insulator (SOI) substrate, or the like, is provided first. The substrate 100 can include a doping to have a conductivity type, such as a P conductivity type. A patterning process, such as a photolithography and etching process, is then performed on the substrate 100 to form a recessed region 106 in the substrate 100. The recessed region 106 has a width W1 in the X direction and a width W2 in the Y direction. According to an embodiment of the present application, the depth TK1 of the recessed region 106 can be between 200 and 300 angstroms, but is not limited thereto.

[0080] As shown in Figure 2A and Figure 2B , another patterning process, such as a photolithography and etching process, is then performed on the substrate 100 to form trenches (not shown) in the substrate 100 and define active regions 102 in the substrate 100. A deposition process, such as a chemical vapor deposition process, is then performed to fill the trenches with a dielectric material. A planarization process, such as a chemical mechanical polishing process, is then performed to remove the dielectric material outside the trenches, thereby obtaining shallow trench isolation structures 104 surrounding the active regions 102. The depth TK2 of the shallow trench isolation structures 104 (the depth from the surface 102s of the active regions 102) can be between 2500 and 3500 angstroms, but is not limited thereto.

[0081] The active region 102 includes a recessed region 106, which is located substantially in the portion of the active region 102 where a channel region is expected to be formed. For example, the recessed region 106 can be located substantially in the middle portion of the active region 102. It is noted that since the recessed region 106 is formed before the active region 102 and the shallow trench isolation structure 104 are formed, the width W2 of the recessed region 106 in the Y direction is reduced from W2 (refer to FIG. 1) to W2' which is the same as the width W2' of the active region 102 by the shallow trench isolation structure 104. Figure 1A ) is shown. The two edges 106b of the recessed region 106 extending in the X direction are cut flush with the two edges 102b of the active region 102 and abut the shallow trench isolation structure 104. The other two edges 106a of the recessed region 106 extending in the Y direction are cut through the interior of the active region 102, leaving a distance from the edges 102a of the active region 102 and not abutting the shallow trench isolation structure 104. Figure 2A ) is shown. The two edges 106b of the recessed region 106 extending in the X direction are cut flush with the two edges 102b of the active region 102 and abut the shallow trench isolation structure 104. The other two edges 106a of the recessed region 106 extending in the Y direction are cut through the interior of the active region 102, leaving a distance from the edges 102a of the active region 102 and not abutting the shallow trench isolation structure 104.

[0082] ) is shown. The two edges 106b of the recessed region 106 extending in the X direction are cut flush with the two edges 102b of the active region 102 and abut the shallow trench isolation structure 104. The other two edges 106a of the recessed region 106 extending in the Y direction are cut through the interior of the active region 102, leaving a distance from the edges 102a of the active region 102 and not abutting the shallow trench isolation structure 104. Figure 3A ) is shown. The two edges 106b of the recessed region 106 extending in the X direction are cut flush with the two edges 102b of the active region 102 and abut the shallow trench isolation structure 104. The other two edges 106a of the recessed region 106 extending in the Y direction are cut through the interior of the active region 102, leaving a distance from the edges 102a of the active region 102 and not abutting the shallow trench isolation structure 104. Figure 3B ) is shown. The two edges 106b of the recessed region 106 extending in the X direction are cut flush with the two edges 102b of the active region 102 and abut the shallow trench isolation structure 104. The other two edges 106a of the recessed region 106 extending in the Y direction are cut through the interior of the active region 102, leaving a distance from the edges 102a of the active region 102 and not abutting the shallow trench isolation structure 104. Figure 3B ) is shown. The two edges 106b of the recessed region 106 extending in the X direction are cut flush with the two edges 102b of the active region 102 and abut the shallow trench isolation structure 104. The other two edges 106a of the recessed region 106 extending in the Y direction are cut through the interior of the active region 102, leaving a distance from the edges 102a of the active region 102 and not abutting the shallow trench isolation structure 104.

[0083] ) is shown. The two edges 106b of the recessed region 106 extending in the X direction are cut flush with the two edges 102b of the active region 102 and abut the shallow trench isolation structure 104. The other two edges 106a of the recessed region 106 extending in the Y direction are cut through the interior of the active region 102, leaving a distance from the edges 102a of the active region 102 and not abutting the shallow trench isolation structure 104. Figure 4A ) is shown. The two edges 106b of the recessed region 106 extending in the X direction are cut flush with the two edges 102b of the active region 102 and abut the shallow trench isolation structure 104. The other two edges 106a of the recessed region 106 extending in the Y direction are cut through the interior of the active region 102, leaving a distance from the edges 102a of the active region 102 and not abutting the shallow trench isolation structure 104. Figure 4BAs shown, the substrate 100 is then subjected to an oxidation fabrication process P1 and a deposition fabrication process P2 in sequence to form a gate dielectric layer 130 on the substrate 100. For example, the substrate 100 can be subjected to an in-situ steam generation (ISSG) oxidation fabrication process to grow a substrate oxide layer 131 along the surface of the active region 102 and the recessed region 106, and then subjected to an atomic layer deposition (ALD) to form a deposited dielectric layer 132 on the substrate oxide layer 131. The gate dielectric layer 130 is formed by the substrate oxide layer 131 and the deposited dielectric layer 132 together, having a double-layer structure, in which the substrate oxide layer 131 is in direct contact with the substrate 100, and the deposited dielectric layer 132 is located on the substrate oxide layer 131 and is separated from the substrate 100 by the substrate oxide layer 131 without being in direct contact with the substrate 100. According to an embodiment of the present application, the substrate oxide layer 131 and the deposited dielectric layer 132 are made of silicon oxide, respectively. In other embodiments, the substrate oxide layer 131 can be made of silicon oxide, and the deposited dielectric layer 132 can be made of a high-k dielectric layer.

[0084] The thickness of the gate dielectric layer 130 can be adjusted according to requirements. According to an embodiment of the present application, the thickness of the gate dielectric layer 130 can be between 200 angstroms and 300 angstroms, but is not limited thereto. The ratio of the thickness of the substrate oxide layer 131 to the thickness of the deposited dielectric layer 132 can be adjusted according to requirements, for example, the thickness of the substrate oxide layer 131 can be between about 1 times and about 2.5 times the thickness of the deposited dielectric layer 132. For example, when the thickness of the gate dielectric layer 130 is about 200 angstroms, the thickness of the substrate oxide layer 131 can be about 140 angstroms, and the thickness of the deposited dielectric layer 132 can be about 60 angstroms. According to an embodiment of the present application, the oxidation fabrication process P1 can also be performed until the substrate oxide layer 131 grows to the expected thickness of the gate dielectric layer 130, for example, between 200 angstroms and 300 angstroms, without performing the deposition fabrication process P2. In other words, the gate dielectric layer 130 is formed by the substrate oxide layer 131 only, having a single-layer structure.

[0085] It is worth noting that since the oxidation fabrication process P1 oxidizes the material of the substrate 100 to form the substrate oxide layer 131, after the oxidation fabrication process P1, the width of the recessed region 106 in the X direction will be W2 (refer to FIG. 1C) which is smaller than the original W1 (refer to FIG. 1A) due to the oxidation of the material of the substrate 100. Figure 2A) is enlarged to a width W1', and the bottom corner 106c of the recessed region 106 and the top corner 102c of the active region 102 are rounded to obtuse angles, and the sidewall 106d is slightly inclined outwardly from the recessed region 106. Overall, the edge portion of the recessed region 106 has a rounded profile after the oxidation process P1. The difference between the width W1 and the width W1' is substantially determined by the thickness of the substrate 100 consumed by the oxidation process P1. According to an embodiment of the present application, the width W1 and the width W1' can differ by about 50 angstroms to 150 angstroms, but are not limited thereto.

[0086] As shown in FIG. 1C, a gate dielectric layer 130 is then formed on the substrate 100. According to an embodiment of the present application, the gate dielectric layer 130 can include a silicon dioxide layer 130a and a high-k dielectric layer 130b. The silicon dioxide layer 130a can be formed by a thermal oxidation process, and the high-k dielectric layer 130b can be formed by a chemical vapor deposition (CVD) process. Figure 5A and Figure 5B As shown in FIG. 1D, a gate material layer (not shown) is then formed on the substrate 100, and a patterning process (e.g., a photolithography and etching process) is performed on the gate material layer to form a gate structure 140 on the gate dielectric layer 130. The gate structure 140 extends along the Y direction across the active region 102 and partially overlaps the shallow trench isolation structure 104. The gate structure 140 and the active region 102 are separated by the gate dielectric layer 130 and do not directly contact each other. The gate structure 140 can be a dummy gate for a subsequent replacement metal gate (RMG) process to form a metal gate. According to an embodiment of the present application, the gate structure 140 can include a polysilicon layer 141 and a hard mask layer 142 on the polysilicon layer 141.

[0087] The gate dielectric layer 130 outside the recessed region 106 can be etched away when the gate structure 140 is formed, and the surface 102s of the active region 102 is exposed. According to an embodiment of the present application, the surface 130s of the gate dielectric layer 130 covered by the gate structure 140 and the surface 102s of the active region 102 can be substantially planar.

[0088] In the present embodiment, the width W3 of the gate structure 140 in the X direction is less than the width W1' of the recessed region 106, and thus the edge portion 130A of the gate dielectric layer 130 is exposed from both sides of the gate structure 140 and overhangs the sidewall 140a of the gate structure 140 by a distance D1. The distance D1 is substantially equal to the distance between the edge 106a of the recessed region 106 and the sidewall 140a of the gate structure 140. According to an embodiment of the present application, the distance D1 can be between 0 angstroms and 250 angstroms, but is not limited thereto. When the width W3 of the gate structure 140 in the X direction is substantially equal to the width W1' of the recessed region 106, the sidewall 140a of the gate structure 140 is substantially flush with the edge 106a of the recessed region 106, and the distance D1 is substantially equal to zero. As shown in FIG. 1E, a work function layer 150 is then formed on the substrate 100. According to an embodiment of the present application, the work function layer 150 can include a titanium layer 150a and a titanium nitride layer 150b. Figure 5BAs shown, the gate structure 140 can partially overlap the lightly doped region 122 in the Z direction (i.e., the vertical direction).

[0089] As shown, a spacer material layer (not shown) can then be formed to cover the substrate 100 and the gate structure 140 entirely, and then an anisotropic etching process can be performed to remove the spacer material layer on the surface of the substrate 100 and the top surface of the gate structure 140, so as to obtain a spacer 150 self-aligned to the sidewall 140a of the gate structure 140. Then, a suitable dopant can be implanted into the active region 102 on both sides of the spacer 150 by using an ion implantation process self-aligned to the spacer 150, so as to form the source / drain region 124. Figure 6A Figure 6B The source / drain region 124 is located in the lightly doped region 122, surrounded by the lightly doped region 122 and separated from the well region 120, and does not directly contact the well region 120. The source / drain region 124 has the same conductivity type as the lightly doped region 122. The dopant of the source / drain region 124 can laterally diffuse into the substrate 100 directly below the spacer 150, so as to

[0090] As shown, the source / drain region 124 can directly contact the edge portion 130A of the gate dielectric layer 130. Figure 6B

[0091] The spacer 150 can include a multi-layer structure, for example, can include a first spacer 151 having an L-shaped cross-sectional shape, and a second spacer 152 located on the first spacer 151. According to an embodiment of the present application, the materials of the first spacer 151 and the second spacer 152 can be selected from silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, nitrogen-doped silicon carbide, or other suitable dielectric materials. The width W4 of the spacer 150 can be controlled by adjusting the thickness of the spacer material layer and the lateral etching of the anisotropic etching process. In the present embodiment, the width W4 of the spacer 150 can be greater than the distance D1 at which the gate dielectric layer 130 extends, so that the spacer 150 will cross the edge 106a of the recessed region 106 (or the top corner 102c of the active region 102), while partially overlapping the gate dielectric layer 130 and the active region 102 in the Z direction (i.e., the vertical direction). According to an embodiment of the present application, the width W4 of the spacer 150 can be between 150 angstroms and 250 angstroms, but is not limited thereto.

[0092] As shown, a spacer material layer (not shown) can then be formed to cover the substrate 100 and the gate structure 140 entirely, and then an anisotropic etching process can be performed to remove the spacer material layer on the surface of the substrate 100 and the top surface of the gate structure 140, so as to obtain a spacer 150 self-aligned to the sidewall 140a of the gate structure 140. Then, a suitable dopant can be implanted into the active region 102 on both sides of the spacer 150 by using an ion implantation process self-aligned to the spacer 150, so as to form the source / drain region 124. Figure 7 ​​As shown, a self-aligned metallization fabrication process is then used to form a metal silicide 126 in the source / drain region 124. A contact etch stop layer 160 and an interlayer dielectric layer 162 are then formed to completely cover the substrate 100 and the gate structure 140. A planarization process (e.g., chemical mechanical polishing) is then performed to remove portions of the interlayer dielectric layer 162 and the gate structure 140 until the top surface of the gate structure 140 is exposed. A replacement metal gate (RMG) fabrication process is then performed to replace the gate structure 140 with a metal gate 170. A contact plug 164 is then formed that passes through the interlayer dielectric layer 162 and the contact etch stop layer 160 and contacts the metal silicide 126 on the source / drain region 124. According to one embodiment of the invention, the material of the contact etch stop layer 160 may include silicon nitride, silicon oxynitride, silicon carbide, or nitrogen-doped silicon carbide, and the material of the interlayer dielectric layer 162 may include silicon oxide, but is not limited thereto.

[0093] like Figure 7 As shown, the metal gate 170 may include a U-shaped work function metal layer 174, a U-shaped barrier layer 175, and a low-resistance metal layer 176. According to one embodiment of the present invention, when the semiconductor device is an N-type transistor, the work function metal layer 174 may be made of a metal material with a work function of 3.9 electron volts (eV) to 4.3 eV, such as titanium aluminide (TiAl), zirconium aluminide (ZrAl), tungsten aluminide (WAl), tantalum aluminide (TaAl), hafnium aluminide (HfAl), or TiAlC (titanium aluminum carbide), but is not limited thereto. According to one embodiment of the present invention, when the semiconductor device is a P-type transistor, the work function metal layer 174 may be made of a metal material with a work function of 4.8 eV to 5.2 eV, such as titanium nitride (TiN), tantalum nitride (TaN), or tantalum carbide (TaC), but is not limited thereto. According to one embodiment of the present invention, the material of the barrier layer 175 may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), etc., but is not limited thereto. The low-resistivity metal layer 176 may include aluminum (Al), tungsten (W), copper (Cu), titanium-aluminum alloy (TiAl), or cobalt tungsten phosphide (CoWP), etc., but is not limited thereto. A U-shaped high-k dielectric layer may be provided between the work function metal layer 174 and the spacer wall 150 and the gate dielectric layer 130, so that the work function metal layer 174 is not in direct contact with the gate dielectric layer 130 and the spacer wall 150. In another embodiment, a T-shaped high-k dielectric layer may be provided between the bottom surface of the work function metal layer 174 and the gate dielectric layer 130, so that the work function metal layer 174 can be in direct contact with the spacer wall 150 but not with the gate dielectric layer 130. In yet another embodiment, the work function metal layer 174 may be in direct contact with the spacer wall 150 and the gate dielectric layer 130, without a high dielectric constant dielectric layer between them.

[0094] Reference is made to Figure 7 and Figure 8 The semiconductor device provided by the present application includes a substrate 100, an active region 102 defined on the substrate 100 by a shallow trench isolation structure 104, a recessed region 106 in the active region 102, a gate dielectric layer 130 on the recessed region 106, a gate structure, such as a metal gate 170, on the gate dielectric layer 130, and source / drain regions 124 in the active region 102 on both sides of the metal gate 170. In some embodiments, the semiconductor device further includes a well region 120 in the active region 102 and surrounding the recessed region 106, and a lightly doped region 122 in the well region 120 on both sides of the recessed region 106 and surrounding the source / drain regions 124. The source / drain regions 124 are separated from the well region 120 by the lightly doped region 122 and do not directly contact the well region 120. The lightly doped region 122 partially overlaps the metal gate 170 in the Z direction (i.e., the vertical direction). The portion of the active region 102 directly under the gate dielectric layer 130 is a recessed channel region of the semiconductor device, and the on and off of the current of the recessed channel region is controlled by the metal gate 170. The present application designs the channel region under the recessed region 106 and uses the oxidation fabrication process P1 (e.g., ISSG) for fabricating the gate dielectric layer 130 to round the bottom corner 106c of the recessed region 106 and the top corner 102c of the active region 102, so that the edge portion 130A of the gate dielectric layer 130 also has a rounded profile along the profile of the bottom corner 106c, the sidewall 106d, and the top corner 102c, thereby reducing the electric field strength between the edge of the metal gate 170 and the source / drain regions 124, and improving the problem of leakage current and reliability reduction caused by GIDL and HCI.

[0095] The following will describe different embodiments of the present application. For simplicity of description, the following description mainly describes the differences between the embodiments, and does not repeat the same parts. The same elements in the embodiments are marked with the same reference numerals for the purpose of mutual reference between the embodiments.

[0096] Reference is made to Figure 9 , which is a partial enlarged schematic view of a semiconductor device according to a second embodiment of the present application, and Figure 8The main difference in the semiconductor device shown is that the sidewall 170a of the metal gate 170 can be pushed outward toward the source / drain region 124 (i.e., the distance D1 becomes smaller), so that the metal gate 170 can overlap directly above the edge portion 130A of the gate dielectric layer 130. In some cases, the sidewall 170a of the metal gate 170 and the edge 106a can be approximately aligned in the Z direction (vertical direction). After the source / drain region 124, which is self-aligned with the spacer wall 150, diffuses laterally, it can still be separated from the edge portion 130A of the gate dielectric layer 130 by a distance, separated from each other by the lightly doped region 122, and not in direct contact.

[0097] Please refer to Figure 10 The diagram shown is a partially enlarged schematic diagram of a semiconductor element according to a third embodiment of the present invention, which is consistent with... Figure 8 The main difference in the semiconductor device shown is that the sidewall 170a of the metal gate 170 can be recessed away from the edge portion 130A of the gate dielectric layer 130 (i.e., the distance D1 increases), or the width W4 of the spacer wall 150 can be reduced. In this case, the source / drain region 124 formed by self-alignment with the spacer wall 150 can completely cover the edge portion 130A of the gate dielectric layer 130 (covering the bottom corner 106c and sidewall 106d of the recessed region 106 and the top corner 102c of the active region 102). In some embodiments, such as Figure 10 As shown, the edge portion 130A of the gate dielectric layer 130 can be exposed from the outside of the spacer wall 150, and the contact etch stop layer 160 can extend across the edge 106a of the recessed region 106 and partially overlap with the gate dielectric layer 130 in the Z direction (i.e., the vertical direction).

[0098] Please refer to Figure 11 The diagram shown is a cross-sectional schematic of a semiconductor device according to a fourth embodiment of the present invention, which is consistent with... Figure 7 The main difference in the semiconductor device shown is that the spacer wall 150 can be removed after the metal silicide 126 is formed, so the subsequently formed contact etch stop layer 160 can extend across the edge 106a of the recessed region 106, directly contact the sidewall 170a of the metal gate 170, and partially overlap with the gate dielectric layer 130 in the Z direction (i.e., the vertical direction).

[0099] Please refer to Figure 12 and Figure 13 , Figure 12 The diagram shown is a cross-sectional view of a semiconductor device after the gate structure 140 has been fabricated according to the fifth embodiment of the present invention (corresponding to...). Figure 5B step), Figure 13 for Figure 12 A cross-sectional view of the semiconductor device after fabrication of the metal gate 170 and contact plug 164 (corresponding to...) Figure 7 Steps). This embodiment andFigure 5B and Figure 7 The main difference between the semiconductor device of the embodiment shown in Figure 12 In the embodiment shown in FIG. 1, the gate dielectric layer 130 (e.g. a base oxide layer 131) on the surface 102s of the active region 102 can remain a partial thickness after the gate structure 140 is formed, and can be used as a screen oxide to protect the surface 102s of the active region 102 during subsequent fabrication processes and to reduce channeling effect of ion implantation to form ultra shallow source / drain regions 124. As shown in FIG. 1, the edge portion 130A of the gate dielectric layer 130 can include a horizontal extension 130a sandwiched between the bottom of the spacer 150 and the source / drain regions 124, and covering the top corner 102c of the active region 102. Figure 13

[0100] Figure 14 FIG. 6 shows a cross-sectional view of a semiconductor device according to a sixth embodiment of the present application. The main difference between the semiconductor device of the embodiment shown in FIG. 6 and that shown in FIG. 5 is that the spacer 150 can be removed after the metal silicide 126 is formed, so that the subsequently formed contact etch stop layer 160 can extend across the edge 106a of the recessed region 106, directly contact the sidewall 170a of the metal gate 170, and partially overlap the horizontal extension 130a of the gate dielectric layer 130 in the Z direction (i.e. the vertical direction). Figure 13

[0101] Figure 15 FIG. 7 shows a top view of a semiconductor device according to a seventh embodiment of the present application after the active region 102, the shallow trench isolation structure 104, and the recessed region 106 are formed. In the embodiment shown in FIG. 7, the recessed region 106 can be formed after the shallow trench isolation structure 104 and the active region 102 are formed, so that the pattern of the recessed region 106 is located in both the shallow trench isolation structure 104 and the active region 102. As shown in FIG. 7, the recessed region 106 can extend into the area of the shallow trench isolation structure 104 along the Y direction. The edge 106b of the recessed region 106 is located in the area of the shallow trench isolation structure 104, and is separated from the edge 102b of the active region 102 by a distance D2. According to an embodiment of the present application, the distance D2 can be between 0 and 200 angstroms, but is not limited thereto. Figure 15

[0102] ​​​In summary, the semiconductor element and the manufacturing method thereof provided by the present application can adjust the electric field intensity of the edge portion of the gate dielectric layer adjacent to the source / drain region, reduce the gate-induced drain leakage current (GIDL) caused by the band-to-band tunneling of the carriers under the action of the strong electric field, and improve the element performance. The present application also has an improved effect on the reliability problem caused by hot carrier injection (HCI).

[0103] The above merely describes the preferred embodiments of the present application, and any equivalent changes and modifications made according to the claims of the present application shall fall within the scope of the present application.

Claims

1. A semiconductor device, comprising: a substrate having an active region thereon; a recessed region in the active region; a gate dielectric layer on the recessed region, wherein an edge portion of the gate dielectric layer has a rounded profile; a gate structure on the gate dielectric layer, wherein in a plan view of the semiconductor device, the active region overlaps less than the recessed region and completely overlaps the recessed region with the gate structure; and a source / drain region in the active region on a side of the gate structure and directly contacting the edge portion of the gate dielectric layer.

2. The semiconductor device of claim 1, wherein the recessed region has a depth of between 200 and 300 angstroms.

3. The semiconductor device of claim 1, further comprising a shallow trench isolation structure surrounding the active region.

4. The semiconductor device of claim 3, wherein an edge of the recessed region is cut flush with an edge of the active region adjacent the shallow trench isolation structure.

5. The semiconductor device of claim 3, wherein the recessed region partially overlaps the shallow trench isolation structure.

6. The semiconductor device of claim 1, further comprising: a well region in the active region and surrounding the recessed region; and a lightly doped region in the well region and surrounding the source / drain region.

7. The semiconductor device of claim 1, wherein the gate dielectric layer comprises: a base oxide layer directly on the substrate; and a deposited dielectric layer on the base oxide layer.

8. The semiconductor device of claim 7, wherein a top surface of the deposited dielectric layer is substantially flush with a surface of the active region.

9. The semiconductor device of claim 1, further comprising a spacer on sidewalls of the gate structure and across an edge of the recessed region.

10. The semiconductor device of claim 1, wherein the gate structure comprises a metal gate.

11. A method of fabricating a semiconductor device, comprising: providing a substrate; forming an active region in the substrate, the active region including a recessed region; performing an oxidation fabrication process on the substrate to form a gate dielectric layer on the recessed region, wherein an edge portion of the gate dielectric layer has a rounded profile; forming a gate structure on the gate dielectric layer, wherein in a plan view of the semiconductor device, the active region overlaps less than the recessed region and completely overlaps the recessed region with the gate structure; and forming a source / drain region in the active region on a side of the gate structure, wherein the source / drain region directly contacts the edge portion of the gate dielectric layer.

12. The method of fabricating a semiconductor device of claim 11, wherein the recessed region has a depth of between 200 and 300 angstroms.

13. The method of fabricating a semiconductor device of claim 11, wherein forming the active region in the substrate comprises: forming the recessed region in the substrate; and forming a shallow trench isolation structure in the substrate to define the active region after forming the recessed region.

14. The method of fabricating a semiconductor device of claim 11, wherein forming the active region in the substrate comprises: forming a shallow trench isolation structure in the substrate to define the active region; and forming a well region in the active region and surrounding the recessed region; and forming a lightly doped region in the well region and surrounding the source / drain region. ​ ​ ​ ​ The recessed region is formed in the shallow trench isolation structure and the active region.

15. The method of claim 11, wherein prior to performing the oxidation fabrication process, further comprising: forming a well region in the active region; and forming a lightly doped region in the well region and surrounding the edges of the recessed region.

16. The method of claim 11, wherein the oxidation fabrication process comprises an in-situ steam generation (ISSG) oxidation fabrication process.

17. The method of claim 11, wherein forming the gate dielectric layer comprises: performing the oxidation fabrication process to form a base oxide layer; and performing a deposition fabrication process to form a deposited dielectric layer on the base oxide layer.

18. The method of claim 17, wherein a top surface of the deposited dielectric layer is substantially planar with a surface of the active region.

19. The method of claim 11, wherein prior to forming the source / drain regions, further comprising: forming a spacer on sidewalls of the gate structure, wherein the spacer spans the edges of the recessed region.

20. The method of claim 11, further comprising performing a replacement metal gate fabrication process to convert the gate structure to a metal gate.

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